KR20000001410A - Ball grid array pacakge - Google Patents

Ball grid array pacakge Download PDF

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Publication number
KR20000001410A
KR20000001410A KR1019980021671A KR19980021671A KR20000001410A KR 20000001410 A KR20000001410 A KR 20000001410A KR 1019980021671 A KR1019980021671 A KR 1019980021671A KR 19980021671 A KR19980021671 A KR 19980021671A KR 20000001410 A KR20000001410 A KR 20000001410A
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KR
South Korea
Prior art keywords
grid array
ball grid
inner leads
array package
package
Prior art date
Application number
KR1019980021671A
Other languages
Korean (ko)
Inventor
김승우
임민빈
Original Assignee
윤종용
삼성전자 주식회사
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Publication date
Application filed by 윤종용, 삼성전자 주식회사 filed Critical 윤종용
Priority to KR1019980021671A priority Critical patent/KR20000001410A/en
Publication of KR20000001410A publication Critical patent/KR20000001410A/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49517—Additional leads
    • H01L23/4952—Additional leads the additional leads being a bump or a wire
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49575—Assemblies of semiconductor devices on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
    • H01L23/49582—Metallic layers on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process

Abstract

PURPOSE: A package is made to reinforce the cost competitiveness of a product by lowering the fabrication cost price and to accomplish the chip scale package. CONSTITUTION: A ball grid array package is composed so that a penetration hole(10) is formed to reveal inner leads(3) of a lead frame on a molding resin(9) of a thin plastic package and a plated layer(11) is formed on the revealed inner leads and conductive balls(13) are connected on the plated layer.

Description

볼그리드어레이 패키지Ball Grid Array Package

본 발명은 볼그리드어레이 패키지에 관한 것으로, 더욱 상세하게는 리드프레임을 사용한 볼그리드어레이패키지에 관한 것이다.The present invention relates to a ball grid array package, and more particularly, to a ball grid array package using a lead frame.

최근, 전자기기와 정보기기의 메모리 용량이 대용량화함에 따라 DRAM과 SRAM과 같은 반도체 메모리소자는 고집적화되면서 칩사이즈가 점차 증대하고 있다. 반도체칩을 내장하는 반도체칩 패키지는 전자기기와 정보기기의 경량화 추세에 맞추어 경박단소화되고 있다. 또한, 전자기기와 정보기기의 다기능화에 맞추어 반도체칩 패키지는 다핀화, 미세 피치화되고 있다.Recently, as the memory capacities of electronic devices and information devices are increased, semiconductor memory devices such as DRAM and SRAM are highly integrated, and chip sizes are gradually increasing. Semiconductor chip packages incorporating semiconductor chips are becoming thin and light in accordance with the trend toward lighter weight of electronic devices and information devices. In addition, the semiconductor chip package has become multipinned and fine pitched in accordance with the multifunctionality of electronic devices and information devices.

이러한 추세에 맞추어 볼그리드어레이 패키지가 기존의 다핀 쿼드 플랫 패키지(QFP)를 대체하기 시작하였다. 인쇄회로기판에 실장된 볼그리드어레이 패키지가 동작하는 동안 발생되는 열은 볼그리드어레이 패키지의 도전성 볼, 예를 들어 솔더 볼을 거쳐 외부로 발출된다. 따라서, 볼그리드어레이 패키지의 열방출 특성이 양호하다.In line with this trend, ball grid array packages have begun to replace the traditional Daffin Quad Flat Package (QFP). Heat generated during operation of the ball grid array package mounted on the printed circuit board is discharged to the outside through the conductive ball, for example, solder ball of the ball grid array package. Therefore, the heat dissipation characteristics of the ball grid array package are good.

뿐만 아니라, 반도체칩에서 모더(mother) 기판인 인쇄회로기판까지의 패턴 길이가 단축되어 반도체칩의 전기적 특성이 향상된다.In addition, the pattern length from the semiconductor chip to the printed circuit board, which is the mother board, is shortened, thereby improving the electrical characteristics of the semiconductor chip.

그러나, 이러한 종래의 볼그리드어레이 패키지는 리드프레임 대신에 회로의 패턴이 형성된 인쇄회로기판을 사용하므로 제조단가가 높고, 제조공정이 어렵고, 흡습율이 높은 문제점을 갖고 있다.However, such a conventional ball grid array package has a problem in that the manufacturing cost is high, the manufacturing process is difficult, and the moisture absorption rate is high because a printed circuit board having a circuit pattern is formed instead of the lead frame.

` 따라서, 본 발명의 목적은 볼그리드어레이 패키지에 인쇄회로기판을 대신하여 리드프레임을 적용하도록 한 것이다.Therefore, an object of the present invention is to apply a lead frame to a ball grid array package in place of a printed circuit board.

또한, 본 발명의 목적은 볼그리드어레이 패키지의 제조원가를 저감시키도록 한 것이다.In addition, an object of the present invention is to reduce the manufacturing cost of the ball grid array package.

도 1은 본 발명에 의한 볼그리드어레이 패키지를 나타낸 단면구조도.1 is a cross-sectional structural view showing a ball grid array package according to the present invention.

도 2a 내지 도 2d는 본 발명에 의한 볼그리드어레이 패키지의 제조방법을 나타낸 단면공정도.Figure 2a to 2d is a cross-sectional view showing a manufacturing method of the ball grid array package according to the present invention.

<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for main parts of the drawings>

1: 반도체칩 2: 센터패드 3: 리드프레임의 내부리드 5: 접착테이프 7: 본딩와이어 9: 몰딩수지 10: 관통홀 11: 도금층 13: 도전성 볼DESCRIPTION OF SYMBOLS 1 Semiconductor chip 2: Center pad 3: Inner lead of lead frame 5: Adhesive tape 7: Bonding wire 9: Molding resin 10: Through hole 11: Plating layer 13: Conductive ball

이와 같은 목적을 달성하기 위한 본 발명에 의한 볼그리드어레이 패키지는 박형 플라스틱 패키지의 몰딩수지에 형성된 관통홀을 거쳐 리드프레임의 내부리드상에 도전성 볼이 안착되도록 구성된다.The ball grid array package according to the present invention for achieving the above object is configured so that the conductive ball is seated on the inner lead of the lead frame through the through-hole formed in the molding resin of the thin plastic package.

따라서, 본 발명은 기존의 박형 패키지의 제조공정을 활용하여 볼그리드어레이 패키지를 제조하여 제품의 제조단가를 낮출 수 있다.Therefore, the present invention can reduce the manufacturing cost of the product by manufacturing the ball grid array package using the existing manufacturing process of the thin package.

이하, 본 발명에 의한 볼그리드어레이 패키지를 첨부된 도면을 참조하여 상세히 설명하기로 한다.Hereinafter, a ball grid array package according to the present invention will be described in detail with reference to the accompanying drawings.

도 1을 참조하면, 본 발명의 볼그리드어레이 패키지는 반도체칩(1)의 센터패드들(2)을 기준으로 좌, 우 양측으로 배열된 리드프레임의 내부리드들(3)이 접착테이프(5)에 의해 반도체칩(1)의 상부면에 접착되고, 내부리드들(3)과 센터패드들(2)이 본딩와이어(7)에 의해 대응하여 전기적으로 연결되고, 상기 각 부들이 몰딩수지(9)에 의해 몰딩되고, 몰딩수지(9)의 관통홀(10) 내의 노출된 내부리드들(3)의 영역 상에 도금층(11)이 형성되고, 도금층(11) 상에 외부 접속단자인 도전성 볼(13)에 전기적으로 연결되도록 구성된다.Referring to FIG. 1, in the ball grid array package of the present invention, the inner leads 3 of the lead frame arranged at both left and right sides of the center pads 2 of the semiconductor chip 1 may have adhesive tapes 5. Bonded to the upper surface of the semiconductor chip 1, the inner leads 3 and the center pads 2 are electrically connected correspondingly by the bonding wires 7, and the respective parts are formed of a molding resin ( 9, a plating layer 11 is formed on a region of the exposed inner leads 3 in the through-hole 10 of the molding resin 9, and an electrically conductive terminal that is an external connection terminal on the plating layer 11 It is configured to be electrically connected to the ball 13.

이와 같이 구성되는 본 발명의 볼그리드어레이 패키지의 제조방법을 도 2a 내지 도 2d를 참조하여 설명하기로 한다.A method of manufacturing the ball grid array package of the present invention configured as described above will be described with reference to FIGS. 2A to 2D.

도 2a를 참조하면, 먼저, 반도체칩(1)의 센터패드들(2)을 기준으로 좌, 우 양측으로 배열된 리드프레임의 내부리드들(3)을 접착테이프(5)에 의해 반도체칩(1)의 상부면에 접착시킨다. 이후, 센터패드들(2)과 내부리드들(3)을 본딩와이어(7)에 의해 대응하여 전기적으로 연결한다. 이어서, 상기 각부들을 몰딩수지(9), 예를 들어 에폭시 몰딩 수지에 의해 몰딩한다.Referring to FIG. 2A, first, internal leads 3 of a lead frame arranged on both left and right sides of the center pads 2 of the semiconductor chip 1 are bonded to each other by an adhesive tape 5. Adhesion to the upper surface of 1). Thereafter, the center pads 2 and the inner leads 3 are correspondingly electrically connected by the bonding wires 7. Subsequently, the parts are molded by a molding resin 9, for example, an epoxy molding resin.

도 2b를 참조하면, 이후, 후술할 도전성 볼들(13)을 안착시키기 위한 내부리드들(3)의 영역을 노출시키기 위해 내부리드들(3)의 지정된 영역 상에 위치한 몰딩수지(9)를 레이저에 의해 제거하여 관통흘들(10)을 형성한다. 이때, 관통홀들(10)은 도전성 볼들(13)의 직경보다 수십 μm 큰 크기로 형성된다.Referring to FIG. 2B, the laser molding resin 9 located on the designated area of the inner leads 3 is then exposed to expose the area of the inner leads 3 for seating the conductive balls 13 to be described later. By removing the through-flow (10) to form. In this case, the through holes 10 are formed to have a size of several tens of micrometers larger than the diameters of the conductive balls 13.

도 2c를 참조하면, 그런 다음, 관통홀들(10) 내의 노출된 내부리드들(3) 상에 전기도금에 의해 도금층(11), 예를 들어 주석층을 형성한다. 이는 관통홀들(10)이 레이저에 의해 형성될 때 발생한 그으름, 몰딩수지(9)의 찌꺼기 등의 이물질을 제거하고, 내부리드들(3)의 산화를 방지하고 내부리드들(3)과 후술할 도전성 볼들(13)의 접착을 용이하게 하기 위함이다.Referring to FIG. 2C, a plating layer 11, for example a tin layer, is then formed by electroplating on the exposed inner leads 3 in the through holes 10. This removes foreign substances such as soot generated when the through holes 10 are formed by the laser, and residues of the molding resin 9, prevents oxidation of the inner leads 3 and prevents the oxidation of the inner leads 3. This is to facilitate the adhesion of the conductive balls 13 to be described later.

도 2d를 참조하면, 계속하여, 관통홀들(10)을 거쳐 도금층들(11) 상에 도전성 볼들(13)을 각각 접합시킨다.Referring to FIG. 2D, the conductive balls 13 are bonded to the plating layers 11 via the through holes 10, respectively.

마지막으로, 도전성 볼들(13)이 접합되고 나면, 몰딩수지(9)의 외측면으로 돌출된 리드프레임의 타이바(도시 안됨)와 외부리드들(도시 안됨)을 절단한다. 따라서, 볼그리드어레이 패키지가 완성된다.Finally, after the conductive balls 13 are bonded, the tie bars (not shown) and the outer leads (not shown) of the lead frame protruding to the outer surface of the molding resin 9 are cut. Thus, the ball grid array package is completed.

한편, 본 발명은 상, 하 균형된 엘오씨(LOC; lead on chip) 패키지를 기준으로 설명하였으나 이에 한정되지 않고 상, 하 불균형 엘오씨 패키지에도 적용 가능하다. 물론, 씨오엘(COL: chip on lead) 패키지에도 적용 가능하다.On the other hand, the present invention has been described on the basis of the upper and lower balanced ELC (LOC) package, but is not limited to this, it is also applicable to the upper and lower unbalanced ELC package. Of course, it is also applicable to chip on lead (COL) packages.

이상에서 살펴본 바와 같이, 본 발명에 의한 볼그리드어레이 패키지는 리드프레임을 이용한 박형 플라스틱 패키지의 몰딩수지에 리드프레임의 내부리드들 노출시키기 위한 관통홀을 형성하고, 노출된 내부리드들 상에 도금층을 형성하고, 도금층 상에 도전성 볼들을 각각 접합시킨다.As described above, the ball grid array package according to the present invention forms through-holes for exposing the inner leads of the lead frame to the molding resin of the thin plastic package using the lead frame, and forms a plating layer on the exposed inner leads. And conductive balls are bonded to each other on the plating layer.

따라서, 본 발명은 기존의 볼그리드어레이 패키지보다 제조원가를 낮추어 제품의 가격 경쟁력을 강화시킬 수 있고, 칩스케일 패키지화를 이룩할 수 있다.Therefore, the present invention can lower the manufacturing cost than the existing ball grid array package to enhance the price competitiveness of the product, it is possible to achieve chip-scale packaging.

한편, 본 발명은 도시된 도면과 상세한 설명에 기술된 내용에 한정하지 않으며 본 발명의 사상을 벗어나지 않는 범위 내에서 다양한 변형이 적용 가능함은 이 분야에 통상의 지식을 가진 자에게는 자명한 사실이다.On the other hand, the present invention is not limited to the contents described in the drawings and detailed description, it is obvious to those skilled in the art that various modifications can be applied without departing from the spirit of the present invention.

Claims (3)

상부면에 센터패드들이 형성된 반도체칩;A semiconductor chip having center pads formed on an upper surface thereof; 상기 반도체칩의 상부면에 접착테이프에 의해 접착되며 상기 반도체칩의 센터패드들을 기준으로 좌, 우 양측으로 배열되는 내부리드들을 갖는 리드프레임;A lead frame bonded to an upper surface of the semiconductor chip by an adhesive tape and having inner leads arranged at left and right sides with respect to the center pads of the semiconductor chip; 상기 내부리드들과 상기 센터패드들을 전기적으로 연결하는 본딩와이어;Bonding wires electrically connecting the inner leads to the center pads; 상기 각 부들을 보호하기 위해 몰딩하며 상기 내부리드들의 소정 영역을 노출시키는 관통홀을 갖는 몰딩수지;A molding resin molded to protect the parts and having a through hole exposing a predetermined area of the inner leads; 상기 내부리드들의 소정 영역에 외부 접속단자로서 접합되는 도전성 볼들을 포함하는 볼그리드어레이 패키지.Ball grid array package including conductive balls bonded to a predetermined region of the inner lead as an external connection terminal. 제 1 항에 있어서, 상기 관통홀은 레이저를 이용하여 상기 몰딩수지에 형성된 것을 특징으로 하는 볼그리드어레이 패키지.The ball grid array package of claim 1, wherein the through hole is formed in the molding resin using a laser. 제 1 항에 있어서, 상기 내부리드들의 소정 영역은 도금층이 형성된 것을 특징으로 하는 볼그리드어레이 패키지.The ball grid array package of claim 1, wherein a predetermined region of the inner leads is formed with a plating layer.
KR1019980021671A 1998-06-11 1998-06-11 Ball grid array pacakge KR20000001410A (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101046251B1 (en) * 2009-05-19 2011-07-04 앰코 테크놀로지 코리아 주식회사 Stacked Semiconductor Packages
CN102874745A (en) * 2011-07-11 2013-01-16 矽品精密工业股份有限公司 Method for manufacturing packaging structure with micro-electromechanical component
KR101356389B1 (en) * 2012-03-07 2014-01-29 에스티에스반도체통신 주식회사 Semiconductor package having conductive terminals on upper surface and method for manufacturing thereof

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101046251B1 (en) * 2009-05-19 2011-07-04 앰코 테크놀로지 코리아 주식회사 Stacked Semiconductor Packages
CN102874745A (en) * 2011-07-11 2013-01-16 矽品精密工业股份有限公司 Method for manufacturing packaging structure with micro-electromechanical component
CN102874745B (en) * 2011-07-11 2015-05-20 矽品精密工业股份有限公司 Method for manufacturing packaging structure with micro-electromechanical component
KR101356389B1 (en) * 2012-03-07 2014-01-29 에스티에스반도체통신 주식회사 Semiconductor package having conductive terminals on upper surface and method for manufacturing thereof

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