KR20030047688A - Semiconductor package - Google Patents

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Publication number
KR20030047688A
KR20030047688A KR1020020045723A KR20020045723A KR20030047688A KR 20030047688 A KR20030047688 A KR 20030047688A KR 1020020045723 A KR1020020045723 A KR 1020020045723A KR 20020045723 A KR20020045723 A KR 20020045723A KR 20030047688 A KR20030047688 A KR 20030047688A
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KR
South Korea
Prior art keywords
semiconductor chip
die bonding
semiconductor
bonding paste
mounting
Prior art date
Application number
KR1020020045723A
Other languages
Korean (ko)
Inventor
고스다메구미
Original Assignee
미쓰비시덴키 가부시키가이샤
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Publication date
Application filed by 미쓰비시덴키 가부시키가이샤 filed Critical 미쓰비시덴키 가부시키가이샤
Publication of KR20030047688A publication Critical patent/KR20030047688A/en

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    • H—ELECTRICITY
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Abstract

PURPOSE: To obtain a semiconductor package in which sufficient bonding strength is attained while preventing a die bond material from projecting. CONSTITUTION: A plurality of recesses 11a are formed in one side of a semiconductor chip 11 and a die pad part 14 for mounting the semiconductor chip fixedly is provided in a package 12. The die pad part 14 has a part 14a for mounting the semiconductor chip, and a part 14c on the periphery of the mounting part provided with a level difference 14b wherein the semiconductor chip 11 is bonded fixedly to the mounting part 14a on the recess 11a side. Furthermore, a groove part 141 may be formed at the mounting part 14a.

Description

반도체 패키지{SEMICONDUCTOR PACKAGE}Semiconductor Package {SEMICONDUCTOR PACKAGE}

본 발명은 내부에 반도체칩을 접착 고정하여 수납하는 반도체 패키지에 관한 것으로, 특히, 반도체칩의 접착면이나 다이패드부에 잉여 접착제(다이 본딩 페이스트)가 배출될 곳이 되는 오목부나 단차를 마련한 반도체 패키지에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package in which a semiconductor chip is fixed and accommodated therein, and more particularly, a semiconductor having recesses and steps for providing excess adhesive (die bonding paste) to the adhesive surface or die pad portion of the semiconductor chip. It's about packages.

최근의 반도체칩의 집적도 향상에 따라, 반도체칩의 입출력 핀이 증가하고, 그 결과, 반도체칩과 패키지를 연결하는 금선도 미세화(파인 피치화)되는 경향이 있다. 이 때문에, 반도체칩의 표면에 이물질이 존재하면, 반도체 패키지의 생산성이 저하할 뿐만 아니라, 그 품질도 저하해 버린다.With the recent improvement in the degree of integration of semiconductor chips, the input / output pins of the semiconductor chips increase, and as a result, the gold wire connecting the semiconductor chip and the package tends to become fine (fine pitch). For this reason, when foreign matter exists on the surface of a semiconductor chip, not only productivity of a semiconductor package will fall but its quality will also fall.

반도체 패키지에서는, 내부의 다이패드부에 반도체칩이 접착 고정되어 있다. 예컨대, 반도체칩을 은 페이스트 등의 다이 본딩 페이스트로 접착 고정할 때, 패키지 내의 다이패드부에 다이 본딩 페이스트를 도포한 후, 소정의 하중을 부가하면서, 반도체칩을 다이패드부에 접착 고정하고 있다.In a semiconductor package, a semiconductor chip is adhesively fixed to an internal die pad portion. For example, when adhesively fixing a semiconductor chip with a die bonding paste, such as silver paste, after apply | coating a die bonding paste to the die pad part in a package, the semiconductor chip is adhesively fixed to a die pad part, applying a predetermined load. .

그런데, 상술한 반도체칩의 가압 공정 시에, 다이 본딩 페이스트가 반도체칩의 표면 등으로 누출되어 버리는 일이 있었다.By the way, the die bonding paste may leak to the surface of a semiconductor chip, etc. at the time of the pressurization process of the semiconductor chip mentioned above.

또한, 최근에는 납을 포함하는 땜납재를 사용하지 않고, 납을 대체하는 융점이 높은 금속을 포함하는 땜납재를 사용하는 경향이 있다. 그 결과, 전자 부품의 실장 시에 있어서의 땜납 리플로우 온도도 고온화하고 있다.Also, in recent years, there is a tendency to use a solder material containing a metal having a high melting point to replace the lead, without using a solder material containing lead. As a result, the solder reflow temperature at the time of mounting an electronic component also becomes high temperature.

따라서, 반도체 패키지를 전자 기판에 실장할 때, 땜납 리플로우에 있어서 열 스트레스가 걸리기 때문에, 반도체칩과 다이패드부의 접착도 해당 열 스트레스에 견딜 수 있는 강도가 필요하게 된다. 이 때문에, 충분한 접착 강도가 얻어질 수 있을 정도로, 다이 본딩 페이스트의 사용량도 결정되어 있다. 따라서, 상기 누출을 억제하기 위해서, 다이 본딩 페이스트의 사용량을 감소시킬 수는 없다.Therefore, when mounting a semiconductor package on an electronic board | substrate, since thermal stress is applied in solder reflow, the adhesion | attachment of a semiconductor chip and a die pad part also requires the strength which can endure the said thermal stress. For this reason, the usage-amount of die bonding paste is also determined so that sufficient adhesive strength can be obtained. Therefore, in order to suppress the leakage, it is not possible to reduce the usage amount of the die bonding paste.

상기 불량을 해소하는 반도체 패키지로서, 예컨대, 일본 특허 공개 평성 제10-163407호 공보에 개시된 것이 있다(이하, 종래예라고 함). 이 종래예에서는, 반도체칩이 접착 고정되는 다이패드부에, 반도체칩이 탑재되는 탑재면인 상단부와, 탑재면의 주변에 단차를 마련한 하단부를 마련하고, 이 하단부에 요철을 형성하고 있다. 이러한 다이패드부를 이용하는 것에 따라, 상기 단차에 의해서 다이 본딩 페이스트의 넓기를 시인할 수 있고, 요철 형상에 따라서 다이 본딩 페이스트의 누출을 억제할 수 있다.As a semiconductor package which eliminates the said defect, there exist some which were disclosed by Unexamined-Japanese-Patent No. 10-163407, for example. In this conventional example, the upper end part which is a mounting surface on which a semiconductor chip is mounted, and the lower end part which provided the step | step with respect to the mounting surface are provided in the die pad part by which the semiconductor chip is adhesively fixed, and the uneven part is formed in this lower end part. By using such a die pad part, the width | variety of the die bonding paste can be visually recognized by the said step | step, and the leak of die bonding paste can be suppressed according to the uneven shape.

종래의 반도체 패키지는 이상과 같이 구성되어 있기 때문에, 하단부에서의 다이 본딩 페이스트(도전성 접착제)의 누출을 억제할 수는 있지만, 상단부와 반도체칩의 접착 강도를 향상시키기에는 한계가 있다는 문제가 있었다.Since the conventional semiconductor package is configured as described above, leakage of the die bonding paste (conductive adhesive) at the lower end can be suppressed, but there is a problem that there is a limit in improving the adhesive strength between the upper end and the semiconductor chip.

상기 과제를 구체적으로 설명하면, 종래의 반도체 패키지에서는, 상단부와 반도체칩의 접착 강도를 향상시키는 구성을 갖고 있지 않기 때문에, 접착 강도를 향상시키기 위해서는 다이 본딩 페이스트의 사용량을 증가시킬 필요가 있다. 이것에 의해, 하단부에서의 다이 본딩 페이스트의 누출을 억제할 수는 있지만, 상단부에서는 다이 본딩 페이스트의 누출을 억제할 수 없어, 반도체칩의 측면 및/또는 표면으로 누출되는 경우가 있었다. 이 결과, 예컨대 금선의 배선에 지장을 초래하고, 나아가서는 반도체 패키지의 품질이 저하될 뿐만 아니라, 생산성도 저하해 버리게 된다.Specifically, the above-mentioned problem is explained. In the conventional semiconductor package, since the adhesive strength between the upper end portion and the semiconductor chip is not improved, it is necessary to increase the amount of die bonding paste used in order to improve the adhesive strength. As a result, leakage of the die bonding paste at the lower end portion can be suppressed, but leakage of the die bonding paste cannot be suppressed at the upper end portion, which may leak to the side and / or surface of the semiconductor chip. As a result, for example, the wiring of the gold wire is disturbed, and furthermore, not only the quality of the semiconductor package is lowered, but also the productivity is lowered.

또한, 상술한 바와 같이 누출을 방지하기 위해서, 다이 본딩 페이스트의 양을 적게 하면, 이번에는 충분한 접착 강도가 얻어지지 않게 되어 버린다.Moreover, in order to prevent leakage as mentioned above, when the amount of die bonding paste is reduced, sufficient adhesive strength will no longer be obtained this time.

어떻게 하여도, 종래의 반도체 패키지에서는, 다이 본딩 페이스트의 양을 많게 하면, 다이 본딩 페이스트가 반도체칩의 측면 및/또는 표면으로 누출되는 불량이 발생한다. 한편, 다이 본딩 페이스트의 양을 적게 하면, 충분한 접착 강도가 얻어지지 않는 경우도 있다.In any case, in a conventional semiconductor package, when the amount of die bonding paste is increased, a defect occurs in which the die bonding paste leaks to the side and / or surface of the semiconductor chip. On the other hand, when the amount of die bonding paste is reduced, sufficient adhesive strength may not be obtained.

본 발명은 상기한 바와 같은 과제를 해결하기 위해서 이루어진 것으로, 반도체칩과 다이패드부의 접착 강도를 향상시키고, 또한 다이 본딩 페이스트의 누출을 억제할 수 있는 반도체 패키지를 얻는 것을 목적으로 한다.This invention is made | formed in order to solve the above subjects, and an object of this invention is to obtain the semiconductor package which can improve the adhesive strength of a semiconductor chip and a die pad part, and can suppress the leakage of die bonding paste.

도 1은 본 발명의 실시예 1에 따른 반도체 패키지를 나타내는 단면도,1 is a cross-sectional view showing a semiconductor package according to Embodiment 1 of the present invention;

도 2는 실시예 1에 따른 반도체 패키지에 있어서 다이 본딩 페이스트의 사용량이 적은 경우를 나타내는 단면도,2 is a cross-sectional view showing a case where the amount of die bonding paste used in the semiconductor package according to Example 1 is small;

도 3은 본 발명의 실시예 2에 따른 반도체 패키지를 나타내는 단면도,3 is a cross-sectional view showing a semiconductor package according to a second embodiment of the present invention;

도 4는 본 발명의 실시예 3에 따른 반도체 패키지를 나타내는 단면도,4 is a cross-sectional view showing a semiconductor package according to Embodiment 3 of the present invention;

도 5는 본 발명의 실시예 4에 따른 반도체 패키지를 나타내는 단면도,5 is a sectional view showing a semiconductor package according to the fourth embodiment of the present invention;

도 6은 본 발명에 따른 반도체 패키지의 다른 예를 나타내는 단면도,6 is a cross-sectional view showing another example of a semiconductor package according to the present invention;

도 7은 본 발명에 따른 반도체 패키지의 또 다른 예를 나타내는 단면도,7 is a cross-sectional view showing another example of a semiconductor package according to the present invention;

도 8은 본 발명에 따른 반도체 패키지의 또 다른 예를 나타내는 단면도,8 is a cross-sectional view showing still another example of a semiconductor package according to the present invention;

도 9는 본 발명에 따른 반도체 패키지의 또 다른 예를 나타내는 단면도,9 is a cross-sectional view showing still another example of a semiconductor package according to the present invention;

도 10은 본 발명에 따른 반도체 패키지의 또 다른 예를 나타내는 단면도이다.10 is a cross-sectional view showing still another example of a semiconductor package according to the present invention.

도면의 주요 부분에 대한 부호의 설명Explanation of symbols for the main parts of the drawings

11 : 반도체칩11a, 11b, 11c : 오목부11 semiconductor chip 11a, 11b, 11c recessed portion

12 : 패키지(패키지 본체)12a : 베이스부12: package (package body) 12a: base portion

12b : 덮개부12c : 입출력 핀12b: cover portion 12c: input and output pins

13 : 반도체 패키지14 : 다이패드부13 semiconductor package 14 die pad portion

14a, 18a, 20a : 탑재부14b, 14d, 18b, 20b : 단차14a, 18a, 20a: mounting portion 14b, 14d, 18b, 20b: step

14c, 18c, 20c : 주변부(하단부)15 : 접속면부14c, 18c, 20c: Peripheral part (lower end) 15: Connection surface part

16 : 금선17 : 다이 본딩 페이스트16: gold wire 17: die bonding paste

18 : 프레임19 : 몰딩 수지18 frame 19 molding resin

20 : 리드 프레임141 : 홈부20: lead frame 141: groove portion

142, 143 : 탑재 부분142, 143: mounting portion

본 발명에 따른 반도체 패키지는, 반도체칩을 수납하는 패키지 본체와, 패키지 본체 내에 마련되어, 반도체칩을 접착 고정하는 다이패드부와, 반도체칩의 접착면에 형성한 오목부를 구비하는 것이다.A semiconductor package according to the present invention includes a package body for accommodating a semiconductor chip, a die pad portion provided in the package body, for adhering and fixing the semiconductor chip, and a recess formed on the adhesive surface of the semiconductor chip.

본 발명에 따른 반도체 패키지는 반도체칩의 접착면에 복수의 오목부를 형성한 것이다.In the semiconductor package according to the present invention, a plurality of recesses are formed on an adhesive surface of a semiconductor chip.

본 발명에 따른 반도체 패키지는, 다이패드부가, 반도체칩이 탑재되는 탑재부와, 해당 탑재부의 주변부에 단차를 마련하여 이루어지는 하단부를 구비하는 것이다.The semiconductor package according to the present invention includes a mounting portion on which the die pad portion is mounted, and a lower portion formed by providing a step on the periphery of the mounting portion.

본 발명의 상기 및 그 밖의 목적, 특징, 국면 및 이익 등은 첨부 도면을 참조로 하여 설명하는 이하의 상세한 실시예로부터 더욱 명백해질 것이다.The above and other objects, features, aspects, advantages, and the like of the present invention will become more apparent from the following detailed embodiments described with reference to the accompanying drawings.

이하, 본 발명의 실시의 일 형태를 설명한다.EMBODIMENT OF THE INVENTION Hereinafter, one Embodiment of this invention is described.

(실시예 1)(Example 1)

도 1은 본 발명의 실시예 1에 따른 반도체 패키지를 나타내는 단면도이다. 이 도면에서는 다이 본딩 페이스트의 사용량이 많은 경우를 나타내고 있다. 도면에 있어서, 참조 부호 11은 반도체칩, 참조 부호 12는 패키지(패키지 본체)이며, 반도체칩(11)이 패키지(12) 내에 수납되어 반도체 패키지(13)가 된다. 또한, 패키지(12)는, 베이스부(12a)와 덮개부(12b)를 갖고 있다. 이 베이스부(12a)의 하면에는 복수의 입출력 핀(12c)이 마련되어 있고, 중앙부에는 다이패드부(14)가 형성되어 있다. 다이패드부(14)는 반도체칩(11)이 탑재되는 탑재부(14a)와, 이 탑재부(14a)의 주위에 단차(14b)를 마련하여 이루어지는 주변부(하단부)(14c)를 갖고 있다.1 is a cross-sectional view illustrating a semiconductor package according to Embodiment 1 of the present invention. In this figure, the case where the usage-amount of die bonding paste is large is shown. In the figure, reference numeral 11 denotes a semiconductor chip, reference numeral 12 denotes a package (package main body), and the semiconductor chip 11 is housed in the package 12 to form a semiconductor package 13. Moreover, the package 12 has the base part 12a and the cover part 12b. A plurality of input / output pins 12c are provided on the bottom surface of the base portion 12a, and a die pad portion 14 is formed in the center portion. The die pad part 14 has a mounting part 14a on which the semiconductor chip 11 is mounted, and a peripheral part (lower end part) 14c formed by providing a step 14b around the mounting part 14a.

주변부(14c)의 외주 측에는, 위쪽으로 상승하는 단차(14d)가 마련되고, 이 단차(14d)를 거쳐서 주변부(14c)에 접속면부(15)가 연속하고 있다. 또한, 접속면부(15)에는 금선(16)이 접속된다. 이것에 의해서, 금선(16)은 입출력 핀(12c) 중 어느 하나에 접속되게 된다. 또한, 반도체칩(11)의 접착면에는 복수의 오목부(11a)가 형성되어 있고, 도시한 바와 같이 파상의 단면을 갖고 있다.On the outer circumferential side of the peripheral portion 14c, a step 14d that rises upward is provided, and the connection surface portion 15 continues to the peripheral portion 14c via the step 14d. In addition, a gold wire 16 is connected to the connection surface portion 15. As a result, the gold wire 16 is connected to any one of the input / output pins 12c. Moreover, the some recessed part 11a is formed in the adhesive surface of the semiconductor chip 11, and has a wavy cross section as shown.

다음에 개요에 대하여 설명한다.Next, the outline will be described.

반도체 패키지(13)를 제조할 때에는, 탑재부(14a)에 다이본딩 페이스트(17)가 도포된다. 그 후, 반도체칩(11)의 접착면, 즉, 오목부(11a)를 아래쪽으로 향하게 해서, 소정의 하중으로 반도체칩(11)을 탑재부(14a)에 가압함으로써, 반도체칩(11)을 탑재부(14a)에 접착 고정한다. 다음에, 반도체칩(11)과 금선(16)을 접속함과 동시에 금선(16)을 접속면부(15)에 접속한다. 그리고, 베이스부(12a)에 덮개부(12b)를 씌워 고정하여, 반도체 패키지(13)로 한다.When manufacturing the semiconductor package 13, the die bonding paste 17 is apply | coated to the mounting part 14a. Then, the semiconductor chip 11 is mounted by pressing the bonding surface of the semiconductor chip 11, that is, the recess 11a downward, and pressing the semiconductor chip 11 to the mounting portion 14a with a predetermined load. Adhesive fixing to 14a. Next, the semiconductor chip 11 and the gold wire 16 are connected, and the gold wire 16 is connected to the connection surface 15. Then, the cover portion 12b is fixed to the base portion 12a to form the semiconductor package 13.

도 1에 도시하는 바와 같이, 다이 본딩 페이스트(17)의 사용량이 많은 경우,반도체칩(11)의 접합면에 형성한 오목부(11a)에 다이 본딩 페이스트(17)의 잉여분이 유도되어, 반도체칩(11)의 접합면 전체로 넓게 퍼지게 된다. 즉, 오목부(11a)가 마치 다이 본딩 페이스트(17)의 안내부로서 작용하게 된다. 또한, 탑재부(14a)에는 단차(14b)를 거쳐서 주변부(14c)가 연속하고 있기 때문에, 잉여분은 단차(14b)로부터 주변부(14c)로 떨어진다. 이 결과, 다이 본딩 페이스트(17)의 잉여분이 반도체칩(11)의 측면 및/또는 표면으로 누출되는 일이 없게 된다.As shown in FIG. 1, when the usage amount of the die bonding paste 17 is large, the surplus of the die bonding paste 17 is guide | induced to the recessed part 11a formed in the bonding surface of the semiconductor chip 11, and a semiconductor It spreads widely throughout the bonding surface of the chip 11. That is, the concave portion 11a acts as a guide portion of the die bonding paste 17. In addition, since the peripheral portion 14c continues to the mounting portion 14a via the step 14b, the surplus falls from the step 14b to the peripheral portion 14c. As a result, the excess of the die bonding paste 17 does not leak to the side surface and / or the surface of the semiconductor chip 11.

또한, 반도체칩과 탑재부(14a)의 접착 강도는, 다이 본딩 페이스트(17)의 양뿐만 아니라, 접착 면적에도 의존하고 있다. 이것을 근거로 하면, 상술한 바와 같이, 반도체칩(11)의 접합면에 오목부(11a)를 형성함으로써, 다이 본딩 페이스트(17)와의 접착 면적이 넓게 되기 때문에, 접착 강도의 향상을 도모할 수 있다.The adhesion strength between the semiconductor chip and the mounting portion 14a depends not only on the amount of the die bonding paste 17 but also on the adhesion area. On the basis of this, as described above, by forming the concave portion 11a on the bonding surface of the semiconductor chip 11, the bonding area with the die bonding paste 17 is increased, so that the adhesive strength can be improved. have.

도 2는 실시예 1에 따른 반도체 패키지에 있어서 다이 본딩 페이스트의 사용량이 적은 경우를 나타내는 단면도이다. 상술한 바와 같이, 종래에는, 다이 본딩 페이스트의 사용량이 적은 경우, 접착 강도를 향상시킬 수는 없었다. 한편, 본 발명에서는, 반도체칩(11)의 접합면에 오목부(11a)를 형성하여 실질적으로 접합면의 면적을 증가시키고 있다. 즉, 다이 본딩 페이스트(17)의 사용량이 적어도, 접착 강도를 향상시킬 수 있다. 이 결과, 다이 본딩 페이스트(17)의 사용량을 감소시킬 수도 있다.2 is a cross-sectional view showing a case where the amount of die bonding paste used in the semiconductor package according to the first embodiment is small. As described above, in the past, when the amount of the die bonding paste used is small, the adhesive strength could not be improved. On the other hand, in this invention, the recessed part 11a is formed in the joining surface of the semiconductor chip 11, and the area of a joining surface is substantially increased. That is, the usage-amount of the die bonding paste 17 can improve an adhesive strength at least. As a result, the usage amount of the die bonding paste 17 can be reduced.

이상과 같이, 본 실시예 1에 따르면, 다이패드부(14)가 탑재부(14a)와, 이 탑재부(14a)의 주위에 단차(14b)를 마련하여 이루어지는 주변부(14c)를 갖고, 반도체칩(11)의 접합면에 복수의 오목부(11a)를 형성했기 때문에, 다이 본딩 페이스트(17)의 누출을 방지할 수 있을 뿐만 아니라, 접착 강도를 향상시킬 수 있다.As described above, according to the first embodiment, the die pad portion 14 includes a mounting portion 14a and a peripheral portion 14c formed by providing a step 14b around the mounting portion 14a. Since the recessed part 11a was formed in the joining surface of 11), the leak of the die bonding paste 17 can be prevented and adhesive strength can be improved.

(실시예 2)(Example 2)

도 3은 본 발명의 실시예 2에 따른 반도체 패키지를 나타내는 단면도이다. 도면에 있어서, 참조 부호 11b는 반도체칩(11)의 접합면에 형성한 복수의 오목부이고, 직사각형 형상의 단면을 구성한다. 또, 도 1과 동일 구성 요소에는 동일 부호를 부여하여 중복하는 설명을 생략한다.3 is a cross-sectional view illustrating a semiconductor package according to a second exemplary embodiment of the present invention. In the figure, reference numeral 11b is a plurality of recesses formed on the bonding surface of the semiconductor chip 11, and constitutes a rectangular cross section. In addition, the description which attaches | subjects the same code | symbol to the same component as FIG. 1, and overlaps is abbreviate | omitted.

다음에 개요에 대하여 설명한다.Next, the outline will be described.

도 3에 나타내는 바와 같은 오목부(11b)를 마련하여도, 다이 본딩 페이스트(17)의 양이 많은 경우에는, 오목부(11b)에 의해서 다이 본딩 페이스트(17)의 잉여분이 유도되어, 반도체칩(11)의 접합면 전체로 넓게 퍼지게 된다. 또한, 탑재부(14a)에는 단차(14b)를 거쳐 주변부(14c)가 연속하고 있기 때문에, 잉여분은 단차(14b)에서 주변부(14c)로 떨어진다. 그 결과, 다이 본딩 페이스트(17)의 잉여분이 반도체칩(11)의 측면 및/또는 표면으로 누출되지 않게 된다. 또한, 다이 본딩 페이스트(17)의 양이 적은 경우에도, 오목부(11b)에 의해서 접합 면적이 증가하고 있기 때문에, 충분한 접착 강도를 얻을 수 있다.Even if the recessed portion 11b as shown in FIG. 3 is provided, when the amount of the die bonding paste 17 is large, the excess portion of the die bonding paste 17 is guided by the recessed portion 11b, thereby providing a semiconductor chip. It spreads all over the joining surface of (11). In addition, since the peripheral portion 14c is continuous to the mounting portion 14a via the step 14b, the surplus falls from the step 14b to the peripheral portion 14c. As a result, the excess of the die bonding paste 17 does not leak to the side and / or the surface of the semiconductor chip 11. In addition, even when the amount of the die bonding paste 17 is small, since the joining area is increased by the recesses 11b, sufficient adhesive strength can be obtained.

이상과 같이, 본 실시예 2에 따르면, 다이패드부(14)가 탑재부(14a)와, 이 탑재부(14a)의 주위에 단차(14b)를 마련하여 이루어지는 주변부(14c)를 갖고, 반도체칩(11)의 접합면에 복수의 오목부(11b)를 형성했으므로, 다이 본딩 페이스트(17)의 누출을 방지할 수 있을 뿐만 아니라, 접착 강도를 향상시킬 수 있다.As described above, according to the second embodiment, the die pad portion 14 includes a mounting portion 14a and a peripheral portion 14c formed by providing a step 14b around the mounting portion 14a. Since the recessed part 11b was formed in the joining surface of 11), the leak of the die bonding paste 17 can be prevented and adhesive strength can be improved.

(실시예 3)(Example 3)

도 4는 본 발명의 실시예 3에 따른 반도체 패키지를 나타내는 단면도이다. 도면에 있어서, 참조 부호 11c는 반도체칩(11)의 접합면에 형성한 홈부(오목부)이다. 또한, 홈부(11c)의 폭은, 반도체칩(11)의 폭보다도 좁으면 좋다. 또, 도 1과 동일 구성 요소에는 동일 부호를 부여하여 중복하는 설명을 생략한다.4 is a cross-sectional view illustrating a semiconductor package according to a third exemplary embodiment of the present invention. In the figure, reference numeral 11c denotes a groove portion (concave portion) formed in the bonding surface of the semiconductor chip 11. In addition, the width of the groove 11c may be smaller than the width of the semiconductor chip 11. In addition, the same code | symbol is attached | subjected to the same component as FIG.

다음에 개요에 대하여 설명한다.Next, the outline will be described.

도 4에 나타내는 바와 같은 홈부(11c)를 마련하여도, 다이 본딩 페이스트(17)의 사용량이 많은 경우에는, 홈부(11c)에 의해서 다이 본딩 페이스트(17)의 잉여분이 유도되고, 또한 탑재부(14a)에는 단차(14b)를 거쳐서 주변부(14c)가 연속하고 있기 때문에, 잉여분은 단차(14b)에서 주변부(14c)로 떨어진다. 그 결과, 다이 본딩 페이스트(17)의 잉여분이 반도체칩(11)의 측면 및/또는 표면으로 누출되는 경우가 없게 된다. 또한, 다이 본딩 페이스트(17)의 사용량이 적은 경우에도, 오목부(11c)에 의해서 접합 면적이 증가하기 때문에, 충분한 접착 강도를 얻을 수 있다.Even when the groove portion 11c as shown in FIG. 4 is provided, when the amount of the use of the die bonding paste 17 is large, the excess portion of the die bonding paste 17 is guided by the groove portion 11c, and the mounting portion 14a is provided. Since the periphery 14c is continuous through the step 14b, the surplus falls from the step 14b to the periphery 14c. As a result, the excess of the die bonding paste 17 does not leak to the side and / or the surface of the semiconductor chip 11. In addition, even when the amount of use of the die bonding paste 17 is small, the bonding area is increased by the recesses 11c, so that sufficient adhesive strength can be obtained.

이상과 같이, 본 실시예 3에 따르면, 다이패드부(14)가 탑재부(14a)와, 이 탑재부(14a)의 주위에 단차(14b)를 마련하여 이루어지는 주변부(14c)를 갖고, 반도체칩(11)의 접합면에 홈부(11c)를 형성했기 때문에, 다이 본딩 페이스트(17)의 누출을 방지할 수 있을 뿐만 아니라, 접착 강도를 향상시킬 수 있다.As described above, according to the third embodiment, the die pad portion 14 includes a mounting portion 14a and a peripheral portion 14c formed by providing a step 14b around the mounting portion 14a. Since the groove part 11c is formed in the joining surface of 11), the leak of the die bonding paste 17 can be prevented and adhesive strength can be improved.

(실시예 4)(Example 4)

도 5는 본 발명의 실시예 4에 따른 반도체 패키지를 나타내는 단면도이다. 도면에 있어, 참조 부호 141은 탑재부(14a)의 중앙부에 형성한 홈부, 참조 부호 142, 143은 홈부(141)에 의해서 분할된 탑재부(14a)의 탑재 부분이다. 또한, 홈부(141)의 폭은, 반도체칩(11)의 폭보다도 좁으면 좋다. 또, 도 1과 동일 구성 요소에는 동일 부호를 부여하여 중복하는 설명을 생략한다.5 is a cross-sectional view illustrating a semiconductor package according to a fourth exemplary embodiment of the present invention. In the figure, reference numeral 141 denotes a groove formed in the center portion of the mounting portion 14a, and reference numerals 142 and 143 denote mounting portions of the mounting portion 14a divided by the groove portion 141. In addition, the width of the groove portion 141 may be smaller than the width of the semiconductor chip 11. In addition, the description which attaches | subjects the same code | symbol to the same component as FIG. 1, and overlaps is abbreviate | omitted.

다음에 개요에 대하여 설명한다.Next, the outline will be described.

다이 본딩 페이스트(17)의 사용량이 많은 경우에는, 오목부(11a)에 의해서 다이 본딩 페이스트(17)의 잉여분이 유도되어, 반도체칩(11)의 접합면 전체로 넓게 퍼지게 된다. 또한, 탑재부(14a)에 홈부(141)가 마련되어 있기 때문에, 잉여분이 이 홈부(141)에도 남게 된다. 또한, 탑재부(14a)에는 단차(14b)를 거쳐서 주변부(14c)가 연속하고 있기 때문에, 잉여분은 단차(14b)에서 주변부(14c)로 떨어지게 된다. 그 결과, 다이 본딩 페이스트(17)의 잉여분이 반도체칩(11)의 측면 및/또는 표면으로 누출되지 않게 된다. 또한, 다이 본딩 페이스트(17)의 사용량이 적은 경우에도, 오목부(11a)에 의해서 접합 면적이 증가하고 있기 때문에, 충분한 접착 강도를 얻을 수 있다.When the usage amount of the die bonding paste 17 is large, the surplus of the die bonding paste 17 is guided by the concave portion 11a, so that it spreads widely throughout the bonding surface of the semiconductor chip 11. Moreover, since the groove part 141 is provided in the mounting part 14a, the surplus will remain in this groove part 141 as well. In addition, since the peripheral portion 14c is continuous to the mounting portion 14a via the step 14b, the surplus drops from the step 14b to the peripheral portion 14c. As a result, the excess of the die bonding paste 17 does not leak to the side and / or the surface of the semiconductor chip 11. In addition, even when the amount of use of the die bonding paste 17 is small, since the bonding area is increased by the recesses 11a, sufficient adhesive strength can be obtained.

이상과 같이, 본 실시예 4에 따르면, 다이패드부(14)가 탑재부(14a)와, 이 탑재부(14a) 주위에 단차(14b)를 마련하여 이루어지는 주변부(14c)와,다이패드부(14)의 탑재부(14a)에 형성한 홈부(141)와, 반도체칩(11)의 접합면에 복수의 오목부(11a)를 형성했으므로, 다이 본딩 페이스트(17)의 누출을 방지할 수 있을 뿐만 아니라, 접착 강도를 향상시킬 수 있다.As described above, according to the fourth embodiment, the die pad portion 14 includes a mounting portion 14a, a peripheral portion 14c formed by providing a step 14b around the mounting portion 14a, and a die pad portion 14. Since the plurality of recesses 11a are formed on the joining surface of the semiconductor chip 11 and the groove portion 141 formed in the mounting portion 14a of the (), it is not only possible to prevent leakage of the die bonding paste 17. , The adhesive strength can be improved.

또, 도 6에 도시하는 바와 같이, 반도체칩(11)의 접합면에 복수의 오목부(11b)를 형성하고, 탑재부(14a)에 홈부(141)를 형성하여도 좋고, 도 7에 도시하는 바와 같이, 반도체칩(11)의 접합면에 홈부(11c)를 형성하고, 탑재부(14a)에 홈부(141)를 형성하여도 좋다. 또한, 도 8에 도시하는 바와 같이, 외부 입출력에 사용하는 단자로서, 침 형상이 아닌 공 형상의 입출력 핀(12d)을 갖는 패키지에 적용하여도 관계없다.As shown in FIG. 6, a plurality of recesses 11b may be formed on the joining surface of the semiconductor chip 11, and grooves 141 may be formed in the mounting portion 14a, as shown in FIG. 7. As described above, the groove 11c may be formed on the joining surface of the semiconductor chip 11, and the groove 141 may be formed in the mounting portion 14a. In addition, as shown in FIG. 8, as a terminal used for external input / output, you may apply to the package which has the ball-shaped input / output pin 12d rather than needle shape.

또한, 본 발명은 몰딩 수지로 프레임에 탑재한 반도체칩을 경화시키는 타입의 반도체 패키지에 적용할 수도 있다. 도 9는 이 타입의 반도체 패키지를 도시하는 도면이고, 본 발명의 효과를 최대한 얻기 위해서, 프레임(18)에도, 반도체칩(11)을 탑재하는 탑재부(18a)와, 이 탑재부(18a)의 주위에 단차(18b)를 마련하여 이루어지는 주변부(하단부)(18c)를 마련하여 둔다. 이 프레임(18)에, 상기 실시예와 마찬가지로 해서, 반도체칩(11)을 실장하고, 몰딩 수지(19)로 경화시킴으로써 상기와 같은 효과를 얻을 수 있다. 또한, 도 10에 도시하는 바와 같이, 입출력 핀(12c, 12d)을 필요로 하지 않는 리드 프레임 타입의 반도체 패키지에 적용하여도 좋다. 예컨대, 표면 실장 타입의 QFP(Quad Flat Package) 또는 SOP(Small Outline Package) 등의 리드 형상에도 적용할 수 있다. 이 경우, 리드 프레임(20)에도, 반도체칩(11)을 탑재하는 탑재부(20a)와, 이 탑재부(20a)의 주위에단차(20b)를 마련하여 이루어지는 주변부(하단부)(20c)를 마련하여 놓음으로써 본 발명의 효과를 최대한 얻을 수 있다.The present invention can also be applied to a semiconductor package of a type for curing a semiconductor chip mounted on a frame with a molding resin. FIG. 9 is a diagram showing this type of semiconductor package. In order to maximize the effect of the present invention, the mounting portion 18a for mounting the semiconductor chip 11 on the frame 18 and the circumference of the mounting portion 18a are shown in FIG. The peripheral part (lower end part) 18c formed by providing the step | step 18b in this is provided. The same effect as described above can be obtained by mounting the semiconductor chip 11 on the frame 18 and curing it with the molding resin 19 in the same manner as in the above embodiment. In addition, as shown in FIG. 10, you may apply to the lead frame type semiconductor package which does not require the input / output pins 12c and 12d. For example, the present invention can also be applied to lead shapes such as a surface mount type quad flat package (QFP) or small outline package (SOP). In this case, the lead frame 20 is also provided with a mounting portion 20a for mounting the semiconductor chip 11 and a peripheral portion (lower end portion) 20c formed by providing a step 20b around the mounting portion 20a. By placing it, the effect of the present invention can be obtained as much as possible.

이상과 같이, 본 발명에 따르면, 반도체칩을 수납하는 패키지 본체마다, 패키지 본체 내에 마련되어, 반도체칩을 접착 고정하는 다이패드부와, 반도체칩의 접착면에 형성한 오목부를 구비하므로, 다이 본딩 페이스트의 누출을 방지할 수 있을 뿐만 아니라 충분한 접착 강도를 얻을 수 있다고 하는 효과가 있다.As described above, according to the present invention, a die bonding paste is provided for each package main body that houses the semiconductor chip, and includes a die pad portion provided in the package main body to fix and fix the semiconductor chip, and a concave portion formed on the adhesive surface of the semiconductor chip. It is effective in that not only can leakage be prevented but also sufficient adhesive strength can be obtained.

본 발명에 따르면, 반도체칩의 접착면에 복수의 오목부를 형성했으므로, 접착 강도를 더욱 향상시킬 수 있다고 하는 효과가 있다.According to the present invention, since a plurality of recesses are formed on the bonding surface of the semiconductor chip, the adhesive strength can be further improved.

본 발명에 따르면, 다이패드부가, 반도체칩이 탑재되는 탑재부와, 해당 탑재부의 주변부에 단차를 마련하여 이루어지는 하단부를 구비하므로, 다이 본딩 페이스트의 누출을 방지할 수 있다고 하는 효과가 있다.According to the present invention, since the die pad portion includes a mounting portion on which the semiconductor chip is mounted, and a lower end portion formed by providing a step in the periphery of the mounting portion, the die bonding paste can be prevented from leaking.

이상 본 발명자에 의해서 이루어진 발명을 상기 실시예에 따라 구체적으로 설명하였지만, 본 발명은 상기 실시예에 한정되는 것이 아니고, 그 요지를 이탈하지 않는 범위에서 여러 가지로 변경 가능한 것은 물론이다.As mentioned above, although the invention made by this inventor was demonstrated concretely according to the said Example, this invention is not limited to the said Example and can be variously changed in the range which does not deviate from the summary.

Claims (3)

반도체칩을 수납하는 패키지 본체와,A package body for storing semiconductor chips, 상기 패키지 본체 내에 마련되고, 상기 반도체칩을 접착 고정하는 다이패드부와,A die pad unit provided in the package main body to adhesively fix the semiconductor chip; 상기 반도체칩의 접착면에 형성한 오목부를 구비한 반도체 패키지.A semiconductor package having a recess formed in the adhesive surface of the semiconductor chip. 제 1 항에 있어서,The method of claim 1, 상기 반도체칩의 상기 접착면에 복수의 오목부를 형성한 것을 특징으로 하는 반도체 패키지.A semiconductor package, characterized in that a plurality of recesses formed on the adhesive surface of the semiconductor chip. 제 1 항 또는 제 2 항에 있어서,The method according to claim 1 or 2, 상기 다이패드부는,The die pad unit, 상기 반도체칩이 탑재되는 탑재부와,A mounting unit on which the semiconductor chip is mounted; 해당 탑재부의 주변부에 단차를 마련하여 이루어지는 하단부를 구비한 것을 특징으로 하는 반도체 패키지.A semiconductor package comprising a lower end formed by providing a step at a periphery of the mounting portion.
KR1020020045723A 2001-12-03 2002-08-02 Semiconductor package KR20030047688A (en)

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