JP5830958B2 - Semiconductor module - Google Patents

Semiconductor module Download PDF

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JP5830958B2
JP5830958B2 JP2011139170A JP2011139170A JP5830958B2 JP 5830958 B2 JP5830958 B2 JP 5830958B2 JP 2011139170 A JP2011139170 A JP 2011139170A JP 2011139170 A JP2011139170 A JP 2011139170A JP 5830958 B2 JP5830958 B2 JP 5830958B2
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semiconductor chip
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mounting substrate
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semiconductor
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JP2013008771A (en
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卓 下村
卓 下村
林 哲也
林  哲也
山上 滋春
滋春 山上
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Nissan Motor Co Ltd
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    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1305Bipolar Junction Transistor [BJT]
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Description

本発明は、半導体チップと実装基材との間に凹凸が形成されて実装された半導体モジュールに関する。   The present invention relates to a semiconductor module mounted with an unevenness formed between a semiconductor chip and a mounting substrate.

従来、半導体レーザ素子の半田接合に際して、過剰な半田がサブマウント細溝を介してサブマウントに流出し、さらに延長溝を通じて外部に排出される技術が、例えば以下に示す文献に記載されている(特許文献1参照)。このような技術を採用することで、半導体レーザアセンブリを製造する際に、半導体レーザ素子、サブマウント、あるいはヒートシンク上で球状接合材残留物が形成されることを防止できる。   Conventionally, a technique in which excessive solder flows into the submount through the submount narrow groove and is discharged to the outside through the extension groove when soldering the semiconductor laser element is described in, for example, the following documents ( Patent Document 1). By adopting such a technique, it is possible to prevent the spherical bonding material residue from being formed on the semiconductor laser element, the submount, or the heat sink when the semiconductor laser assembly is manufactured.

国際公開WO2004/077630号公報International Publication No. WO2004 / 077630

上述したような半導体素子の実装技術においては、半導体素子の消費電力が大きくなるにつれて発熱対策が重要な課題であった。動作時に発熱する半導体素子において、温度上昇は半導体素子の破壊の原因となるため、熱伝達経路の熱抵抗を低減して冷却性能を向上する必要がある。半田などの接合材を介して半導体チップを実装基材上に実装した場合に、実装基材に比べて接合材は熱伝導率が低いため、熱伝達経路の熱抵抗を低減するためには接合材の薄化が有効である。   In the semiconductor element mounting technology as described above, a countermeasure for heat generation has become an important issue as the power consumption of the semiconductor element increases. In a semiconductor element that generates heat during operation, a rise in temperature causes destruction of the semiconductor element. Therefore, it is necessary to improve the cooling performance by reducing the thermal resistance of the heat transfer path. When a semiconductor chip is mounted on a mounting substrate via a bonding material such as solder, the bonding material has a lower thermal conductivity than the mounting substrate, so bonding is necessary to reduce the thermal resistance of the heat transfer path. Thinning the material is effective.

一方、接合材は、半導体チップと実装基材の間の線膨張係数差により発生する熱応力を緩和する効果がある。これにより、使用時の温度変化による繰り返し熱応力を考慮した長期信頼性を確保するためには、接合材には適切な厚さが必要である。   On the other hand, the bonding material has an effect of relieving thermal stress generated due to a difference in linear expansion coefficient between the semiconductor chip and the mounting substrate. Accordingly, in order to ensure long-term reliability in consideration of repeated thermal stress due to temperature changes during use, the bonding material needs to have an appropriate thickness.

従来の実装構造では、熱抵抗の低減のために接合材を薄化すると、半導体チップと実装基材とが対向する側の平面部同士が近接することになる。このため、半導体チップと実装基材との近接部で熱応力による応力集中が顕著に発生して、接合材の長期信頼性が低下する。したがって、従来の実装構造では、冷却性能の向上と長期信頼性の確保の両立は困難であった。   In the conventional mounting structure, when the bonding material is thinned in order to reduce the thermal resistance, the plane portions on the side where the semiconductor chip and the mounting base material face each other are close to each other. For this reason, stress concentration due to thermal stress is prominently generated in the vicinity of the semiconductor chip and the mounting substrate, and the long-term reliability of the bonding material is lowered. Therefore, it has been difficult for the conventional mounting structure to achieve both improved cooling performance and long-term reliability.

そこで、本発明は、上記に鑑みてなされたものであり、その目的とするところは、半導体チップを実装基材に実装する際に、冷却性能の向上と長期信頼性の確保との双方を満足させる半導体モジュールを提供することにある。   Therefore, the present invention has been made in view of the above, and the object of the present invention is to satisfy both improvement of cooling performance and securing of long-term reliability when a semiconductor chip is mounted on a mounting substrate. An object of the present invention is to provide a semiconductor module.

上記目的を達成するために、本発明は、接合材材を介して半導体チップと実装基材とが接合された際に、半導体チップの電極部と実装基材との接合面の端部を跨ぐように凹凸が配置形成され、凹凸の凸部頂点で実装基材と半導体チップとが最も近接していることを特徴とする。   In order to achieve the above object, the present invention straddles the end of the bonding surface between the electrode portion of the semiconductor chip and the mounting substrate when the semiconductor chip and the mounting substrate are bonded via the bonding material. Thus, the mounting substrate and the semiconductor chip are closest to each other at the apex of the protrusion.

本発明によれば、凹凸が半導体チップの電極部と実装基材との接合面の端部を跨ぐように配置形成されるので、接合材の厚さを低減して熱抵抗を減少させることが可能となり、冷却性能を向上することができる。また、半導体チップと実装基材との近接部の面積を減少させて熱応力の集中を緩和することが可能となり、長期信頼性を確保することができる。   According to the present invention, the unevenness is arranged and formed so as to straddle the end portion of the bonding surface between the electrode portion of the semiconductor chip and the mounting substrate, so that the thickness of the bonding material can be reduced to reduce the thermal resistance. This makes it possible to improve the cooling performance. In addition, it is possible to reduce the area of the proximity portion between the semiconductor chip and the mounting substrate to alleviate the concentration of thermal stress, and to ensure long-term reliability.

本発明の実施形態1に係る半導体モジュールの構成を示す断面図である。It is sectional drawing which shows the structure of the semiconductor module which concerns on Embodiment 1 of this invention. 図1に示す凹凸部の形状例を示す断面図である。It is sectional drawing which shows the example of a shape of the uneven | corrugated | grooved part shown in FIG. 図1に示す凹凸部の配置例を示す図である。It is a figure which shows the example of arrangement | positioning of the uneven | corrugated | grooved part shown in FIG. 図1に示す凹凸部の配置例を示す図である。It is a figure which shows the example of arrangement | positioning of the uneven | corrugated | grooved part shown in FIG. 半導体チップの実装面に対する図1に示す凹凸部の配置例を示す平面図である。It is a top view which shows the example of arrangement | positioning of the uneven | corrugated | grooved part shown in FIG. 1 with respect to the mounting surface of a semiconductor chip. 半導体チップの実装面に対する図1に示す凹凸部の配置例を示す平面図である。It is a top view which shows the example of arrangement | positioning of the uneven | corrugated | grooved part shown in FIG. 1 with respect to the mounting surface of a semiconductor chip. 半導体チップの実装面に対する図1に示す凹凸部の配置例を示す平面図である。It is a top view which shows the example of arrangement | positioning of the uneven | corrugated | grooved part shown in FIG. 1 with respect to the mounting surface of a semiconductor chip. 本発明の実施形態2に係る半導体モジュールの構成を示す断面図である。It is sectional drawing which shows the structure of the semiconductor module which concerns on Embodiment 2 of this invention. 本発明の実施形態3に係る半導体モジュールの構成を示す断面図である。It is sectional drawing which shows the structure of the semiconductor module which concerns on Embodiment 3 of this invention. 図6に示す凹凸部材形状例を示す断面図である。It is sectional drawing which shows the uneven | corrugated member shape example shown in FIG. 図6に示す凹凸部材の配置例を示す図である。It is a figure which shows the example of arrangement | positioning of the uneven | corrugated member shown in FIG. 図6に示す凹凸部材の配置例を示す図である。It is a figure which shows the example of arrangement | positioning of the uneven | corrugated member shown in FIG. 本発明の実施形態4に係る半導体モジュールの構成を示す断面図である。It is sectional drawing which shows the structure of the semiconductor module which concerns on Embodiment 4 of this invention.

以下、図面を用いて本発明を実施するための実施形態を説明する。   Hereinafter, embodiments for carrying out the present invention will be described with reference to the drawings.

(実施形態1)
図1は本発明の実施形態1に係る半導体モジュールの構成を示す図であり、同図(a)は平面図、同図(b)は断面図である。
(Embodiment 1)
1A and 1B are diagrams showing a configuration of a semiconductor module according to Embodiment 1 of the present invention, where FIG. 1A is a plan view and FIG. 1B is a cross-sectional view.

図1において、半導体チップ11は、接合材12を介して実装基材13に接合されて実装され、これらにより半導体モジュールが構成されている。なお、半導体モジュールは、電圧印加時に耐放電に対する沿面距離および空間距離の確保や長期信頼性の維持のため、任意の部位が絶縁層で覆われている。半導体チップ11は、例えば車両を駆動するモータに電力を供給するインバータ回路などの電力変換用のパワーモジュールで構成され、例えば数百ボルトおよび数百アンペア定格のパワー半導体装置で構成される。一般的に、パワーモジュールにはダイオードとスイッチング素子の2種類の半導体素子を使用し、本発明は両半導体チップに適応可能である。半導体チップ11は、例えば厚さ100マイクロメートル前後で縦横サイズは数ミリメートル程度である。半導体チップ11としては、例えばSi、SiC、GaNや有機物系等の半導体基板材料、および集積度にかかわらず広範囲の半導体チップが使用可能である。   In FIG. 1, a semiconductor chip 11 is mounted by being bonded to a mounting substrate 13 via a bonding material 12, thereby forming a semiconductor module. In the semiconductor module, an arbitrary portion is covered with an insulating layer in order to ensure a creepage distance and a spatial distance against discharge and to maintain long-term reliability when a voltage is applied. The semiconductor chip 11 is configured by a power conversion power module such as an inverter circuit that supplies power to a motor that drives a vehicle, for example, and is configured by a power semiconductor device rated at several hundred volts and several hundred amperes, for example. In general, the power module uses two types of semiconductor elements, a diode and a switching element, and the present invention is applicable to both semiconductor chips. The semiconductor chip 11 has a thickness of about 100 micrometers, for example, and a vertical and horizontal size of about several millimeters. As the semiconductor chip 11, for example, a wide range of semiconductor chips can be used regardless of the semiconductor substrate material such as Si, SiC, GaN, organic type, and the degree of integration.

接合材12は、この実施形態1では半田で構成される。なお、接合材12は、半導体チップ11の耐熱性や電気特性等の性能劣化の要因とならない熱伝導可能な無機または有機系の接合材や、それらを複合した接合材から適宜選択するが可能である。また、接合材12の特性としては、熱や電磁波、振動等の一定条件により硬化または軟化する接合材が望ましい。   In the first embodiment, the bonding material 12 is made of solder. The bonding material 12 can be appropriately selected from an inorganic or organic bonding material capable of conducting heat that does not cause performance deterioration such as heat resistance and electrical characteristics of the semiconductor chip 11 or a bonding material obtained by combining them. is there. Moreover, as a characteristic of the bonding material 12, a bonding material that is hardened or softened under certain conditions such as heat, electromagnetic waves, and vibrations is desirable.

さらに、接合材12は、各接合場所に適した接合材および接合法の選択が可能である。例えば、半導体チップ11と実装基材13との接合部の中央と外周、あるいは凹凸部131と平坦部で組成の異なる接合材の選択や、金属結合、化学接合、物理結合、複合接合等から異なる接合法の選択が可能である。   Furthermore, the joining material 12 can select the joining material and joining method suitable for each joining location. For example, it differs from the selection of a bonding material having a different composition between the center and outer periphery of the bonding portion between the semiconductor chip 11 and the mounting substrate 13, or the uneven portion 131 and the flat portion, metal bonding, chemical bonding, physical bonding, composite bonding, and the like. Selection of joining method is possible.

実装基材13は、この実施形態1では熱伝導および電気伝導性に優れるCu(銅)材で構成される。実装基材13は、Cuの他に例えば熱伝導が可能な無機および有機系やそれらの複合材を用いることも可能である。   In the first embodiment, the mounting substrate 13 is made of a Cu (copper) material that is excellent in thermal conductivity and electrical conductivity. For the mounting substrate 13, it is possible to use, for example, inorganic and organic materials capable of conducting heat or composite materials thereof other than Cu.

実装基材13の大きさは、半導体チップ11の熱耐性により異なる。例えば、半導体チップ11の発熱量が多い場合や熱伝達経路の熱抵抗が大きい場合には、実装基材13を大きくすることが可能である。この実施形態1では、例えば一辺が数ミリから数十ミリメートル程度の大きさである。なお、半導体チップ11の特性によっては、半導体チップ11の面積よりも小さい実装基材13を用いることも可能である。すなわち、半導体チップ11と実装基材13との面積の大小関係にかかわらず、半導体チップ11と実装基材13との大きさを選択して組み合わせることが可能である。   The size of the mounting substrate 13 varies depending on the heat resistance of the semiconductor chip 11. For example, when the heat generation amount of the semiconductor chip 11 is large or the heat resistance of the heat transfer path is large, the mounting substrate 13 can be enlarged. In the first embodiment, for example, one side has a size of several millimeters to several tens of millimeters. Depending on the characteristics of the semiconductor chip 11, it is possible to use a mounting substrate 13 smaller than the area of the semiconductor chip 11. That is, it is possible to select and combine the sizes of the semiconductor chip 11 and the mounting substrate 13 regardless of the size relationship between the semiconductor chip 11 and the mounting substrate 13.

実装基材13を半導体チップ11の電流経路として使用する場合には、導電性を有する熱伝導が可能な無機および有機系やそれらの複合材の選択が可能である。例えば、CuやAlやMoやW等の金属単体、またはこれらの合金または複合材を用いることが可能である。また、エポキシ系やアクリル系やイミド系等の樹脂やセラミクス、これらの樹脂と導電体や絶縁体の複合材、またはこれらの金属や樹脂やセラミクス等を積層した複合材を用いることが可能である。   When the mounting substrate 13 is used as a current path of the semiconductor chip 11, it is possible to select inorganic and organic materials that can conduct heat and have conductivity, or composite materials thereof. For example, a simple metal such as Cu, Al, Mo, or W, or an alloy or composite material thereof can be used. Moreover, it is possible to use epoxy-type, acrylic-type, imide-type, etc. resins and ceramics, composite materials of these resins and conductors or insulators, or composite materials in which these metals, resins, ceramics, etc. are laminated. .

実装基材13には、半導体チップ11と対向して半導体チップ11が実装される側の実装面に、凹凸部131が形成されている。この凹凸部131は、少なくとも半導体チップ11の電極部と実装基材13とが接合材12を介して電気的に接合される接合面の端部を跨ぐように配置形成されている。ここで、半導体チップの電極部とは、例えばスイッチング素子を構成するトランジスタのゲート端子、ソース端子、ドレイン端子などであり、ダイオードのアノード端子やカソード端子などである。   On the mounting substrate 13, an uneven portion 131 is formed on the mounting surface on the side where the semiconductor chip 11 is mounted facing the semiconductor chip 11. The concavo-convex portion 131 is disposed and formed so as to straddle at least the end portion of the bonding surface where the electrode portion of the semiconductor chip 11 and the mounting base material 13 are electrically bonded via the bonding material 12. Here, the electrode portion of the semiconductor chip is, for example, a gate terminal, a source terminal, a drain terminal, or the like of a transistor that constitutes a switching element, such as an anode terminal or a cathode terminal of a diode.

図2に凹凸部131の断面形状の一例を示す。図2において、同図(a)は凸部1311の断面が角錐状、同図(b)は凸部1312の断面の先端部分が円錐状、同図(c)は凸部1313の断面の先端部分が切り妻状の例を示している。凹凸部131の断面形状の特徴は、凸部が半導体チップ11の接合面に対して傾斜を有していることである。この傾斜により、半導体チップ11と実装基材13との接合後、半導体チップ11と凹凸部131との近接部は、点状または線状となる。   FIG. 2 shows an example of the cross-sectional shape of the uneven portion 131. 2A, the projection 1311 has a pyramidal cross section, FIG. 2B shows the tip of the projection 1312 having a conical tip, and FIG. 2C shows the tip of the projection 1313. The part shows an example of a gable. A feature of the cross-sectional shape of the concavo-convex portion 131 is that the convex portion is inclined with respect to the bonding surface of the semiconductor chip 11. Due to this inclination, after the semiconductor chip 11 and the mounting substrate 13 are joined, the proximity portion between the semiconductor chip 11 and the concavo-convex portion 131 becomes a dot or a line.

先にも触れたが、接合材12は、半導体チップ11と実装基材13との間の熱応力を緩和する効果があるので、接合材12には適切な厚さが必要となる。仮に、凹凸部131が無い場合には、半導体チップ11と実装基材13との接合後の近接部は平面となる。このため、半導体チップ11と実装基材13との近接部で熱応力による応力集中が顕著に発生し、接合材12の長期信頼性が低下する。これに対して、実装基材13に凹凸部131を設けることで、半導体チップ11と実装基材13との近接部の面積は設けない場合に比べて少なくなる。これにより、応力集中の発生を抑制することが可能となる。   As mentioned above, since the bonding material 12 has an effect of relieving the thermal stress between the semiconductor chip 11 and the mounting substrate 13, the bonding material 12 needs to have an appropriate thickness. Temporarily, when there is no uneven part 131, the proximity part after joining of semiconductor chip 11 and mounting substrate 13 becomes a plane. For this reason, stress concentration due to thermal stress occurs remarkably in the vicinity of the semiconductor chip 11 and the mounting substrate 13, and the long-term reliability of the bonding material 12 is reduced. In contrast, by providing the mounting substrate 13 with the concavo-convex portion 131, the area of the proximity portion between the semiconductor chip 11 and the mounting substrate 13 is reduced as compared with the case where it is not provided. Thereby, generation | occurrence | production of stress concentration can be suppressed.

図1に示す凹凸部131の形状は、図2(a)に示すような四角錐形状である。四角錐形状にすることにより、凹凸部131の凸部と半導体チップ11との近接部の面積は非常に少なくなる。これにより、熱応力による応力集中の発生を抑えることが可能となる。図1に示す凹凸部131の内角は、約60度程度であるが、より鋭角な形状や三角錐とすることで、熱応力による応力集中を分散し易い形状となり、長期信頼性が更に向上することが可能となる。   The shape of the uneven portion 131 shown in FIG. 1 is a quadrangular pyramid shape as shown in FIG. By adopting the quadrangular pyramid shape, the area of the proximate part between the convex part of the concave-convex part 131 and the semiconductor chip 11 becomes very small. Thereby, it is possible to suppress the occurrence of stress concentration due to thermal stress. The internal angle of the concavo-convex portion 131 shown in FIG. 1 is about 60 degrees, but by using a sharper shape or a triangular pyramid, the stress concentration due to thermal stress can be easily dispersed, and long-term reliability is further improved. It becomes possible.

図2(b)に示す断面形状は、凸部の先端が曲面である。このため、実装工程時に半導体チップ11と実装基材13を加圧して接合する場合でも、同図(a)、(c)に示す断面形状に比べて加圧による応力集中が抑制される。したがって、凹凸形状の変形が少なく、半田厚を一定に保つことが可能となる。   In the cross-sectional shape shown in FIG. 2B, the tip of the convex portion is a curved surface. For this reason, even when the semiconductor chip 11 and the mounting base material 13 are pressed and bonded during the mounting process, stress concentration due to pressing is suppressed compared to the cross-sectional shapes shown in FIGS. Therefore, there is little deformation of the uneven shape, and the solder thickness can be kept constant.

また、上記断面形状を混在させることも可能である。例えば熱応力発生時に応力集中が大きい部位では、図2(a)の断面形状を用い、それ以外は熱抵抗を抑えるため同図(b)の断面形状を用いる。これにより、混在させない場合に比べて、長期信頼性の確保と冷却性能の向上をより一層向上することができる。   Moreover, it is also possible to mix the said cross-sectional shape. For example, the cross-sectional shape of FIG. 2A is used in a portion where the stress concentration is large when thermal stress is generated, and the cross-sectional shape of FIG. As a result, it is possible to further improve the long-term reliability and the improvement of the cooling performance as compared with the case where they are not mixed.

実装基材13の凹凸部131の高さは、例えば数十から数百マイクロメータ前後である。なお、凹凸部131の高さは、接合材12や実装基材13の物性や半導体モジュールの実際の使用温度やそのサイクルを考慮して決められる。すなわち、接合材12および凹凸部131の近傍に発生する熱応力を、目標とする疲労限度以下に抑えることが可能な高さが望ましい。   The height of the uneven portion 131 of the mounting substrate 13 is, for example, about several tens to several hundreds of micrometers. The height of the concavo-convex portion 131 is determined in consideration of the physical properties of the bonding material 12 and the mounting substrate 13, the actual use temperature of the semiconductor module, and the cycle thereof. That is, it is desirable that the thermal stress generated in the vicinity of the bonding material 12 and the concavo-convex portion 131 can be suppressed to a target fatigue limit or less.

また、凹凸部131の高さは、すべての凹凸部131で同一ではなく、使用する接合材12や熱応力による応力集中の発生状況に応じて、複数の高さを用いることも可能である。   Further, the height of the concavo-convex portion 131 is not the same for all the concavo-convex portions 131, and a plurality of heights can be used according to the bonding material 12 to be used and the state of occurrence of stress concentration due to thermal stress.

例えば、半導体チップ11と実装基材13との接合部中央は外周に比べて高くする一方、その逆であっても可能である。 For example, the center of the joint between the semiconductor chip 11 and the mounting substrate 13 is made higher than the outer periphery, and vice versa.

凸部が図2(a)〜同図(c)に示す断面構造を有する凹凸部131は、図3A(a1),(a2)〜同図(d1),(d2)、図3B(e1),(e2)〜同図(h1)、(h2)に示すような配置が可能である。図3A(a2)〜図3B(h2)は図3A(a1)〜図3B(h1)の破線に沿った断面図である。図3A(a1),(a2)では、円錐状の凸部1312が離散的に格子状に配置されている。図3A(b1),(b2)では、円錐状の凸部1312が離散的に互い違いに格子状に配置されている。図3A(c1),(c2)では、高さが異なる三角錐の凸部1311が接して格子状に配置されている。図3A(d1),(d2)では、四角錐の凸部1311が接して格子状に配置されている。   3A (a1), (a2) to FIG. 3 (d1), (d2), and FIG. 3B (e1). , (E2) to (h1), (h2) are possible. 3A (a2) to FIG. 3B (h2) are cross-sectional views taken along the broken lines in FIG. 3A (a1) to FIG. 3B (h1). In FIG. 3A (a1) and (a2), the conical convex part 1312 is discretely arrange | positioned at the grid | lattice form. In FIGS. 3A (b1) and (b2), the conical convex portions 1312 are discretely arranged in a lattice pattern alternately. 3A (c1) and (c2), triangular pyramid convex portions 1311 having different heights are in contact with each other and arranged in a lattice pattern. In FIG. 3A (d1) and (d2), the convex portions 1311 of the quadrangular pyramids are in contact with each other and arranged in a lattice shape.

一方、図3B(e1),(e2)では、鞍状(かまぼこ状)の凸部1314が複数並列して配置されている。図3B(f1),(f2)では、鞍状の凸部1314が互い違いに離散的に配置されている。図3B(g1),(g2)では、隣り合う列の鞍状の凸部1314が半導体チップ11との近接部の方向が異なるように離散的に配置されている。図3B(h1),(h2)では、鞍状の凸部1314が格子状に配置されている。   On the other hand, in FIG. 3B (e1) and (e2), a plurality of ridge-shaped (kamaboko-shaped) convex portions 1314 are arranged in parallel. In FIG. 3B (f1) and (f2), the hook-shaped convex parts 1314 are alternately arranged discretely. In FIG. 3B (g1) and (g2), the saddle-shaped convex portions 1314 in adjacent rows are discretely arranged so that the directions of the proximity portions to the semiconductor chip 11 are different. In FIG. 3B (h1) and (h2), the hook-shaped convex portions 1314 are arranged in a lattice pattern.

実装基材13の凹凸部131は、先にも触れたが、半導体チップ11の電極部と実装基材13との接合面の端部を跨いで配置されている。これにより、実装時に、低粘度な条件下における余剰な接合材12は、凹凸部131の毛細管現象により半導体チップ11の電極部下から連続的に半導体チップ11の外周まで案内される。したがって、余剰な接合材12が半導体チップ11の電極部と実装基材13との間に留まり、接合材12の厚さが必要以上に厚くなることは回避される。この結果、冷却性能が低下することを抑制することができる。   As described above, the uneven portion 131 of the mounting substrate 13 is disposed across the end portion of the bonding surface between the electrode portion of the semiconductor chip 11 and the mounting substrate 13. Thereby, at the time of mounting, the excessive bonding material 12 under the low viscosity condition is continuously guided from the bottom of the electrode portion of the semiconductor chip 11 to the outer periphery of the semiconductor chip 11 by the capillary phenomenon of the uneven portion 131. Therefore, it is avoided that the excessive bonding material 12 stays between the electrode portion of the semiconductor chip 11 and the mounting base material 13 and the bonding material 12 becomes thicker than necessary. As a result, it can suppress that cooling performance falls.

図4A(a)〜図4C(j)は、半導体チップ11の実装面に対する凹凸部131の配置例を示す平面図である。図4A(a)に示すように、半導体チップ11の全外周にわたって実装基材13に凹凸部131を配置することで、冷却性能低下の抑制能力を高めることができる。   4A (a) to 4C (j) are plan views illustrating an arrangement example of the uneven portion 131 with respect to the mounting surface of the semiconductor chip 11. FIG. As shown in FIG. 4A (a), by disposing the concavo-convex portion 131 on the mounting substrate 13 over the entire outer periphery of the semiconductor chip 11, the ability to suppress the cooling performance degradation can be increased.

一方、図4A(b)では、半導体チップ11が配置される部分の四隅に凹凸部131を配置している。接合時の半導体チップ11は、接合材12の実装基材13への接触状態(濡れ状態)や、接合材12の表面張力により実装基材13の接合面に対して多少傾く。このため、余剰接合材が半導体チップ11の四隅に溜まりやすくなる。したがって、接合材12の厚さが必要以上に厚くなり冷却性能が低下しやすい。そこで、図4A(b)に示す配置にすることで、半導体チップ11の四隅の余剰な接合材12を毛細管現象により半導体チップ11の外周に案内して半導体チップ11外に排出することができる。この結果、接合材12の厚さを適正かつ均一に保つことが可能となる。   On the other hand, in FIG. 4A (b), uneven portions 131 are arranged at the four corners of the portion where the semiconductor chip 11 is arranged. The semiconductor chip 11 at the time of bonding is slightly inclined with respect to the bonding surface of the mounting base material 13 due to the contact state (wetting state) of the bonding material 12 to the mounting base material 13 and the surface tension of the bonding material 12. For this reason, the excess bonding material is likely to accumulate at the four corners of the semiconductor chip 11. Therefore, the thickness of the bonding material 12 becomes thicker than necessary, and the cooling performance tends to be lowered. 4A (b), the excess bonding material 12 at the four corners of the semiconductor chip 11 can be guided to the outer periphery of the semiconductor chip 11 by capillary action and discharged out of the semiconductor chip 11. As a result, the thickness of the bonding material 12 can be kept appropriate and uniform.

図4A(c)では、先の同図(b)の配置に対して半導体チップ11の中央部にも対向して凹凸部131を加えて配置している。このような配置とすることで、図4A(b)に対して半導体チップ11における温度が上昇しやすい中央部に対して、半導体チップ11と熱伝導率が高い凹凸部131との近接部が設けられる。これにより、冷却性能をさらに一層向上することが可能となる。   In FIG. 4A (c), with respect to the arrangement of FIG. With such an arrangement, a proximity portion between the semiconductor chip 11 and the concavo-convex portion 131 having high thermal conductivity is provided in the central portion where the temperature in the semiconductor chip 11 is likely to rise as compared to FIG. 4A (b). It is done. As a result, the cooling performance can be further improved.

図4A(d)では、半導体チップ11の四隅を除いた各辺部に対応して凹凸部131を配置している。半導体チップ11の四隅は接合材12への応力が集中しやすい。したがって、図4A(d)に示すような配置にすることで、先の図4A(a)に比べて半導体チップ11の四隅の接合材12の平均厚さを厚くすることができる。この結果、熱応力が分散されて長期信頼性をより一層向上することが可能となる。   In FIG. 4A (d), the concavo-convex portion 131 is arranged corresponding to each side portion excluding the four corners of the semiconductor chip 11. Stress on the bonding material 12 tends to concentrate at the four corners of the semiconductor chip 11. Therefore, by arranging as shown in FIG. 4A (d), the average thickness of the bonding material 12 at the four corners of the semiconductor chip 11 can be increased as compared with FIG. 4A (a). As a result, thermal stress is dispersed and long-term reliability can be further improved.

図4B(e)〜同図(h)では、半導体チップ11の中央部に対応して配置された凹凸部131が途切れることなく半導体チップ11の外周へと連続して配置されている。このような配置にすることで、半導体チップ11の中央部の余剰な接合材12を確実に外周へ案内して半導体チップ11外に排出することが可能となる。この結果、冷却性能の低下を抑制することができる。また、半導体チップ11の中央部に、熱伝導率が高い凹凸部131と半導体チップ11との近接部を設けることができるので、冷却性能を向上することが可能となる。   4B (e) to FIG. 4 (h), the concavo-convex portion 131 disposed corresponding to the central portion of the semiconductor chip 11 is continuously disposed on the outer periphery of the semiconductor chip 11 without interruption. With such an arrangement, it is possible to reliably guide the excessive bonding material 12 in the central portion of the semiconductor chip 11 to the outer periphery and discharge it outside the semiconductor chip 11. As a result, it is possible to suppress a decrease in cooling performance. Moreover, since the proximity part of the uneven | corrugated | grooved part 131 with high heat conductivity and the semiconductor chip 11 can be provided in the center part of the semiconductor chip 11, it becomes possible to improve cooling performance.

図4C(i)では、凹凸部131が半導体チップ11の接合面全体にわたって配置されている。このような配置とすることで、先の図4A(a)に比べて半導体チップ11と実装基材13との近接部が増加する。これにより、接合材12の平均厚さを低減することが可能となり、冷却性能を向上することが可能となる。   In FIG. 4C (i), the concavo-convex portion 131 is arranged over the entire bonding surface of the semiconductor chip 11. By setting it as such arrangement | positioning, the proximity | contact part of the semiconductor chip 11 and the mounting base material 13 increases compared with previous FIG. 4A (a). Thereby, the average thickness of the bonding material 12 can be reduced, and the cooling performance can be improved.

図4C(j)では、先の図4C(i)に示す配置例において、凹凸形状が異なる凹凸部を配置している。例えば、半導体チップ11の外周部には図2(a)に示すような凸部が錘状体の第1の凹凸部131−1を配置する。一方、半導体チップ11の中央部には図3B(e1),(e2)〜同図(h1),(h2)に示すような凸部が鞍状の第2の凹凸部131−2を配置する。   In FIG. 4C (j), the uneven | corrugated | grooved part from which the uneven | corrugated shape differs in the example of arrangement | positioning shown to previous FIG. 4C (i) is arrange | positioned. For example, the first concavo-convex portion 131-1 having a convex body as shown in FIG. 2A is arranged on the outer peripheral portion of the semiconductor chip 11. On the other hand, a second concavo-convex portion 131-2 having a ridge shape as shown in FIGS. 3B (e1), (e2) to (h1), (h2) is disposed in the central portion of the semiconductor chip 11. .

このような配置とすることで、接合材12に応力集中が発生しやすい半導体チップ11の端部は、図2(a)の錘状体とすることにより半導体チップ11と実装基材13との近接部の面積を低減することが可能となる。これにより、応力集中を抑制して長期信頼性を確保することが可能となる。また、半導体チップ11の発熱により高温になりやすい半導体チップ11の中央部は、図3Bに示す鞍状とすることにより接合材12の平均厚さを低減して熱抵抗を低減することができる。この結果、冷却性能を向上することが可能となる。   By adopting such an arrangement, the end of the semiconductor chip 11 where stress concentration is likely to occur in the bonding material 12 is formed into a weight-like body as shown in FIG. The area of the proximity portion can be reduced. This makes it possible to suppress long-term reliability by suppressing stress concentration. Further, the central portion of the semiconductor chip 11 that is likely to become high temperature due to heat generation of the semiconductor chip 11 is formed in a bowl shape shown in FIG. 3B, whereby the average thickness of the bonding material 12 can be reduced and the thermal resistance can be reduced. As a result, it is possible to improve the cooling performance.

実装基材13の凹凸部131の凸部頂点の個数は、半導体チップ11の安定した接合を考慮すると、半導体チップ11と凹凸部131との接合面では3点以上が望ましい。これにより、接合材12の厚さを一定に保つことが可能となり、極端な応力集中部の発生を防ぐことができ、長期信頼性の確保が可能となる。   In consideration of stable bonding of the semiconductor chip 11, the number of convex vertices of the concavo-convex portion 131 of the mounting substrate 13 is desirably three or more on the bonding surface between the semiconductor chip 11 and the concavo-convex portion 131. Thereby, the thickness of the bonding material 12 can be kept constant, the generation of an extreme stress concentration portion can be prevented, and long-term reliability can be ensured.

また、凹凸部131の頂点間距離は、広げるほど接合面における接合材12の割合が多くなる。このため、熱抵抗の大きな接合材12により冷却性能が悪化する。したがって、凹凸部131の頂点間距離は、凹凸部131における凸部の高さと同等以下が望ましい。   In addition, the proportion of the bonding material 12 on the bonding surface increases as the distance between the apexes of the uneven portion 131 increases. For this reason, the cooling performance is deteriorated by the bonding material 12 having a large thermal resistance. Therefore, the distance between the vertices of the concavo-convex portion 131 is desirably equal to or less than the height of the convex portion in the concavo-convex portion 131.

これにより、熱の伝達経路および拡散部を確保するとともに接合材12の平均厚さを低減して、冷却性能を向上することが可能となる。凹凸部131の頂点間距離は、例えば数十から数百マイクロメータ程度で実施することが可能である。 As a result, it is possible to secure the heat transfer path and the diffusion portion and reduce the average thickness of the bonding material 12 to improve the cooling performance. The distance between the vertices of the concavo-convex portion 131 can be implemented, for example, in the order of several tens to several hundreds of micrometers.

凹凸部131の頂点間距離は、種類の異なる接合材12の使用や、接合材12の流動性を制御する場合には、上記頂点間距離の範囲内で複数の混在も可能である。また、凹凸部131の頂点間距離と凸部の高さは、接合材12に固形の添加物などを混入させた場合には、混入した添加物に応じて上記要件を変えることが可能である。すなわち、混入した添加物を含む接合材12が、凹凸部131を通って半導体チップ11の外周部に確実に案内されて半導体チップ11外に排出される程度に変更される。   The distance between the vertices of the concavo-convex portion 131 can be mixed within a range of the distance between the vertices when using different types of the bonding material 12 or controlling the fluidity of the bonding material 12. Moreover, when the solid additive etc. are mixed in the joining material 12, the said requirements can be changed for the distance between the vertexes of the uneven | corrugated | grooved part 131, and the height of a convex part according to the mixed additive. . That is, the bonding material 12 containing the mixed additive is changed to such an extent that it is guided to the outer peripheral portion of the semiconductor chip 11 through the uneven portion 131 and discharged out of the semiconductor chip 11.

なお、図1に示す実装例では、半導体チップ11と実装基材13の凹凸部131における凸部頂点が接触して場合を例示しているが、必ずしも接触している必要はない。すなわち、冷却性能など各部仕様性能を損なわない範囲で両者が直接接触せずに接合材12が介在して近接した状態であってもかまわない。   In the mounting example shown in FIG. 1, the case where the semiconductor chip 11 and the convex portion vertex of the concave and convex portion 131 of the mounting substrate 13 are in contact with each other is illustrated, but it is not always necessary to be in contact. That is, as long as the specification performance of each part, such as the cooling performance, is not impaired, the two may not be in direct contact with each other and the bonding material 12 may be interposed therebetween.

また、上記実施形態1では、実装基材13に凹凸部131が形成されているが、例えば半導体チップ11が実装基材13によりも大きな場合には、実装基材13に設けたと同様の凹凸部131を実装基材13に代えて半導体チップ11側に設けることも可能である。このような構成であっても、実装基材13に設けた場合と同様の効果を得ることができる。   In the first embodiment, the uneven portion 131 is formed on the mounting base material 13. However, for example, when the semiconductor chip 11 is larger than the mounting base material 13, the same uneven portion as that provided on the mounting base material 13. It is also possible to provide 131 on the semiconductor chip 11 side instead of the mounting substrate 13. Even if it is such a structure, the effect similar to the case where it provides in the mounting base material 13 can be acquired.

半導体モジュールの冷却性能は、熱伝達経路の熱抵抗の大きさに左右され、実装基材13に比べて熱伝導率が低い接合材12の薄化で向上する。この実施形態1では、半導体チップ11の電極部と実装基材13の接合面の端部を跨ぐように凹凸部131を有する。これにより、毛細管現象により半導体チップ11下の接合材12が半導体チップ11の外周の凹凸部131まで流れ出し、半導体チップ11下の接合材12の厚さが減少する。また、凸部と半導体チップ11が近接することにより接合材12の平均厚さは低減し、熱抵抗を低減することで冷却性能を向上することが可能となる。   The cooling performance of the semiconductor module depends on the magnitude of the thermal resistance of the heat transfer path, and is improved by thinning the bonding material 12 having a lower thermal conductivity than the mounting substrate 13. In the first embodiment, the uneven portion 131 is provided so as to straddle the electrode portion of the semiconductor chip 11 and the end portion of the joint surface of the mounting substrate 13. Thereby, the bonding material 12 under the semiconductor chip 11 flows out to the concavo-convex portion 131 on the outer periphery of the semiconductor chip 11 due to a capillary phenomenon, and the thickness of the bonding material 12 under the semiconductor chip 11 decreases. In addition, the average thickness of the bonding material 12 is reduced by the proximity of the convex portion and the semiconductor chip 11, and the cooling performance can be improved by reducing the thermal resistance.

半導体モジュールの長期信頼性は、異種接合部の線膨張係数差および熱応力発生時の応力集中量と各部材の耐力で決まる。この実施形態1では、半導体チップ11と実装基材13が近接する平行面の面積と距離(接合材12の厚さ)で決まるので、平行面の面積の減少および距離の増加により長期信頼性を向上することができる。凹凸部131の凸部は、半導体チップ11に対して傾斜を持つため、半導体チップ11と凸部頂点の近接部の平行面の面積が最少となり、長期信頼性の確保が可能となる。   The long-term reliability of a semiconductor module is determined by the difference in linear expansion coefficient between different types of joints, the amount of stress concentration when thermal stress is generated, and the yield strength of each member. In the first embodiment, since the area and distance of the parallel surface where the semiconductor chip 11 and the mounting substrate 13 are close to each other (the thickness of the bonding material 12) are determined, long-term reliability is improved by reducing the area of the parallel surface and increasing the distance. Can be improved. Since the convex portion of the concavo-convex portion 131 is inclined with respect to the semiconductor chip 11, the area of the parallel surface between the semiconductor chip 11 and the proximate portion of the convex vertex is minimized, and long-term reliability can be ensured.

半導体チップ11と凹凸部131が点状または線状で近接することにより、近接部の平行面の面積が最少となる。さらに、半導体チップ11と凹凸部131は少なくとも1つ以上の点もしくは線状に近接しているため、凹凸部131の凹部における接合材12に必要な最小の厚さが確保されるため、長期信頼性の確保が可能となる。   When the semiconductor chip 11 and the concavo-convex portion 131 are close to each other in a dot shape or a line shape, the area of the parallel surface of the proximity portion is minimized. Further, since the semiconductor chip 11 and the concavo-convex portion 131 are close to each other in at least one point or a line shape, the minimum thickness necessary for the bonding material 12 in the concave portion of the concavo-convex portion 131 is ensured. It is possible to ensure the sex.

半導体チップ11と凹凸部131接合部に接合材12を用いずに、互いの材料が拡散し合う直接の接合を用いることで、熱抵抗の高い接合材が介在しない部位が発生するため、接合材の平均厚さが低減し、冷却性能を向上することが可能である。   Since the bonding material 12 is not used for the bonding portion of the semiconductor chip 11 and the concavo-convex portion 131 and a direct bonding in which each material diffuses is used, a portion where no bonding material having a high thermal resistance is present is generated. It is possible to reduce the average thickness and improve the cooling performance.

凹凸部131を、半導体チップ11と実装基材13との接合面における外周の全部もしくは一部に配置形成することで、余剰な接合材12を半導体チップ11外に排出することが可能となり、接合材12の厚さを適正に保ち冷却性能の低下を抑制することができる。   By arranging and forming the uneven portion 131 on the whole or a part of the outer periphery of the bonding surface between the semiconductor chip 11 and the mounting substrate 13, it becomes possible to discharge the excess bonding material 12 outside the semiconductor chip 11. It is possible to keep the thickness of the material 12 properly and to suppress a decrease in cooling performance.

(実施形態2)
図5は本発明の実施形態2に係る半導体モジュールの構成を示す断面図である。この実施形態2において、先の実施形態1と異なる点は、半導体チップ11にも凹凸部111を設けたことである。図5(a)に示す構成では、半導体チップ11の実装基材13との接合面に凹凸部111を設け、半導体チップ11の外周の実装基材13に先の実施形態1と同様の凹凸部131を設けている。
(Embodiment 2)
FIG. 5 is a cross-sectional view showing a configuration of a semiconductor module according to Embodiment 2 of the present invention. The second embodiment is different from the first embodiment in that the semiconductor chip 11 is provided with the uneven portion 111. In the configuration shown in FIG. 5A, the uneven portion 111 is provided on the joint surface of the semiconductor chip 11 with the mounting substrate 13, and the uneven portion similar to that of the first embodiment is formed on the outer peripheral mounting substrate 13 of the semiconductor chip 11. 131 is provided.

このような構成により、接合材12の平均厚さを低減して熱抵抗を低減することが可能となり、この結果、冷却性能を向上することができる。さらに加えて、半導体チップ11の熱容量が凹凸部111により増加し、半導体チップ11の過渡的な発熱に対して熱の拡散と伝達を俊敏に行うことができる。この結果、過渡的な発熱による半導体チップ11の熱破壊を防ぐことが可能となる。
図5(b)に示す構成では、先の同図(a)に示す構成に対して、半導体チップ11の中央部に対向した実装基材13の接合面に凹凸部131を加えたものである。このような構成により、先の図5(a)の構成で得られる効果に対して、接合材12の平均厚さをより一層低減して熱抵抗を低減することが可能となり、この結果、より一層冷却性能を向上することができる。
With such a configuration, it becomes possible to reduce the average thickness of the bonding material 12 and reduce the thermal resistance, and as a result, the cooling performance can be improved. In addition, the heat capacity of the semiconductor chip 11 is increased by the concavo-convex portion 111, so that heat can be diffused and transmitted quickly with respect to the transient heat generation of the semiconductor chip 11. As a result, it is possible to prevent thermal destruction of the semiconductor chip 11 due to transient heat generation.
In the configuration shown in FIG. 5B, an uneven portion 131 is added to the bonding surface of the mounting substrate 13 facing the central portion of the semiconductor chip 11 with respect to the configuration shown in FIG. . With such a configuration, it becomes possible to further reduce the average thickness of the bonding material 12 to reduce the thermal resistance with respect to the effect obtained in the configuration of FIG. The cooling performance can be further improved.

半導体モジュールの冷却性能は、熱伝達経路の熱抵抗の大きさに左右され、実装基材13に比べて熱伝導率が低い接合材12の薄化で向上する。この実施形態1では、半導体チップ11の電極部と実装基材13の接合面の端部を跨ぐように凹凸部131を有する。これにより、毛細管現象により半導体チップ11下の接合材12が半導体チップ11の外周の凹凸部131まで流れ出し、半導体チップ11下の接合材12の厚さが減少する。また、凸部と半導体チップ11が近接することにより接合材12の平均厚さは低減し、熱抵抗を低減することで冷却性能を向上することが可能となる。   The cooling performance of the semiconductor module depends on the magnitude of the thermal resistance of the heat transfer path, and is improved by thinning the bonding material 12 having a lower thermal conductivity than the mounting substrate 13. In the first embodiment, the uneven portion 131 is provided so as to straddle the electrode portion of the semiconductor chip 11 and the end portion of the joint surface of the mounting substrate 13. Thereby, the bonding material 12 under the semiconductor chip 11 flows out to the concavo-convex portion 131 on the outer periphery of the semiconductor chip 11 due to a capillary phenomenon, and the thickness of the bonding material 12 under the semiconductor chip 11 decreases. In addition, the average thickness of the bonding material 12 is reduced by the proximity of the convex portion and the semiconductor chip 11, and the cooling performance can be improved by reducing the thermal resistance.

半導体モジュールの長期信頼性は、異種接合部の線膨張係数差および熱応力発生時の応力集中量と各部材の耐力で決まる。この実施形態2では、半導体チップ11と実装基材13が近接する平行面の面積と距離(接合材12の厚さ)で決まるので、平行面の面積の減少および距離の増加により長期信頼性を向上することができる。凹凸部131の凸部は、半導体チップ11に対して傾斜を持つため、半導体チップ11と凸部頂点の近接部の平行面の面積が最少となり、長期信頼性の確保が可能となる。   The long-term reliability of a semiconductor module is determined by the difference in linear expansion coefficient between different types of joints, the amount of stress concentration when thermal stress is generated, and the yield strength of each member. In the second embodiment, since the area and distance of the parallel surface where the semiconductor chip 11 and the mounting substrate 13 are close to each other (the thickness of the bonding material 12) are determined, long-term reliability is improved by reducing the area of the parallel surface and increasing the distance. Can be improved. Since the convex portion of the concavo-convex portion 131 is inclined with respect to the semiconductor chip 11, the area of the parallel surface between the semiconductor chip 11 and the proximate portion of the convex vertex is minimized, and long-term reliability can be ensured.

半導体チップ11と凹凸部131が点状または線状で近接することにより、近接部の平行面の面積が最少となる。さらに、半導体チップ11と凹凸部131は少なくとも1つ以上の点もしくは線状に近接しているため、凹凸部131の凹部における接合材12に必要な最小の厚さが確保されるため、長期信頼性の確保が可能となる。   When the semiconductor chip 11 and the concavo-convex portion 131 are close to each other in a dot shape or a line shape, the area of the parallel surface of the proximity portion is minimized. Further, since the semiconductor chip 11 and the concavo-convex portion 131 are close to each other in at least one point or a line, the minimum thickness necessary for the bonding material 12 in the concave portion of the concavo-convex portion 131 is ensured. It is possible to ensure the sex.

半導体チップ11と凹凸部131の接合部に接合材12を用いずに、互いの材料が拡散し合う直接の接合を用いることで、熱抵抗の高い接合材が介在しない部位が発生するため、接合材の平均厚さが低減し、冷却性能を向上することが可能である。   Since the bonding material 12 is not used at the bonding portion between the semiconductor chip 11 and the concavo-convex portion 131 and a direct bonding in which each material diffuses is used, a portion where no bonding material having a high thermal resistance is present is generated. It is possible to reduce the average thickness of the material and improve the cooling performance.

凹凸部131を、半導体チップ11と実装基材13との接合面における外周の全部もしくは一部に配置形成することで、余剰な接合材12を半導体チップ11外に排出することが可能となり、接合材12の厚さを適正に保ち冷却性能の低下を抑制することができる。   By arranging and forming the uneven portion 131 on the whole or a part of the outer periphery of the bonding surface between the semiconductor chip 11 and the mounting substrate 13, it becomes possible to discharge the excess bonding material 12 outside the semiconductor chip 11. It is possible to keep the thickness of the material 12 properly and to suppress a decrease in cooling performance.

(実施形態3)
図6は本発明の実施形態3に係る半導体モジュールの構成を示す断面図であり、同図(a)は接合前の各部材の断面図であり、同図(b)は接合後の各部材の断面図である。
(Embodiment 3)
FIG. 6 is a cross-sectional view showing a configuration of a semiconductor module according to Embodiment 3 of the present invention. FIG. 6A is a cross-sectional view of each member before joining, and FIG. 6B is each member after joining. FIG.

この実施形態3において、先の実施形態1,2と異なる点は、実装基材13に形成された凹凸部131や半導体チップ11に形成された凹凸部111を、半導体チップ11や実装基材13とは別体の凹凸部材61として構成したことである。   The third embodiment is different from the first and second embodiments in that the uneven portion 131 formed on the mounting substrate 13 and the uneven portion 111 formed on the semiconductor chip 11 are replaced with the semiconductor chip 11 and the mounting substrate 13. Is configured as a separate concavo-convex member 61.

なお、実装基材13および凹凸部材61の材質、大きさ、配置、ならびに半導体チップ11、凹凸部材61ならびに実装基材13の接合方法は、先の実施形態1の同様である。   The material, size, and arrangement of the mounting substrate 13 and the concavo-convex member 61 and the method for joining the semiconductor chip 11, the concavo-convex member 61, and the mounting substrate 13 are the same as those in the first embodiment.

凹凸部材61は、例えば実装基材13と同様のCuで形成され、小さいもので1つの大きさが数十から数百マイクロメータ程度である。図6に示す構成では、先の図1に示すと同様の凸部が角錐状に形成された凹凸部材61を介在させて、図1と同様に半導体チップ11と実装基材13とを接合して実装している。   The concavo-convex member 61 is formed of, for example, the same Cu as that of the mounting substrate 13 and is small and has a size of about several tens to several hundreds of micrometers. In the configuration shown in FIG. 6, the semiconductor chip 11 and the mounting substrate 13 are joined in the same manner as in FIG. 1 by interposing an uneven member 61 in which convex portions similar to those shown in FIG. 1 are formed in a pyramid shape. Have been implemented.

接合後の構成として、凹凸部材61が先の実施形態1と同様の形状である場合に、先の実施形態1と異なる点は、図6(b)に示すように、実装基材13と凹凸部材61との間に接合材12が介在することである。これにより、先の実施形態1に比べて応力集中を抑える効果が高まり、長期信頼性をより一層向上することが可能となる。   As a configuration after joining, when the uneven member 61 has the same shape as that of the previous embodiment 1, the difference from the previous embodiment 1 is that the mounting substrate 13 and the uneven member are formed as shown in FIG. That is, the bonding material 12 is interposed between the member 61 and the member 61. As a result, the effect of suppressing stress concentration is increased as compared with the first embodiment, and long-term reliability can be further improved.

なお、実装基材13と凹凸部材61の線膨張係数の差が少ない場合には、互いの材料が拡散し合う直接の接合も可能である。このような場合には、熱抵抗となる接合材12が存在しない部位が生じるので、接合材12の平均厚さが低減し、冷却性能をより一層向上することが可能となる。   In addition, when the difference of the linear expansion coefficient of the mounting base material 13 and the uneven | corrugated member 61 is small, the direct joining which a mutual material diffuses is also possible. In such a case, a portion where the bonding material 12 serving as thermal resistance does not exist is generated, so that the average thickness of the bonding material 12 is reduced and the cooling performance can be further improved.

図7に凹凸部材61の断面形状の一例を示す。図7において、同図(a)は凸部611の断面が角錐状、同図(b)は凸部612の断面が円形、同図(c)は凸部613の断面が菱形の例を示している。また、図7(d)は凸部614の先端部分の断面が円錐状、同図(e)は凸部615の先端部分の断面が切り妻状の例を示している。   FIG. 7 shows an example of the cross-sectional shape of the concavo-convex member 61. 7A shows an example in which the convex portion 611 has a pyramidal cross section, FIG. 7B shows an example in which the convex portion 612 has a circular cross section, and FIG. 7C shows an example in which the convex portion 613 has a rhombic cross section. ing. 7D shows an example in which the cross section of the tip portion of the convex portion 614 is conical, and FIG. 7E shows an example in which the cross section of the tip portion of the convex portion 615 is gable.

図7に示す断面構造を有する凹凸部材61は、実装基材13に対して図8A(a1),(a2)〜図8B(h1),(h2)に示すような配置が可能である。図8A(a2)〜図8B(h2)は、図8A(a1)〜図8B(h1)の断面図である。図8A(a1),(a2)では、図7(b)に示す断面形状で球体の凸部612が離散的に格子状に配置されている。図8A(b1),(b2)では、図7(b)に示す断面形状で球体の凸部612が離散的に互い違いに格子状に配置されている。図8A(c1),(c2)では、凹凸部材61における高さが異なる三角錐の凸部611が接して格子状に配置されている。図8A(d1),(d2)では、図7(a)に示す四角錐の凸部611が接して格子状に配置されている。   7 can be arranged with respect to the mounting substrate 13 as shown in FIGS. 8A (a1), (a2) to 8B (h1), (h2). 8A (a2) to FIG. 8B (h2) are cross-sectional views of FIG. 8A (a1) to FIG. 8B (h1). In FIGS. 8A (a1) and (a2), the spherical convex portions 612 are discretely arranged in a lattice shape in the cross-sectional shape shown in FIG. 7B. In FIGS. 8A (b1) and (b2), the convex portions 612 of the sphere are discretely arranged in a lattice pattern in a cross-sectional shape shown in FIG. 7B. In FIGS. 8A (c1) and (c2), the triangular pyramid convex portions 611 having different heights in the concavo-convex member 61 are arranged in a grid pattern. In FIGS. 8A (d1) and (d2), the convex portions 611 of the quadrangular pyramid shown in FIG.

図8B(e1),(e2)では、図7(b)に示す断面形状で円柱状の凸部616が複数並列して配置されている。図8B(f1),(f2)では、図7(b)に示す断面形状で円柱状の凸部616が互い違いに離散的に配置され、図8B(g1),(g2)では、隣り合う列の凸部616が半導体チップ11との近接部の方向が異なるように離散的に配置されている。図8B(h1),(h2)では、図7(b)に示す断面形状で円柱状の凸部616が格子状に配置されている。   8B (e1) and (e2), a plurality of columnar convex portions 616 having the cross-sectional shape shown in FIG. 7B are arranged in parallel. 8B (f1) and (f2), the columnar convex portions 616 having the cross-sectional shape shown in FIG. 7B are arranged alternately and discretely. In FIGS. 8B (g1) and (g2), adjacent rows The convex portions 616 are discretely arranged so that the directions of the proximity portions to the semiconductor chip 11 are different. In FIG. 8B (h1) and (h2), cylindrical convex portions 616 having the cross-sectional shape shown in FIG. 7B are arranged in a lattice shape.

なお、図示していないが、図8B(e1),(e2)〜同図(h1),(h2)において、図7(b)に示す断面形状の凸部に代えて、図7(a),(c)〜(e)に示す断面形状の凸部とすることも可能である。   Although not shown, in FIGS. 8B (e1) and (e2) to (h1) and (h2), instead of the cross-sectional convex portion shown in FIG. 7B, FIG. , (C) to (e) can be convex portions having a cross-sectional shape.

図7(a),(d),(e)に示す断面形状では、線膨張係数の差が最も大きく熱応力が多く発生する半導体チップ11と凹凸部材61の接合面に、凸部頂点が点または線状で接触もしくは近接する構造となる。これにより、応力集中を抑えて熱応力の発生を緩和することが可能となる。また、実装基材13と凹凸部材61との接合面は、面で近接することで接合材12の平均厚さを低減し、冷却性能を向上することが可能となる。   In the cross-sectional shapes shown in FIGS. 7A, 7 </ b> D, and 7 </ b> E, the vertex of the convex portion is dotted on the joint surface between the semiconductor chip 11 and the concavo-convex member 61 where the difference in linear expansion coefficient is the largest and the thermal stress is generated. Or it becomes a structure which contacts or adjoins in a linear form. As a result, the stress concentration can be suppressed and the generation of thermal stress can be reduced. Further, the bonding surfaces of the mounting substrate 13 and the concavo-convex member 61 are close to each other so that the average thickness of the bonding material 12 can be reduced and the cooling performance can be improved.

図7(b),(c)に示す断面形状では、凹凸部材61の上下面を共に点または線により接触または近接する構造となる。これにより、図7(a),(d),(e)に示す断面形状に比べて応力集中を更に抑えることが可能となり、長期信頼性をより一層向上することができる。   The cross-sectional shapes shown in FIGS. 7B and 7C have a structure in which the upper and lower surfaces of the concavo-convex member 61 are in contact with or close to each other by dots or lines. This makes it possible to further suppress stress concentration compared to the cross-sectional shapes shown in FIGS. 7A, 7D, and 7E, and to further improve long-term reliability.

このような凹凸部材61を製造する場合に、例えば複数の凹凸部材61を任意の配置に整列するためのメス型形状の治具を用いて、実装前に予め凹凸部材61を実装基材13に接合することも可能である。   When manufacturing such a concavo-convex member 61, the concavo-convex member 61 is mounted on the mounting substrate 13 in advance before mounting, for example, using a female-shaped jig for aligning the plurality of concavo-convex members 61 in an arbitrary arrangement. It is also possible to join.

半導体モジュールの冷却性能は、熱伝達経路の熱抵抗の大きさに左右され、実装基材13に比べて熱伝導率が低い接合材12の薄化で向上する。この実施形態1では、半導体チップ11の電極部と実装基材13の接合面の端部を跨ぐように凹凸部131を有する。これにより、毛細管現象により半導体チップ11下の接合材12が半導体チップ11の外周の凹凸部131まで流れ出し、半導体チップ11下の接合材12の厚さが減少する。また、凸部と半導体チップ11が近接することにより接合材12の平均厚さは低減し、熱抵抗を低減することで冷却性能を向上することが可能となる。   The cooling performance of the semiconductor module depends on the magnitude of the thermal resistance of the heat transfer path, and is improved by thinning the bonding material 12 having a lower thermal conductivity than the mounting substrate 13. In the first embodiment, the uneven portion 131 is provided so as to straddle the electrode portion of the semiconductor chip 11 and the end portion of the joint surface of the mounting substrate 13. Thereby, the bonding material 12 under the semiconductor chip 11 flows out to the concavo-convex portion 131 on the outer periphery of the semiconductor chip 11 due to a capillary phenomenon, and the thickness of the bonding material 12 under the semiconductor chip 11 decreases. In addition, the average thickness of the bonding material 12 is reduced by the proximity of the convex portion and the semiconductor chip 11, and the cooling performance can be improved by reducing the thermal resistance.

半導体モジュールの長期信頼性は、異種接合部の線膨張係数差および熱応力発生時の応力集中量と各部材の耐力で決まる。この実施形態3では、半導体チップ11と実装基材13が近接する平行面の面積と距離(接合材12の厚さ)で決まるので、平行面の面積の減少および距離の増加により長期信頼性を向上することができる。凹凸部131の凸部は、半導体チップ11に対して傾斜を持つため、半導体チップ11と凸部頂点の近接部の平行面の面積が最少となり、長期信頼性の確保が可能となる。   The long-term reliability of a semiconductor module is determined by the difference in linear expansion coefficient between different types of joints, the amount of stress concentration when thermal stress is generated, and the yield strength of each member. In the third embodiment, since the area and distance (the thickness of the bonding material 12) of the parallel surface where the semiconductor chip 11 and the mounting substrate 13 are close to each other are determined, long-term reliability is achieved by reducing the area of the parallel surface and increasing the distance. Can be improved. Since the convex portion of the concavo-convex portion 131 is inclined with respect to the semiconductor chip 11, the area of the parallel surface between the semiconductor chip 11 and the proximate portion of the convex vertex is minimized, and long-term reliability can be ensured.

半導体チップ11と凹凸部131が点状または線状で近接することにより、近接部の平行面の面積が最少となる。さらに、半導体チップ11と凹凸部131は少なくとも1つ以上の点もしくは線状に近接しているため、凹凸部131の凹部における接合材12に必要な最少の厚さが確保されるため、長期信頼性の確保が可能となる。   When the semiconductor chip 11 and the concavo-convex portion 131 are close to each other in a dot shape or a line shape, the area of the parallel surface of the proximity portion is minimized. Furthermore, since the semiconductor chip 11 and the concavo-convex portion 131 are close to each other in at least one or more points or lines, the minimum thickness necessary for the bonding material 12 in the concave portion of the concavo-convex portion 131 is ensured. It is possible to ensure the sex.

半導体チップ11ならびに実装基材13とは別体として凹凸部材61を構成することで、応力緩和が可能な層(凹凸部材61)が増加し、更に長期信頼性を向上することが可能となる。   By configuring the concavo-convex member 61 as a separate body from the semiconductor chip 11 and the mounting substrate 13, the number of layers capable of stress relaxation (the concavo-convex member 61) increases, and long-term reliability can be further improved.

半導体チップ11と凹凸部131の接合部に接合材12を用いずに、互いの材料が拡散し合う直接の接合を用いることで、熱抵抗の高い接合材が介在しない部位が発生するため、接合材の平均厚さが低減し、冷却性能を向上することが可能である。   Since the bonding material 12 is not used at the bonding portion between the semiconductor chip 11 and the concavo-convex portion 131 and a direct bonding in which each material diffuses is used, a portion where no bonding material having a high thermal resistance is present is generated. It is possible to reduce the average thickness of the material and improve the cooling performance.

凹凸部131を、半導体チップ11と実装基材13との接合面における外周の全部もしくは一部に配置形成することで、余剰な接合材12を半導体チップ11外に排出することが可能となり、接合材12の厚さを適正に保ち冷却性能の低下を抑制することができる。   By arranging and forming the uneven portion 131 on the whole or a part of the outer periphery of the bonding surface between the semiconductor chip 11 and the mounting substrate 13, it becomes possible to discharge the excess bonding material 12 outside the semiconductor chip 11. It is possible to keep the thickness of the material 12 properly and to suppress a decrease in cooling performance.

(実施形態4)
図9は本発明の実施形態4に係る半導体モジュールの構成を示す断面図である。
(Embodiment 4)
FIG. 9 is a cross-sectional view showing a configuration of a semiconductor module according to Embodiment 4 of the present invention.

この実施形態4の特徴とするところは、先の実施形態1に対して、半導体チップ11における、実装基材13が接合された側の一方の面(図1では下面)と反対側の面(図1では上面)に電極材91、92を接合したことにある。また、半導体チップ11における、電極材92と接合する側の面に先の実施形態2と同様の凹凸部112を形成したことにある。   The feature of the fourth embodiment is that the surface of the semiconductor chip 11 opposite to the one surface (the lower surface in FIG. 1) of the semiconductor chip 11 on the side to which the mounting substrate 13 is bonded (the lower surface in FIG. 1). This is because the electrode materials 91 and 92 are joined to the upper surface in FIG. In addition, the uneven portion 112 similar to that of the second embodiment is formed on the surface of the semiconductor chip 11 on the side to be joined to the electrode material 92.

半導体チップ11、半導体チップ11の凹凸部112、接合材12、実装基材13、実装基材13の凹凸部131の材質、大きさ、配置、ならびに各部材の接合方法は、先の実施形態1,2と同様である。   The material, size and arrangement of the semiconductor chip 11, the uneven portion 112 of the semiconductor chip 11, the bonding material 12, the mounting base material 13, the uneven portion 131 of the mounting base material 13, and the bonding method of each member are the same as those in the first embodiment. , 2.

電極材91、92は、例えば実装基材13と同様にCuで構成され、電極材91には、先の実施形態1で説明した実装基材13に形成されたのと同様の凹凸部911が形成されている。電極材91、92は、接合材12を介して半導体チップ11に接合される。例えば半導体チップ11にIGBTなどの縦型のトランジスタが形成されている場合には、電極材91にはトランジスタの例えばソース電極が接合され、電極材92にはゲート電極が接合され、ドレイン電極が実装基材13に接合される。   The electrode materials 91 and 92 are made of Cu, for example, similarly to the mounting base material 13. The electrode material 91 has an uneven portion 911 similar to that formed on the mounting base material 13 described in the first embodiment. Is formed. The electrode materials 91 and 92 are bonded to the semiconductor chip 11 via the bonding material 12. For example, when a vertical transistor such as an IGBT is formed on the semiconductor chip 11, for example, a source electrode of the transistor is bonded to the electrode material 91, a gate electrode is bonded to the electrode material 92, and a drain electrode is mounted. Bonded to the substrate 13.

半導体チップ11と実装基材13との接合において、互いの線膨張係数が異なる場合は、実施形態1で採用した構成では、半導体チップ11全体にバイメタル効果により反り応力が発生しやすくなる。このため、半導体チップ11が変形しやすく半導体チップ11の損傷を招きやすくなる。   In the joining of the semiconductor chip 11 and the mounting base material 13, when the linear expansion coefficients are different from each other, in the configuration adopted in the first embodiment, warping stress is likely to be generated in the entire semiconductor chip 11 due to the bimetal effect. For this reason, the semiconductor chip 11 is easily deformed, and the semiconductor chip 11 is easily damaged.

これに対して、この実施形態4では、図9に示すように半導体チップ11の上面に電極材91、92を接合することで、半導体チップ11の下面を上面と同様の接合状態としている。これにより、上述したような反り応力が相殺され、半導体チップ11の変形を抑えることが可能となる。   On the other hand, in the fourth embodiment, as shown in FIG. 9, the electrode materials 91 and 92 are bonded to the upper surface of the semiconductor chip 11 so that the lower surface of the semiconductor chip 11 is in the same bonding state as the upper surface. As a result, the warping stress as described above is offset, and the deformation of the semiconductor chip 11 can be suppressed.

また、半導体チップ11に対して実装基材13に加えて電極材91、92を接合している。このため、実施形態1に比べて、熱伝達経路および熱容量が増加し、半導体チップ11の過渡的な発熱に対して熱の拡散と伝達が俊敏に行われ、過渡的な発熱による半導体チップ11の熱破壊を防ぐことが可能となる。   In addition to the mounting substrate 13, electrode materials 91 and 92 are bonded to the semiconductor chip 11. For this reason, compared with the first embodiment, the heat transfer path and the heat capacity are increased, and the diffusion and transfer of heat is agile with respect to the transient heat generation of the semiconductor chip 11, and the semiconductor chip 11 caused by the transient heat generation. It becomes possible to prevent thermal destruction.

なお、この実施形態4は、半導体チップ11ならびに実装基材13に凹凸部を設けることに代えて、実施形態3で採用したの凹凸部材61を介在させて各部材を接合することも可能である。   In the fourth embodiment, each member can be joined by interposing the concavo-convex member 61 employed in the third embodiment, instead of providing the semiconductor chip 11 and the mounting substrate 13 with the concavo-convex portion. .

半導体モジュールの冷却性能は、熱伝達経路の熱抵抗の大きさに左右され、実装基材13に比べて熱伝導率が低い接合材12の薄化で向上する。この実施形態1では、半導体チップ11の電極部と実装基材13の接合面の端部を跨ぐように凹凸部131を有する。これにより、毛細管現象により半導体チップ11下の接合材12が半導体チップ11の外周の凹凸部131まで流れ出し、半導体チップ11下の接合材12の厚さが減少する。また、凸部と半導体チップ11が近接することにより接合材12の平均厚さは低減し、熱抵抗を低減することで冷却性能を向上することが可能となる。   The cooling performance of the semiconductor module depends on the magnitude of the thermal resistance of the heat transfer path, and is improved by thinning the bonding material 12 having a lower thermal conductivity than the mounting substrate 13. In the first embodiment, the uneven portion 131 is provided so as to straddle the electrode portion of the semiconductor chip 11 and the end portion of the joint surface of the mounting substrate 13. Thereby, the bonding material 12 under the semiconductor chip 11 flows out to the concavo-convex portion 131 on the outer periphery of the semiconductor chip 11 due to a capillary phenomenon, and the thickness of the bonding material 12 under the semiconductor chip 11 decreases. In addition, the average thickness of the bonding material 12 is reduced by the proximity of the convex portion and the semiconductor chip 11, and the cooling performance can be improved by reducing the thermal resistance.

半導体モジュールの長期信頼性は、異種接合部の線膨張係数差および熱応力発生時の応力集中量と各部材の耐力で決まる。この実施形態4では、半導体チップ11と実装基材13が近接する平行面の面積と距離(接合材12の厚さ)で決まるので、平行面の面積の減少および距離の増加により長期信頼性を向上することができる。凹凸部131の凸部は、半導体チップ11に対して傾斜を持つため、半導体チップ11と凸部頂点の近接部の平行面の面積が最少となり、長期信頼性の確保が可能となる。   The long-term reliability of a semiconductor module is determined by the difference in linear expansion coefficient between different types of joints, the amount of stress concentration when thermal stress is generated, and the yield strength of each member. In the fourth embodiment, since the area and distance (thickness of the bonding material 12) of the parallel surface where the semiconductor chip 11 and the mounting substrate 13 are close to each other are determined, long-term reliability is improved by reducing the area of the parallel surface and increasing the distance. Can be improved. Since the convex portion of the concavo-convex portion 131 is inclined with respect to the semiconductor chip 11, the area of the parallel surface between the semiconductor chip 11 and the proximate portion of the convex vertex is minimized, and long-term reliability can be ensured.

半導体チップ11と凹凸部131が点状または線状で近接することにより、近接部の平行面の面積が最少となる。さらに、半導体チップ11と凹凸部131は少なくとも1つ以上の点もしくは線状に近接しているため、凹凸部131の凹部における接合材12の最低厚さが確保されるため、長期信頼性の確保が可能となる。   When the semiconductor chip 11 and the concavo-convex portion 131 are close to each other in a dot shape or a line shape, the area of the parallel surface of the proximity portion is minimized. Further, since the semiconductor chip 11 and the concavo-convex portion 131 are close to each other in at least one point or line shape, the minimum thickness of the bonding material 12 in the concave portion of the concavo-convex portion 131 is ensured, and thus long-term reliability is ensured. Is possible.

半導体チップ11と凹凸部131の接合部に接合材12を用いずに、互いの材料が拡散し合う直接の接合を用いることで、熱抵抗の高い接合材が介在しない部位が発生するため、接合材の平均厚さが低減し、冷却性能を向上することが可能である。   Since the bonding material 12 is not used at the bonding portion between the semiconductor chip 11 and the concavo-convex portion 131 and a direct bonding in which each material diffuses is used, a portion where no bonding material having a high thermal resistance is present is generated. It is possible to reduce the average thickness of the material and improve the cooling performance.

凹凸部131を、半導体チップ11と実装基材13との接合面における外周の全部もしくは一部に配置形成することで、余剰な接合材12を半導体チップ11外に排出することが可能となり、接合材12の厚さを適正に保ち冷却性能の低下を抑制することができる。   By arranging and forming the uneven portion 131 on the whole or a part of the outer periphery of the bonding surface between the semiconductor chip 11 and the mounting substrate 13, it becomes possible to discharge the excess bonding material 12 outside the semiconductor chip 11. It is possible to keep the thickness of the material 12 properly and to suppress a decrease in cooling performance.

半導体チップ11の上面に設けられた電極材91、92を、実装基材13と同様の接合形態にすることでバイメタル効果による反り応力を相殺し、半導体チップ11の変形による破壊を抑えることが可能となる。また、半導体チップ11に対して上下両面の接合により、熱伝達経路および熱容量が増加し、半導体チップ11の過渡的な発熱に対して熱の拡散と伝達を俊敏に行うことが可能となる。これにより、過渡的な発熱による半導体チップ11の熱破壊を防ぐことが可能となる。   By making the electrode materials 91 and 92 provided on the upper surface of the semiconductor chip 11 in the same bonding form as the mounting base material 13, it is possible to cancel the warping stress due to the bimetal effect and to suppress the breakage due to deformation of the semiconductor chip 11. It becomes. Also, the heat transfer path and the heat capacity are increased by bonding the upper and lower surfaces to the semiconductor chip 11, and it becomes possible to quickly diffuse and transfer the heat with respect to the transient heat generation of the semiconductor chip 11. As a result, it is possible to prevent thermal destruction of the semiconductor chip 11 due to transient heat generation.

半導体チップ11の上面に複数の電極材が接合された半導体チップ11において、半導体チップ11の上面に有するすべての電極部を下面と同様の構造にすることで、更にバイメタル効果による反り応力の相殺効果が増大して、反り応力の発生を極力少なくすることができる。これにより、上面に2極以上の電極部を有する半導体チップ11において、半導体チップ11の変形による破壊を抑制することが可能となる。   In the semiconductor chip 11 in which a plurality of electrode materials are bonded to the upper surface of the semiconductor chip 11, all electrode portions on the upper surface of the semiconductor chip 11 have the same structure as that of the lower surface, thereby further canceling the warping stress due to the bimetal effect. Increases, and the generation of warping stress can be minimized. Thereby, in the semiconductor chip 11 having two or more electrode portions on the upper surface, it is possible to suppress the breakage due to the deformation of the semiconductor chip 11.

11…半導体チップ
12…接合材
13…実装基材
61…凹凸部材
91,92…電極材
111,112,131,131−1,131−2,911…凹凸部
611〜616,1311〜1314…凸部
DESCRIPTION OF SYMBOLS 11 ... Semiconductor chip 12 ... Bonding material 13 ... Mounting base material 61 ... Uneven member 91, 92 ... Electrode material 111, 112, 131, 131-1, 131-2, 911 ... Uneven portion 611-616, 1311-1314 ... Convex Part

Claims (8)

接合部材を介して実装基材に半導体チップが実装された半導体モジュールにおいて、
前記実装基材における前記半導体チップと接合する側の面と前記半導体チップにおける前記実装基材と接合する側の面の一方または双方に凹凸が形成され、前記凹凸は、前記半導体チップと前記実装基材とが接合された際に、前記半導体チップの電極部と前記実装基材との接合面の端部を跨ぐように配置され、前記凹凸の頂点間距離は、前記凹凸における凸部の高さと同等以下であり、前記実装基材と前記半導体チップとは、前記凹凸の凸部頂点で最も近接している
ことを特徴とする半導体モジュール。
In a semiconductor module in which a semiconductor chip is mounted on a mounting substrate via a bonding member,
Concavities and convexities are formed on one or both of a surface of the mounting base that is to be joined to the semiconductor chip and a surface of the semiconductor chip that is to be joined to the mounting base, and the concavities and convexities are formed on the semiconductor chip and the mounting base. When the material is bonded, it is arranged so as to straddle the end of the bonding surface between the electrode portion of the semiconductor chip and the mounting substrate, and the distance between the vertices of the unevenness is the height of the protruding portion in the unevenness. A semiconductor module , wherein the mounting substrate and the semiconductor chip are closest to each other at the convex vertex of the irregularities.
前記半導体チップにおける、前記実装基材が接合される面と反対の面に電極材が電気的に接合され、前記電極材における前記半導体チップと接合する側の面と前記半導体チップにおける前記電極材と接合する側の面の一方または双方に凹凸が形成され、前記凹凸は、前記半導体チップと前記電極材とが接合された際に、前記半導体チップの電極部と前記電極材との接合面の端部を跨ぐように配置され、前記電極材と前記半導体チップとは、前記凹凸の凸部頂点で最も近接している
ことを特徴とする請求項1に記載の半導体モジュール。
An electrode material is electrically bonded to a surface of the semiconductor chip opposite to a surface to which the mounting base material is bonded, a surface of the electrode material on the side to be bonded to the semiconductor chip, and the electrode material of the semiconductor chip. Concavities and convexities are formed on one or both of the surfaces to be joined, and the concavities and convexities are edges of the joining surface between the electrode portion of the semiconductor chip and the electrode material when the semiconductor chip and the electrode material are joined. 2. The semiconductor module according to claim 1, wherein the electrode material and the semiconductor chip are disposed closest to each other at a convex vertex of the unevenness.
接合部材を介して実装基材に半導体チップが実装された半導体モジュールにおいて、
前記実装基材と前記半導体チップとの間に凹凸部材を有し、前記凹凸部材は、前記凹凸部材を介在させて前記半導体チップと前記実装基材とが接合された際に、前記半導体チップの電極部と前記実装基材との接合面の端部を跨ぐように配置され、前記凹凸部材の頂点間距離は、前記凹凸部材における凸部の高さと同等以下であり、前記凹凸部材と前記半導体チップとは、前記凹凸部材の凸部頂点で最も近接している
ことを特徴とする半導体モジュール。
In a semiconductor module in which a semiconductor chip is mounted on a mounting substrate via a bonding member,
There is a concavo-convex member between the mounting substrate and the semiconductor chip, and the concavo-convex member is formed on the semiconductor chip when the semiconductor chip and the mounting substrate are joined with the concavo-convex member interposed therebetween. It is arranged so as to straddle the end of the joint surface between the electrode part and the mounting substrate, and the distance between the apexes of the uneven member is equal to or less than the height of the protruded part of the uneven member, and the uneven member and the semiconductor A chip is a semiconductor module that is closest to the apex of the convex portion of the concave-convex member.
前記半導体チップにおける、前記実装基材が接合される面と反対の面に電極材が電気的に接合され、前記電極材と前記半導体チップとの間に凹凸部材を有し、前記凹凸部材は、前記凹凸部材を介在させて前記半導体チップと前記電極材とが接合された際に、前記半導体チップの電極部と前記電極材との接合面の端部を跨ぐように配置され、前記凹凸部材と前記半導体チップとは、前記凹凸部材の凸部頂点で最も近接している
ことを特徴とする請求項3に記載の半導体モジュール。
In the semiconductor chip, an electrode material is electrically bonded to a surface opposite to a surface to which the mounting substrate is bonded, and has a concavo-convex member between the electrode material and the semiconductor chip. When the semiconductor chip and the electrode material are joined with the uneven member interposed, the semiconductor chip and the electrode member are disposed so as to straddle the end of the joint surface between the electrode part and the electrode material, The semiconductor module according to claim 3, wherein the semiconductor chip is closest to a vertex of the convex portion of the concave-convex member.
前記凹凸または前記凹凸部材は、前記半導体チップと前記実装基材または電極材との接合面に対して傾斜を有する形状である
ことを特徴とする請求項1〜4の何れか1項に記載の半導体モジュール。
The said unevenness | corrugation or the said uneven | corrugated member is a shape which has an inclination with respect to the joint surface of the said semiconductor chip and the said mounting base material or an electrode material, The any one of Claims 1-4 characterized by the above-mentioned. Semiconductor module.
前記凹凸または前記凹凸部材の凸部頂点は、少なくとも1以上の点または線状に近接している
ことを特徴とする請求項1〜5の何れか1項に記載の半導体モジュール。
6. The semiconductor module according to claim 1, wherein at least one point or a line is close to the ridge of the concavo-convex or the concavo-convex member.
前記半導体チップと前記実装基材または前記凹凸部材もしくは前記電極材は、前記接合材または直接接合により接合されている
ことを特徴とする請求項1〜6の何れか1項に記載の半導体モジュール。
The semiconductor module according to any one of claims 1 to 6, wherein the semiconductor chip and the mounting substrate or the concavo-convex member or the electrode material are bonded by the bonding material or direct bonding.
前記凹凸または前記凹凸部材は、前記半導体チップと前記実装基材または前記電極材との接合面における外周の全部または一部に配置形成されている
ことを特徴とする請求項1〜7の何れか1項に記載の半導体モジュール。
The unevenness or the unevenness member is disposed and formed on all or part of the outer periphery of the bonding surface between the semiconductor chip and the mounting base material or the electrode material. 2. The semiconductor module according to item 1.
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