JPS59125833U - semiconductor equipment - Google Patents

semiconductor equipment

Info

Publication number
JPS59125833U
JPS59125833U JP1833983U JP1833983U JPS59125833U JP S59125833 U JPS59125833 U JP S59125833U JP 1833983 U JP1833983 U JP 1833983U JP 1833983 U JP1833983 U JP 1833983U JP S59125833 U JPS59125833 U JP S59125833U
Authority
JP
Japan
Prior art keywords
semiconductor element
conductive paste
semiconductor equipment
semiconductor
abstract
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1833983U
Other languages
Japanese (ja)
Inventor
孝志 八木
Original Assignee
日本電気ホームエレクトロニクス株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日本電気ホームエレクトロニクス株式会社 filed Critical 日本電気ホームエレクトロニクス株式会社
Priority to JP1833983U priority Critical patent/JPS59125833U/en
Publication of JPS59125833U publication Critical patent/JPS59125833U/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015—Shape
    • H01L2924/10155—Shape being other than a cuboid
    • H01L2924/10158—Shape being other than a cuboid at the passive surface

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Die Bonding (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は従来例の側断面図、第２図は半導体素子のマウ
ント方法を示す側断面図、第３図は本案の一実施例を示
す側断面図、第４図は要部拡大図、第５図は半導体素子
の下面図である。 図中、１は基板（放熱板）、２は半導体素子、３は銀ペ
ースト、４は溝部、５はリード、６は金属細線、７は樹
脂材である。 第２図FIG. 1 is a side sectional view of a conventional example, FIG. 2 is a side sectional view showing a method of mounting a semiconductor element, FIG. 3 is a side sectional view showing an embodiment of the present invention, and FIG. 4 is an enlarged view of main parts. FIG. 5 is a bottom view of the semiconductor element. In the figure, 1 is a substrate (heat sink), 2 is a semiconductor element, 3 is a silver paste, 4 is a groove, 5 is a lead, 6 is a thin metal wire, and 7 is a resin material. Figure 2

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 基板に半導体素子を導電性ペーストを介在させて固定す
ると共に、半導体素子の電極とリードとを電気的に接続
し、かつ半導体素子を含む主要部分を樹脂材にてモール
ド被覆したものにおいて、上記半導体素子の導電性ペー
ストとの接触面に溝部を形成すると共に、導電性ペース
トの平均的な厚みを１５μｍ以下に設定したことを特徴
とする半導体装置。A semiconductor element is fixed to a substrate with a conductive paste interposed therebetween, electrodes and leads of the semiconductor element are electrically connected, and the main part including the semiconductor element is molded and covered with a resin material. 1. A semiconductor device, characterized in that a groove is formed in a contact surface of an element with a conductive paste, and the average thickness of the conductive paste is set to 15 μm or less.
JP1833983U 1983-02-09 1983-02-09 semiconductor equipment Pending JPS59125833U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1833983U JPS59125833U (en) 1983-02-09 1983-02-09 semiconductor equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1833983U JPS59125833U (en) 1983-02-09 1983-02-09 semiconductor equipment

Publications (1)

Publication Number Publication Date
JPS59125833U true JPS59125833U (en) 1984-08-24

Family

ID=30149541

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1833983U Pending JPS59125833U (en) 1983-02-09 1983-02-09 semiconductor equipment

Country Status (1)

Country Link
JP (1) JPS59125833U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013008771A (en) * 2011-06-23 2013-01-10 Nissan Motor Co Ltd Semiconductor module

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013008771A (en) * 2011-06-23 2013-01-10 Nissan Motor Co Ltd Semiconductor module

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