JP2020136293A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

To provide a semiconductor device in which poor joint of an external terminal fixed to a mounting board and a conductive layer on an insulation board can be prevented, even when the mounting board is bent.SOLUTION: A semiconductor device includes a chip mounting board (1a, 1b) placed on the top face of insulation boards 11a, 11b, and having conductive layers 12a, 12b provided with center side grooves 5b, 5c and peripheral side grooves 5a, 5d at an upper part, a mounting board 3 placed oppositely to the top face of the insulation boards 11a, 11b, and having a peripheral region 102 bending for a central region 101, external terminals 7b, 7c fixed to the central region 101, and having an end joined to joint materials 6b, 6c in the grooves 5b, 5c, and external terminals 7a, 7d fixed to the peripheral region 102, and having an end joined to joint materials 6a, 6d in the grooves 5a, 5d. The end of the external terminals 7b, 7c has a gap height G1 for the end of the external terminals 7a, 7d due to bending of the mounting board 3, and the grooves 5b, 5c and 5a, 5d have a depth D1 deeper than the gap height G1.SELECTED DRAWING: Figure 1

Description

The present invention relates to a semiconductor device having an insulating substrate on which a semiconductor chip is mounted and a mounting substrate such as a printed circuit board, and a method for manufacturing the same.

As a conventional semiconductor module, an insulating substrate on which a semiconductor chip is mounted and a mounting substrate such as a printed circuit board are prepared, and the ends of external terminals fixed to the mounting substrate are soldered to the conductive layer on the insulating substrate. The mounting structure joined together is known.

In such a semiconductor module, the coefficient of thermal expansion of the base material and the wiring material that make up the mounting board are different from each other. There is a possibility that thermal warpage may occur on the mounting board due to heating when joining with solder. If this warp is large, a gap may occur between a part of the external terminals fixed to the mounting board and the conductive layer on the insulating board, resulting in poor bonding.

In Patent Document 1, a recess in which a protrusion electrode of an LSI chip is fitted is formed in a wiring board, a concave LSI connection pad is formed in the recess, and the protrusion electrode of the LSI chip is soldered to the recess LSI connection pad. Is disclosed. However, Patent Document 1 does not disclose anything about bending the LSI chip.

Patent Document 2 discloses that a concave pad portion is provided on the upper surface of a wiring board, and a lead pin of a semiconductor device is inserted into the concave pad portion and joined by soldering. However, Patent Document 2 does not disclose anything about bending of a semiconductor device.

In Patent Document 3, a semiconductor chip is mounted on a wiring board having a wiring pattern, and the surface of the wiring board on the semiconductor chip side is molded with a sealing resin, and the semiconductor device has an external connection terminal side. It is disclosed that there is a warp with a convex shape. Further, in Patent Document 3, the external connection terminal composed of solder bumps connected to the wiring pattern through the through hole formed in the wiring board gradually becomes taller from the center to the outer periphery of the semiconductor device. It is disclosed that the vertices of the external connection terminals are arranged on the same plane and each external connection terminal has a pillar shape.

In Patent Document 4, a joint portion for joining an electrode terminal of a semiconductor element and an electrode terminal of a circuit board is formed on a protruding electrode formed on the electrode terminal of the semiconductor element and an electrode of the circuit board. The area of the tip of the protruding electrode of the semiconductor element including the protruding electrode and the solder is larger than the area of the tip of the protruding electrode of the circuit board, and the area of the portion of the electrode terminal exposed from the circuit board is large. , It is disclosed that there are a plurality of types in the plane of the circuit board.

In Patent Document 5, the arrangement of the plurality of lands of the printed wiring board is such that the corner portion is the first land, the central portion or the innermost peripheral portion is the third land, and the first land and the third land are the first. It is disclosed that it is in 2 lands. However, in Patent Documents 3 to 5, the gap height of the external terminal fixed to the curved mounting board cannot be compensated by the depth of the groove provided in the insulating board arranged to face the mounting board. Nothing is disclosed.

Japanese Unexamined Patent Publication No. 5-175275 JP-A-63-52497 JP-A-2002-164473 Japanese Unexamined Patent Publication No. 2013-239543 Japanese Unexamined Patent Publication No. 2011-103398

In view of the above problems, the present invention prevents poor bonding between the external terminals fixed to the mounting board and the conductive layer on the insulating board arranged to face the mounting board even when the mounting board is curved. It is an object of the present invention to provide a semiconductor device capable of producing a semiconductor device and a method for manufacturing the same.

One aspect of the present invention has (a) an insulating substrate and an upper surface conductive layer having a central groove arranged in a central portion and a peripheral groove arranged in a peripheral portion on the upper surface of the insulating substrate. The chip mounting board, (b) the mounting board which is arranged so as to face the upper surface of the insulating board and whose peripheral region is curved with respect to the central region corresponding to the central portion, and (c) the mounting board so as to penetrate the central region of the mounting board. The outer terminal on the central side, which is fixed to and the end is joined to the joint material in the groove on the central side, and (d) the end is fixed to the joint material in the groove on the peripheral side so as to penetrate the peripheral region of the mounting board. (E) Due to the curvature of the mounting board, the end of the peripheral side external terminal located on the chip mounting board side is the center side external terminal because it is provided with a peripheral side external terminal having the same length as the central side external terminal. It is a gist that the semiconductor device has a gap height with an end portion located on the chip mounting substrate side, and the central groove and the peripheral groove have a depth equal to or higher than the gap height.

Other aspects of the present invention include (a) a step of preparing a chip-mounted substrate having an insulating substrate and an upper surface conductive layer arranged on the upper surface of the insulating substrate, and (b) a central groove and a central groove on the upper surface of the upper surface conductive layer. The process of forming the peripheral groove, (c) the process of mounting the bonding material in the central groove and the peripheral groove, and (d) the central external terminal is fixed so as to penetrate the central region and is the same as the central external terminal. The process of preparing a mounting board in which the peripheral external terminals of the length are fixed so as to penetrate the peripheral area, and (e) the mounting board is opposed to the upper surface side of the insulating layer of the chip mounting board and joined by heating. This includes a step of melting the material and joining the ends of the central external terminal and the peripheral external terminal to the bonding material in the central groove and the peripheral groove, respectively, and the peripheral region with respect to the central region of the mounting substrate by heating. The center side groove and the periphery so as to be equal to or greater than the gap height between the end portion of the central external terminal located on the chip mounting board side and the end portion of the peripheral side external terminal located on the chip mounting substrate side when The gist is that it is a method for manufacturing a semiconductor device that sets the depth of a side groove.

According to the present invention, even when the mounting substrate is curved, a semiconductor capable of preventing poor bonding between an external terminal fixed to the mounting substrate and a conductive layer on an insulating substrate arranged facing the mounting substrate can be prevented. An apparatus and a method for manufacturing the apparatus can be provided.

It is sectional drawing which shows an example of the semiconductor device which concerns on embodiment. It is sectional drawing which shows an example of the semiconductor device which concerns on a comparative example. It is a process sectional view which shows an example of the manufacturing method of the semiconductor device which concerns on embodiment. It is a process cross-sectional view following FIG. 3 which shows an example of the manufacturing method of the semiconductor device which concerns on embodiment. It is a process cross-sectional view following FIG. 4 which shows an example of the manufacturing method of the semiconductor device which concerns on embodiment. It is a process cross-sectional view following FIG. 5 which shows an example of the manufacturing method of the semiconductor device which concerns on embodiment. It is sectional drawing which shows an example of the semiconductor device which concerns on 1st modification of embodiment. It is sectional drawing which shows an example of the semiconductor device which concerns on the 2nd modification of embodiment. It is sectional drawing which shows an example of the semiconductor device which concerns on 3rd modification of embodiment. It is sectional drawing which shows an example of the semiconductor device which concerns on 4th modification of embodiment. It is sectional drawing which shows an example of the semiconductor device which concerns on other embodiment.

Hereinafter, embodiments will be described with reference to the drawings. In the description of the drawings referred to in the following description, the same or similar parts are designated by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between the thickness and the plane dimension, the ratio of the thickness of each layer, etc. are different from the actual ones. Therefore, the specific thickness and dimensions should be determined in consideration of the following explanation. In addition, it goes without saying that the drawings include parts having different dimensional relationships and ratios from each other.

Further, the definition of the vertical direction and the like in the following description is merely a definition for convenience of explanation, and does not limit the technical idea of the present invention. For example, "upper" and "lower" in the "upper surface conductive layer" and "lower surface conductive layer" in the following description are merely selections for convenience, and are not defined with respect to the direction of the earth's gravity. Therefore, it goes without saying that if the object is rotated 90 ° and observed, the top and bottom are converted to left and right and read, and if the object is rotated 180 ° and observed, the top and bottom are reversed and read.

<Semiconductor device>
As shown in FIG. 1, the semiconductor device according to the embodiment is arranged so as to face the upper surface of the chip mounting substrate (1a, 1b) and the chip mounting substrate (1a, 1b), and is a peripheral region with respect to the central region 101. It is a semiconductor module including a mounting substrate 3 in which (peripheral region) 102 has a possibility of being curved. Although not shown in FIG. 1, a sealing material for sealing the periphery of the chip mounting substrate (1a, 1b) and the mounting substrate 3 may be provided.

The chip mounting substrate (1a, 1b) has an insulating substrate (11a, 11b) and an upper surface conductive layer (12a, 12b, 12c, 12d) arranged on the upper surface of the insulating substrate (11a, 11b). As shown in FIG. 1, the insulating substrate (11a, 11b) may be composed of two sheets, a first insulating substrate 11a and a second insulating substrate 11a. In this case, the chip mounting board (1a, 1b) is composed of two boards, a first circuit board 1a and a second circuit board 1b.

The chip mounting substrate (1a, 1b) has an upper surface conductive layer (12a, 12a, which is provided with central groove (recess) 5b, 5c arranged in the central portion and peripheral groove (recess) 5a, 5d arranged in the peripheral portion at the upper portion. It has 12b, 12c, 12d). The central portion of the upper surface conductive layer (12a, 12b, 12c, 12d) corresponds to the central region 101 of the mounting substrate 3, and the peripheral portion of the upper surface conductive layer (12a, 12b, 12c, 12d) is the periphery of the mounting substrate 3. Corresponds to region 102. In FIG. 1, the case where the upper surface conductive layer (12a, 12b, 12c, 12d) is composed of four layers of the first upper surface conductive layer 12a, 12b and the second upper surface conductive layer 12c, 12d is illustrated. .. The number and arrangement positions of the upper surface conductive layers (12a, 12b, 12c, 12d) are not particularly limited.

Each of the first circuit board 1a and the second circuit board 1b may be, for example, a direct copper bonded (DCB) substrate, an active brazing (AMB) substrate, or the like. The first circuit board 1a shown on the left side in FIG. 1 is formed on the first insulating substrate 11a, the first upper surface conductive layers 12a and 12b arranged on the upper surface of the first insulating substrate 11a, and the lower surface of the first insulating substrate 11a. It has a first lower surface conductive layer 13a arranged. The second circuit board 1b shown on the right side in FIG. 1 is formed on the second insulating substrate 11b, the second upper surface conductive layers 12c and 12d arranged on the upper surface of the second insulating substrate 11b, and the lower surface of the second insulating substrate 11b. It has a second lower surface conductive layer 13b arranged.

The first insulating substrate 11a and the second insulating substrate 11b are plate-shaped members composed of insulating ceramics such as aluminum oxide (Al ₂ O ₃ ), aluminum nitride (AlN), and silicon nitride (Si ₃ N ₄ ). is there. As the first upper surface conductive layers 12a and 12b and the second upper surface conductive layers 12c and 12d, and the first lower surface conductive layer 13a and the second lower surface conductive layer 13b, conductor foils such as copper (Cu) and aluminum (Al) are used. It is possible. The lower surfaces of the first lower surface conductive layer 13a and the second lower surface conductive layer 13b may be attached to the cooling fins via the heat radiating metal base. Alternatively, the lower surfaces of the first lower surface conductive layer 13a and the second lower surface conductive layer 13b may be directly attached to the cooling fins.

A first semiconductor element (semiconductor chip) 2a and a second semiconductor element (semiconductor chip) 2b are arranged on the first upper surface conductive layer 12a via bonding materials 4a and 4b such as solder. A third semiconductor element (semiconductor chip) 2c and a fourth semiconductor element (semiconductor chip) 2d are arranged on the second upper surface conductive layer 12c via bonding materials 4c and 4d such as solder. Each of the first semiconductor element 2a to the fourth semiconductor element 2d can be composed of, for example, a transistor such as a MOSFET or an IGBT, or a power semiconductor element such as a thyristor. Each of the first semiconductor element 2a to the fourth semiconductor element 2d may be composed of, for example, a silicon (Si) substrate, or may be composed of a wide bandgap semiconductor substrate such as silicon carbide (SiC) or gallium nitride (GaN). May be good. The type, number, and arrangement position of the first semiconductor element 2a to the fourth semiconductor element 2d are not particularly limited. Further, the bonding materials 4a to 4d are not limited to solder, and may be silver (Ag) or copper (Cu) -based sintered materials.

The electrode on the upper surface of the first semiconductor element 2a is connected to the electrode on the upper surface of the second semiconductor element 2b by a bonding wire 21. The electrodes on the upper surface of the second semiconductor element 2b are connected to the first upper surface conductive layer 12b by the bonding wire 22. The electrode on the upper surface of the third semiconductor element 2c is connected to the electrode on the upper surface of the fourth semiconductor element 2d by the bonding wire 23. The electrodes on the upper surface of the fourth semiconductor element 2d are connected to the second upper surface conductive layer 12d by the bonding wire 24. Instead of the connection using the bonding wires 21 to 24, the connection using a lead frame made of copper (Cu) or the like may be used.

As can be seen from FIG. 1, a peripheral groove 5a is provided on the upper portion of the first upper surface conductive layers 12a and 12b on the one end side, and a central groove is provided on the other end side of the first upper surface conductive layers 12a and 12b. 5b is provided. The end portion of the peripheral side external terminal 7a is inserted into the peripheral side groove 5a and is joined to the first upper surface conductive layer 12a via the solder 6a. The end of the central external terminal 7b is inserted into the central groove 5b and is joined to the first upper surface conductive layer 12b via the solder 6b.

On the other hand, a central groove 5c is provided in the upper portion of the end portion of the second upper surface conductive layers 12c and 12d on the side adjacent to the first circuit board 1a, and is provided in the upper portion on the end side away from the first circuit board 1a. Is provided with a peripheral groove 5d. The end of the central external terminal 7c is inserted into the central groove 5c and is joined to the second upper surface conductive layer 12c via the solder 6c. The end of the peripheral external terminal 7d is inserted into the peripheral groove 5d and is joined to the second upper surface conductive layer 12d via the solder 6d.

In FIG. 1, the case where the bottom surfaces of the central side grooves 5b and 5c and the peripheral side grooves 5a and 5d have a curvature is illustrated, but the bottom surfaces of the central side grooves 5b and 5c and the peripheral side grooves 5a and 5d may be flat. The planar shapes of the central side grooves 5b and 5c and the peripheral side grooves 5a and 5d are not particularly limited as long as the ends of the peripheral side external terminals 7a and 7d and the central side external terminals 7b and 7c can be inserted. The planar shapes of the central side grooves 5b and 5c and the peripheral side grooves 5a and 5d may be, for example, circular or rectangular.

The peripheral external terminals 7a and 7d and the central external terminals 7b and 7c penetrate the mounting board 3 and are fixed to the mounting board 3. As the material of the peripheral side external terminals 7a and 7d and the central side external terminals 7b and 7c, for example, a conductive material such as Cu or Al can be used. The peripheral external terminals 7a and 7d and the central external terminals 7b and 7c are, for example, cylindrical, but may have other shapes such as prismatic, plate-shaped, and block-shaped. The peripheral external terminals 7a and 7d and the central external terminals 7b and 7c transfer the potentials of the first semiconductor elements 2a to 4th semiconductor elements 2d via the first upper surface conductive layers 12a and 12b and the second upper surface conductive layers 12c and 12d. And take it out.

The mounting board 3 can be composed of a printed circuit board having an insulating layer 31, a first wiring layer 32 arranged on the upper surface side of the insulating layer 31, and a second wiring layer 33 arranged on the lower surface side of the insulating layer 31. .. The mounting substrate 3 may be a multilayer substrate having two or more insulating layers, in which insulating layers and wiring layers are alternately laminated.

The insulating layer 31 may be a resin substrate made of a combination of glass fiber and epoxy resin or the like. Further, the insulating layer 31 may be a ceramic substrate containing Al ₂ O ₃ , Al N, Si ₃ N ₄ or the like as a main component.

As the material of the first wiring layer 32 and the second wiring layer 33, for example, a conductive material such as a metal such as silver (Ag), copper (Cu), or aluminum (Al) can be used. The first wiring layer 32 and the second wiring layer 33 may be laminated with a Cu plate or an Al plate, or may be plated with Cu, nickel (Ni), tin (Sn), or the like. The thickness of the first wiring layer 32 and the second wiring layer 33 may be a relatively thin wiring layer of about 10 μm or more and 50 μm or less, or a relatively thick wiring layer of about 1 mm or more and about 3 mm or less.

In the manufacturing process of the semiconductor device according to the embodiment, the mounting substrate 3 may be warped due to thermal deformation or an external force generated in the assembly process. For example, since the insulating layer 31 of the mounting substrate 3 and the first wiring layer 32 and the second wiring layer 33 have different coefficients of thermal expansion, the difference in the pattern shape and thickness of each layer affects the mounting during the manufacturing process. Thermal warpage occurs on the substrate 3. Here, with respect to the central region 101 of the mounting substrate 3 of FIG. 1, peripheral regions 102 are defined and described on both sides of the central region 101. FIG. 1 illustrates a case where the peripheral region 102 is curved with respect to the central region 101 of the mounting substrate 3 due to thermal warpage. That is, in FIG. 1, it is assumed that the mounting board 3 is curved convexly toward the first circuit board 1a and the second circuit board 1b.

In the situation shown in FIG. 1, the ends of the external terminals 7b and 7c located in the central region 101 of the mounting board 3 are larger than the ends of the peripheral external terminals 7a and 7d located in the peripheral region 102 of the mounting board 3. , The gap height G1 protrudes toward the lower first circuit board 1a and the second circuit board 1b. That is, the gap height between the ends of the external terminals 7b and 7c located in the central region 101 of the mounting board 3 and the ends of the peripheral external terminals 7a and 7d located in the peripheral region 102 of the mounting board 3 is 1 minute. Have a difference.

The central side grooves 5b, 5c and the peripheral side grooves 5a, 5d provided in the first upper surface conductive layers 12a, 12b and the second upper surface conductive layers 12c, 12d are provided so as to have a depth D1 having a gap height G1 or more. ing. Therefore, the ends of the external terminals 7b and 7c located in the central region 101 of the mounting substrate 3 are inserted deep into the grooves 5b and 5c to be joined to the joining materials 6b and 6c. On the other hand, the ends of the peripheral external terminals 7a and 7d located in the peripheral region 102 of the mounting substrate 3 are inserted to shallow positions near the openings of the grooves 5a and 5d to be joined to the joining materials 6a and 6d. The ends of the peripheral external terminals 7a and 7d located in the peripheral region 102 of the mounting substrate 3 are not inserted into the grooves 5a and 5d, but are formed from the upper surfaces of the first upper surface conductive layer 12a and the second upper surface conductive layer 12d. May be joined to the joining materials 6a and 6d at an upper position.

That is, the peripheral side external terminals 7a, 7d and the central side are provided by the depth D1 of the central side grooves 5b, 5c and the peripheral side grooves 5a, 5d provided in the first upper surface conductive layers 12a, 12b and the second upper surface conductive layers 12c, 12d. The gap height G1 at the ends of the external terminals 7b and 7c can be compensated, and the peripheral external terminals 7a and 7d, the central external terminals 7b and 7c, the first upper surface conductive layers 12a and 12b, and the second upper surface conductive layer can be compensated. It is possible to prevent poor bonding with 12c and 12d.

<Comparison example>
Here, the semiconductor device according to the comparative example will be described. As shown in FIG. 2, the semiconductor device according to the comparative example is basically the same as the configuration of the semiconductor device according to the embodiment, but the first upper surface conductive layers 12a and 12b and the second upper surface conductive layers 12c and 12d. The configuration of the semiconductor device according to the embodiment is different from that of the semiconductor device in that the central grooves 5b and 5c and the peripheral grooves 5a and 5d are not provided in the upper part of the above. In the semiconductor device according to the comparative example, the bonding materials 6a to 6d are arranged on the first upper surface conductive layers 12a and 12b and the second upper surface conductive layers 12c and 12d.

The ends of the external terminals 7b and 7c located in the central region 101 of the mounting board 3 are chip mounting boards having a gap height G1 more than the ends of the peripheral external terminals 7a and 7d located in the peripheral region 102 of the mounting board 3. It protrudes to the (1a, 1b) side. Therefore, the ends of the external terminals 7b and 7c located in the central region 101 of the mounting substrate 3 are joined to the bonding materials 6b and 6c on the first upper surface conductive layer 12b and the second upper surface conductive layer 12c. At the ends of the peripheral external terminals 7a and 7d located in the peripheral region 102 of the mounting substrate 3, a gap is generated between the first upper surface conductive layer 12a and the bonding materials 6a and 6d on the second upper surface conductive layer 12d. , The joint is poor.

On the other hand, according to the semiconductor device according to the embodiment, as shown in FIG. 1, even if the mounting substrate 3 is warped, the ends of the central external terminals 7b and 7c are the central grooves 5b and 5c. At the position of, it penetrates deeper than the outermost surfaces of the first upper surface conductive layer 12b and the second upper surface conductive layer 12c, and the ends of the peripheral side external terminals 7a and 7d and the first upper surface conductive layer 12a and the second upper surface conductive layer 12d The gap can be closed. Therefore, it is possible to prevent poor bonding between the external terminals 7a to 7d fixed to the mounting board 3 and the upper conductive layers (12a, 12b, 12c, 12d) of the chip mounting board (1a, 1b), and the electricity can be prevented. Conduction can be ensured.

<Manufacturing method of semiconductor module>
Next, an example of the method for manufacturing the semiconductor device according to the embodiment will be described with reference to FIGS. 3 to 6 and the like.

First, as shown in FIG. 3, a mounting board 3 including an insulating layer 31, a first wiring layer 32, and a second wiring layer 33 is prepared. Then, the peripheral side external terminals 7a and 7d and the central side external terminals 7b and 7c are inserted into the through holes formed in the mounting board 3 and fixed. The peripheral external terminals 7a and 7d and the central external terminals 7b and 7c may be fixed by press fitting or may be fixed by a joining material such as solder. At the stage of FIG. 3, the mounting substrate 3 may not be curved and may be flat.

On the other hand, as shown in FIG. 4, a first circuit board 1a composed of a first insulating substrate 11a, a first upper surface conductive layer 12a, 12b and a first lower surface conductive layer 13a, a second insulating substrate 11b, and a second upper surface conductive layer A chip-mounted substrate (1a, 1b) composed of a second circuit board 1b composed of 12c, 12d and a second lower surface conductive layer 13b is prepared. Then, a peripheral groove 5a is provided above the planned connection position of the first upper surface conductive layer 12a with the peripheral external terminal 7a, and a central groove 5b is provided above the planned connection position of the first upper surface conductive layer 12b with the central external terminal 7b. To form. Similarly, a central groove 5c is provided above the planned connection position of the second upper surface conductive layer 12c with the central external terminal 7c, and a peripheral groove is provided above the planned connection position of the second upper surface conductive layer 12d with the peripheral external terminal 7d. Form 5d. The central side grooves 5b, 5c and the peripheral side grooves 5a, 5d may be formed by chemical etching, physical drilling, or laser irradiation. As for the depth D1 of the central side grooves 5b, 5c and the peripheral side grooves 5a, 5d, the gap height G1 when the mounting substrate 3 is warped is obtained in advance by an experiment or the like as shown in FIG. 1, and the gap height G1 It is set to be as above.

Next, a paste-like or plate-like Ag or Cu system is printed or dispensed at the planned mounting positions of the first semiconductor element 2a to the fourth semiconductor element 2d on the first upper surface conductive layer 12a and the second upper surface conductive layer 12c. 4a to 4d of the bonding materials made of the sintered material of the above are applied. Then, as shown in FIG. 5, the first semiconductor element 2a to the fourth semiconductor element 2d are mounted on the first upper surface conductive layer 12a and the second upper surface conductive layer 12c, and the first semiconductor element 2a to the fourth semiconductor element 2d The first upper surface conductive layer 12a and the second upper surface conductive layer 12c are joined via the bonding materials 4a to 4d. Further, the bonding wires 21 to 24 provide between the electrodes on the upper surface of the first semiconductor element 2a and the electrodes on the upper surface of the second semiconductor element 2b, and the electrodes on the upper surface of the second semiconductor element 2b and the first upper surface conductive layer 12b. Between the electrodes on the upper surface of the third semiconductor element 2c and the electrodes on the upper surface of the fourth semiconductor element 2d, and between the electrodes on the upper surface of the fourth semiconductor element 2d and the conductive layer 12d on the second upper surface, respectively.

Next, as shown in FIG. 6, a plate shape is used in the central side grooves 5b, 5c and the peripheral side grooves 5a, 5d provided in the first upper surface conductive layers 12a, 12b and the second upper surface conductive layers 12c, 12d. Alternatively, the bonding materials 6a to 6d such as paste-like solder are mounted.

Next, the first circuit board 1a and the second circuit board 1b, and the mounting board 3 to which the peripheral external terminals 7a and 7d and the central external terminals 7b and 7c shown in FIG. 3 are fixed are attached to a jig such as carbon. To overlap and face each other using. Then, the bonding materials 6a to 6d are melted by heating at a temperature of 200 ° C. or higher and 350 ° C. or lower to melt the peripheral side external terminals 7a and 7d and the central side external terminals 7b and 7c fixed to the mounting substrate 3. Is inserted into the central grooves 5b, 5c and the peripheral grooves 5a, 5d of the upper surface conductive layer (12a, 12b, 12c, 12d) to be joined.

Due to the heating at this time, thermal warpage occurs in the mounting substrate 3 as shown in FIG. 2. It penetrates deeper than the outermost surface of the upper surface conductive layer 12c, and can eliminate the gap between the end portions of the peripheral external terminals 7a and 7d and the first upper surface conductive layer 12a and the second upper surface conductive layer 12d. Therefore, it is possible to suppress the occurrence of poor bonding between the end portions of the peripheral side external terminals 7a and 7d and the central side external terminals 7b and 7c and the upper surface conductive layer (12a, 12b, 12c, 12d) and ensure electrical continuity. can do.

According to the method for manufacturing a semiconductor device according to the embodiment, even when the mounting substrate 3 is curved, the external terminals 7a to 7d fixed to the mounting substrate 3 and the upper surface conductive layer (12a) of the chip mounting substrate (1a, 1b) , 12b, 12c, 12d) can be prevented from being poorly joined.

The method for manufacturing a semiconductor device according to the above-described embodiment is an example, and is not limited thereto. For example, when both the bonding materials 4a to 4d and the bonding materials 6a to 6d are solders, the first semiconductor element 2a to the fourth semiconductor element 2d are bonded to the first upper surface conductive layer 12a and the second upper surface conductive layer 12c. The steps of joining via the materials 4a to 4d and the end portions of the peripheral side external terminals 7a and 7d and the central side external terminals 7b and 7c fixed to the mounting substrate 3 are formed by the upper surface conductive layer (12a, 12b, 12c, 12d). The step of joining the solders via the bonding materials 6a to 6d may be performed at the same time. After that, the bonding wires 21 to 24 of the first semiconductor element 2a to the fourth semiconductor element 2d may be connected.

<First modification>
In the semiconductor device according to the first modification of the embodiment, as shown in FIG. 7, the mounting board 3 is curved in a convex shape on the side opposite to the first circuit board 1a and the second circuit board 1b side. It differs from the configuration of the semiconductor device according to the embodiment shown in FIG.

In the semiconductor device according to the first modification of the embodiment, the chip mounting substrate (1a, 1b) has a gap height G1 between the ends of the peripheral external terminals 7a and 7d and the ends of the central external terminals 7b and 7c. Protruding to the side. The central side grooves 5b and 5c and the peripheral side grooves 5a and 5d have a depth D1 having a gap height G1 or more. The ends of the peripheral external terminals 7a and 7d can be inserted deep into the peripheral grooves 5a and 5d and connected to the first upper surface conductive layer 12a and the second upper surface conductive layer 12d via the bonding materials 6a and 6d. On the other hand, the ends of the central external terminals 7b and 7c are inserted at shallow positions near the openings of the central grooves 5b and 5c, and the first upper surface conductive layer 12b and the second upper surface conductive layer 12b and the second upper surface conductive via the bonding materials 6b and 6c. Can be connected to layer 12c. Since the other configurations are substantially the same as the configurations of the semiconductor device according to the embodiment shown in FIG. 1, duplicate description will be omitted.

According to the semiconductor device according to the first modification of the embodiment, even when the mounting board 3 is convexly curved to the side opposite to the first circuit board 1a and the second circuit board 1b side, the mounting board It is possible to prevent poor bonding between the external terminals 7a to 7d fixed to 3 and the upper surface conductive layers (12a, 12b, 12c, 12d) of the chip mounting substrate (1a, 1b).

<Second modification>
As shown in FIG. 8, the semiconductor device according to the second modification of the embodiment is a single piece in which the first insulating substrate 11a and the second insulating substrate 11b of the first circuit board 1a and the second circuit board 1b are connected to each other. It is different from the configuration of the semiconductor device according to the embodiment shown in FIG. 1 in that it is composed of the insulating substrates (11a, 11b) of. Further, the first lower surface conductive layer 13a and the second lower surface conductive layer 13b of the first circuit board 1a and the second circuit board 1b are connected to each other and are composed of one second conductive layer (13a, 13b). However, the configuration of the semiconductor device according to the embodiment shown in FIG. 1 is different. Since the other configurations are substantially the same as the configurations of the semiconductor device according to the embodiment shown in FIG. 1, duplicate description will be omitted.

<Third modification example>
As shown in FIG. 9, the semiconductor device according to the third modification of the embodiment has only the central grooves 5b and 5c in the first upper surface conductive layer 12b and the second upper surface conductive layer 12c below the central region 101 of the mounting substrate 3. The point that the peripheral side grooves 5a and 5d are not provided in the first upper surface conductive layer 12a and the second upper surface conductive layer 12d below the peripheral region 102 of the mounting substrate 3 is related to the embodiment shown in FIG. It is different from the configuration of the semiconductor device.

In the semiconductor device according to the third modification of the embodiment, the peripheral side external terminals 7a and 7d are the first upper surface conductive layer via the bonding materials 6a and 6d on the first upper surface conductive layer 12a and the second upper surface conductive layer 12d. It is connected to 12a and the second upper surface conductive layer 12d. On the other hand, the central side external terminals 7b and 7c are inserted into the central side grooves 5b and 5c and are connected to the first upper surface conductive layer 12b and the second upper surface conductive layer 12c via the bonding materials 6b and 6c. Since the other configurations are substantially the same as the configurations of the semiconductor device according to the embodiment shown in FIG. 1, duplicate description will be omitted.

According to the semiconductor device according to the third modification of the embodiment, even when the first upper surface conductive layer 12b and the second upper surface conductive layer 12c below the central region 101 of the mounting substrate 3 have only the central side grooves 5b and 5c. It is possible to prevent poor bonding between the external terminals 7a to 7d fixed to the mounting board 3 and the upper conductive layers (12a, 12b, 12c, 12d) of the chip mounting board (1a, 1b).

<Fourth modification>
As shown in FIG. 10, the semiconductor device according to the fourth modification of the embodiment has only peripheral grooves 5a and 5d in the first upper surface conductive layer 12a and the second upper surface conductive layer 12d below the peripheral region 102 of the mounting substrate 3. The point that the central side grooves 5b and 5c are not provided in the first upper surface conductive layer 12b and the second upper surface conductive layer 12c below the central region 101 of the mounting substrate 3 is related to the embodiment shown in FIG. It is different from the configuration of the semiconductor device.

In the semiconductor device according to the fourth modification of the embodiment, the central side external terminals 7b and 7c are the first upper surface conductive layer via the bonding materials 6b and 6c on the first upper surface conductive layer 12b and the second upper surface conductive layer 12c. It can be connected to 12b and the second upper surface conductive layer 12c. On the other hand, the peripheral external terminals 7a and 7d can be inserted into the grooves 5a and 5d and connected to the first upper surface conductive layer 12a and the second upper surface conductive layer 12d via the bonding materials 6a and 6d. Since the other configurations are substantially the same as the configurations of the semiconductor device according to the embodiment shown in FIG. 1, duplicate description will be omitted.

According to the semiconductor device according to the fourth modification of the embodiment, even when the first upper surface conductive layer 12a and the second upper surface conductive layer 12d below the peripheral region 102 of the mounting substrate 3 have only peripheral side grooves 5a and 5d. It is possible to prevent poor bonding between the external terminals 7a to 7d fixed to the mounting board 3 and the upper conductive layers (12a, 12b, 12c, 12d) of the chip mounting board (1a, 1b).

(Other embodiments)
As mentioned above, although the present invention has been described by embodiment, the discourses and drawings that form part of this disclosure should not be understood to limit the invention. Various alternative embodiments, examples and operational techniques will be apparent to those skilled in the art from this disclosure.

For example, in the semiconductor device according to the embodiment, the case where the mounting substrate 3 is curved has been described, but as shown in FIG. 11, the mounting substrate 3 is not curved, and the central region 101 and the peripheral region 102 are flat. You may. In this case, the peripheral side external terminals 7a and 7d and the central side external terminals 7b and 7c do not have a gap height. The peripheral external terminals 7a and 7d and the central external terminals 7b and 7c are inserted into the central grooves 5b and 5c and the peripheral grooves 5a and 5d by the same depth, and are electrically conductive on the first upper surface via the bonding materials 6a to 6d. It is joined to the layers 12a and 12b and the second upper surface conductive layers 12c and 12d.

As described above, it goes without saying that the present invention includes various embodiments not described here. Therefore, the technical scope of the present invention is defined only by the matters specifying the invention relating to the reasonable claims from the above description.

1a ... 1st circuit board 1b ... 2nd circuit board 2a ... 1st semiconductor element 2b ... 2nd semiconductor element 2c ... 3rd semiconductor element 2d ... 4th semiconductor element 3 ... Mounting board 4a, 4b, 4c, 4d ... Bonding material 5a, 5d ... Peripheral side grooves 5b, 5c ... Central side grooves 6a, 6b, 6c, 6d ... Bonding material 7a, 7d ... Peripheral side external terminals 7b, 7c ... Central side external terminals 11a ... First insulating substrate 11b ... Second insulating substrate 12a, 12b ... 1st upper surface conductive layer 12c, 12d ... 2nd upper surface conductive layer 13a ... 1st lower surface conductive layer 13b ... 2nd lower surface conductive layer 21, 22, 23, 24 ... Bonding wire 31 ... Insulation layer 32 ... 1st Wiring layer 33 ... Second wiring layer 101 ... Central area 102 ... Peripheral area

Claims (5)

A chip-mounted substrate having an insulating substrate, an upper surface conductive layer having a central groove arranged in a central portion and a peripheral groove arranged in a peripheral portion on the upper surface of the insulating substrate, and a top conductive layer.
A mounting board which is arranged so as to face the upper surface of the insulating substrate and whose peripheral region is curved with respect to the central region corresponding to the central portion.
A central external terminal fixed so as to penetrate the central region of the mounting substrate and having an end bonded to a bonding material in the central groove.
A peripheral external terminal having the same length as the central external terminal, which is fixed so as to penetrate the peripheral region of the mounting substrate and whose end is bonded to the bonding material in the peripheral groove,
With
Due to the curvature of the mounting board, the end portion of the peripheral side external terminal located on the chip mounting board side has a gap height with the end portion of the central side external terminal located on the chip mounting board side.
A semiconductor device characterized in that the central groove and the peripheral groove have a depth equal to or greater than the gap height. The chip mounting board
A first circuit board having a first upper surface conductive layer having the central groove on one end side and the peripheral groove on the other end side.
A second upper surface conductive layer having the central groove on the end side adjacent to the first circuit board and the peripheral groove on the end side on the side away from the first circuit board. 2 circuit boards and
The semiconductor device according to claim 1, wherein the semiconductor device comprises. The semiconductor device according to claim 1 or 2, wherein the mounting substrate is curved in a convex shape toward the chip mounting substrate side. The semiconductor device according to claim 1 or 2, wherein the mounting substrate is curved in a convex shape on a side opposite to the chip mounting substrate side. A step of preparing a chip-mounted substrate having an insulating substrate and a top conductive layer arranged on the upper surface of the insulating substrate, and
A step of forming a central groove and a peripheral groove on the upper part of the upper surface conductive layer, and
The process of mounting the bonding material in the central groove and the peripheral groove, and
A process of preparing a mounting board in which the central external terminal is fixed so as to penetrate the central region and the peripheral external terminal having the same length as the central external terminal is fixed so as to penetrate the peripheral region.
The mounting substrate is opposed to the upper surface side of the insulating layer of the chip mounting substrate, the bonding material is melted by heating, and the ends of the central side external terminal and the peripheral side external terminal are formed into the central side groove. And the process of joining to the joining material in the peripheral groove, respectively.
Including
When the peripheral region is curved with respect to the central region of the mounting substrate due to the heating, the end portion of the central external terminal located on the chip mounting substrate side and the peripheral region external terminal located on the chip mounting substrate side. A method for manufacturing a semiconductor device, characterized in that the depths of the central groove and the peripheral groove are set so as to be equal to or larger than the gap height with the end portion.

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