JP2012129336A - Semiconductor device and manufacturing method of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which improves positioning accuracy at low cost and achieves the size reduction and high density assembly of a semiconductor chip, and to provide a manufacturing method of the semiconductor device.SOLUTION: A first recessed part 5 on which a semiconductor chip 9 is placed is formed on a conductive pattern 4 of an insulation substrate with conductive patterns 1. A positioning external terminal 17 fastened to each conductive pattern 4 penetrates through a through hole 12 of a printed substrate with post pins 11, thereby positioning tips of the post pins 16 on a gate pad 9b and an emitter electrode pad 9a of the semiconductor chip 9. This structure significantly improves the positioning accuracy of the post pins 16 on the pad 9b at low cost.

Description

  The present invention relates to a semiconductor device such as a semiconductor module and a manufacturing method thereof.

  14A and 14B are configuration diagrams of a conventional power semiconductor module 700. FIG. 14A is a plan view of the main part, and FIG. 14B is a cross-sectional view of the main part taken along line XX of FIG. It is. FIG. 15 is a plan view of a main part arranged in the conductive pattern 53 when the semiconductor chip 55 shown in FIG. 14 is an IGBT (insulated gate bipolar transistor) chip. A dotted circle 67 indicates the position of the post pin 57.

  In FIG. 14, a power semiconductor module 700 includes a cooling base 52, an insulating substrate 51 with a conductive pattern that is fixed to the cooling base 52 directly or via a bonding material such as solder, and a conductive pattern 53 with solder 54. A semiconductor chip 55 whose back surface is fixed, a post pin 57 fixed to the surface of the semiconductor chip 55 with solder 56, an external terminal 59 fixed to the recess 58 of the conductive pattern 53 with solder 54, and a post pin 57. The printed board 60 with post pins to be fixed and the through holes 61 of the printed board 60 with post pins through which the external terminals 59 penetrate. A conductive pattern 62 is formed on the front side of the printed circuit board 60 with post pins. Reference numeral 63 in the figure denotes solder for electrically connecting and fixing the external terminal 59 electrically connected to the gate pad 55b and the conductive pattern 62.

  In this power semiconductor module 700, the semiconductor chip 55 is joined to the insulating substrate 51 with the conductive pattern by the solder 54, and the electric wiring with the surface electrodes (gate pad 55b, emitter electrode pad 55a) of the semiconductor chip 55 is connected to the printed board 60 with post pins. The post pin 57 has a structure (see, for example, Patent Document 5).

FIG. 16 shows a method of manufacturing the power semiconductor module of FIG. 14, and FIGS. 16A to 18C are cross-sectional views of the main part manufacturing process shown in the order of steps.
In FIG. 2A, the semiconductor chip 55 is placed in the recess 72 of the carbon jig 71, and the solder 56 is placed on the semiconductor chip 55. The printed circuit board 60 with post pins is inserted into the carbon jig 71 from above, and the tips of the post pins 57 are brought into contact with the solder 56.

  Next, in FIG. 4B, the assembly of FIG. 6A is melted and solidified by solder 56 in a reflow furnace, and the surface electrode (gate pad 55b, emitter electrode pad 55a) of the semiconductor chip 55 and the post pin are assembled. The tip of 57 is fixed. Subsequently, the insulating substrate 51 with the conductive pattern is put in another carbon jig 73, the solder 54 is placed on the conductive pattern 53, and the printed circuit board 60 with the post pin with the semiconductor chip 55 is placed thereon from the carbon jig 73. The solder 54 and the back surface of the semiconductor chip 55 are brought into contact with each other. Further, the external terminal 59 is brought into contact with the solder 54 in the recess 58 on the conductive pattern 53 through the through hole 61 of the printed circuit board 60 with post pins.

  Next, in FIG. 4C, the assembly of FIG. 4B is melted and solidified by a reflow furnace, and the back surface of the semiconductor chip 55 and the external terminal 59 are fixed to the conductive pattern 53. . Thereafter, the assembly is taken out from the flow furnace and sealed with the resin 64, and then the thick cooling base 52 on the back surface is ground and flattened.

  Further, in Patent Document 1, by soldering the periphery of the semiconductor chip mounting portion on the metal plate in the bonding substrate between the ceramic substrate and the metal plate, the solder for fixing the semiconductor chip flows or the position of the semiconductor chip It is described that the shift is prevented.

  Further, in Patent Document 2, in a semiconductor module in which a semiconductor chip is mounted on a metal base, a recess is formed at a predetermined position where the semiconductor chip is mounted at the same time as the punching process of the metal base. It is described that positioning can be performed.

  Further, in Patent Document 3, a land pattern for soldering a semiconductor chip for joining the entire bottom surface of a semiconductor chip to be mounted on a substrate via solder is formed with a solder resist, and is formed at four corners of the bottom surface of the semiconductor chip. A pattern having substantially matching corners and solder reservoirs (relief portions) protruding outward from the sides corresponding to the sides of the bottom surface of the semiconductor chip. By doing so, it is described that the semiconductor chip can be positioned at a predetermined position with high accuracy with a simple configuration by positioning the semiconductor chip using the self-alignment effect without using a positioning jig. .

  Further, in Patent Document 4, a solder dam (inside the dam is a solder reservoir) that dams the flow of molten solder so as to surround the periphery of the semiconductor chip in order to prevent unnecessary spread of the molten solder on the heat spreader. ) Is provided in a convex shape. The height of the convex portion is about the thickness of the solder. Further, among the convex solder dams, linear convex portions are formed along the sides of the rectangular semiconductor chip. At the corner, the convex part is formed in a circular shape so that the melted solder away from the corner of the semiconductor chip spreads outward, and the semiconductor chip is positioned by self-alignment with respect to the inclination of the semiconductor chip and the heat spreader. It is described that it can be controlled simply and inexpensively.

  In Patent Document 5, in a semiconductor device such as a power semiconductor module, a metal foil is formed on the first main surface of the insulating plate, and at least one other metal foil is formed on the second main surface of the insulating plate. Is done. In addition, the printed circuit board is disposed so as to face at least one semiconductor chip bonded on another metal foil and the main surface of the insulating plate on which the semiconductor chip is disposed. The metal foil formed on the first main surface of the printed circuit board or another metal foil formed on the second main surface of the printed circuit board and the main electrode of the semiconductor chip are formed by a plurality of post electrodes (post pins). Electrically connected. Thus, it is described that a semiconductor device having high reliability, excellent operating characteristics, and high productivity can be obtained.

  In Patent Document 6, a conductive post (post pin) and an external terminal are soldered to a printed circuit board by first solder reflow. On the surface of the thick metal block bonded to the metal foil bonding insulating substrate (insulating substrate with conductive pattern), a protrusion serving as a chip positioning means is formed around the bonding region of the semiconductor chip, and the semiconductor chip is subjected to the second solder reflow. Positioning was performed. Thus, it is described that the semiconductor chip can simultaneously perform solder bonding with the thick metal block and the conductive post by solder under the chip and solder on the chip.

JP-A-10-242331 JP 2000-31358 A JP 2002-353255 A JP 2010-10574 A JP 2009-64852 A JP 2010-165664 A

  In the power semiconductor module 700 of FIG. 14 described above, the alignment of the semiconductor chip 55 and the post pin 57 is performed via the carbon jig 71. In order to take out the semiconductor chip 55 from the recess 72 of the carbon jig 71, it is necessary to provide play (the distance D1 is about 0.2 mm) between the recess 72 of the carbon jig 71 and the semiconductor chip 55. Further, in order to take out the printed circuit board 60 with post pins from the carbon jig 71, it is necessary to provide play (the distance D2 is about 0.2 mm) between the printed circuit board 60 with post pins and the carbon jig 71.

  Further, in order to take out the insulating substrate 51 with the conductive pattern from the carbon jig 73, it is necessary to provide play (the distance D3 is about 0.2 mm) between the insulating substrate 51 with the conductive pattern and the carbon jig 73. However, this play (interval D3) does not cause a problem with respect to the positional deviation between the semiconductor chip 55 and the conductive pattern 53 because the conductive pattern 53 has a large area.

  In the process of FIG. 16A, the positional deviation between the post pin 57 and the semiconductor chip 55 is about D1 + D2 = 0.4 mm. The process shown in FIG. 16B is entered with this misalignment, the solder 54 is melted in a reflow furnace, and then solidified, and the post pins 57 and the semiconductor chip 55 are soldered. Therefore, the positional deviation between the post pin 57 and the semiconductor chip 55 is about 0.4 mm at the maximum. The positional misalignment between the gate electrode 55b and the post pin 57 having a small area on the surface electrode is 0.4 mm at the maximum.

  The semiconductor chip 55 is placed on the conductive pattern 53 via the solder 54 in a state where the positional deviation has occurred. Subsequently, the solder 56 once solidified on the semiconductor chip 55 and the solder 54 below the semiconductor chip 55 are melted and then solidified in a reflow furnace. At this time, the semiconductor chip 55 is displaced with respect to the position (initial position) before the solders 54 and 56 are melted. As shown in FIG. 17 to be described later, this positional deviation is about 0.3 mm at the maximum.

Therefore, the positional deviation between the post pin 57 and the gate pad 55b is about 0.3 mm + about 0.4 mm = about 0.7 mm at the maximum.
As described above, when the carbon jigs 71 and 73 are used, the alignment accuracy between the gate pad 55b of the semiconductor chip 55 and the post pin 57 is significantly lowered. For this reason, it is difficult to reduce the size of the semiconductor chip 55, and it is difficult to increase the integration of the semiconductor chip 55.

  On the other hand, in recent years, WBG (Wide Band Gap) elements are used to improve the performance of power semiconductor modules. As a typical example, a SiC (silicon carbide) element capable of high-temperature operation is used, but this SiC element is smaller in size than the Si element at the same rating, and the size of the gate pad and the emitter electrode pad (MOSFET). In this case, the size of the source electrode pad) is reduced. Therefore, the alignment accuracy between the post pins and these pads needs to be higher than that of the Si element.

FIG. 17 is a diagram showing a positional deviation from an initial position before melting a semiconductor chip and solder of a conventional power semiconductor module.
The measurement of the positional deviation is performed by measuring the distance from the center of the initial position 65 placed on the conductive pattern 53 to the center of the semiconductor chip 55 with 20 samples in the X direction and the Y direction, and calculating the larger value. Adopted. From FIG. 17, the positional deviation occurs from 0.1 mm to 0.3 mm around 0.2 mm.

  In the above-mentioned Patent Document 1, the depth of the step processing into which only solder is fitted, and the chip positioning largely depends on the self-alignment effect of the solder. In mounting only by this self-alignment effect, the chip may protrude from the stepped portion, and high-precision positioning is difficult.

Further, in Patent Documents 1 and 2, since there is no enlargement processing that becomes a solder reservoir (solder dam), position correction is not performed well, and there is a concern about an increase in voids.
Further, in Patent Document 3, since the size of the enlargement process of the solder reservoir (solder escape portion) is about 1 mm, the interval between the semiconductor chips needs to be 2 mm or more. It becomes difficult. In addition, since the solder reservoir is formed of a solder resist, a manufacturing cost increases if a photolithography process is used for the solder resist patterning.

  Further, in Patent Document 4, since the solder dam is formed of a solder resist, if a photolithography process is used for patterning the solder resist, the manufacturing cost increases. Moreover, since the width of this solder resist is as narrow as 20 to 100 μm and the height is about the thickness of the solder, the solder may protrude beyond the solder resist. Then, the chip is pulled by the protruding solder and moves largely in the lateral direction. That is, there is a possibility that the positional deviation becomes large.

In Patent Document 5, as described above, since the carbon jig is used, the alignment accuracy between the pads of the semiconductor chip and the post pins is low.
Further, in Patent Document 6, the semiconductor chip is positioned on the insulating substrate with the conductive pattern by the protrusions provided on the insulating substrate with the conductive pattern, and the semiconductor chip is pressed by several protrusions. It is difficult to achieve highly accurate positioning.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device that can solve the above-described problems, can improve the alignment accuracy at a low cost, and can further reduce the size and high-density mounting of a semiconductor chip, and a method for manufacturing the same.

  In order to achieve the above object, according to the first aspect of the present invention, an insulating substrate with a conductive pattern, a concave portion having a rectangular planar shape arranged in the conductive pattern, and the concave portion are provided. A semiconductor chip mounted and fixed with a bonding material, a connection conductor column having one end fixed with a bonding material on the semiconductor chip, a printed circuit board to which the connection conductor column is fixed, and a positioning fixed to the conductive pattern A first external terminal that is also used, a second external terminal other than the first external terminal fixed to the conductive pattern, a first through hole through which the first external terminal passes and is disposed in the printed circuit board, In the semiconductor device having a second through-hole penetrating through the second external terminal and disposed in the printed circuit board, the connection conductor column and the semiconductor chip are positioned by the first external terminal and the first through-hole, Wherein in parts semiconductor chip and the conductive pattern is positioned, the size of the first through hole and a smaller size configuration of the second through hole.

  According to a second aspect of the present invention, the planar shape of the first through hole and the first external terminal are both circular in the first aspect of the invention, and the first through hole The difference between the diameter of the hole and the diameter of the first external terminal is preferably 50 μm or less.

  According to the invention of claim 3, the insulating substrate with a conductive pattern, the first concave portion having a planar shape arranged in the conductive pattern, and the first concave portion are placed and bonded to the first concave portion. A semiconductor chip fixed by a material, a connecting conductor column having one end fixed by a bonding material on the semiconductor chip, a printed circuit board to which the connecting conductor column is fixed, and a positioning column fixed to the printed circuit board The positioning recess is inserted into the conductive pattern and the positioning recess is inserted into the conductive pattern, the external terminal fixed to the conductive pattern, and the external terminal penetrates through the printed circuit board. It is set as the structure which has a hole.

  According to the invention described in claim 4 of the claims, the insulating substrate with a conductive pattern, the planar shape arranged in the conductive pattern is mounted on the first concave portion having a square shape, and placed on the first concave portion. A semiconductor chip fixed by a bonding material, a connection conductor column having one end fixed by a bonding material on the semiconductor chip, a printed circuit board to which the connection conductor column is fixed, and a positioning column are attached to and detached from the conductive pattern A second recessed portion for positioning, an external terminal fixed to the conductive pattern, a first through hole through which the external terminal passes and disposed in the printed circuit board, and the positioning column to be attached and detached pass through. A second through-hole disposed in the printed circuit board, and the second recess is located immediately below the second through-hole.

  According to the invention described in claim 5 of the claims, in the invention described in any one of claims 1, 3, or 4, the depth of the recess or the first recess is the recess. Alternatively, it may be deeper than the thickness of the bonding material placed in the first recess and shallower than the combined thickness of the bonding material and the semiconductor chip.

  According to the invention as set forth in claim 6, in the invention as set forth in claim 1, 3 or 4, the bonding material contains solder, brazing material or metal particles. It is good that it is a joining material.

  According to the invention described in claim 7 of the claims, in the invention described in any one of claims 1, 3, or 4, the conductive pattern is a quadrangle of the recess or the first recess. It is preferable to have a solder reservoir portion in contact with the four corners.

  According to the invention described in claim 8 of the claims, in the invention described in any one of claims 1, 3, or 4, the conductive pattern is a quadrangle of the recess or the first recess. It is preferable to have a first solder reservoir that is in contact with the four corners and a second solder reservoir that is in contact with each of the square sides of the recess.

According to the ninth aspect of the present invention, in the sixth aspect, the solder may be high-temperature solder.
According to the invention of claim 10, the first recess having a larger opening than the semiconductor chip, the first external terminal for positioning, and the other first in the conductive pattern of the insulating substrate with the conductive pattern. 2 forming a second recess for fixing the external terminal, fitting the first external terminal for positioning and the other second external terminal into the second recess of the conductive pattern, and the first Placing the solder in the recess, placing the semiconductor chip on the solder, placing the solder on the gate pad and the main electrode pad of the semiconductor chip, and providing the printed circuit board with the connecting conductor column The first external terminal for positioning is passed through the first through hole for positioning, the second external terminal is passed through the second through hole other than the first through hole, and the tip of the connecting conductor column and the gate pad And the main electrode The step of positioning the solder on the lid and pressing the printed circuit board with connecting conductor columns from above, and putting the whole (the assembly) in a reflow furnace, melting the solder, and then solidifying, Fixing the connection conductor pillar to the gate pad and the main electrode pad via the solder.

  According to the invention of claim 11, the step of forming the first recess having a larger opening than the semiconductor chip and the third recess for positioning in the conductive pattern of the insulating substrate with the conductive pattern; A step of placing solder in the first recess, placing the semiconductor chip on the solder, and placing the solder on the gate pad and the main electrode pad of the semiconductor chip, and having a positioning post A positioning support of a printed circuit board with a column is inserted into a third recess provided in a conductive pattern to position the tip of the connection conductor column and the solder on the gate pad and the main electrode pad, and the print with the connection conductor column The step of pressing the substrate from the top and the whole (the assembly) is put in a reflow furnace, the solder is melted, and then solidified, so that the connection conductor pillar is connected to the gate pad. A method of manufacturing a semiconductor device including the step of securing via the solder pre said main electrode pads.

  According to the invention of claim 12, the step of forming a first recess having a larger opening than the semiconductor chip and a third recess for positioning in the conductive pattern of the insulating substrate with a conductive pattern; A step of placing solder in the first recess and placing the semiconductor chip on the solder; placing the solder on the gate pad and the main electrode pad of the semiconductor chip; The alignment column is passed through a through hole provided in the first hole, the tip of the alignment column is inserted into a third recess, and the solder on the tip of the connection conductor column, the gate pad, and the main electrode pad And then pressing the printed circuit board with connection conductor columns from above, and putting the whole (the assembly) in a reflow furnace to melt the solder and then solidify the connection conductor columns. A method of manufacturing a semiconductor device, comprising: a step of fixing to the gate pad and the main electrode pad via the solder; and a step of extracting the alignment column from the third recess and the printed circuit board with connection conductor columns. .

  According to the present invention, the recess for mounting the semiconductor chip is formed in the conductive pattern of the insulating substrate with the conductive pattern, the positioning external terminal fixed to the conductive pattern is passed through the through-hole of the printed board with post pin, and the semiconductor chip By positioning the tip of the post pin on the gate pad and the emitter electrode pad, the alignment accuracy of the post pin and the pad can be greatly improved at low cost.

Furthermore, the positioning accuracy can be further improved by providing the solder reservoir adjacent to the recess.
Further, since the alignment accuracy is improved, semiconductor chips can be mounted at a high density.

Further, by providing the positioning pin, it is not necessary to perform positioning with the external terminal, and the cross-sectional shape of the external terminal can be an arbitrary shape other than a circle such as a quadrangle or a polygon.
Further, by removing the positioning pins after the soldering process, the degree of freedom of positioning pins is increased, and the printed circuit board with post pins can be downsized.

BRIEF DESCRIPTION OF THE DRAWINGS It is a block diagram of the semiconductor device of 1st Example of this invention, (a) is a principal part top view, (b) is principal part sectional drawing cut | disconnected by the XX line of (a). The semiconductor device 100 is exemplified by a power semiconductor module. Here, one phase of the inverter circuit is shown. FIG. 2 is a plan view of a main part of each component shown in FIG. 1, (a) is a plan view of a conductive pattern to which a semiconductor chip, positioning external terminals and rotation prevention external terminals are fixed, and (b) is a plan view of a printed circuit board with post pins. FIG. FIG. 2 is a plan view of a main part in which a semiconductor chip is disposed in a first recess shown in FIG. 1. 1 is a manufacturing method of the semiconductor device of FIG. It is a figure which shows the position shift of a semiconductor chip and a 1st recessed part. It is a figure which shows a mode that the semiconductor chip shifted significantly, (a) is a principal part top view, (b) is principal part sectional drawing cut | disconnected by the XX line of (a). It is a block diagram of the semiconductor device of 2nd Example of this invention, (a) is a principal part top view, (b) is principal part sectional drawing cut | disconnected by the XX line of (a). It is a figure which shows the position shift of a semiconductor chip and a recessed part. It is a principal part top view of the semiconductor device of 3rd Example of this invention. It is principal part sectional drawing of the semiconductor device of 4th Example of this invention. 10 is a method for manufacturing the semiconductor device of FIG. 10, and FIGS. It is principal part sectional drawing of the semiconductor device of 5th Example of this invention. It is principal part sectional drawing of the semiconductor device of 6th Example of this invention. It is a block diagram of the conventional power semiconductor module 700, (a) is a principal part top view, (b) is principal part sectional drawing cut | disconnected by the XX line of (a). It is a principal part top view arrange | positioned at the conductive pattern 53 at the time of using the semiconductor chip 55 shown in FIG. 14 as an IGBT chip | tip. 14 is a method for manufacturing the power semiconductor module of FIG. 14, and FIGS. It is a figure which shows the position shift from the initial position before melting the semiconductor chip and solder of the conventional power semiconductor module.

  Embodiments will be described in the following examples.

  FIG. 1 is a block diagram of a semiconductor device according to a first embodiment of the present invention. FIG. 1 (a) is a plan view of an essential part, and FIG. 1 (b) is cut along line XX in FIG. It is principal part sectional drawing. The semiconductor device 100 is exemplified by a power semiconductor module. Here, one phase of the inverter circuit is shown.

  2 is a plan view of the main part of each component shown in FIG. 1. FIG. 2A is a plan view of a conductive pattern to which a semiconductor chip, a positioning external terminal and a rotation preventing external terminal are fixed, and FIG. ) Is a plan view of a printed circuit board with post pins.

FIG. 3 is a plan view of a main part in which a semiconductor chip is arranged in the first recess shown in FIG. The dotted circle indicates the post pin 16 for reference.
1 to 3, a semiconductor device 100 includes an insulating substrate 1 with a conductive pattern in which a cooling base 2 is fixed to the back side of an insulating plate 3 such as a ceramic plate, and a conductive pattern 4 formed of metal foil is fixed to the front side. A first recess 5 for positioning semiconductor chips 9 and 10 (9 is, for example, an IGBT chip, 10 is a diode chip) formed on the conductive pattern 4 on the front side, and the back surface is fixed to the first recess 5 via solder 8. Semiconductor chips 9 and 10.

  Further, a post pin 16 fixed to the gate pad 9b and the emitter electrode pad 9a (main electrode pad) of the semiconductor chip 9 via the solder 15 and a post pin fixed to the insulating plate 11a on which the conductive pattern 14 is formed. The printed circuit board 11, the first external terminal 17 that is also used for positioning and fitted to the second recess 6 of the conductive pattern 4, and the first external that is fitted and fixed to the third recess 7 of the conductive pattern 4. Second external terminal 18 other than terminal 17, first through hole 12 for positioning formed in printed board 11 with post pin through which first external terminal 17 passes, and printed board with post pin through which second external terminal 18 passes. The second through-hole 13 other than the first through-hole formed in the.

  The post pin 16 is a connecting conductor column whose tip is soldered to the gate pad 9b or emitter electrode pad 9a of the semiconductor chip 9 and the anode electrode of the semiconductor chip 10, and the post pin 16 is a conductive pattern 14. The base is fitted and fixed to the insulating plate 11a (printed circuit board) on which is formed. In the following description, an IGBT (Insulated Gate Bipolar Transistor) chip may be taken as an example of the semiconductor chip, and in this case, the reference numeral is only 9.

  By fixing the second concave portion 6, the third concave portion 7, the first external terminal 17, and the second external terminal 18 via solder (not shown), the concave portion and the first external terminal 17, The fixing strength of the second external terminal 18 is increased. Further, the openings of the recesses 6 and 7 may be enlarged so that the first external terminal 17 and the second external terminal 18 are fixed only with solder.

  Further, when a conductive pattern 14 (not shown) is arranged on the insulating plate 11a around the through holes 12 and 13, and the conductive pattern 14, the first external terminal 17 and the second external terminal 18 are fixed to each other via solder, one layer is obtained. The fixing strength of the external terminal is increased.

  The first external terminal 17 and the second external terminal 18 have the same length and diameter (about 0.6 mm to 1 mm), and the post pin 16 has a diameter of about 0.1 mm to 0.3 mm. The depth of the first recess 5 is about 0.2 mm.

  The square opening of the first recess 5 formed in the conductive pattern 4 is made larger by about 50 μm than the dimensions of the outer periphery of the semiconductor chips 9, 10. Similar to 10 external shapes.

  The depth of the first recess 5 is made deeper than the thickness of the solder 8 and shallower than the total thickness of the solder 8 and the semiconductor chips 9 and 10. The diameter of the first through hole 12 of the printed board 11 with post pins is increased by about 50 μm with respect to the diameter of the first external terminal 17. The size of the opening of the first through hole 12 through which the first external terminal 17 serving also for positioning passes is made smaller than the size of the opening of the second through hole 13.

  The two first external terminals 17 that are also used for positioning are provided to prevent the printed circuit board 11 with post pins from rotating with respect to the semiconductor chip 9. By increasing the distance between the two first external terminals 17 that are also used for positioning as compared with the semiconductor chip 9, the rotational movement can be reduced and the positioning accuracy can be improved.

  Further, depending on the required accuracy of positioning, the size of the through hole 12 through which the two first external terminals 17 are passed may be formed slightly larger than the size used for positioning.

Further, since it is not necessary to take out the semiconductor chips 9 and 10 from the first recess 5, the gap 21 between the semiconductor chips 9 and 10 and the first recess 5 can be about 75 μm or less.
The interval 22 between the first external terminal 17 serving also for positioning and the first through hole 12 formed in the printed board 11 with post pins is set to about 25 μm.

  As shown in FIG. 5 described later, the maximum value of the positional deviation between the first recess 5 and the semiconductor chips 9 and 10 is 70 μm. When the maximum value of the positional deviation between the first external terminal 17 and the first through hole 12 for positioning the printed board 11 with post pin is added to this positional deviation, the maximum value of the positional deviation between the post pin 16 and the gate pad 9b is obtained. That is, the maximum value of the positional deviation between the post pin 16 and the gate pad 9b is about 70 μm + 25 μm = 95 μm.

  This is because the maximum value of the positional deviation between the post pin 16 and the gate pad 9b of the present embodiment is about 1/7 with respect to 0.7 mm which is the maximum positional deviation between the conventional post pin 57 and the gate pad 55b. By using, the alignment accuracy can be greatly improved. The positioning accuracy between the post pin 16 and the gate pad 9b is directly used as the positioning accuracy between the post pin 16 and the emitter electrode pad. As described above, by improving the alignment accuracy, the semiconductor chips 9 and 10 can be mounted at high density.

  Further, by making the thickness of the solder 8 entering the first recess 5 thinner than the depth of the first recess 5, the semiconductor chips 9 and 10 can get over the side wall of the first recess 5 even when the solder 8 is melted. Since it remains in the 1st recessed part 5, compared with the past, alignment accuracy can be improved significantly.

  In addition, since the alignment accuracy is improved, the interval between the semiconductor chips 9 and 10 can be reduced. For example, even when processing limits due to machining or the like are taken into consideration, the interval can be reduced to about 0.7 mm (about 2 mm in the past), and the semiconductor chips 9 and 10 can be mounted at high density.

  The semiconductor chips 9 and 10 are not only Si chips but also SiC chips such as SiC-IGBT chips, SiC-MOSFET chips, and SiC-SBD (Schottky barrier diode) chips. In particular, the SiC chip is suitable for miniaturization, and the present invention can exhibit the effect.

FIG. 4 shows a manufacturing method of the semiconductor device 100 of FIG. 1, and FIGS. 4A to 4D are cross-sectional views of main part manufacturing steps shown in the order of steps.
In FIG. 6A, a first recess 5, a second recess 6, and a third recess 7 (not shown) are formed in the conductive pattern 4 of the insulating substrate 1 with a conductive pattern. The semiconductor chips 9 and 10 (10 not shown) are placed, and the first external terminal 17 and the second external terminal 18 (not shown) are fitted into the second recess 6 and the third recess 7, respectively. The depth of the first recess 5 is deeper than the thickness of the solder 8 and shallower than the total thickness of the solder 8 and the semiconductor chips 9 and 10. The first, second, and third recesses 5, 6, and 7 (7 are not shown) are formed by machining, etching with a chemical, cutting by laser processing, or the like. As the solders 8 and 15, high-temperature lead-free solder is preferably used in order to cope with WBG (wide band gap) elements (such as SiC chips).

  More specifically, the high-temperature lead-free solder will be described. The high-temperature lead-free solder includes, for example, SnAgCuNiGe solder, SnAg solder, SnSb solder, SnAgCu solder, SnAgBi solder, SnCuBi solder, SnCu solder, SnAu solder, AuSi solder, AgSi solder, AgGe solder There is solder. Further, a joining material containing metal particles such as brazing material or nano Ag instead of solder may be used.

  Examples of the brazing material include silver brazing, copper brazing, brass brazing, aluminum brazing, gold brazing, phosphor copper brazing, etc., but considering the chip bonding, a low temperature brazing material having a melting point of about 300 ° C. is preferable. Au-Sn brazing is preferable.

  The bonding material including the metal particles is a bonding material in which Ag particles of about 100 μm or less are bound and covered with an organic substance and mixed with a solvent to form a paste. By heating and pressurizing depending on conditions, the solvent / organic matter is decomposed and volatilized, and the metal is sintered to function as a bonding material. Examples of the metal particles include Zn particles, Au particles, Al particles, Ni particles, Sb particles, Bi particles, Sn particles, Pd particles, and Cu particles in addition to the above Ag particles (nano Ag).

  If the planar shape of the solder 8 is a quadrangle, alignment is required when it is inserted into the first recess. However, it is preferable to make the solder 8 circular because alignment with the first recess 5 becomes unnecessary. However, it is necessary to manage the amount of solder so that the melted circular solder 8 can ensure a predetermined thickness uniformly in the first recess 5.

  Next, in FIG. 2B, the solder 15 is placed on the semiconductor chips 9 and 10, and the printed circuit board 11 with post pins is placed so that the tips of the post pins 16 are in contact with the solder 15. At this time, the front end of the post pin 16 and the emitter electrode pad 9a and gate pad 9b of the semiconductor chip 9 are positioned by passing the first external terminal 17 serving also for positioning through the first through hole 12 for positioning of the printed board 11. At the same time, the second external terminal 18 is passed through the second through hole 13. It is in contact with the conductive pattern 14 (conductive pattern indicated by a in FIG. 2B) of the printed board 11 connected to the gate pad 9b and the second external terminal 18 (second external terminal indicated by b in FIG. 2B). Solder 20 (shown in FIG. 2B) is placed on the substrate.

  In connecting the gate pad 9b and the second external terminal 18, two post pins 16 are provided on the conductive pattern 14 of the printed circuit board 11 with post pins, one of which is connected to the gate pad 9b, and the other is connected to the second external terminal. When connected to the conductive pattern 4 to which 18 is fixed, it is not necessary to connect the second external terminal 18 and the conductive pattern 14 in which the second through hole 13 is formed via the solder 13.

1c electrically connects the conductive pattern 14 of the printed board 11 and the conductive pattern 4 of the insulating substrate 1 with the conductive pattern.
Next, in FIG. 4C, a box-shaped carbon jig (not shown) for mounting members is used, and a carbon jig (not shown) that holds the printed board 11 with post pins from above. ), And melting and solidifying the solders 8, 15, and 20 through a reflow furnace, the semiconductor chips 9, 10 and the first recess 5, the semiconductor chips 9, 10, the post pin 16, the conductive pattern 14, and the first external terminal 17. Solder the second external terminal 18. This carbon jig is used not as a positioning of each member but as a weight for pressing the printed board 11 with post pins and a carry-in box when put into the reflow furnace.

  When the conductive pattern 14 is formed around the through holes 12 and 13 of the printed circuit board 11 that penetrates the first external terminal 17 and the second external terminal 18 and fixed with solder, the recesses 6 and 7 and the through holes 12 and 13 are formed. Therefore, the fixing strength of the first external terminal 17 and the second external terminal 18 is preferably increased. Further, it is preferable to reinforce the fitting portions of the recesses 6 and 7 with solder because the fixing strength is increased.

  Next, in FIG. 4D, the semiconductor device 100 is completed by taking out the insulating substrate 1 with conductive pattern, the semiconductor chips 9, 10 and the printed substrate 11 with post pins using a resin 19 from the reflow furnace.

  The alignment of the semiconductor chips 9 and 10 and the post pin 16 is performed by the second concave portion 6 of the conductive pattern 4 and the first external terminal 17 serving also for positioning. The first external terminal 17 functions in the same manner as the other normal second external terminals 18 and becomes a wiring between the external wiring and the conductive pattern 4. Compared to the conventional method of aligning using a carbon jig, the method of not using the carbon jig for alignment as in the present invention has fewer steps that cause misalignment and is placed in the first recess 5. Since it is not necessary to take out the semiconductor chips 9 and 10 from the first recess 5, it is not necessary to provide more play than necessary in the first recess 5. Therefore, it is possible to increase the accuracy of alignment of the gate pins 9b and emitter electrode pads 9a (main electrode pads) of the semiconductor chip 9 and the post pins 16.

  As described above, the difference between the outer diameter of the first external terminal 17 that is also used for positioning and the diameter of the through hole 12 of the printed circuit board 11 with post pins is about 50 μm or less (the gap 22 is about 25 μm or less). The positional deviation of the first through holes 12 formed in the first external terminals 17 and the post-pinned printed circuit board 11 can be reduced to about 25 μm or less. Thus, by reducing the positional deviation between the semiconductor chips 9 and 10, the first recess 5, the first external terminal 17 for positioning and the first through hole 12 of the printed circuit board 11 with post pin, the gate pad 9 b and the post pin 16 can be displaced. The positional deviation can be reduced to about 95 μm or less. As a result, the positional deviation can be greatly reduced as compared to the positional deviation of about 0.5 mm between each pad of the semiconductor chip and the post pin in the conventional carbon jig.

  FIG. 5 is a diagram illustrating a positional deviation between the semiconductor chip and the first recess. A conventional example is also shown for comparison. For the measurement of the positional deviation, the deviation of the semiconductor chip 9 from the center of the first recess 5 in the X direction and the Y direction was measured from 20 centers, and a large value was adopted as the positional deviation. The dimensions of the sample are: the depth of the first recess 5 is 0.2 mm, the size of the semiconductor chip 9 is □ 2.5 mm (□ is the length of one side of the square), the thickness is 0.35 mm, and the solder 8 Is Φ2.5 mm and the thickness is 0.1 mm.

  From FIG. 5, the positional deviation is 0.03 mm to 0.07 mm with 0.05 mm as the center. If the positional deviation of 25 μm between the first external terminal 17 that is also used for positioning and the first through hole 12 for positioning formed in the printed board 11 with post pin is added to this positional deviation, the positional deviation between the post pin 16 and the gate pad 9b is maximum. Is 95 μm. This misalignment is significantly smaller than that of the conventional power semiconductor module 500, and the alignment accuracy between the post pin 16 and the gate pad 9b is greatly improved.

  Solder 8 is placed on the first recess 5 of the conductive pattern 4, the semiconductor chips 9, 10 are placed thereon, and the printed circuit board 11 with post pins is in contact with the tips of the post pins 16 on the semiconductor chips 9, 10. When the solders 8 and 15 on the lower surface and the upper surface of the semiconductor chips 9 and 10 are melted, the semiconductor chips 9 and 10 move in the first recess 5 due to the surface tension of the solders 8 and 15, and further the semiconductor chip. The surface of 9, 10 may be inclined.

  FIGS. 6A and 6B are views showing a state in which the semiconductor chip is greatly displaced. FIG. 6A is a plan view of the main part, and FIG. 6B is a cross-sectional view taken along line XX in FIG. FIG. This figure shows the first recess 5 in an enlarged manner. When a positional shift occurs in the semiconductor chips 9 and 10 (10 is not shown), the semiconductor chip 9 may be tilted as shown in FIG. 5B. When the semiconductor chip 9 is tilted, the semiconductor chip 9 and the post pin 16 are tilted. Will not be satisfactorily fixed. Further, when the positional deviation increases, the post pin 16 cannot be fixed to the gate pad 9b. Further, when the semiconductor chips 9 and 10 are inserted into the first recess 5, the semiconductor chips 9 and 10 may come into contact with the corners of the first recess 5 to cause chipping.

  A method for preventing such misalignment and preventing chipping of the semiconductor chips 9 and 10 will be described in the next embodiment.

  FIGS. 7A and 7B are configuration diagrams of a semiconductor device according to a second embodiment of the present invention. FIG. 7A is a plan view of the main part, and FIG. 7B is cut along line XX in FIG. It is principal part sectional drawing. In this figure, semiconductor chips 9 and 10 (10 not shown) are fixed to the first recess 5 with solder 8.

  The difference between the semiconductor device 100 of FIG. 1 and the semiconductor device 200 is that solder reservoirs 5 a are provided at the four corners of the rectangular first recess 5. The depth of the solder reservoir 5a is the same as that of the first recess 5. By providing this solder reservoir 5a, when the solder 8 is melted, it flows into the reservoir 5a at the four corners and below the semiconductor chip 9. The thickness of the melted solder 8 is uniformly reduced. Further, at the time of reflow, the voids contained in the melted solder 8 flow into the solder reservoir 5a, so that the voids can escape from the melted solder 8 under the semiconductor chips 9 and 10. By installing the solder reservoir 5a, the extent to which the semiconductor chips 9 and 10 move in the lateral direction is reduced. Further, the inclination of the semiconductor chips 9 and 10 is almost eliminated. As a result, the gap 21 between the first recess 5 and the semiconductor chips 9 and 10 can be reduced to about 50 μm, and the alignment accuracy between the post pin 16 and the gate pad 9b can be improved.

  FIG. 8 is a diagram showing a positional deviation between the semiconductor chip and the recess. The number of samples is 20. The positional deviation is 0.01 mm to 0.05 mm centered on 0.025 mm, and the alignment accuracy can be improved compared to the case of the semiconductor device 100 of the first embodiment. The sample specifications are the same as in FIG.

  Further, the planar shape of the solder reservoir 5a may be circular, elliptical, or rectangular. When the solder reservoir 5a is circular, the solder reservoir 5a may be formed with a radius r of about 0.2 mm to 0.3 mm from the four corners of the first recess 5. Moreover, it is good also as a circle | round | yen of the said radius r centering on the position of 0.1 mm-0.15 mm toward the center of a solder reservoir from the corner | angular corners of the opening part of the 1st recessed part 5. FIG.

  As described above, by providing the solder reservoir 5a at the corner of the first recess 5, the maximum positional deviation between the first recess 5 and the semiconductor chip 9 can be reduced to about 50 μm or less. As a result, the maximum positional deviation between the gate pad 9b and the post pin 16 can be reduced to about 75 μm or less. This is smaller than the first embodiment by about 25 μm.

Further, by providing the solder reservoir 5a, the solder void can be reduced to 5% or less (in the case of Example 1, 10%).
However, when the size of the semiconductor chip is larger than □ 3 mm, when the solder reservoir 5a is provided at the four corners of the recess, the flow path of the molten solder 8 to the solder reservoir 5a becomes longer, and the thickness of the molten solder 8 increases. Unevenness occurs and voids are likely to occur. In order to prevent this, it is necessary to disperse the solder reservoirs 5a and make the length of the flow path of the molten solder 8 to the solder reservoirs 5a uniform and short. This method will be described in the accompanying examples.

FIG. 9 is a plan view of an essential part of a semiconductor device according to a third embodiment of the present invention. This figure is a plan view corresponding to FIG.
The difference between the semiconductor device 200 of FIG. 7 and the semiconductor device 300 is that a solder reservoir 5 b is also provided at the center of the side of the first recess 5. By doing so, the length of the flow path of the molten solder 8 to the solder reservoirs 5a and 5b can be made uniform and short, and the semiconductor chips 9 and 10 (10 is not shown) and the first recess 5 are formed. The positional deviation can be made as small as a semiconductor chip.

If the semiconductor chip is larger, the number of solder reservoirs 5b on the side may be increased. The planar shape of the solder reservoir 5b may be circular, elliptical, or rectangular.
When the solder reservoir 5b is circular, the solder reservoir 5b may be formed with a radius r of about 0.2 mm to 0.3 mm from the side of the opening of the first recess 5. Moreover, it is good also as a circle | round | yen of the said radius centering on 0.1 mm-0.15mm opening part inner side from the edge | side of the opening part of the 1st recessed part 5. FIG.

  Further, in the case of using high-temperature lead-free solder that has low wettability and easily generates voids, it is effective to increase the solder reservoir portion 5b in this way. Further, the positional deviation between the first recess 5 and the semiconductor chips 9 and 10 is substantially the same as in the second embodiment.

  FIG. 10 is a cross-sectional view of the principal part of the semiconductor device according to the fourth embodiment of the present invention. The difference between FIG. 1 and the semiconductor device 100 and the semiconductor device 400 is that a dedicated positioning pin 26 is provided on the printed circuit board 11 with post pins as a positioning post instead of the first external terminal 17 that also serves as a positioning. . The dedicated positioning pin 26 is inserted and fixed in the positioning fourth recess 25 formed in the conductive pattern 4. Although not shown, the positioning pins 26 may be fixed to the conductive pattern 4 and the positioning pins 26 may be passed through positioning positioning holes formed in the printed circuit board 11 with post pins. .

In this way, the cross-sectional size and cross-sectional shape of the second external terminal 18 can be arbitrarily determined such as a square or a polygon without depending on the size or planar shape of the through-hole 13.
FIG. 11 shows a manufacturing method of the semiconductor device 400 of FIG. 10, and FIGS. 11A to 11D are cross-sectional views of main part manufacturing steps shown in the order of steps.

  In FIG. 2A, a first recess 5 is formed in the conductive pattern 4 of the insulating substrate 1 with a conductive pattern, and solder 8 and semiconductor chips 9 and 10 (10 not shown) are placed in the first recess 5. Then, the solder 8 is mounted in the fourth recess 25.

  In FIG. 2B, the solder 15 is placed on the semiconductor chips 9 and 10, and the printed circuit board 11 with post pins is placed so that the tips of the post pins 16 are in contact with the solder 15. Further, the second external terminal 18 is placed on the solder 8 disposed in the second recess 6 of the conductive pattern 4 through the through hole 13 of the printed board 11 with post pin. Positioning is performed by inserting two dedicated positioning pins 26 fixed to the printed board 11 with post pins into the fourth recess 25 of the conductive pattern 4.

  Next, in FIG. 2C, a box-shaped carbon jig (not shown) for mounting members is used, and a carbon jig (not shown) for pressing the printed board 11 with post pins from above. And melting the solders 8 and 15 through a reflow furnace and solidifying them, thereby soldering the semiconductor chips 9 and 10 and the second external terminals 18 and the second recesses 6, the semiconductor chips 9 and 10 and the tips of the post pins 16. . This carbon jig is used not as a positioning of each member but as a weight for pressing the printed board 11 with post pins and a carry-in box when put into the reflow furnace.

Next, in FIG. 4D, the semiconductor device 400 is completed by taking out from the reflow furnace and sealing with the resin 19.
However, there may be a case where electrical insulation between the dedicated positioning pin 26 and the conductive pattern 14 of the printed board 11 cannot be ensured. A measure for preventing this will be described in the next embodiment.

  FIG. 12 is a fragmentary cross-sectional view of the semiconductor device according to the fifth embodiment of the present invention. The difference between FIG. 12 and the semiconductor device 400 and the semiconductor device 500 is that the dedicated positioning pin 25 is used as a removable dedicated positioning pin 27 and the semiconductor chips 9 and 10 are soldered in a reflow furnace, and then the positioning pin 25 is used. 27 is removed from the insulating substrate with conductive pattern 1 and the fourth recess 25. By doing so, it is not necessary to pay attention to the insulation strength between the positioning pin 27 and the second external terminal 18 or the internal wiring pattern, and the degree of freedom of arrangement of the positioning pin 27 is increased.

A fourth recess 25 into which a detachable positioning pin 27 is inserted is disposed immediately below the through hole 28.
The difference between this manufacturing method and the manufacturing method of FIG. 11 is that the dedicated positioning pin 27 is removed after the step of FIG. Other steps are the same as those in FIG.

  Thus, by removing the dedicated positioning pins 27 after soldering by reflow, it is possible to prevent a decrease in insulation strength between the positioning pins 25 and the conductive pattern 14 of the printed circuit board 11, which is regarded as a problem in FIG. 10. Further, the degree of freedom of arrangement of the dedicated positioning pin 27 is increased, and the through hole 28 through which the positioning pin 27 is passed can be formed at an arbitrary position of the printed board 11 with the post pin.

  FIG. 13 is a fragmentary cross-sectional view of the semiconductor device according to the sixth embodiment of the present invention. The semiconductor device 600 is a semiconductor unit on which one IGBT chip (semiconductor chip 9) and one FWD (free wheel diode) chip (semiconductor chip 10) are mounted. By combining a plurality of these semiconductor units, the same function as that of the power semiconductor module can be provided.

1 Insulating substrate with conductive pattern 2 Cooling base 3 Insulating plate (insulating substrate with conductive pattern)
4 Conductive pattern (insulating substrate with conductive pattern)
5 1st recessed part 5a Solder reservoir part 6 2nd recessed part 7 3rd recessed part 8 Solder (adhesion of a recessed part and a semiconductor chip)
9 Semiconductor chip (eg, IGBT chip)
9a Emitter electrode pad 9b Gate pad 10 Semiconductor chip (for example, FWD chip)
11 Printed circuit board with post pin 11a Insulation board (printed circuit board with post pin)
12 1st through-hole 13 2nd through-hole 14 Conductive pattern (printed board with a post pin)
15 Solder (adhesion of post pin and semiconductor chip)
16 Post pin 17 First external terminal 18 Second external terminal 19 Resin 20 Solder (adhesion between second external terminal and conductive pattern 14)
21 gap (between the recess 5 and the semiconductor chip 9)
22 Gap (between the first external terminal and the first through hole 12)
25 4th recessed part 26 Dedicated positioning pin 27 Removable positioning pin 28 Through-hole (removable positioning pin)
100, 200, 300, 400, 500, 600 Semiconductor device

Claims (12)

An insulating substrate with a conductive pattern, a concave portion having a square shape arranged in the conductive pattern, a semiconductor chip placed in the concave portion and fixed with a bonding material, and one end fixed on the semiconductor chip with a bonding material Connecting conductor pillars, a printed circuit board to which the connecting conductor pillars are fixed, a first external terminal for positioning and fixed to the conductive pattern, and a second external terminal other than the first external terminal fixed to the conductive pattern In a semiconductor device having a terminal, a first through hole through which the first external terminal passes and is arranged in the printed board, and a second through hole through which the second external terminal penetrates and is arranged in the printed board,
The connection conductor column and the semiconductor chip are positioned by the first external terminal and the first through hole, the semiconductor chip and the conductive pattern are positioned by the recess, and the size of the first through hole is the second size. A semiconductor device having a size smaller than that of the through hole.   2. The planar shape of the first through hole and the first external terminal are both circular, and the difference between the diameter of the first through hole and the diameter of the first external terminal is 50 μm or less. A semiconductor device according to 1.   An insulating substrate with a conductive pattern, a first recess having a square shape arranged in the conductive pattern, a semiconductor chip placed on the first recess and fixed by a bonding material, and a bonding material on the semiconductor chip A connection conductor column to which one end is fixed, a printed board to which the connection conductor column is fixed, a positioning column to be fixed to the printed circuit board, and a tip of the positioning column are inserted and arranged in the conductive pattern. A semiconductor device comprising: a second concave portion for positioning; an external terminal fixed to the conductive pattern; and a through hole through which the external terminal passes and is disposed in the printed circuit board.   An insulating substrate with a conductive pattern, a first recess having a square shape arranged in the conductive pattern, a semiconductor chip placed on the first recess and fixed by a bonding material, and a bonding material on the semiconductor chip A connection conductor column to which one end is fixed, a printed circuit board to which the connection conductor column is fixed, a positioning second recess that is attached to and removed from the positioning pattern, and is fixed to the conductive pattern. An external terminal; a first through-hole through which the external terminal penetrates and disposed in the printed circuit board; and a second through-hole through which the detachable positioning column is disposed and disposed in the printed circuit board. 2. A semiconductor device, wherein two recesses are located immediately below the second through hole.   The depth of the recess or the first recess is deeper than the thickness of the bonding material placed in the recess or the first recess and shallower than the combined thickness of the bonding material and the semiconductor chip. Item 5. The semiconductor device according to any one of Items 1, 3 and 4.   The semiconductor device according to claim 1, wherein the bonding material is a bonding material containing solder, brazing material, or metal particles.   5. The semiconductor device according to claim 1, wherein the conductive pattern has a solder reservoir portion in contact with four corners of the quadrangle of the concave portion or the first concave portion.   The conductive pattern includes a first solder reservoir that contacts four corners of the quadrangle of the recess or the first recess, and a second solder reservoir that contacts each side of the quadrangle of the recess. Item 5. The semiconductor device according to any one of Items 1, 3 and 4.   The semiconductor device according to claim 6, wherein the solder is high-temperature solder. Forming a first recess having a larger opening than the semiconductor chip, a first external terminal for positioning, and a second recess for fixing the other second external terminal in the conductive pattern of the insulating substrate with the conductive pattern;
Fitting the first external terminal for positioning and the other second external terminal to the second recess of the conductive pattern;
Placing solder in the first recess, placing the semiconductor chip on the solder; and
Solder is placed on the gate pad and the main electrode pad of the semiconductor chip, and a first external terminal for positioning is passed through a first through hole for positioning provided in a printed circuit board with a connecting conductor column. The second external terminal is passed through a second through hole other than the hole, and the tip of the connection conductor column and the solder on the gate pad and the main electrode pad are positioned, and the printed circuit board with the connection conductor column is placed on the top. The process of pressing from the
The whole is put into a reflow furnace, the solder is melted, and then solidified, thereby fixing the connection conductor column to the gate pad and the main electrode pad via the solder. A method for manufacturing a semiconductor device. Forming a first recess having a larger opening than the semiconductor chip and a third recess for positioning in the conductive pattern of the insulating substrate with the conductive pattern;
Placing solder in the first recess, placing the semiconductor chip on the solder; and
Solder is placed on the gate pad and the main electrode pad of the semiconductor chip, and the positioning column of the printed circuit board with the connection conductor column having the positioning column is inserted into the third recess provided in the conductive pattern, and the connection conductor column Positioning the tip and the solder on the gate pad and the main electrode pad and pressing the printed circuit board with connection conductor columns from above;
The whole is put into a reflow furnace, the solder is melted, and then solidified, thereby fixing the connection conductor column to the gate pad and the main electrode pad via the solder. A method for manufacturing a semiconductor device. Forming a first recess having a larger opening than the semiconductor chip and a third recess for positioning in the conductive pattern of the insulating substrate with the conductive pattern;
Placing solder in the first recess, placing the semiconductor chip on the solder; and
Solder is placed on the gate pad and the main electrode pad of the semiconductor chip, and an alignment post is passed through a through-hole provided in the printed circuit board with connection conductor columns, and the tip of the alignment column is inserted into the third column. Inserting into the recess, positioning the tip of the connection conductor pillar and the solder on the gate pad and the main electrode pad and pressing the printed circuit board with the connection conductor pillar from above;
The whole is put in a reflow furnace, the solder is melted, and then solidified to fix the connection conductor pillar to the gate pad and the main electrode pad via the solder;
A method of manufacturing a semiconductor device, comprising: a step of pulling out the alignment column from the third recess and the printed circuit board with connection conductor columns.

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