WO2016024333A1 - Semiconductor module - Google Patents

Semiconductor module Download PDF

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Publication number
WO2016024333A1
WO2016024333A1 PCT/JP2014/071318 JP2014071318W WO2016024333A1 WO 2016024333 A1 WO2016024333 A1 WO 2016024333A1 JP 2014071318 W JP2014071318 W JP 2014071318W WO 2016024333 A1 WO2016024333 A1 WO 2016024333A1
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WO
WIPO (PCT)
Prior art keywords
semiconductor
connector
pair
ceramic substrates
semiconductor module
Prior art date
Application number
PCT/JP2014/071318
Other languages
French (fr)
Japanese (ja)
Inventor
康亮 池田
雄司 森永
Original Assignee
新電元工業株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 新電元工業株式会社 filed Critical 新電元工業株式会社
Priority to JP2015504441A priority Critical patent/JP5930565B1/en
Priority to PCT/JP2014/071318 priority patent/WO2016024333A1/en
Publication of WO2016024333A1 publication Critical patent/WO2016024333A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5385—Assembly of a plurality of insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L24/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L24/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0618—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/06181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H01L2224/37001—Core members of the connector
    • H01L2224/37099—Material
    • H01L2224/371—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/37138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/37147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H01L2224/848—Bonding techniques
    • H01L2224/84801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3735—Laminates or multilayers, e.g. direct bond copper ceramic substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L24/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L24/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector

Definitions

  • the present invention relates to a semiconductor module.
  • a circuit is configured by mounting a plurality of semiconductor elements on a substrate.
  • a ceramic substrate in which a conductive layer functioning as a circuit of a semiconductor module is formed on the main surface of a ceramic plate is often used as a substrate of a semiconductor module such as a power device module.
  • semiconductor modules such as power device modules are required to have high-density mounting or high-density integration of semiconductor elements.
  • a semiconductor module for example, the first ceramic substrate, the first semiconductor element, the connector, the second semiconductor element, and the second ceramic substrate are sequentially laminated, and these components are joined by soldering. Things can be considered.
  • the semiconductor module when such a semiconductor module is manufactured, there is a problem in that it is difficult to position the semiconductor element and the connector with respect to each ceramic substrate, particularly when each component is joined with solder. That is, there is a problem that the semiconductor module cannot be manufactured efficiently.
  • An object of one embodiment of the present invention is to provide a semiconductor module in which a semiconductor element and a connector can be easily positioned with respect to each ceramic substrate and can be efficiently manufactured.
  • a semiconductor module as one embodiment of the present invention includes a pair of ceramic substrates in which a conductive layer is provided on at least one main surface of a ceramic plate and a semiconductor bonded to the conductive layers of the pair of ceramic substrates facing each other.
  • a positioning recess for individually inserting the semiconductor element and the connector is formed.
  • the semiconductor element and the connector when a semiconductor module is manufactured, can be easily positioned with respect to each ceramic substrate simply by inserting the semiconductor element and the connector into the positioning recesses of the ceramic substrate. It becomes possible to do. Therefore, it becomes possible to manufacture a semiconductor module efficiently.
  • the semiconductor module 1 includes a pair of ceramic substrates 2 and 3, semiconductor elements 4 and 5, and a connector 6.
  • the semiconductor elements 4 and 5 are bonded to at least one conductive layer 22 and 32 of a pair of ceramic substrates 2 and 3 to be described later.
  • the type and shape of the semiconductor elements 4 and 5 are not particularly limited.
  • the semiconductor elements 4 and 5 of this embodiment are formed in a plate shape and have electrodes on both main surfaces.
  • the semiconductor elements 4 and 5 of this embodiment are diodes having one electrode on each main surface.
  • Each ceramic substrate 2, 3 includes plate-shaped ceramic plates 21, 31 having insulating properties, and conductive layers 22, 32 provided on the main surfaces of the ceramic plates 21, 31.
  • conductive layers 22 and 32 are provided on both main surfaces of the ceramic plates 21 and 31.
  • the conductive layers 22 and 32 may be conductive, but may be made of a material having high electrical conductivity such as copper.
  • the pair of ceramic substrates 2 and 3 are spaced in the thickness direction of the ceramic plates 21 and 31 so that one of the conductive layers 22A and 32A (hereinafter referred to as the first conductive layers 22A and 32A) is opposed to each other. It is arranged with a gap.
  • the first conductive layers 22 ⁇ / b> A and 32 ⁇ / b> A of the ceramic substrates 2 and 3 are formed as a wiring pattern constituting a circuit of the semiconductor module 1 together with the semiconductor elements 4 and 5 and the connector 6.
  • Semiconductor elements 4 and 5 are bonded to the first conductive layers 22A and 32A of the pair of ceramic substrates 2 and 3, respectively. Specifically, one main surface of each of the semiconductor elements 4 and 5 is bonded to the first conductive layers 22A and 32A of the ceramic substrates 2 and 3 by a conductive adhesive (not shown) such as solder. Thus, the semiconductor elements 4 and 5 are electrically connected to the first conductive layers 22A and 32A of the ceramic substrates 2 and 3, respectively. In this embodiment, the electrodes of the semiconductor elements 4 and 5 bonded to the ceramic substrates 2 and 3 are different from each other.
  • the semiconductor element 4 bonded to the first conductive layer 22 ⁇ / b> A of the lower ceramic substrate 2 (hereinafter also referred to as the first ceramic substrate 2) is also referred to as the first semiconductor element 4.
  • the semiconductor element 5 bonded to the first conductive layer 32 ⁇ / b> A of the upper ceramic substrate 3 (hereinafter also referred to as the second ceramic substrate 3) is also referred to as the second semiconductor element 5.
  • the element positioning recess 23 into which the first semiconductor element 4 is inserted is also referred to as an element positioning recess 23 or a first element positioning recess 23.
  • the connector positioning recess 24 into which the connector 6 is inserted is also referred to as a connector positioning recess 24.
  • the region where the first element positioning recess 23 is formed and the region where the connector positioning recess 24 is formed are electrically independent from each other.
  • a positioning recess 33 for inserting the second semiconductor element 5 is formed in the first conductive layer 32 ⁇ / b> A of the second ceramic substrate 3.
  • the element positioning recess 33 into which the second semiconductor element 5 is inserted is also referred to as an element positioning recess 33 or a second element positioning recess 33.
  • the semiconductor elements 4 and 5 are bonded to the bottom surfaces of the element positioning recesses 23 and 33 in the first conductive layers 22A and 32A.
  • the size of each of the element positioning recesses 23 and 33 is such that the side portions of the semiconductor elements 4 and 5 are in the element positioning recesses while the semiconductor elements 4 and 5 are joined to the bottom surfaces of the element positioning recesses 23 and 33.
  • 23 and 33 are set so as not to contact the inner side surfaces.
  • the gap between the side portions of the semiconductor elements 4 and 5 and the inner side surfaces of the element positioning recesses 23 and 33 is preferably as small as possible.
  • the depth dimensions of the element positioning recesses 23 and 33 are such that the semiconductor elements 4 and 5 are joined to the bottom surfaces of the element positioning recesses 23 and 33 and the semiconductor elements 4 and 5 are in contact with the element positioning recesses 23 and 33. Is set so as not to protrude from the surfaces of the first conductive layers 22A and 32A that are open. In a state where the semiconductor elements 4 and 5 are inserted into the element positioning recesses 23 and 33, for example, the main surfaces of the semiconductor elements 4 and 5 joined to the connector 6 described later are the surfaces of the first conductive layers 22A and 32A. It may be located at the same height as or lower than the surfaces of the first conductive layers 22A and 32A.
  • the pair of ceramic substrates 2 and 3 are arranged such that the first element positioning recess 23 and the second element positioning recess 33 face each other. That is, the pair of semiconductor elements 4 and 5 respectively joined to the pair of ceramic substrates 2 and 3 are arranged side by side in the arrangement direction of the pair of ceramic substrates 2 and 3.
  • the connector 6 electrically connects the semiconductor elements 4 and 5 joined to the pair of ceramic substrates 2 and 3 and is joined to the first conductive layers 22A and 32A of at least one of the ceramic substrates 2 and 3.
  • the connector 6 of this embodiment is joined to the first conductive layer 22 ⁇ / b> A of the first ceramic substrate 2.
  • the connector 6 is made of a conductive material such as copper.
  • the connector 6 includes a band plate-shaped main body plate portion 61, an element joining portion 62 provided at a first end portion in the longitudinal direction of the main body plate portion 61 (right end portion in FIG. 1), and a main body plate portion 61. And a substrate bonding portion 63 provided at the second end (the left end in FIG. 1).
  • the element joint 62 is disposed between the element positioning recesses 23 and 33 of the pair of ceramic substrates 2 and 3 and is bonded to the pair of semiconductor elements 4 and 5 inserted into the element positioning recesses 23 and 33. .
  • the element joint portion 62 is formed in a block shape larger than the thickness dimension of the main body plate portion 61.
  • the element joint portion 62 of the present embodiment is formed to protrude on both sides in the thickness direction of the main body plate portion 61. Both protruding ends of the element bonding portion 62 are bonded to the main surfaces of the pair of semiconductor elements 4 and 5 facing each other by a conductive adhesive (not shown) such as solder. That is, the element junction 62 is sandwiched between the pair of semiconductor elements 4 and 5.
  • the substrate bonding portion 63 is bonded to the first conductive layer 22A of the first ceramic substrate 2 by a conductive adhesive (not shown) such as solder.
  • the substrate bonding portion 63 extends in the thickness direction of the main body plate portion 61 from the main body plate portion 61 toward the first ceramic substrate 2 side.
  • the substrate bonding portion 63 is formed by bending the second end portion of the main body plate portion 61.
  • the front end of the board bonding portion 63 in the extending direction is inserted into the connector positioning recess 24. In the illustrated example, there is no gap between the board joint 63 inserted in the connector positioning recess 24 and the inner surface of the connector positioning recess 24, but the present invention is not limited to this.
  • a conductive adhesive such as solder for bonding the substrate bonding portion 63 to the first conductive layer 22A is interposed. There may be.
  • the semiconductor elements 4, 5 and the connector 6 are inserted into the positioning recesses 23, 24, 25 of the ceramic substrates 2, 3, respectively. 5 and the connector 6 can be easily positioned with respect to the ceramic substrates 2 and 3. Therefore, the semiconductor module 1 can be manufactured efficiently.
  • the semiconductor elements 4, 5 and the connector 6 are positioned with respect to the ceramic substrates 2, 3 only by appropriately arranging the semiconductor elements 4, 5 and the connector 6 between the pair of ceramic substrates 2, 3.
  • solder reflow is performed in a state where the semiconductor elements 4 and 5 and the connector 6 are disposed between the pair of ceramic substrates 2 and 3, and the bonding between the ceramic substrates 2 and 3 and the semiconductor elements 4 and 5 is performed. Bonding between the elements 4 and 5 and the connector 6 and bonding between the ceramic substrates 2 and 3 and the connector 6 can be performed collectively.
  • the semiconductor module 1 is manufactured in comparison with the case where the semiconductor elements 4 and 5 and the connector 6 are positioned with respect to the pair of ceramic substrates 2 and 3 using a jig. It is possible to improve the manufacturing efficiency and the yield of the module 1. If it demonstrates concretely, when positioning the semiconductor elements 4 and 5 and the connector 6 with respect to the ceramic substrates 2 and 3 using a jig
  • the manufacture efficiency of a semiconductor module may fall. Furthermore, when the solder at the above-mentioned joining portion adheres to the jig, chip cracks may occur in the semiconductor elements 4 and 5 when the jig is removed, which leads to a decrease in the yield of the semiconductor module.
  • the above-described jig is not required when manufacturing the semiconductor module 1, so that attachment and detachment of the jig are not required, and the manufacturing efficiency of the semiconductor module 1 is improved. Can be planned. Further, when the semiconductor module 1 is manufactured, the chip crack does not occur, so that the yield of the semiconductor module 1 can be improved.
  • the semiconductor module 1 of the present embodiment since the semiconductor elements 4 and 5 are inserted into the element positioning recesses 23 and 33, the semiconductor module 1 can be thinned.
  • the semiconductor elements 4 and 5 inserted into the element positioning recesses 23 and 33 do not protrude from the surfaces of the first conductive layers 22A and 32A where the element positioning recesses 23 and 33 are opened. For this reason, the semiconductor module 1 can be further reduced in thickness.
  • the first conductive layers 22A and 32A are formed with the element positioning recesses 23 and 33, whereby the first conductive layer 22A in the junction region of the semiconductor elements 4 and 5 is formed.
  • 32A is thinner than the thickness of the first conductive layers 22A, 32A in the other regions. For this reason, the heat generated in the semiconductor elements 4 and 5 can be efficiently released to the ceramic plates 21 and 31. That is, the heat dissipation efficiency of the semiconductor elements 4 and 5 can be improved.
  • the pair of semiconductor elements 4 and 5 joined to the pair of ceramic substrates 2 and 3 are arranged side by side in the arrangement direction of the pair of ceramic substrates 2 and 3. For this reason, the heat of the semiconductor elements 4 and 5 can be efficiently released to both the pair of ceramic substrates 2 and 3.
  • the heat of the first semiconductor element 4 bonded to the first ceramic substrate 2 not only escapes to the first ceramic substrate 2 side but also passes through the second semiconductor element 5 bonded to the second ceramic substrate 3. It can also escape to the two ceramic substrate 3 side.
  • the heat dissipation path of the first semiconductor element 4 in the connector 6 interposed between the pair of semiconductor elements 4 and 5 is minimized, and the heat of the first semiconductor element 4 is also efficiently transferred to the second ceramic substrate 3 side. It is possible to escape well.
  • the first semiconductor element 4 bonded to the first ceramic substrate 2 has the first conductive layer 22A in which the first element positioning recess 23 of the first ceramic substrate 2 is opened. Does not protrude from the surface of For this reason, the height position of the connector 6 (particularly the main body plate portion 61) with respect to the surface of the first conductive layer 22A of the first ceramic substrate 2, that is, the loop height of the connector 6 can be set low. Therefore, the semiconductor module 1 can be further reduced in thickness.
  • the height position of the connector 6 (particularly the main body plate portion 61) with respect to the surface of the first conductive layer 22A of the first ceramic substrate 2 is lowered, so that the first ceramic element 2 to the first ceramic substrate 2 are firstly connected.
  • the length of the connector 6 reaching the conductive layer 22A can be set short. Therefore, the wiring resistance and parasitic inductance of the connector 6 can be reduced.
  • the semiconductor module 1A according to the present embodiment is configured in the same manner as the semiconductor module 1 of the first embodiment described above.
  • the semiconductor module 1 ⁇ / b> A of the present embodiment includes a spacer 7 that is sandwiched between the first conductive layers 22 ⁇ / b> A and 32 ⁇ / b> A of the pair of ceramic substrates 2 and 3.
  • only one spacer 7 is provided, but a plurality of spacers may be provided, for example.
  • the spacer 7 is formed in a rod shape such as a prism or a cylinder, a plate shape, or a block shape, for example.
  • the spacer 7 of this embodiment is a conductive component that electrically connects the first conductive layers 22 ⁇ / b> A and 32 ⁇ / b> A of the pair of ceramic substrates 2 and 3.
  • Examples of the conductive component include a wiring part, a resistor, and a capacitor.
  • the conductive component in the illustrated example is a capacitor having electrodes at both ends in the longitudinal direction.
  • the spacer 7 of this embodiment, which is a conductive component constitutes a circuit of the semiconductor module 1A together with the first conductive layers 22A and 32A, the semiconductor elements 4 and 5 and the connector 6 of the ceramic substrates 2 and 3.
  • the first conductive layers 22A and 32A of the pair of ceramic substrates 2 and 3 are formed with spacer positioning recesses 25 and 35 into which the end portions of the spacer 7 are inserted.
  • a conductive adhesive such as solder
  • each end of the spacer 7 is joined to both the bottom surface and the inner surface, which are the inner surfaces of the spacer positioning recesses 25 and 35.
  • the present invention is not limited to this.
  • the same effects as those of the first embodiment can be obtained. Further, according to the semiconductor module 1A of the present embodiment, since both end portions of the spacer 7 are inserted into the spacer positioning recesses 25 and 35 of the ceramic substrates 2 and 3, the positioning accuracy between the pair of ceramic substrates 2 and 3 is improved. Can be improved.
  • the dimension (length dimension) of the spacer 7 in the arrangement direction of the pair of ceramic substrates 2 and 3 is larger than the dimension of the connector 6 (particularly the element joint portion 62). Can be set.
  • the spacer 7 is more preferable than the connector 6. It expands and contracts greatly in the arranged direction. For this reason, the stress applied to the semiconductor elements 4 and 5 can be reduced based on the expansion and contraction of the connector 6 during the thermal shock test. That is, the semiconductor elements 4 and 5 can be protected even when the semiconductor module 1A is rapidly heated and cooled.
  • the spacer 7 is a conductive component constituting the circuit of the semiconductor module 1A. That is, the spacer 7 of the present embodiment has a function of positioning the pair of ceramic substrates 2 and 3 and a function of constituting a circuit of the semiconductor module 1A. For this reason, the number of components of the semiconductor module 1A can be reduced.
  • the spacer 7 is a conductive component
  • the conductive component mounting area on the ceramic substrates 2 and 3 can be set smaller than when the conductive component is mounted only on one of the ceramic substrates 2 and 3. Accordingly, the size of the ceramic substrates 2 and 3 can be reduced to reduce the size (shrink) of the semiconductor module 1A.
  • the spacer 7 when the spacer 7 is a wiring part or a resistor, there are two paths of current flowing between the pair of ceramic substrates 2 and 3.
  • the first current path is a path that passes through the pair of semiconductor elements 4 and 5 and the connector 6, and the second current path is a path that passes through the spacer 7 that is a conductive component.
  • the circuit of the semiconductor module 1A is set so that the directions of the currents flowing through the first current path and the second current path are opposite to each other, the inductance of the circuit of the semiconductor module 1A is reduced by the mutual inductance. Can also be planned.
  • the semiconductor module according to the present embodiment is configured similarly to the semiconductor module 1A of the second embodiment described above.
  • the elastic member 8 is provided between the bottom surfaces 25 a and 35 a of the spacer positioning recesses 25 and 35 and the end portions of the spacer 7. Yes.
  • the elastic member 8 may be a spring, for example, but may be a resin that can be easily elastically deformed, such as a silicone resin.
  • a liquid silicone resin may be poured into the spacer positioning recesses 25 and 35 and then cured in a gel state.
  • the dimension of the elastic member 8 is preferably set smaller than the depth dimension of the spacer positioning recesses 25 and 35 so that the end of the spacer 7 can be inserted into the spacer positioning recesses 25 and 35. In this case, the end of the spacer 7 inserted into the spacer positioning recesses 25 and 35 can be brought into contact with the inner side surfaces of the spacer positioning recesses 25 and 35. For this reason, even if the spacer 7 is a conductive component as in the illustrated example, the end portion of the spacer 7 and the first conductive layers 22A and 32A of the ceramic substrates 2 and 3 can be electrically connected.
  • the end of the spacer 7 and the inner surface of the spacer positioning recesses 25 and 35 are connected by a conductive adhesive (not shown) such as solder. It may be joined.
  • the same effects as those of the second embodiment can be obtained. Furthermore, according to the semiconductor module of this embodiment, the stress applied to the semiconductor elements 4 and 5 can be relieved by the elastic member 8 being elastically deformed even when pressurized during solder reflow. Specifically, during solder reflow, the semiconductor elements 4, 5 and the connector 6 are appropriately disposed between the pair of ceramic substrates 2, 3 and then between the pair of ceramic substrates 2, 3. A force for sandwiching the semiconductor elements 4 and 5 and the connector 6 is applied, that is, pressure is applied from the arrangement direction of the pair of ceramic substrates 2 and 3.
  • the elastic member 8 is provided between the bottom surfaces 25a and 35a of the spacer positioning recesses 25 and 35 and the end of the spacer 7, the elastic member 8 is elastically deformed by the applied pressure during solder reflow. It is possible to suppress an excessive force from being applied to the semiconductor elements 4 and 5.
  • the length dimension of the spacer 7 in the arrangement direction of the pair of ceramic substrates 2 and 3 is larger than the dimension of the connector 6, and the linear expansion coefficient of the connector 6 and the spacer 7 is larger.
  • the spacer 7 expands and contracts more in the arrangement direction than the connector 6.
  • the elastic member 8 is not provided, there is a possibility that a large stress is applied to the connection portion between the end portion of the spacer 7 and the first conductive layers 22A and 32A.
  • the elastic member 8 when the elastic member 8 is present, the elastic member 8 is elastically deformed as the spacer 7 expands and contracts, so that the stress applied to the joint portion between the end portion of the spacer 7 and the first conductive layers 22A and 32A. Can be relaxed. Therefore, deterioration of the spacer 7 and the first conductive layers 22A and 32A can be prevented.
  • the semiconductor module according to the present embodiment is configured similarly to the semiconductor module 1 of the first embodiment.
  • the molten solder 9 has its own surface tension. This facilitates the flow into the narrow gap between the bottom surfaces 23a, 33a of the element positioning recesses 23, 33 and the inner side surfaces 23b, 33b. That is, the melted solder 9 tends to wet and spread on the bottom surfaces 23 a and 33 a of the element positioning recesses 23 and 33. Thereby, the solder rise to the side surface of the semiconductor elements 4 and 5 can be suppressed. Therefore, it is possible to prevent the electrodes on both main surfaces of the semiconductor elements 4 and 5 from being short-circuited by the solder 9.
  • the configuration of the semiconductor module of the fourth embodiment is also applicable to the semiconductor modules of the second and third embodiments.
  • the semiconductor module 10 includes a pair of ceramic substrates 12 and 13, semiconductor elements 14 and 15, and connectors 16 and 17, as in the first embodiment.
  • the semiconductor elements 14 and 15 are bonded to at least one conductive layer 122 and 132 of a pair of ceramic substrates 12 and 13 described later. Similar to the first embodiment, the semiconductor elements 14 and 15 of the present embodiment are formed in a plate shape and have electrodes on both main surfaces. In the semiconductor elements 14 and 15 of this embodiment, two electrodes (source electrodes 14S and 15S and gate electrodes 14G and 15G) are provided on the first main surface, and one electrode (drain electrodes 14D and 15D) is provided on the second main surface. MOS-FET provided with In the present embodiment, the connectors 16 and 17 are also bonded to the conductive layers 122 and 132 of the pair of ceramic substrates 12 and 13 at least one by one.
  • the ceramic substrates 12 and 13 are configured by providing conductive layers 122 and 132 on both main surfaces of the ceramic plates 121 and 131, respectively.
  • the pair of ceramic substrates 12 and 13 are arranged at an interval in the thickness direction of the ceramic plates 121 and 131 so that the first conductive layers 122A and 132A face each other.
  • the first conductive layers 122A and 132A of the ceramic substrates 12 and 13 are formed as a wiring pattern constituting a circuit of the semiconductor module 10 together with the semiconductor elements 14 and 15 and the connectors 16 and 17.
  • Semiconductor elements 14 and 15 are bonded to the first conductive layers 122A and 132A of the pair of ceramic substrates 12 and 13, respectively. Specifically, one main surface of each of the semiconductor elements 14 and 15 is joined to the first conductive layers 122A and 132A of the ceramic substrates 12 and 13 by a conductive adhesive (not shown) such as solder. Thereby, the semiconductor elements 14 and 15 are electrically connected to the first conductive layers 122A and 132A of the ceramic substrates 12 and 13, respectively. In the present embodiment, the electrodes of the semiconductor elements 14 and 15 bonded to the ceramic substrates 12 and 13 are different from each other.
  • the semiconductor element 14 and the connector 16 bonded to the first conductive layer 122A of the lower ceramic substrate 12 are respectively referred to as the first semiconductor element 14 and the first connector 16. Also called.
  • the semiconductor element 15 and the connector 17 bonded to the first conductive layer 132A of the upper ceramic substrate 13 are referred to as the second semiconductor element 15 and the second connector 17, respectively.
  • Positioning recesses 123 and 124 into which the first semiconductor element 14 and the first connector 16 are individually inserted are formed in the first conductive layer 122A of the first ceramic substrate 12.
  • the element positioning recess 123 into which the first semiconductor element 14 is inserted is also referred to as an element positioning recess 123 or a first element positioning recess 123.
  • the connector positioning recess 124 into which the first connector 16 is inserted is also referred to as a first connector positioning recess 124.
  • the region where the first element positioning recess 123 is formed and the region where the first connector positioning recess 124 is formed are electrically independent from each other.
  • positioning recesses 133 and 134 into which the second semiconductor element 15 and the second connector 17 are individually inserted are formed in the first conductive layer 132A of the second ceramic substrate 13.
  • the element positioning recess 133 into which the second semiconductor element 15 is inserted is also referred to as an element positioning recess 133 or a second element positioning recess 133.
  • the connector positioning recess 134 into which the second connector 17 is inserted is also referred to as a second connector positioning recess 134.
  • the region where the second element positioning recess 133 is formed and the region where the second connector positioning recess 134 is formed are electrically independent from each other.
  • the semiconductor elements 14 and 15 are bonded to the bottom surfaces of the element positioning recesses 123 and 133 in the first conductive layers 122A and 132A.
  • the sizes of the element positioning recesses 123 and 133 are set so that the side portions of the semiconductor elements 14 and 15 do not contact the inner side surfaces of the element positioning recesses 123 and 133.
  • the gap between the side portions of the semiconductor elements 14 and 15 and the inner side surfaces of the element positioning recesses 123 and 133 is preferably as small as possible.
  • the depth dimensions of the element positioning recesses 123 and 133 are the same as those of the first embodiment, with the semiconductor elements 14 and 15 being joined to the bottom surfaces of the element positioning recesses 123 and 133.
  • the positioning recesses 123 and 133 are set so as not to protrude from the surfaces of the first conductive layers 122A and 132A that are opened.
  • the shape of the first element positioning recess 123 is This is the same as in the first embodiment.
  • the first main surface of the second semiconductor element 15 formed with two electrodes (the source electrode 15S and the gate electrode 15G) is joined to the bottom surface of the second element positioning recess 133.
  • the second element positioning recess 133 is formed with a groove 135 that is recessed from the bottom surface and reaches the ceramic plate 131. Two regions on the bottom surface of the second element positioning recess 133 where the two electrodes (the source electrode 15S and the gate electrode 15G) of the second semiconductor element 15 are joined are electrically independent from each other by the groove 135.
  • the pair of ceramic substrates 12 and 13 are arranged such that the first element positioning recess 123 and the second element positioning recess 133 are opposed to each other. That is, the pair of semiconductor elements 14 and 15 bonded to the pair of ceramic substrates 12 and 13 are arranged in the arrangement direction of the pair of ceramic substrates 12 and 13.
  • the first conductive layer 122 ⁇ / b> A of the first ceramic substrate 12 and the first semiconductor element 14 are electrically connected to the connectors 16 and 17 of the present embodiment and joined to the first conductive layer 122 ⁇ / b> A of the first ceramic substrate 12.
  • the semiconductor elements 14 and 15 bonded to the pair of ceramic substrates 12 and 13 are electrically connected to each other, and the first ceramic substrate 13 is connected to the first connector 16.
  • the first connector 16 includes a band plate-shaped main body plate portion 161, an element joint portion 162 provided at a first end portion in the longitudinal direction of the main body plate portion 161 (right end portion in FIG. 5), and a main body plate. And a substrate bonding portion 163 provided at a second end portion (left end portion in FIG. 5) of the portion 161.
  • the element joint 162 of the first connector 16 is joined to the first semiconductor element 14 inserted into the first element positioning recess 123 of the first ceramic substrate 12 by a conductive adhesive (not shown) such as solder. .
  • the element junction 162 is joined to the gate electrode 14G on the first main surface of the first semiconductor element 14.
  • the element bonding portion 162 extends in the thickness direction of the main body plate portion 161 from the main body plate portion 161 toward the first ceramic substrate 12 side.
  • the element joint portion 162 is formed by, for example, bending the first end portion of the main body plate portion 161.
  • the board joint 163 of the first connector 16 is joined to the first conductive layer 122A of the first ceramic board 12 by a conductive adhesive (not shown) such as solder.
  • the substrate bonding portion 163 extends in the thickness direction of the main body plate portion 161 from the main body plate portion 161 toward the first ceramic substrate 12 side.
  • the substrate bonding portion 163 is formed by bending the second end portion of the main body plate portion 161.
  • substrate junction part 163 is inserted in the positioning recessed part 124 for 1st connectors. In the illustrated example, there is no gap between the board joint 163 inserted into the first connector positioning recess 124 and the inner surface of the first connector positioning recess 124, but this is not restrictive.
  • a conductive adhesive such as solder for bonding the substrate bonding portion 163 to the first conductive layer 122A is interposed between the substrate bonding portion 163 and the inner surface of the first connector positioning recess 124. There may be a gap.
  • the second connector 17 includes a band plate-shaped main body plate portion 171, an element joint portion 172 provided at a first end portion in the longitudinal direction of the main body plate portion 171 (left end portion in FIG. 5), and a main body plate. And a substrate bonding portion 173 provided at the second end of the portion 171 (the right end in FIG. 5).
  • the element connecting portion 172 of the second connector 17 is disposed between the element positioning recesses 123 and 133 of the pair of ceramic substrates 12 and 13 and is inserted into the element positioning recesses 123 and 133. , 15.
  • the element joint portion 172 is formed in a block shape larger than the thickness dimension of the main body plate portion 171.
  • the element joint portion 172 is formed so as to protrude on both sides in the thickness direction of the main body plate portion 171.
  • One end of the element joining portion 172 in the protruding direction is joined to the source electrode 14S on the first main surface of the first semiconductor element 14 by a conductive adhesive (not shown) such as solder.
  • the other protruding end portion of the element bonding portion 172 is bonded to the drain electrode 15D on the second main surface of the second semiconductor element 15 by a conductive adhesive (not shown) such as solder.
  • the drain electrode 15D of the second semiconductor element 15 is larger than the source electrode 14S of the first semiconductor element 14.
  • the board joint portion 173 of the second connector 17 is joined to the first conductive layer 132A of the second ceramic board 13 by a conductive adhesive (not shown) such as solder.
  • the substrate bonding portion 173 extends in the thickness direction of the main body plate portion 171 from the main body plate portion 171 toward the second ceramic substrate 13 side.
  • the substrate bonding portion 173 is formed by bending the second end portion of the main body plate portion 171.
  • the front end of the board bonding portion 173 in the extending direction is inserted into the second connector positioning recess 134. In the illustrated example, there is no gap between the board joint portion 173 inserted into the second connector positioning recess 134 and the inner surface of the second connector positioning recess 134, but this is not restrictive.
  • a conductive adhesive such as solder for bonding the substrate bonding portion 173 to the first conductive layer 132A is interposed between the substrate bonding portion 173 and the inner surface of the second connector positioning recess 134. There may be a gap.
  • the semiconductor module 10 of this embodiment described above the same effects as those of the first embodiment can be obtained. That is, when manufacturing the semiconductor module 10, the semiconductor elements 14, 15 and the connectors 16, 17 are simply inserted into the positioning recesses 123, 124, 133, 134 of the ceramic substrates 12, 13, respectively. 15 and connectors 16 and 17 can be easily positioned with respect to the ceramic substrates 12 and 13, respectively. Therefore, the semiconductor module 10 can be manufactured efficiently.
  • the semiconductor module 10 can be thinned. Further, since the element positioning recesses 123 and 133 are formed in the first conductive layers 122A and 132A, the thickness of the first conductive layers 122A and 132A in the bonding region of the semiconductor elements 14 and 15 is the first in other regions. Since the thickness is smaller than that of the conductive layers 122A and 132A, the heat generated in the semiconductor elements 14 and 15 can be efficiently released to the ceramic plates 121 and 131.
  • the semiconductor module 10 of the present embodiment since the pair of semiconductor elements 14 and 15 are arranged in the arrangement direction of the pair of ceramic substrates 12 and 13, the heat of each semiconductor element 14 and 15 is paired. It is possible to efficiently escape to the ceramic substrates 12 and 13.
  • the semiconductor elements 14 and 15 bonded to the ceramic substrates 12 and 13 are formed from the surface of the first conductive layers 122A and 132A where the element positioning recesses 123 and 133 are opened. Does not protrude. Therefore, the height positions of the connectors 16, 17 (particularly the main body plate portions 161, 171) with respect to the surfaces of the first conductive layers 122A, 132A of the ceramic substrates 12, 13, that is, the loop heights of the connectors 16, 17 are as follows. Can be set low. Therefore, the semiconductor module 10 can be further reduced in thickness. Moreover, since the length of each connector 16, 17 can be set short by reducing the loop height of each connector 16, 17, the wiring resistance and parasitic inductance of each connector 16, 17 can be reduced. Can do.
  • the conductive layer of the ceramic substrate is not limited to being provided on both main surfaces of the ceramic plate, and may be provided only on one main surface of the ceramic plate.
  • a sealing resin for sealing the semiconductor element and the connector may be provided between the pair of ceramic substrates.

Abstract

This semiconductor module is provided with: a pair of ceramic substrates provided with a conductive layer at the primary surface of a ceramic plate; semiconductor elements joined to the mutually opposing first conductive layers of the pair of ceramic substrates; and a connector that electrically connects the semiconductor elements joined to the pair of ceramic substrates, and is joined to the first conductive layer of one of the ceramic substrates. Positioning indentations for individually inserting semiconductor elements and the connector are formed at the first conductive layers.

Description

半導体モジュールSemiconductor module
この発明は、半導体モジュールに関する。 The present invention relates to a semiconductor module.
従来の半導体モジュールには、例えば特許文献１のように、基板上に複数の半導体素子を搭載して回路を構成したものがある。
また、近年では、パワーデバイスモジュール等の半導体モジュールの基板として、セラミック板の主面に半導体モジュールの回路として機能する導電層を形成したセラミック基板が用いられることが多い。 As a conventional semiconductor module, for example, as disclosed in Patent Document 1, a circuit is configured by mounting a plurality of semiconductor elements on a substrate.
In recent years, a ceramic substrate in which a conductive layer functioning as a circuit of a semiconductor module is formed on the main surface of a ceramic plate is often used as a substrate of a semiconductor module such as a power device module.
特開２０１０－０１０６４４号公報JP 2010-010644 A
　ところで、パワーデバイスモジュール等の半導体モジュールには、半導体素子の高密度実装あるいは高密度集積が求められている。このような半導体モジュールとしては、例えば、第一セラミック基板、第一半導体素子、接続子、第二半導体素子及び第二セラミック基板の各部品を順番に積層して、これらの部品をはんだにより接合したものが考えられる。
しかしながら、このような半導体モジュールを製造する場合、特に各部品をはんだで接合する際には、各セラミック基板に対する半導体素子や接続子の位置決めが難しい、という問題がある。すなわち、半導体モジュールを効率よく製造できない、という問題がある。 Incidentally, semiconductor modules such as power device modules are required to have high-density mounting or high-density integration of semiconductor elements. As such a semiconductor module, for example, the first ceramic substrate, the first semiconductor element, the connector, the second semiconductor element, and the second ceramic substrate are sequentially laminated, and these components are joined by soldering. Things can be considered.
However, when such a semiconductor module is manufactured, there is a problem in that it is difficult to position the semiconductor element and the connector with respect to each ceramic substrate, particularly when each component is joined with solder. That is, there is a problem that the semiconductor module cannot be manufactured efficiently.
本発明の一態様は、半導体素子や接続子を各セラミック基板に対して容易に位置決めでき、効率よく製造することが可能な半導体モジュールを提供することを目的とする。 An object of one embodiment of the present invention is to provide a semiconductor module in which a semiconductor element and a connector can be easily positioned with respect to each ceramic substrate and can be efficiently manufactured.
本発明の一態様としての半導体モジュールは、セラミック板の少なくとも一方の主面に導電層を設けた一対のセラミック基板と、相互に対向する一対の前記セラミック基板の前記導電層にそれぞれ接合される半導体素子と、一対の前記セラミック基板に接合された前記半導体素子同士を電気接続すると共に、少なくとも一方の前記セラミック基板の前記導電層に接合される接続子と、を備え、前記セラミック基板の前記導電層に、前記半導体素子及び前記接続子を個別に挿入する位置決め凹部が形成されている。 A semiconductor module as one embodiment of the present invention includes a pair of ceramic substrates in which a conductive layer is provided on at least one main surface of a ceramic plate and a semiconductor bonded to the conductive layers of the pair of ceramic substrates facing each other. An electrical connection between the semiconductor elements bonded to the pair of ceramic substrates, and a connector bonded to the conductive layer of at least one of the ceramic substrates, the conductive layer of the ceramic substrate In addition, a positioning recess for individually inserting the semiconductor element and the connector is formed.
本発明の一態様によれば、半導体モジュールを製造する際に、半導体素子及び接続子をそれぞれセラミック基板の位置決め凹部に挿入するだけで、半導体素子及び接続子を各セラミック基板に対して容易に位置決めすることが可能となる。したがって、半導体モジュールを効率よく製造することが可能となる。 According to one aspect of the present invention, when a semiconductor module is manufactured, the semiconductor element and the connector can be easily positioned with respect to each ceramic substrate simply by inserting the semiconductor element and the connector into the positioning recesses of the ceramic substrate. It becomes possible to do. Therefore, it becomes possible to manufacture a semiconductor module efficiently.
本発明の第一実施形態に係る半導体モジュールの概略断面図である。It is a schematic sectional drawing of the semiconductor module which concerns on 1st embodiment of this invention. 本発明の第二実施形態に係る半導体モジュールの概略断面図である。It is a schematic sectional drawing of the semiconductor module which concerns on 2nd embodiment of this invention. 本発明の第三実施形態に係る半導体モジュールの要部を示す拡大断面図である。It is an expanded sectional view showing an important section of a semiconductor module concerning a third embodiment of the present invention. 本発明の第四実施形態に係る半導体モジュールの要部を示す断面図である。It is sectional drawing which shows the principal part of the semiconductor module which concerns on 4th embodiment of this invention. 本発明の第五実施形態に係る半導体モジュールの概略断面図である。It is a schematic sectional drawing of the semiconductor module which concerns on 5th embodiment of this invention.
〔第一実施形態〕
以下、図１を参照して本発明の第一実施形態について説明する。
図１に示すように、本実施形態に係る半導体モジュール１は、一対のセラミック基板２，３、半導体素子４，５及び接続子６を備える。 [First embodiment]
The first embodiment of the present invention will be described below with reference to FIG.
As shown in FIG. 1, the semiconductor module 1 according to this embodiment includes a pair of ceramic substrates 2 and 3, semiconductor elements 4 and 5, and a connector 6.
半導体素子４，５は、後述する一対のセラミック基板２，３の導電層２２，３２に少なくとも一つずつ接合される。半導体素子４，５の種類や形状は、特に限定されるものではない。本実施形態の半導体素子４，５は、板状に形成され、両主面に電極を有する。本実施形態の半導体素子４，５は、各主面に電極を一つずつ有するダイオードである。 The semiconductor elements 4 and 5 are bonded to at least one conductive layer 22 and 32 of a pair of ceramic substrates 2 and 3 to be described later. The type and shape of the semiconductor elements 4 and 5 are not particularly limited. The semiconductor elements 4 and 5 of this embodiment are formed in a plate shape and have electrodes on both main surfaces. The semiconductor elements 4 and 5 of this embodiment are diodes having one electrode on each main surface.
各セラミック基板２，３は、絶縁性を有する板状のセラミック板２１，３１と、セラミック板２１，３１の主面に設けられた導電層２２，３２と、を備える。本実施形態のセラミック基板２，３では、セラミック板２１，３１の両主面に導電層２２，３２が設けられている。導電層２２，３２は、導電性を有していればよいが、例えば銅などのように電気伝導率の高い材料からなるとよい。
一対のセラミック基板２，３は、これらの一方の導電層２２Ａ，３２Ａ（以下、第一導電層２２Ａ，３２Ａと呼ぶ）が相互に対向するように、セラミック板２１，３１の厚さ方向に間隔をあけて配されている。各セラミック基板２，３の第一導電層２２Ａ，３２Ａは、半導体素子４，５及び接続子６と共に半導体モジュール１の回路を構成する配線パターンとして形成されている。 Each ceramic substrate 2, 3 includes plate-shaped ceramic plates 21, 31 having insulating properties, and conductive layers 22, 32 provided on the main surfaces of the ceramic plates 21, 31. In the ceramic substrates 2 and 3 of this embodiment, conductive layers 22 and 32 are provided on both main surfaces of the ceramic plates 21 and 31. The conductive layers 22 and 32 may be conductive, but may be made of a material having high electrical conductivity such as copper.
The pair of ceramic substrates 2 and 3 are spaced in the thickness direction of the ceramic plates 21 and 31 so that one of the conductive layers 22A and 32A (hereinafter referred to as the first conductive layers 22A and 32A) is opposed to each other. It is arranged with a gap. The first conductive layers 22 </ b> A and 32 </ b> A of the ceramic substrates 2 and 3 are formed as a wiring pattern constituting a circuit of the semiconductor module 1 together with the semiconductor elements 4 and 5 and the connector 6.
一対のセラミック基板２，３の第一導電層２２Ａ，３２Ａには、それぞれ半導体素子４，５が接合される。具体的には、各半導体素子４，５の一方の主面が、はんだ等の導電性接着剤（不図示）によって各セラミック基板２，３の第一導電層２２Ａ，３２Ａに接合される。これにより、各半導体素子４，５が各セラミック基板２，３の第一導電層２２Ａ，３２Ａに電気接続される。本実施形態では、各セラミック基板２，３に接合される半導体素子４，５の電極が互いに異なる。
以下、下側のセラミック基板２（以下、第一セラミック基板２とも呼ぶ）の第一導電層２２Ａに接合される半導体素子４を、第一半導体素子４とも呼ぶ。また、上側のセラミック基板３（以下、第二セラミック基板３とも呼ぶ）の第一導電層３２Ａに接合される半導体素子５を、第二半導体素子５とも呼ぶ。 Semiconductor elements 4 and 5 are bonded to the first conductive layers 22A and 32A of the pair of ceramic substrates 2 and 3, respectively. Specifically, one main surface of each of the semiconductor elements 4 and 5 is bonded to the first conductive layers 22A and 32A of the ceramic substrates 2 and 3 by a conductive adhesive (not shown) such as solder. Thus, the semiconductor elements 4 and 5 are electrically connected to the first conductive layers 22A and 32A of the ceramic substrates 2 and 3, respectively. In this embodiment, the electrodes of the semiconductor elements 4 and 5 bonded to the ceramic substrates 2 and 3 are different from each other.
Hereinafter, the semiconductor element 4 bonded to the first conductive layer 22 </ b> A of the lower ceramic substrate 2 (hereinafter also referred to as the first ceramic substrate 2) is also referred to as the first semiconductor element 4. The semiconductor element 5 bonded to the first conductive layer 32 </ b> A of the upper ceramic substrate 3 (hereinafter also referred to as the second ceramic substrate 3) is also referred to as the second semiconductor element 5.
第一セラミック基板２の第一導電層２２Ａには、第一半導体素子４及び接続子６を個別に挿入する位置決め凹部２３，２４が形成されている。以下、第一半導体素子４が挿入される素子用の位置決め凹部２３を、素子用位置決め凹部２３あるいは第一素子用位置決め凹部２３とも呼ぶ。また、接続子６が挿入される接続子用の位置決め凹部２４を、接続子用位置決め凹部２４とも呼ぶ。第一セラミック基板２の第一導電層２２Ａにおいて、第一素子用位置決め凹部２３を形成した領域と、接続子用位置決め凹部２４を形成した領域とは、互いに電気的に独立している。
一方、第二セラミック基板３の第一導電層３２Ａには、第二半導体素子５を挿入する位置決め凹部３３が形成されている。以下、第二半導体素子５が挿入される素子用の位置決め凹部３３を、素子用位置決め凹部３３あるいは第二素子用位置決め凹部３３とも呼ぶ。 In the first conductive layer 22A of the first ceramic substrate 2, positioning recesses 23 and 24 for inserting the first semiconductor element 4 and the connector 6 individually are formed. Hereinafter, the element positioning recess 23 into which the first semiconductor element 4 is inserted is also referred to as an element positioning recess 23 or a first element positioning recess 23. The connector positioning recess 24 into which the connector 6 is inserted is also referred to as a connector positioning recess 24. In the first conductive layer 22A of the first ceramic substrate 2, the region where the first element positioning recess 23 is formed and the region where the connector positioning recess 24 is formed are electrically independent from each other.
On the other hand, a positioning recess 33 for inserting the second semiconductor element 5 is formed in the first conductive layer 32 </ b> A of the second ceramic substrate 3. Hereinafter, the element positioning recess 33 into which the second semiconductor element 5 is inserted is also referred to as an element positioning recess 33 or a second element positioning recess 33.
各半導体素子４，５は、各第一導電層２２Ａ，３２Ａのうち素子用位置決め凹部２３，３３の底面に接合される。ここで、各素子用位置決め凹部２３，３３の大きさは、半導体素子４，５を素子用位置決め凹部２３，３３の底面に接合した状態で、半導体素子４，５の側部が素子用位置決め凹部２３，３３の内側面に接触しないように設定されている。ただし、半導体素子４，５の側部と素子用位置決め凹部２３，３３の内側面との隙間は、できる限り小さくした方がよい。 The semiconductor elements 4 and 5 are bonded to the bottom surfaces of the element positioning recesses 23 and 33 in the first conductive layers 22A and 32A. Here, the size of each of the element positioning recesses 23 and 33 is such that the side portions of the semiconductor elements 4 and 5 are in the element positioning recesses while the semiconductor elements 4 and 5 are joined to the bottom surfaces of the element positioning recesses 23 and 33. 23 and 33 are set so as not to contact the inner side surfaces. However, the gap between the side portions of the semiconductor elements 4 and 5 and the inner side surfaces of the element positioning recesses 23 and 33 is preferably as small as possible.
また、各素子用位置決め凹部２３，３３の深さ寸法は、半導体素子４，５を素子用位置決め凹部２３，３３の底面に接合した状態で、半導体素子４，５が素子用位置決め凹部２３，３３が開口する第一導電層２２Ａ，３２Ａの表面から突出しないように設定されている。半導体素子４，５が素子用位置決め凹部２３，３３に挿入された状態では、例えば、後述する接続子６に接合される半導体素子４，５の主面が、第一導電層２２Ａ，３２Ａの表面と同じ高さに位置してもよいし、第一導電層２２Ａ，３２Ａの表面よりも低く位置してもよい。 The depth dimensions of the element positioning recesses 23 and 33 are such that the semiconductor elements 4 and 5 are joined to the bottom surfaces of the element positioning recesses 23 and 33 and the semiconductor elements 4 and 5 are in contact with the element positioning recesses 23 and 33. Is set so as not to protrude from the surfaces of the first conductive layers 22A and 32A that are open. In a state where the semiconductor elements 4 and 5 are inserted into the element positioning recesses 23 and 33, for example, the main surfaces of the semiconductor elements 4 and 5 joined to the connector 6 described later are the surfaces of the first conductive layers 22A and 32A. It may be located at the same height as or lower than the surfaces of the first conductive layers 22A and 32A.
一対のセラミック基板２，３は、上記した第一素子用位置決め凹部２３及び第二素子用位置決め凹部３３が相互に対向するように配されている。すなわち、一対のセラミック基板２，３にそれぞれ接合された一対の半導体素子４，５は、一対のセラミック基板２，３の配列方向に並べて配置されている。 The pair of ceramic substrates 2 and 3 are arranged such that the first element positioning recess 23 and the second element positioning recess 33 face each other. That is, the pair of semiconductor elements 4 and 5 respectively joined to the pair of ceramic substrates 2 and 3 are arranged side by side in the arrangement direction of the pair of ceramic substrates 2 and 3.
接続子６は、一対のセラミック基板２，３に接合された半導体素子４，５同士を電気接続すると共に、少なくとも一方のセラミック基板２，３の第一導電層２２Ａ，３２Ａに接合される。本実施形態の接続子６は、第一セラミック基板２の第一導電層２２Ａに接合される。
接続子６は、銅などの導電性材料からなる。接続子６は、帯板状の本体板部６１と、本体板部６１の長手方向の第一端部（図１において右側の端部）に設けられた素子接合部６２と、本体板部６１の第二端部（図１において左側の端部）に設けられた基板接合部６３と、を備える。 The connector 6 electrically connects the semiconductor elements 4 and 5 joined to the pair of ceramic substrates 2 and 3 and is joined to the first conductive layers 22A and 32A of at least one of the ceramic substrates 2 and 3. The connector 6 of this embodiment is joined to the first conductive layer 22 </ b> A of the first ceramic substrate 2.
The connector 6 is made of a conductive material such as copper. The connector 6 includes a band plate-shaped main body plate portion 61, an element joining portion 62 provided at a first end portion in the longitudinal direction of the main body plate portion 61 (right end portion in FIG. 1), and a main body plate portion 61. And a substrate bonding portion 63 provided at the second end (the left end in FIG. 1).
素子接合部６２は、一対のセラミック基板２，３の素子用位置決め凹部２３，３３の間に配され、各素子用位置決め凹部２３，３３に挿入された一対の半導体素子４，５に接合される。素子接合部６２は、本体板部６１の厚さ寸法よりも大きいブロック状に形成されている。本実施形態の素子接合部６２は、本体板部６１の厚さ方向の両側に突出して形成されている。素子接合部６２の両方の突出方向先端部は、はんだ等の導電性接着剤（不図示）によって相互に対向する一対の半導体素子４，５の主面に接合される。すなわち、素子接合部６２は、一対の半導体素子４，５によって挟み込まれる。 The element joint 62 is disposed between the element positioning recesses 23 and 33 of the pair of ceramic substrates 2 and 3 and is bonded to the pair of semiconductor elements 4 and 5 inserted into the element positioning recesses 23 and 33. . The element joint portion 62 is formed in a block shape larger than the thickness dimension of the main body plate portion 61. The element joint portion 62 of the present embodiment is formed to protrude on both sides in the thickness direction of the main body plate portion 61. Both protruding ends of the element bonding portion 62 are bonded to the main surfaces of the pair of semiconductor elements 4 and 5 facing each other by a conductive adhesive (not shown) such as solder. That is, the element junction 62 is sandwiched between the pair of semiconductor elements 4 and 5.
基板接合部６３は、はんだ等の導電性接着剤（不図示）によって第一セラミック基板２の第一導電層２２Ａに接合される。基板接合部６３は、本体板部６１から第一セラミック基板２側に向けて本体板部６１の厚さ方向に延びている。基板接合部６３は、本体板部６１の第二端部を折り曲げることで形成されている。基板接合部６３の延出方向先端部は、接続子用位置決め凹部２４に挿入される。
図示例では、接続子用位置決め凹部２４に挿入された基板接合部６３と接続子用位置決め凹部２４の内面との間に隙間が無いが、これに限ることはない。例えば、基板接合部６３と接続子用位置決め凹部２４の内面との間には、基板接合部６３を第一導電層２２Ａに接合するためのはんだ等の導電性接着剤が介在する程度の隙間があってもよい。 The substrate bonding portion 63 is bonded to the first conductive layer 22A of the first ceramic substrate 2 by a conductive adhesive (not shown) such as solder. The substrate bonding portion 63 extends in the thickness direction of the main body plate portion 61 from the main body plate portion 61 toward the first ceramic substrate 2 side. The substrate bonding portion 63 is formed by bending the second end portion of the main body plate portion 61. The front end of the board bonding portion 63 in the extending direction is inserted into the connector positioning recess 24.
In the illustrated example, there is no gap between the board joint 63 inserted in the connector positioning recess 24 and the inner surface of the connector positioning recess 24, but the present invention is not limited to this. For example, there is a gap between the substrate bonding portion 63 and the inner surface of the connector positioning recess 24 so that a conductive adhesive such as solder for bonding the substrate bonding portion 63 to the first conductive layer 22A is interposed. There may be.
上記した本実施形態の半導体モジュール１を製造する際には、半導体素子４，５及び接続子６をそれぞれセラミック基板２，３の位置決め凹部２３，２４，２５に挿入するだけで、半導体素子４，５及び接続子６を各セラミック基板２，３に対して容易に位置決めすることが可能となる。したがって、半導体モジュール１を効率よく製造することができる。
例えば、一対のセラミック基板２，３の間に半導体素子４，５及び接続子６を適宜配置するだけで、半導体素子４，５及び接続子６がセラミック基板２，３に対して位置決めされる。これにより、一対のセラミック基板２，３の間に半導体素子４，５及び接続子６を配置した状態ではんだリフローを実施して、セラミック基板２，３と半導体素子４，５との接合、半導体素子４，５と接続子６との接合、及び、セラミック基板２，３と接続子６との接合を一括して行うことができる。 When manufacturing the semiconductor module 1 of the above-described embodiment, the semiconductor elements 4, 5 and the connector 6 are inserted into the positioning recesses 23, 24, 25 of the ceramic substrates 2, 3, respectively. 5 and the connector 6 can be easily positioned with respect to the ceramic substrates 2 and 3. Therefore, the semiconductor module 1 can be manufactured efficiently.
For example, the semiconductor elements 4, 5 and the connector 6 are positioned with respect to the ceramic substrates 2, 3 only by appropriately arranging the semiconductor elements 4, 5 and the connector 6 between the pair of ceramic substrates 2, 3. Thus, solder reflow is performed in a state where the semiconductor elements 4 and 5 and the connector 6 are disposed between the pair of ceramic substrates 2 and 3, and the bonding between the ceramic substrates 2 and 3 and the semiconductor elements 4 and 5 is performed. Bonding between the elements 4 and 5 and the connector 6 and bonding between the ceramic substrates 2 and 3 and the connector 6 can be performed collectively.
また、本実施形態の半導体モジュール１によれば、その製造に際して、治具を用いて一対のセラミック基板２，３に対する半導体素子４，５及び接続子６の位置決めを行う場合と比較して、半導体モジュール１の製造効率向上及び歩留まり向上を図ることができる。
具体的に説明すれば、治具を用いてセラミック基板２，３に対する半導体素子４，５及び接続子６の位置決めを行う場合、治具を取り付ける工程、取り外す工程が必要となる。また、はんだリフローの際にセラミック基板２，３と半導体素子４，５との接合部分等のはんだが治具にも付着し、治具を取り外し難くなる可能性がある。このため、半導体モジュールの製造効率が低下する虞がある。さらに、上記した接合部分のはんだが治具に付着すると、治具を取り外す際に半導体素子４，５にチップクラックが発生することがあるため、半導体モジュールの歩留まり低下を招いてしまう。
これに対し、本実施形態の半導体モジュール１によれば、これを製造する際に上記した治具が不要となるため、治具の取付及び取外しが不要となり、半導体モジュール１の製造効率の向上を図ることができる。また、半導体モジュール１を製造する際には、上記チップクラックが発生することもないため、半導体モジュール１の歩留まり向上を図ることもできる。 In addition, according to the semiconductor module 1 of the present embodiment, the semiconductor module 1 is manufactured in comparison with the case where the semiconductor elements 4 and 5 and the connector 6 are positioned with respect to the pair of ceramic substrates 2 and 3 using a jig. It is possible to improve the manufacturing efficiency and the yield of the module 1.
If it demonstrates concretely, when positioning the semiconductor elements 4 and 5 and the connector 6 with respect to the ceramic substrates 2 and 3 using a jig | tool, the process of attaching a jig | tool and the process of removing are needed. In addition, during solder reflow, solder such as a joint between the ceramic substrates 2 and 3 and the semiconductor elements 4 and 5 may adhere to the jig, making it difficult to remove the jig. For this reason, there exists a possibility that the manufacture efficiency of a semiconductor module may fall. Furthermore, when the solder at the above-mentioned joining portion adheres to the jig, chip cracks may occur in the semiconductor elements 4 and 5 when the jig is removed, which leads to a decrease in the yield of the semiconductor module.
On the other hand, according to the semiconductor module 1 of the present embodiment, the above-described jig is not required when manufacturing the semiconductor module 1, so that attachment and detachment of the jig are not required, and the manufacturing efficiency of the semiconductor module 1 is improved. Can be planned. Further, when the semiconductor module 1 is manufactured, the chip crack does not occur, so that the yield of the semiconductor module 1 can be improved.
さらに、本実施形態の半導体モジュール１によれば、半導体素子４，５が素子用位置決め凹部２３，３３に挿入されるため、半導体モジュール１の薄型化を図ることができる。
特に、本実施形態において、素子用位置決め凹部２３，３３に挿入された半導体素子４，５は、素子用位置決め凹部２３，３３が開口する第一導電層２２Ａ，３２Ａの表面から突出しない。このため、半導体モジュール１の薄型化をさらに図ることができる。 Furthermore, according to the semiconductor module 1 of the present embodiment, since the semiconductor elements 4 and 5 are inserted into the element positioning recesses 23 and 33, the semiconductor module 1 can be thinned.
In particular, in this embodiment, the semiconductor elements 4 and 5 inserted into the element positioning recesses 23 and 33 do not protrude from the surfaces of the first conductive layers 22A and 32A where the element positioning recesses 23 and 33 are opened. For this reason, the semiconductor module 1 can be further reduced in thickness.
また、本実施形態の半導体モジュール１によれば、第一導電層２２Ａ，３２Ａに素子用位置決め凹部２３，３３が形成されていることで、半導体素子４，５の接合領域における第一導電層２２Ａ，３２Ａの厚みが他の領域における第一導電層２２Ａ，３２Ａの厚みよりも薄くなる。このため、半導体素子４，５において発生した熱を効率よくセラミック板２１，３１に逃がすことも可能となる。すなわち、半導体素子４，５の放熱効率向上を図ることができる。 Further, according to the semiconductor module 1 of the present embodiment, the first conductive layers 22A and 32A are formed with the element positioning recesses 23 and 33, whereby the first conductive layer 22A in the junction region of the semiconductor elements 4 and 5 is formed. , 32A is thinner than the thickness of the first conductive layers 22A, 32A in the other regions. For this reason, the heat generated in the semiconductor elements 4 and 5 can be efficiently released to the ceramic plates 21 and 31. That is, the heat dissipation efficiency of the semiconductor elements 4 and 5 can be improved.
さらに、本実施形態の半導体モジュール１によれば、一対のセラミック基板２，３に接合された一対の半導体素子４，５が、一対のセラミック基板２，３の配列方向に並べて配置されている。このため、半導体素子４，５の熱を一対のセラミック基板２，３の両方に効率よく逃がすことが可能となる。
例えば、第一セラミック基板２に接合された第一半導体素子４の熱は、第一セラミック基板２側に逃がすだけではなく、第二セラミック基板３に接合された第二半導体素子５を介して第二セラミック基板３側にも逃がすことができる。特に、一対の半導体素子４，５の間に介在する接続子６における第一半導体素子４の放熱経路を最小限に抑えて、第一半導体素子４の熱を第二セラミック基板３側にも効率よく逃がすことが可能となる。 Furthermore, according to the semiconductor module 1 of the present embodiment, the pair of semiconductor elements 4 and 5 joined to the pair of ceramic substrates 2 and 3 are arranged side by side in the arrangement direction of the pair of ceramic substrates 2 and 3. For this reason, the heat of the semiconductor elements 4 and 5 can be efficiently released to both the pair of ceramic substrates 2 and 3.
For example, the heat of the first semiconductor element 4 bonded to the first ceramic substrate 2 not only escapes to the first ceramic substrate 2 side but also passes through the second semiconductor element 5 bonded to the second ceramic substrate 3. It can also escape to the two ceramic substrate 3 side. In particular, the heat dissipation path of the first semiconductor element 4 in the connector 6 interposed between the pair of semiconductor elements 4 and 5 is minimized, and the heat of the first semiconductor element 4 is also efficiently transferred to the second ceramic substrate 3 side. It is possible to escape well.
また、本実施形態の半導体モジュール１によれば、第一セラミック基板２に接合された第一半導体素子４は、第一セラミック基板２の第一素子用位置決め凹部２３が開口する第一導電層２２Ａの表面から突出しない。このため、第一セラミック基板２の第一導電層２２Ａの表面に対する接続子６（特に本体板部６１）の高さ位置、すなわち接続子６のループ高さを低く設定できる。したがって、半導体モジュール１の薄型化をさらに図ることができる。 Further, according to the semiconductor module 1 of the present embodiment, the first semiconductor element 4 bonded to the first ceramic substrate 2 has the first conductive layer 22A in which the first element positioning recess 23 of the first ceramic substrate 2 is opened. Does not protrude from the surface of For this reason, the height position of the connector 6 (particularly the main body plate portion 61) with respect to the surface of the first conductive layer 22A of the first ceramic substrate 2, that is, the loop height of the connector 6 can be set low. Therefore, the semiconductor module 1 can be further reduced in thickness.
また、第一セラミック基板２の第一導電層２２Ａの表面に対する接続子６（特に本体板部６１）の高さ位置が低くなることで、第一半導体素子４から第一セラミック基板２の第一導電層２２Ａに至る接続子６の長さを短く設定できる。したがって、接続子６の配線抵抗及び寄生インダクタンスの低減を図ることができる。 Further, the height position of the connector 6 (particularly the main body plate portion 61) with respect to the surface of the first conductive layer 22A of the first ceramic substrate 2 is lowered, so that the first ceramic element 2 to the first ceramic substrate 2 are firstly connected. The length of the connector 6 reaching the conductive layer 22A can be set short. Therefore, the wiring resistance and parasitic inductance of the connector 6 can be reduced.
〔第二実施形態〕
次に、本発明の第二実施形態について、図２を参照して第一実施形態との相違点を中心に説明する。なお、第一実施形態と共通する構成については、同一符号を付し、その説明を省略する。 [Second Embodiment]
Next, a second embodiment of the present invention will be described with a focus on differences from the first embodiment with reference to FIG. In addition, about the structure which is common in 1st embodiment, the same code | symbol is attached | subjected and the description is abbreviate | omitted.
図２に示すように、本実施形態に係る半導体モジュール１Ａは、上記した第一実施形態の半導体モジュール１と同様に構成されている。その上で、本実施形態の半導体モジュール１Ａは、一対のセラミック基板２，３の第一導電層２２Ａ，３２Ａの間に挟み込まれるスペーサ７を備える。図示例では、スペーサ７が一つだけ設けられているが、例えば複数設けられてもよい。 As shown in FIG. 2, the semiconductor module 1A according to the present embodiment is configured in the same manner as the semiconductor module 1 of the first embodiment described above. In addition, the semiconductor module 1 </ b> A of the present embodiment includes a spacer 7 that is sandwiched between the first conductive layers 22 </ b> A and 32 </ b> A of the pair of ceramic substrates 2 and 3. In the illustrated example, only one spacer 7 is provided, but a plurality of spacers may be provided, for example.
スペーサ７は、例えば角柱や円柱等の棒状あるいは板状あるいはブロック状に形成されている。本実施形態のスペーサ７は、一対のセラミック基板２，３の第一導電層２２Ａ，３２Ａ同士を電気接続する導電部品である。導電部品としては、例えば配線部、抵抗器、コンデンサなどが挙げられる。図示例の導電部品は、長手方向の両端部に電極を有するコンデンサである。
導電部品である本実施形態のスペーサ７は、各セラミック基板２，３の第一導電層２２Ａ，３２Ａ、半導体素子４，５及び接続子６と共に半導体モジュール１Ａの回路を構成する。 The spacer 7 is formed in a rod shape such as a prism or a cylinder, a plate shape, or a block shape, for example. The spacer 7 of this embodiment is a conductive component that electrically connects the first conductive layers 22 </ b> A and 32 </ b> A of the pair of ceramic substrates 2 and 3. Examples of the conductive component include a wiring part, a resistor, and a capacitor. The conductive component in the illustrated example is a capacitor having electrodes at both ends in the longitudinal direction.
The spacer 7 of this embodiment, which is a conductive component, constitutes a circuit of the semiconductor module 1A together with the first conductive layers 22A and 32A, the semiconductor elements 4 and 5 and the connector 6 of the ceramic substrates 2 and 3.
一対のセラミック基板２，３の各第一導電層２２Ａ，３２Ａには、上記したスペーサ７の各端部を挿入するスペーサ位置決め凹部２５，３５が形成されている。
図示例では、スペーサ位置決め凹部２５，３５に挿入されたスペーサ７の各端部と各スペーサ位置決め凹部２５，３５の内面との間に隙間が無いが、これに限ることはない。例えば、スペーサ７の各端部と各スペーサ位置決め凹部２５，３５の内面との間には、スペーサ７の端部を第一導電層２２Ａ，３２Ａに接合するためのはんだ等の導電性接着剤（不図示）が介在する程度の隙間があってもよい。本実施形態では、スペーサ７の各端部が、各スペーサ位置決め凹部２５，３５の内面である底面及び内側面の両方に接合される。
また、図示例では、各セラミック基板２，３の第一導電層２２Ａ，３２Ａにおいて、スペーサ位置決め凹部２５，３５を形成した領域と、素子用位置決め凹部２３，３３や接続子用位置決め凹部２４を形成した領域とが、互いに電気的に独立しているが、これに限ることはない。 The first conductive layers 22A and 32A of the pair of ceramic substrates 2 and 3 are formed with spacer positioning recesses 25 and 35 into which the end portions of the spacer 7 are inserted.
In the illustrated example, there is no gap between each end of the spacer 7 inserted into the spacer positioning recesses 25 and 35 and the inner surface of each spacer positioning recess 25 and 35, but this is not restrictive. For example, between each end of the spacer 7 and the inner surface of each spacer positioning recess 25, 35, a conductive adhesive (such as solder) for joining the end of the spacer 7 to the first conductive layers 22A, 32A ( There may be a gap to the extent that (not shown) intervenes. In the present embodiment, each end of the spacer 7 is joined to both the bottom surface and the inner surface, which are the inner surfaces of the spacer positioning recesses 25 and 35.
In the illustrated example, in the first conductive layers 22A and 32A of the ceramic substrates 2 and 3, regions where the spacer positioning recesses 25 and 35 are formed, element positioning recesses 23 and 33, and connector positioning recesses 24 are formed. However, the present invention is not limited to this.
本実施形態の半導体モジュール１Ａによれば、第一実施形態と同様の効果を奏する。
また、本実施形態の半導体モジュール１Ａによれば、スペーサ７の両端部が各セラミック基板２，３のスペーサ位置決め凹部２５，３５に挿入されるため、一対のセラミック基板２，３同士の位置決め精度を向上させることができる。 According to the semiconductor module 1A of the present embodiment, the same effects as those of the first embodiment can be obtained.
Further, according to the semiconductor module 1A of the present embodiment, since both end portions of the spacer 7 are inserted into the spacer positioning recesses 25 and 35 of the ceramic substrates 2 and 3, the positioning accuracy between the pair of ceramic substrates 2 and 3 is improved. Can be improved.
さらに、本実施形態の半導体モジュール１Ａによれば、一対のセラミック基板２，３の配列方向におけるスペーサ７の寸法（長さ寸法）を、接続子６（特に素子接合部６２）の寸法よりも大きく設定できる。その上で、接続子６とスペーサ７の熱膨張係数が同じである場合、半導体モジュール１Ａを急激に加熱冷却する熱衝撃試験を実施した際には、接続子６よりもスペーサ７の方が上記した配列方向に大きく伸縮する。このため、熱衝撃試験時における接続子６の膨張収縮に基づいて半導体素子４，５にかかる応力を低減できる。すなわち、半導体モジュール１Ａを急激に加熱冷却しても半導体素子４，５を保護することができる。 Furthermore, according to the semiconductor module 1A of the present embodiment, the dimension (length dimension) of the spacer 7 in the arrangement direction of the pair of ceramic substrates 2 and 3 is larger than the dimension of the connector 6 (particularly the element joint portion 62). Can be set. In addition, when the thermal expansion coefficient of the connector 6 and the spacer 7 is the same, when the thermal shock test for rapidly heating and cooling the semiconductor module 1A is performed, the spacer 7 is more preferable than the connector 6. It expands and contracts greatly in the arranged direction. For this reason, the stress applied to the semiconductor elements 4 and 5 can be reduced based on the expansion and contraction of the connector 6 during the thermal shock test. That is, the semiconductor elements 4 and 5 can be protected even when the semiconductor module 1A is rapidly heated and cooled.
また、本実施形態の半導体モジュール１Ａでは、スペーサ７が半導体モジュール１Ａの回路を構成する導電部品である。すなわち、本実施形態のスペーサ７は、一対のセラミック基板２，３同士を位置決めする機能、及び、半導体モジュール１Ａの回路を構成する機能を有する。このため、半導体モジュール１Ａの構成部品点数を削減できる。 Further, in the semiconductor module 1A of the present embodiment, the spacer 7 is a conductive component constituting the circuit of the semiconductor module 1A. That is, the spacer 7 of the present embodiment has a function of positioning the pair of ceramic substrates 2 and 3 and a function of constituting a circuit of the semiconductor module 1A. For this reason, the number of components of the semiconductor module 1A can be reduced.
さらに、スペーサ７が導電部品である場合、導電部品をいずれかのセラミック基板２，３のみに搭載する場合と比較して、セラミック基板２，３における導電部品の搭載領域を小さく設定できる。したがって、セラミック基板２，３の大きさを小さくして、半導体モジュール１Ａの小型化（シュリンク）を図ることができる。 Furthermore, when the spacer 7 is a conductive component, the conductive component mounting area on the ceramic substrates 2 and 3 can be set smaller than when the conductive component is mounted only on one of the ceramic substrates 2 and 3. Accordingly, the size of the ceramic substrates 2 and 3 can be reduced to reduce the size (shrink) of the semiconductor module 1A.
また、本実施形態の半導体モジュール１Ａにおいて、スペーサ７が配線部や抵抗器である場合、一対のセラミック基板２，３の間において流れる電流の経路が二つ存在する。第一の電流経路は一対の半導体素子４，５及び接続子６を通る経路であり、第二の電流経路は導電部品であるスペーサ７を通る経路である。ここで、第一の電流経路及び第二の電流経路を流れる電流の向きが互いに逆向きとなるように半導体モジュール１Ａの回路を設定すれば、相互インダクタンスによって、半導体モジュール１Ａの回路の低インダクタンス化を図ることもできる。 Further, in the semiconductor module 1A of the present embodiment, when the spacer 7 is a wiring part or a resistor, there are two paths of current flowing between the pair of ceramic substrates 2 and 3. The first current path is a path that passes through the pair of semiconductor elements 4 and 5 and the connector 6, and the second current path is a path that passes through the spacer 7 that is a conductive component. Here, if the circuit of the semiconductor module 1A is set so that the directions of the currents flowing through the first current path and the second current path are opposite to each other, the inductance of the circuit of the semiconductor module 1A is reduced by the mutual inductance. Can also be planned.
〔第三実施形態〕
次に、本発明の第三実施形態について、図３を参照して第二実施形態との相違点を中心に説明する。なお、第一、第二実施形態と共通する構成については、同一符号を付し、その説明を省略する。 [Third embodiment]
Next, a third embodiment of the present invention will be described with a focus on differences from the second embodiment with reference to FIG. In addition, about the structure which is common in 1st, 2nd embodiment, the same code | symbol is attached | subjected and the description is abbreviate | omitted.
本実施形態に係る半導体モジュールは、上記した第二実施形態の半導体モジュール１Ａと同様に構成されている。その上で、本実施形態の半導体モジュールでは、図３に示すように、各スペーサ位置決め凹部２５，３５の底面２５ａ，３５ａとスペーサ７の各端部との間に、弾性部材８が設けられている。
弾性部材８としては、例えばバネであってもよいが、例えばシリコーン樹脂などのように容易に弾性変形可能な樹脂であってもよい。弾性部材８がシリコーン樹脂である場合には、例えば、液体状のシリコーン樹脂をスペーサ位置決め凹部２５，３５に流し込んだ後、ゲル状に硬化させればよい。 The semiconductor module according to the present embodiment is configured similarly to the semiconductor module 1A of the second embodiment described above. In addition, in the semiconductor module of the present embodiment, as shown in FIG. 3, the elastic member 8 is provided between the bottom surfaces 25 a and 35 a of the spacer positioning recesses 25 and 35 and the end portions of the spacer 7. Yes.
The elastic member 8 may be a spring, for example, but may be a resin that can be easily elastically deformed, such as a silicone resin. In the case where the elastic member 8 is a silicone resin, for example, a liquid silicone resin may be poured into the spacer positioning recesses 25 and 35 and then cured in a gel state.
弾性部材８の寸法は、スペーサ７の端部をスペーサ位置決め凹部２５，３５に挿入できるように、スペーサ位置決め凹部２５，３５の深さ寸法よりも小さく設定されているとよい。この場合、スペーサ位置決め凹部２５，３５に挿入されたスペーサ７の端部をスペーサ位置決め凹部２５，３５の内側面に接触させることができる。このため、スペーサ７が図示例のように導電部品であっても、スペーサ７の端部と各セラミック基板２，３の第一導電層２２Ａ，３２Ａとを電気接続することができる。
スペーサ７と第一導電層２２Ａ，３２Ａとを電気接続させるためには、例えば、スペーサ７の端部とスペーサ位置決め凹部２５，３５の内側面とがはんだ等の導電性接着剤（不図示）によって接合されてもよい。 The dimension of the elastic member 8 is preferably set smaller than the depth dimension of the spacer positioning recesses 25 and 35 so that the end of the spacer 7 can be inserted into the spacer positioning recesses 25 and 35. In this case, the end of the spacer 7 inserted into the spacer positioning recesses 25 and 35 can be brought into contact with the inner side surfaces of the spacer positioning recesses 25 and 35. For this reason, even if the spacer 7 is a conductive component as in the illustrated example, the end portion of the spacer 7 and the first conductive layers 22A and 32A of the ceramic substrates 2 and 3 can be electrically connected.
In order to electrically connect the spacer 7 and the first conductive layers 22A and 32A, for example, the end of the spacer 7 and the inner surface of the spacer positioning recesses 25 and 35 are connected by a conductive adhesive (not shown) such as solder. It may be joined.
本実施形態の半導体モジュールによれば、第二実施形態と同様の効果を奏する。
さらに、本実施形態の半導体モジュールによれば、はんだリフロー時に加圧しても弾性部材８が弾性変形することで、半導体素子４，５にかかる応力を緩和することができる。具体的に説明すれば、はんだリフローの際には、一対のセラミック基板２，３の間に半導体素子４，５及び接続子６を適宜配置した上で、一対のセラミック基板２，３の間に半導体素子４，５及び接続子６を挟み込む力を加える、すなわち、一対のセラミック基板２，３の配列方向から加圧する。ここで、スペーサ位置決め凹部２５，３５の底面２５ａ，３５ａとスペーサ７の端部との間に弾性部材８が設けられていれば、はんだリフロー時における加圧力によって弾性部材８が弾性変形するため、半導体素子４，５に過度な力が加わることを抑制できる。 According to the semiconductor module of the present embodiment, the same effects as those of the second embodiment can be obtained.
Furthermore, according to the semiconductor module of this embodiment, the stress applied to the semiconductor elements 4 and 5 can be relieved by the elastic member 8 being elastically deformed even when pressurized during solder reflow. Specifically, during solder reflow, the semiconductor elements 4, 5 and the connector 6 are appropriately disposed between the pair of ceramic substrates 2, 3 and then between the pair of ceramic substrates 2, 3. A force for sandwiching the semiconductor elements 4 and 5 and the connector 6 is applied, that is, pressure is applied from the arrangement direction of the pair of ceramic substrates 2 and 3. Here, if the elastic member 8 is provided between the bottom surfaces 25a and 35a of the spacer positioning recesses 25 and 35 and the end of the spacer 7, the elastic member 8 is elastically deformed by the applied pressure during solder reflow. It is possible to suppress an excessive force from being applied to the semiconductor elements 4 and 5.
また、第二実施形態において述べたように、一対のセラミック基板２，３の配列方向におけるスペーサ７の長さ寸法が接続子６の寸法よりも大きく、接続子６とスペーサ７の線膨張係数が同じである場合には、半導体モジュールに対して熱衝撃試験を実施した際に、スペーサ７が接続子６よりも配列方向に大きく伸縮する。ここで、弾性部材８が無い場合には、スペーサ７の端部と第一導電層２２Ａ，３２Ａとの接続部分に大きな応力がかかる虞がある。これに対し、弾性部材８がある場合には、スペーサ７の伸縮に伴って弾性部材８が弾性変形することで、スペーサ７の端部と第一導電層２２Ａ，３２Ａとの接合部分にかかる応力を緩和できる。したがって、スペーサ７や第一導電層２２Ａ，３２Ａの劣化を防ぐことができる。 Further, as described in the second embodiment, the length dimension of the spacer 7 in the arrangement direction of the pair of ceramic substrates 2 and 3 is larger than the dimension of the connector 6, and the linear expansion coefficient of the connector 6 and the spacer 7 is larger. In the case of the same, when the thermal shock test is performed on the semiconductor module, the spacer 7 expands and contracts more in the arrangement direction than the connector 6. Here, when the elastic member 8 is not provided, there is a possibility that a large stress is applied to the connection portion between the end portion of the spacer 7 and the first conductive layers 22A and 32A. On the other hand, when the elastic member 8 is present, the elastic member 8 is elastically deformed as the spacer 7 expands and contracts, so that the stress applied to the joint portion between the end portion of the spacer 7 and the first conductive layers 22A and 32A. Can be relaxed. Therefore, deterioration of the spacer 7 and the first conductive layers 22A and 32A can be prevented.
〔第四実施形態〕
次に、本発明の第四実施形態について、図４を参照して第一実施形態との相違点を中心に説明する。なお、第一実施形態と共通する構成については、同一符号を付し、その説明を省略する。 [Fourth embodiment]
Next, a fourth embodiment of the present invention will be described with a focus on differences from the first embodiment with reference to FIG. In addition, about the structure which is common in 1st embodiment, the same code | symbol is attached | subjected and the description is abbreviate | omitted.
本実施形態に係る半導体モジュールは、第一実施形態の半導体モジュール１と同様に構成される。その上で、本実施形態の半導体モジュールでは、図４に示すように、各セラミック基板２，３の第一導電層２２Ａ，３２Ａに形成された素子用位置決め凹部２３，３３の内側面２３ｂ，３３ｂが、素子用位置決め凹部２３，３３の底面２３ａ，３３ａから開口側に向かうにしたがって内側に傾斜している。 The semiconductor module according to the present embodiment is configured similarly to the semiconductor module 1 of the first embodiment. In addition, in the semiconductor module of this embodiment, as shown in FIG. 4, inner side surfaces 23b and 33b of the element positioning recesses 23 and 33 formed in the first conductive layers 22A and 32A of the ceramic substrates 2 and 3, respectively. However, it inclines inside as it goes to the opening side from the bottom face 23a, 33a of the positioning recessed parts 23, 33 for elements.
本実施形態の半導体モジュールによれば、はんだリフローによって半導体素子４，５の一方の主面を素子用位置決め凹部２３，３３の底面２３ａ，３３ａに接合する際、溶融したはんだ９が自身の表面張力によって素子用位置決め凹部２３，３３の底面２３ａ，３３ａと内側面２３ｂ，３３ｂとの狭い隙間に流れ込みやすくなる。すなわち、溶融したはんだ９が素子用位置決め凹部２３，３３の底面２３ａ，３３ａにおいて濡れ広がりやすくなる。これにより、半導体素子４，５の側面へのはんだ上がりを抑制することができる。したがって、半導体素子４，５の両主面の電極同士がはんだ９によって短絡することを防止できる。 According to the semiconductor module of this embodiment, when one main surface of the semiconductor elements 4 and 5 is joined to the bottom surfaces 23a and 33a of the element positioning recesses 23 and 33 by solder reflow, the molten solder 9 has its own surface tension. This facilitates the flow into the narrow gap between the bottom surfaces 23a, 33a of the element positioning recesses 23, 33 and the inner side surfaces 23b, 33b. That is, the melted solder 9 tends to wet and spread on the bottom surfaces 23 a and 33 a of the element positioning recesses 23 and 33. Thereby, the solder rise to the side surface of the semiconductor elements 4 and 5 can be suppressed. Therefore, it is possible to prevent the electrodes on both main surfaces of the semiconductor elements 4 and 5 from being short-circuited by the solder 9.
第四実施形態の半導体モジュールの構成は、第二、第三実施形態の半導体モジュールにも適用可能である。 The configuration of the semiconductor module of the fourth embodiment is also applicable to the semiconductor modules of the second and third embodiments.
〔第五実施形態〕
以下、図５を参照して本発明の第五実施形態について説明する。
図５に示すように、本実施形態に係る半導体モジュール１０は、第一実施形態と同様に、一対のセラミック基板１２，１３、半導体素子１４，１５及び接続子１６，１７を備える。 [Fifth embodiment]
Hereinafter, a fifth embodiment of the present invention will be described with reference to FIG.
As shown in FIG. 5, the semiconductor module 10 according to the present embodiment includes a pair of ceramic substrates 12 and 13, semiconductor elements 14 and 15, and connectors 16 and 17, as in the first embodiment.
半導体素子１４，１５は、後述する一対のセラミック基板１２，１３の導電層１２２，１３２に少なくとも一つずつ接合される。本実施形態の半導体素子１４，１５は、第一実施形態と同様に、板状に形成され、両主面に電極を有する。本実施形態の半導体素子１４，１５は、第一主面に二つの電極（ソース電極１４Ｓ，１５Ｓ、ゲート電極１４Ｇ，１５Ｇ）を設け、第二主面に一つの電極（ドレイン電極１４Ｄ，１５Ｄ）を設けたＭＯＳ－ＦＥＴである。
本実施形態では、接続子１６，１７も一対のセラミック基板１２，１３の導電層１２２，１３２に少なくとも一つずつ接合される。 The semiconductor elements 14 and 15 are bonded to at least one conductive layer 122 and 132 of a pair of ceramic substrates 12 and 13 described later. Similar to the first embodiment, the semiconductor elements 14 and 15 of the present embodiment are formed in a plate shape and have electrodes on both main surfaces. In the semiconductor elements 14 and 15 of this embodiment, two electrodes ( source electrodes 14S and 15S and gate electrodes 14G and 15G) are provided on the first main surface, and one electrode ( drain electrodes 14D and 15D) is provided on the second main surface. MOS-FET provided with
In the present embodiment, the connectors 16 and 17 are also bonded to the conductive layers 122 and 132 of the pair of ceramic substrates 12 and 13 at least one by one.
各セラミック基板１２，１３は、第一実施形態と同様に、セラミック板１２１，１３１の両主面に導電層１２２，１３２を設けて構成されている。
一対のセラミック基板１２，１３は、これらの第一導電層１２２Ａ，１３２Ａが相互に対向するように、セラミック板１２１，１３１の厚さ方向に間隔をあけて配されている。各セラミック基板１２，１３の第一導電層１２２Ａ，１３２Ａは、半導体素子１４，１５及び接続子１６，１７と共に半導体モジュール１０の回路を構成する配線パターンとして形成されている。 As in the first embodiment, the ceramic substrates 12 and 13 are configured by providing conductive layers 122 and 132 on both main surfaces of the ceramic plates 121 and 131, respectively.
The pair of ceramic substrates 12 and 13 are arranged at an interval in the thickness direction of the ceramic plates 121 and 131 so that the first conductive layers 122A and 132A face each other. The first conductive layers 122A and 132A of the ceramic substrates 12 and 13 are formed as a wiring pattern constituting a circuit of the semiconductor module 10 together with the semiconductor elements 14 and 15 and the connectors 16 and 17.
一対のセラミック基板１２，１３の第一導電層１２２Ａ，１３２Ａには、それぞれ半導体素子１４，１５が接合される。具体的には、各半導体素子１４，１５の一方の主面が、はんだ等の導電性接着剤（不図示）によって各セラミック基板１２，１３の第一導電層１２２Ａ，１３２Ａに接合される。これにより、各半導体素子１４，１５が各セラミック基板１２，１３の第一導電層１２２Ａ，１３２Ａに電気接続される。本実施形態では、各セラミック基板１２，１３に接合される半導体素子１４，１５の電極が互いに異なる。
以下、下側のセラミック基板１２（以下、第一セラミック基板１２とも呼ぶ）の第一導電層１２２Ａに接合される半導体素子１４、接続子１６を、それぞれ第一半導体素子１４、第一接続子１６とも呼ぶ。また、上側のセラミック基板１３（以下、第二セラミック基板１３とも呼ぶ）の第一導電層１３２Ａに接合される半導体素子１５、接続子１７を、それぞれ第二半導体素子１５、第二接続子１７とも呼ぶ。 Semiconductor elements 14 and 15 are bonded to the first conductive layers 122A and 132A of the pair of ceramic substrates 12 and 13, respectively. Specifically, one main surface of each of the semiconductor elements 14 and 15 is joined to the first conductive layers 122A and 132A of the ceramic substrates 12 and 13 by a conductive adhesive (not shown) such as solder. Thereby, the semiconductor elements 14 and 15 are electrically connected to the first conductive layers 122A and 132A of the ceramic substrates 12 and 13, respectively. In the present embodiment, the electrodes of the semiconductor elements 14 and 15 bonded to the ceramic substrates 12 and 13 are different from each other.
Hereinafter, the semiconductor element 14 and the connector 16 bonded to the first conductive layer 122A of the lower ceramic substrate 12 (hereinafter also referred to as the first ceramic substrate 12) are respectively referred to as the first semiconductor element 14 and the first connector 16. Also called. Further, the semiconductor element 15 and the connector 17 bonded to the first conductive layer 132A of the upper ceramic substrate 13 (hereinafter also referred to as the second ceramic substrate 13) are referred to as the second semiconductor element 15 and the second connector 17, respectively. Call.
第一セラミック基板１２の第一導電層１２２Ａには、第一半導体素子１４及び第一接続子１６を個別に挿入する位置決め凹部１２３，１２４が形成されている。以下、第一半導体素子１４が挿入される素子用の位置決め凹部１２３を、素子用位置決め凹部１２３あるいは第一素子用位置決め凹部１２３とも呼ぶ。また、第一接続子１６が挿入される接続子用の位置決め凹部１２４を、第一接続子用位置決め凹部１２４とも呼ぶ。第一セラミック基板１２の第一導電層１２２Ａにおいて、第一素子用位置決め凹部１２３を形成した領域と、第一接続子用位置決め凹部１２４を形成した領域とは、互いに電気的に独立している。 Positioning recesses 123 and 124 into which the first semiconductor element 14 and the first connector 16 are individually inserted are formed in the first conductive layer 122A of the first ceramic substrate 12. Hereinafter, the element positioning recess 123 into which the first semiconductor element 14 is inserted is also referred to as an element positioning recess 123 or a first element positioning recess 123. Further, the connector positioning recess 124 into which the first connector 16 is inserted is also referred to as a first connector positioning recess 124. In the first conductive layer 122A of the first ceramic substrate 12, the region where the first element positioning recess 123 is formed and the region where the first connector positioning recess 124 is formed are electrically independent from each other.
一方、第二セラミック基板１３の第一導電層１３２Ａには、第二半導体素子１５及び第二接続子１７を個別に挿入する位置決め凹部１３３，１３４が形成されている。以下、第二半導体素子１５が挿入される素子用の位置決め凹部１３３を、素子用位置決め凹部１３３あるいは第二素子用位置決め凹部１３３とも呼ぶ。また、第二接続子１７が挿入される接続子用の位置決め凹部１３４を、第二接続子用位置決め凹部１３４とも呼ぶ。第二セラミック基板１３の第一導電層１３２Ａにおいて、第二素子用位置決め凹部１３３を形成した領域と、第二接続子用位置決め凹部１３４を形成した領域とは、互いに電気的に独立している。 On the other hand, positioning recesses 133 and 134 into which the second semiconductor element 15 and the second connector 17 are individually inserted are formed in the first conductive layer 132A of the second ceramic substrate 13. Hereinafter, the element positioning recess 133 into which the second semiconductor element 15 is inserted is also referred to as an element positioning recess 133 or a second element positioning recess 133. The connector positioning recess 134 into which the second connector 17 is inserted is also referred to as a second connector positioning recess 134. In the first conductive layer 132A of the second ceramic substrate 13, the region where the second element positioning recess 133 is formed and the region where the second connector positioning recess 134 is formed are electrically independent from each other.
各半導体素子１４，１５は、各第一導電層１２２Ａ，１３２Ａのうち素子用位置決め凹部１２３，１３３の底面に接合される。ここで、各素子用位置決め凹部１２３，１３３の大きさは、半導体素子１４，１５の側部が素子用位置決め凹部１２３，１３３の内側面に接触しないように設定されている。ただし、半導体素子１４，１５の側部と素子用位置決め凹部１２３，１３３の内側面との隙間は、できる限り小さくした方がよい。
各素子用位置決め凹部１２３，１３３の深さ寸法は、第一実施形態と同様に、半導体素子１４，１５を素子用位置決め凹部１２３，１３３の底面に接合した状態で、半導体素子１４，１５が素子用位置決め凹部１２３，１３３が開口する第一導電層１２２Ａ，１３２Ａの表面から突出しないように設定されている。 The semiconductor elements 14 and 15 are bonded to the bottom surfaces of the element positioning recesses 123 and 133 in the first conductive layers 122A and 132A. Here, the sizes of the element positioning recesses 123 and 133 are set so that the side portions of the semiconductor elements 14 and 15 do not contact the inner side surfaces of the element positioning recesses 123 and 133. However, the gap between the side portions of the semiconductor elements 14 and 15 and the inner side surfaces of the element positioning recesses 123 and 133 is preferably as small as possible.
As in the first embodiment, the depth dimensions of the element positioning recesses 123 and 133 are the same as those of the first embodiment, with the semiconductor elements 14 and 15 being joined to the bottom surfaces of the element positioning recesses 123 and 133. The positioning recesses 123 and 133 are set so as not to protrude from the surfaces of the first conductive layers 122A and 132A that are opened.
第一素子用位置決め凹部１２３の底面には、一つの電極（ドレイン電極１４Ｄ）だけを設けた第一半導体素子１４の第二主面が接合されるため、第一素子用位置決め凹部１２３の形状は、第一実施形態と同様である。
一方、第二素子用位置決め凹部１３３の底面には、二つの電極（ソース電極１５Ｓ及びゲート電極１５Ｇ）を形成した第二半導体素子１５の第一主面が接合される。このため、第二素子用位置決め凹部１３３の形状は、第一実施形態と異なる。第二素子用位置決め凹部１３３には、その底面から窪んでセラミック板１３１まで到達する溝１３５が形成されている。第二半導体素子１５の二つの電極（ソース電極１５Ｓ及びゲート電極１５Ｇ）を接合させる第二素子用位置決め凹部１３３の底面の二つ領域は、溝１３５によって互いに電気的に独立している。 Since the second main surface of the first semiconductor element 14 provided with only one electrode (drain electrode 14D) is joined to the bottom surface of the first element positioning recess 123, the shape of the first element positioning recess 123 is This is the same as in the first embodiment.
On the other hand, the first main surface of the second semiconductor element 15 formed with two electrodes (the source electrode 15S and the gate electrode 15G) is joined to the bottom surface of the second element positioning recess 133. For this reason, the shape of the positioning recess 133 for the second element is different from that of the first embodiment. The second element positioning recess 133 is formed with a groove 135 that is recessed from the bottom surface and reaches the ceramic plate 131. Two regions on the bottom surface of the second element positioning recess 133 where the two electrodes (the source electrode 15S and the gate electrode 15G) of the second semiconductor element 15 are joined are electrically independent from each other by the groove 135.
一対のセラミック基板１２，１３は、上記した第一素子用位置決め凹部１２３及び第二素子用位置決め凹部１３３が相互に対向するように配されている。すなわち、一対のセラミック基板１２，１３にそれぞれ接合された一対の半導体素子１４，１５は、一対のセラミック基板１２，１３の配列方向に並べて配置されている。 The pair of ceramic substrates 12 and 13 are arranged such that the first element positioning recess 123 and the second element positioning recess 133 are opposed to each other. That is, the pair of semiconductor elements 14 and 15 bonded to the pair of ceramic substrates 12 and 13 are arranged in the arrangement direction of the pair of ceramic substrates 12 and 13.
本実施形態の接続子１６，１７には、第一セラミック基板１２の第一導電層１２２Ａと第一半導体素子１４とを電気接続し、第一セラミック基板１２の第一導電層１２２Ａに接合される第一接続子１６と、第一実施形態の接続子６と同様に、一対のセラミック基板１２，１３に接合された半導体素子１４，１５同士を電気接続すると共に、第二セラミック基板１３の第一導電層１３２Ａに接合される第二接続子１７と、がある。第一接続子１６及び第二接続子１７は、いずれも銅などの導電性材料からなる。 The first conductive layer 122 </ b> A of the first ceramic substrate 12 and the first semiconductor element 14 are electrically connected to the connectors 16 and 17 of the present embodiment and joined to the first conductive layer 122 </ b> A of the first ceramic substrate 12. Similarly to the first connector 16 and the connector 6 of the first embodiment, the semiconductor elements 14 and 15 bonded to the pair of ceramic substrates 12 and 13 are electrically connected to each other, and the first ceramic substrate 13 is connected to the first connector 16. And a second connector 17 bonded to the conductive layer 132A. Both the first connector 16 and the second connector 17 are made of a conductive material such as copper.
第一接続子１６は、帯板状の本体板部１６１と、本体板部１６１の長手方向の第一端部（図５において右側の端部）に設けられた素子接合部１６２と、本体板部１６１の第二端部（図５において左側の端部）に設けられた基板接合部１６３と、を備える。
第一接続子１６の素子接合部１６２は、はんだ等の導電性接着剤（不図示）によって第一セラミック基板１２の第一素子用位置決め凹部１２３に挿入された第一半導体素子１４に接合される。素子接合部１６２は、第一半導体素子１４の第一主面上のゲート電極１４Ｇに接合される。素子接合部１６２は、本体板部１６１から第一セラミック基板１２側に向けて本体板部１６１の厚さ方向に延びている。素子接合部１６２は、例えば本体板部１６１の第一端部を折り曲げることで形成される。 The first connector 16 includes a band plate-shaped main body plate portion 161, an element joint portion 162 provided at a first end portion in the longitudinal direction of the main body plate portion 161 (right end portion in FIG. 5), and a main body plate. And a substrate bonding portion 163 provided at a second end portion (left end portion in FIG. 5) of the portion 161.
The element joint 162 of the first connector 16 is joined to the first semiconductor element 14 inserted into the first element positioning recess 123 of the first ceramic substrate 12 by a conductive adhesive (not shown) such as solder. . The element junction 162 is joined to the gate electrode 14G on the first main surface of the first semiconductor element 14. The element bonding portion 162 extends in the thickness direction of the main body plate portion 161 from the main body plate portion 161 toward the first ceramic substrate 12 side. The element joint portion 162 is formed by, for example, bending the first end portion of the main body plate portion 161.
第一接続子１６の基板接合部１６３は、はんだ等の導電性接着剤（不図示）によって第一セラミック基板１２の第一導電層１２２Ａに接合される。基板接合部１６３は、本体板部１６１から第一セラミック基板１２側に向けて本体板部１６１の厚さ方向に延びている。基板接合部１６３は、本体板部１６１の第二端部を折り曲げることで形成されている。基板接合部１６３の延出方向先端部は、第一接続子用位置決め凹部１２４に挿入される。
図示例では、第一接続子用位置決め凹部１２４に挿入された基板接合部１６３と第一接続子用位置決め凹部１２４の内面との間に隙間が無いが、これに限ることはない。例えば、基板接合部１６３と第一接続子用位置決め凹部１２４の内面との間には、基板接合部１６３を第一導電層１２２Ａに接合するためのはんだ等の導電性接着剤が介在する程度の隙間があってもよい。 The board joint 163 of the first connector 16 is joined to the first conductive layer 122A of the first ceramic board 12 by a conductive adhesive (not shown) such as solder. The substrate bonding portion 163 extends in the thickness direction of the main body plate portion 161 from the main body plate portion 161 toward the first ceramic substrate 12 side. The substrate bonding portion 163 is formed by bending the second end portion of the main body plate portion 161. The front-end | tip part of the extension direction of the board | substrate junction part 163 is inserted in the positioning recessed part 124 for 1st connectors.
In the illustrated example, there is no gap between the board joint 163 inserted into the first connector positioning recess 124 and the inner surface of the first connector positioning recess 124, but this is not restrictive. For example, a conductive adhesive such as solder for bonding the substrate bonding portion 163 to the first conductive layer 122A is interposed between the substrate bonding portion 163 and the inner surface of the first connector positioning recess 124. There may be a gap.
第二接続子１７は、帯板状の本体板部１７１と、本体板部１７１の長手方向の第一端部（図５において左側の端部）に設けられた素子接合部１７２と、本体板部１７１の第二端部（図５において右側の端部）に設けられた基板接合部１７３と、を備える。
第二接続子１７の素子接合部１７２は、一対のセラミック基板１２，１３の素子用位置決め凹部１２３，１３３の間に配され、各素子用位置決め凹部１２３，１３３に挿入された一対の半導体素子１４，１５に接合される。素子接合部１７２は、本体板部１７１の厚さ寸法よりも大きいブロック状に形成されている。素子接合部１７２は、本体板部１７１の厚さ方向の両側に突出して形成されている。 The second connector 17 includes a band plate-shaped main body plate portion 171, an element joint portion 172 provided at a first end portion in the longitudinal direction of the main body plate portion 171 (left end portion in FIG. 5), and a main body plate. And a substrate bonding portion 173 provided at the second end of the portion 171 (the right end in FIG. 5).
The element connecting portion 172 of the second connector 17 is disposed between the element positioning recesses 123 and 133 of the pair of ceramic substrates 12 and 13 and is inserted into the element positioning recesses 123 and 133. , 15. The element joint portion 172 is formed in a block shape larger than the thickness dimension of the main body plate portion 171. The element joint portion 172 is formed so as to protrude on both sides in the thickness direction of the main body plate portion 171.
素子接合部１７２の一方の突出方向先端部は、はんだ等の導電性接着剤（不図示）によって第一半導体素子１４の第一主面上のソース電極１４Ｓに接合される。また、素子接合部１７２の他方の突出方向先端部は、はんだ等の導電性接着剤（不図示）によって第二半導体素子１５の第二主面上のドレイン電極１５Ｄに接合される。
第二半導体素子１５のドレイン電極１５Ｄは第一半導体素子１４のソース電極１４Ｓよりも大きい。このため、他方の突出方向先端部は、一方の突出方向先端部よりも大きく形成されているが、例えば一方の突出方向先端部と同じ大きさに形成されてもよい。 One end of the element joining portion 172 in the protruding direction is joined to the source electrode 14S on the first main surface of the first semiconductor element 14 by a conductive adhesive (not shown) such as solder. In addition, the other protruding end portion of the element bonding portion 172 is bonded to the drain electrode 15D on the second main surface of the second semiconductor element 15 by a conductive adhesive (not shown) such as solder.
The drain electrode 15D of the second semiconductor element 15 is larger than the source electrode 14S of the first semiconductor element 14. For this reason, although the other protrusion direction front-end | tip part is formed larger than one protrusion direction front-end | tip part, for example, you may form in the same magnitude | size as one protrusion direction front-end | tip part.
第二接続子１７の基板接合部１７３は、はんだ等の導電性接着剤（不図示）によって第二セラミック基板１３の第一導電層１３２Ａに接合される。基板接合部１７３は、本体板部１７１から第二セラミック基板１３側に向けて本体板部１７１の厚さ方向に延びている。基板接合部１７３は、本体板部１７１の第二端部を折り曲げることで形成されている。基板接合部１７３の延出方向先端部は、第二接続子用位置決め凹部１３４に挿入される。
図示例では、第二接続子用位置決め凹部１３４に挿入された基板接合部１７３と第二接続子用位置決め凹部１３４の内面との間に隙間が無いが、これに限ることはない。例えば、基板接合部１７３と第二接続子用位置決め凹部１３４の内面との間には、基板接合部１７３を第一導電層１３２Ａに接合するためのはんだ等の導電性接着剤が介在する程度の隙間があってもよい。 The board joint portion 173 of the second connector 17 is joined to the first conductive layer 132A of the second ceramic board 13 by a conductive adhesive (not shown) such as solder. The substrate bonding portion 173 extends in the thickness direction of the main body plate portion 171 from the main body plate portion 171 toward the second ceramic substrate 13 side. The substrate bonding portion 173 is formed by bending the second end portion of the main body plate portion 171. The front end of the board bonding portion 173 in the extending direction is inserted into the second connector positioning recess 134.
In the illustrated example, there is no gap between the board joint portion 173 inserted into the second connector positioning recess 134 and the inner surface of the second connector positioning recess 134, but this is not restrictive. For example, a conductive adhesive such as solder for bonding the substrate bonding portion 173 to the first conductive layer 132A is interposed between the substrate bonding portion 173 and the inner surface of the second connector positioning recess 134. There may be a gap.
上記した本実施形態の半導体モジュール１０によれば、第一実施形態と同様の効果を奏する。すなわち、半導体モジュール１０を製造する際には、半導体素子１４，１５及び接続子１６，１７をそれぞれセラミック基板１２，１３の位置決め凹部１２３，１２４，１３３，１３４に挿入するだけで、半導体素子１４，１５及び接続子１６，１７を各セラミック基板１２，１３に対して容易に位置決めすることが可能となる。したがって、半導体モジュール１０を効率よく製造することができる。 According to the semiconductor module 10 of this embodiment described above, the same effects as those of the first embodiment can be obtained. That is, when manufacturing the semiconductor module 10, the semiconductor elements 14, 15 and the connectors 16, 17 are simply inserted into the positioning recesses 123, 124, 133, 134 of the ceramic substrates 12, 13, respectively. 15 and connectors 16 and 17 can be easily positioned with respect to the ceramic substrates 12 and 13, respectively. Therefore, the semiconductor module 10 can be manufactured efficiently.
また、半導体素子１４，１５が素子用位置決め凹部１２３，１３３に挿入されるため、半導体モジュール１０の薄型化を図ることができる。
さらに、第一導電層１２２Ａ，１３２Ａに素子用位置決め凹部１２３，１３３が形成されていることで、半導体素子１４，１５の接合領域における第一導電層１２２Ａ，１３２Ａの厚みが他の領域における第一導電層１２２Ａ，１３２Ａの厚みよりも薄くなるため、半導体素子１４，１５において発生した熱を効率よくセラミック板１２１，１３１に逃がすことも可能となる。 Further, since the semiconductor elements 14 and 15 are inserted into the element positioning recesses 123 and 133, the semiconductor module 10 can be thinned.
Further, since the element positioning recesses 123 and 133 are formed in the first conductive layers 122A and 132A, the thickness of the first conductive layers 122A and 132A in the bonding region of the semiconductor elements 14 and 15 is the first in other regions. Since the thickness is smaller than that of the conductive layers 122A and 132A, the heat generated in the semiconductor elements 14 and 15 can be efficiently released to the ceramic plates 121 and 131.
また、本実施形態の半導体モジュール１０によれば、一対の半導体素子１４，１５が一対のセラミック基板１２，１３の配列方向に並べて配置されているため、各半導体素子１４，１５の熱を一対のセラミック基板１２，１３に効率よく逃がすことが可能となる。 Further, according to the semiconductor module 10 of the present embodiment, since the pair of semiconductor elements 14 and 15 are arranged in the arrangement direction of the pair of ceramic substrates 12 and 13, the heat of each semiconductor element 14 and 15 is paired. It is possible to efficiently escape to the ceramic substrates 12 and 13.
さらに、本実施形態の半導体モジュール１０によれば、各セラミック基板１２，１３に接合された半導体素子１４，１５は、素子用位置決め凹部１２３，１３３が開口する第一導電層１２２Ａ，１３２Ａの表面から突出しない。このため、各セラミック基板１２，１３の第一導電層１２２Ａ，１３２Ａの表面に対する各接続子１６，１７（特に本体板部１６１，１７１）の高さ位置、すなわち各接続子１６，１７のループ高さを低く設定できる。したがって、半導体モジュール１０の薄型化をさらに図ることができる。
また、各接続子１６，１７のループ高さを低くなることで、各接続子１６，１７の長さを短く設定できるため、各接続子１６，１７の配線抵抗及び寄生インダクタンスの低減も図ることができる。 Furthermore, according to the semiconductor module 10 of the present embodiment, the semiconductor elements 14 and 15 bonded to the ceramic substrates 12 and 13 are formed from the surface of the first conductive layers 122A and 132A where the element positioning recesses 123 and 133 are opened. Does not protrude. Therefore, the height positions of the connectors 16, 17 (particularly the main body plate portions 161, 171) with respect to the surfaces of the first conductive layers 122A, 132A of the ceramic substrates 12, 13, that is, the loop heights of the connectors 16, 17 are as follows. Can be set low. Therefore, the semiconductor module 10 can be further reduced in thickness.
Moreover, since the length of each connector 16, 17 can be set short by reducing the loop height of each connector 16, 17, the wiring resistance and parasitic inductance of each connector 16, 17 can be reduced. Can do.
上記した第五実施形態の半導体モジュール１０には、前述した第二～第四実施形態の構成を適用することが可能である。 The configurations of the second to fourth embodiments described above can be applied to the semiconductor module 10 of the fifth embodiment described above.
以上、本発明の詳細について説明したが、本発明は上述した実施形態に限定されるものではなく、本発明の主旨を逸脱しない範囲において種々の変更を加えることができる。
例えば、セラミック基板の導電層は、セラミック板の両主面に設けられることに限らず、セラミック板の一方の主面のみに設けられてもよい。
また、一対のセラミック基板の間には、例えば半導体素子及び接続子を封止する封止樹脂が設けられてもよい。 Although the details of the present invention have been described above, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention.
For example, the conductive layer of the ceramic substrate is not limited to being provided on both main surfaces of the ceramic plate, and may be provided only on one main surface of the ceramic plate.
Moreover, between the pair of ceramic substrates, for example, a sealing resin for sealing the semiconductor element and the connector may be provided.
１，１Ａ　半導体モジュール
２，３　セラミック基板
２１，３１　セラミック板
２２，２２Ａ，３２，３２Ａ　導電層
２３，３３　素子用位置決め凹部
２３ａ，３３ａ　底面
２３ｂ，３３ｂ　内側面
２４　接続子用位置決め凹部
２５，３５　スペーサ位置決め凹部
２５ａ，３５ａ　底面
４，５　半導体素子
６　接続子
７　スペーサ
８　弾性部材
１０　半導体モジュール
１２，１３　セラミック基板
１２１，１３１　セラミック板
１２２，１２２Ａ，１３２，１３２Ａ　導電層
１２３，１３３　素子用位置決め凹部
１２４，１３４　接続子用位置決め凹部
１４，１５　半導体素子
１６，１７　接続子 1, 1A Semiconductor module 2, 3 Ceramic substrate 21, 31 Ceramic plate 22, 22A, 32, 32A Conductive layer 23, 33 Element positioning recess 23a, 33a Bottom surface 23b, 33b Inner side surface 24 Connector positioning recess 25, 35 Spacer Positioning recesses 25a, 35a Bottom surface 4, 5 Semiconductor element 6 Connector 7 Spacer 8 Elastic member 10 Semiconductor module 12, 13 Ceramic substrate 121, 131 Ceramic plates 122, 122A, 132, 132A Conductive layers 123, 133 Element positioning recess 124, 134 Positioning recesses 14 and 15 for connectors Semiconductor elements 16 and 17 Connectors

Claims (7)

  1. セラミック板の少なくとも一方の主面に導電層を設けた一対のセラミック基板と、
    相互に対向する一対の前記セラミック基板の前記導電層にそれぞれ接合される半導体素子と、
    一対の前記セラミック基板に接合された前記半導体素子同士を電気接続すると共に、少なくとも一方の前記セラミック基板の前記導電層に接合される接続子と、を備え、
    前記セラミック基板の前記導電層に、前記半導体素子及び前記接続子を個別に挿入する位置決め凹部が形成されている半導体モジュール。     A pair of ceramic substrates provided with a conductive layer on at least one main surface of the ceramic plate;
    A semiconductor element bonded to each of the conductive layers of the pair of ceramic substrates facing each other;
    And electrically connecting the semiconductor elements bonded to a pair of ceramic substrates, and a connector bonded to the conductive layer of at least one of the ceramic substrates,
    A semiconductor module in which a positioning recess for individually inserting the semiconductor element and the connector is formed in the conductive layer of the ceramic substrate.
  2. 一対の前記セラミック基板にそれぞれ接合された一対の前記半導体素子が、一対の前記セラミック基板の配列方向に並べて配置されている請求項１に記載の半導体モジュール。 The semiconductor module according to claim 1, wherein the pair of semiconductor elements respectively bonded to the pair of ceramic substrates are arranged side by side in an arrangement direction of the pair of ceramic substrates.
  3. 一対の前記セラミック基板の前記導電層の間に挟み込まれるスペーサを備え、
    一対の前記セラミック基板の各導電層に、前記スペーサの端部を挿入するスペーサ位置決め凹部が形成されている請求項１又は請求項２に記載の半導体モジュール。     A spacer sandwiched between the conductive layers of the pair of ceramic substrates;
    The semiconductor module according to claim 1, wherein a spacer positioning recess for inserting an end of the spacer is formed in each conductive layer of the pair of ceramic substrates.
  4. 前記スペーサが、一対の前記セラミック基板の前記導電層同士を電気接続する導電部品である請求項３に記載の半導体モジュール。 The semiconductor module according to claim 3, wherein the spacer is a conductive component that electrically connects the conductive layers of the pair of ceramic substrates.
  5. 前記スペーサ位置決め凹部の底面と前記スペーサの端部との間に、弾性部材が設けられる請求項３又は請求項４に記載の半導体モジュール。 The semiconductor module according to claim 3, wherein an elastic member is provided between a bottom surface of the spacer positioning recess and an end portion of the spacer.
  6. 前記位置決め凹部に挿入された前記半導体素子は、前記位置決め凹部が開口する前記導電層の表面から突出しない請求項１から請求項５のいずれか一項に記載の半導体モジュール。 The semiconductor module according to claim 1, wherein the semiconductor element inserted into the positioning recess does not protrude from the surface of the conductive layer where the positioning recess opens.
  7. 前記半導体素子を挿入する素子用の前記位置決め凹部の内側面は、素子用の前記位置決め凹部の底面から開口側に向かうにしたがって内側に傾斜している請求項１から請求項６のいずれか一項に記載の半導体モジュール。 The inner surface of the positioning recess for an element into which the semiconductor element is inserted is inclined inward as it goes from the bottom surface of the positioning recess for the element toward the opening side. The semiconductor module described in 1.
PCT/JP2014/071318 2014-08-12 2014-08-12 Semiconductor module WO2016024333A1 (en)

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