WO2016024333A1 - Module semi-conducteur - Google Patents

Module semi-conducteur Download PDF

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Publication number
WO2016024333A1
WO2016024333A1 PCT/JP2014/071318 JP2014071318W WO2016024333A1 WO 2016024333 A1 WO2016024333 A1 WO 2016024333A1 JP 2014071318 W JP2014071318 W JP 2014071318W WO 2016024333 A1 WO2016024333 A1 WO 2016024333A1
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WO
WIPO (PCT)
Prior art keywords
semiconductor
connector
pair
ceramic substrates
semiconductor module
Prior art date
Application number
PCT/JP2014/071318
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English (en)
Japanese (ja)
Inventor
康亮 池田
雄司 森永
Original Assignee
新電元工業株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 新電元工業株式会社 filed Critical 新電元工業株式会社
Priority to PCT/JP2014/071318 priority Critical patent/WO2016024333A1/fr
Priority to JP2015504441A priority patent/JP5930565B1/ja
Publication of WO2016024333A1 publication Critical patent/WO2016024333A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5385—Assembly of a plurality of insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L24/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L24/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0618—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/06181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H01L2224/37001—Core members of the connector
    • H01L2224/37099—Material
    • H01L2224/371—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/37138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/37147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H01L2224/848—Bonding techniques
    • H01L2224/84801—Soldering or alloying
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3735—Laminates or multilayers, e.g. direct bond copper ceramic substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L24/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L24/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector

Definitions

  • the present invention relates to a semiconductor module.
  • a circuit is configured by mounting a plurality of semiconductor elements on a substrate.
  • a ceramic substrate in which a conductive layer functioning as a circuit of a semiconductor module is formed on the main surface of a ceramic plate is often used as a substrate of a semiconductor module such as a power device module.
  • semiconductor modules such as power device modules are required to have high-density mounting or high-density integration of semiconductor elements.
  • a semiconductor module for example, the first ceramic substrate, the first semiconductor element, the connector, the second semiconductor element, and the second ceramic substrate are sequentially laminated, and these components are joined by soldering. Things can be considered.
  • the semiconductor module when such a semiconductor module is manufactured, there is a problem in that it is difficult to position the semiconductor element and the connector with respect to each ceramic substrate, particularly when each component is joined with solder. That is, there is a problem that the semiconductor module cannot be manufactured efficiently.
  • An object of one embodiment of the present invention is to provide a semiconductor module in which a semiconductor element and a connector can be easily positioned with respect to each ceramic substrate and can be efficiently manufactured.
  • a semiconductor module as one embodiment of the present invention includes a pair of ceramic substrates in which a conductive layer is provided on at least one main surface of a ceramic plate and a semiconductor bonded to the conductive layers of the pair of ceramic substrates facing each other.
  • a positioning recess for individually inserting the semiconductor element and the connector is formed.
  • the semiconductor element and the connector when a semiconductor module is manufactured, can be easily positioned with respect to each ceramic substrate simply by inserting the semiconductor element and the connector into the positioning recesses of the ceramic substrate. It becomes possible to do. Therefore, it becomes possible to manufacture a semiconductor module efficiently.
  • the semiconductor module 1 includes a pair of ceramic substrates 2 and 3, semiconductor elements 4 and 5, and a connector 6.
  • the semiconductor elements 4 and 5 are bonded to at least one conductive layer 22 and 32 of a pair of ceramic substrates 2 and 3 to be described later.
  • the type and shape of the semiconductor elements 4 and 5 are not particularly limited.
  • the semiconductor elements 4 and 5 of this embodiment are formed in a plate shape and have electrodes on both main surfaces.
  • the semiconductor elements 4 and 5 of this embodiment are diodes having one electrode on each main surface.
  • Each ceramic substrate 2, 3 includes plate-shaped ceramic plates 21, 31 having insulating properties, and conductive layers 22, 32 provided on the main surfaces of the ceramic plates 21, 31.
  • conductive layers 22 and 32 are provided on both main surfaces of the ceramic plates 21 and 31.
  • the conductive layers 22 and 32 may be conductive, but may be made of a material having high electrical conductivity such as copper.
  • the pair of ceramic substrates 2 and 3 are spaced in the thickness direction of the ceramic plates 21 and 31 so that one of the conductive layers 22A and 32A (hereinafter referred to as the first conductive layers 22A and 32A) is opposed to each other. It is arranged with a gap.
  • the first conductive layers 22 ⁇ / b> A and 32 ⁇ / b> A of the ceramic substrates 2 and 3 are formed as a wiring pattern constituting a circuit of the semiconductor module 1 together with the semiconductor elements 4 and 5 and the connector 6.
  • Semiconductor elements 4 and 5 are bonded to the first conductive layers 22A and 32A of the pair of ceramic substrates 2 and 3, respectively. Specifically, one main surface of each of the semiconductor elements 4 and 5 is bonded to the first conductive layers 22A and 32A of the ceramic substrates 2 and 3 by a conductive adhesive (not shown) such as solder. Thus, the semiconductor elements 4 and 5 are electrically connected to the first conductive layers 22A and 32A of the ceramic substrates 2 and 3, respectively. In this embodiment, the electrodes of the semiconductor elements 4 and 5 bonded to the ceramic substrates 2 and 3 are different from each other.
  • the semiconductor element 4 bonded to the first conductive layer 22 ⁇ / b> A of the lower ceramic substrate 2 (hereinafter also referred to as the first ceramic substrate 2) is also referred to as the first semiconductor element 4.
  • the semiconductor element 5 bonded to the first conductive layer 32 ⁇ / b> A of the upper ceramic substrate 3 (hereinafter also referred to as the second ceramic substrate 3) is also referred to as the second semiconductor element 5.
  • the element positioning recess 23 into which the first semiconductor element 4 is inserted is also referred to as an element positioning recess 23 or a first element positioning recess 23.
  • the connector positioning recess 24 into which the connector 6 is inserted is also referred to as a connector positioning recess 24.
  • the region where the first element positioning recess 23 is formed and the region where the connector positioning recess 24 is formed are electrically independent from each other.
  • a positioning recess 33 for inserting the second semiconductor element 5 is formed in the first conductive layer 32 ⁇ / b> A of the second ceramic substrate 3.
  • the element positioning recess 33 into which the second semiconductor element 5 is inserted is also referred to as an element positioning recess 33 or a second element positioning recess 33.
  • the semiconductor elements 4 and 5 are bonded to the bottom surfaces of the element positioning recesses 23 and 33 in the first conductive layers 22A and 32A.
  • the size of each of the element positioning recesses 23 and 33 is such that the side portions of the semiconductor elements 4 and 5 are in the element positioning recesses while the semiconductor elements 4 and 5 are joined to the bottom surfaces of the element positioning recesses 23 and 33.
  • 23 and 33 are set so as not to contact the inner side surfaces.
  • the gap between the side portions of the semiconductor elements 4 and 5 and the inner side surfaces of the element positioning recesses 23 and 33 is preferably as small as possible.
  • the depth dimensions of the element positioning recesses 23 and 33 are such that the semiconductor elements 4 and 5 are joined to the bottom surfaces of the element positioning recesses 23 and 33 and the semiconductor elements 4 and 5 are in contact with the element positioning recesses 23 and 33. Is set so as not to protrude from the surfaces of the first conductive layers 22A and 32A that are open. In a state where the semiconductor elements 4 and 5 are inserted into the element positioning recesses 23 and 33, for example, the main surfaces of the semiconductor elements 4 and 5 joined to the connector 6 described later are the surfaces of the first conductive layers 22A and 32A. It may be located at the same height as or lower than the surfaces of the first conductive layers 22A and 32A.
  • the pair of ceramic substrates 2 and 3 are arranged such that the first element positioning recess 23 and the second element positioning recess 33 face each other. That is, the pair of semiconductor elements 4 and 5 respectively joined to the pair of ceramic substrates 2 and 3 are arranged side by side in the arrangement direction of the pair of ceramic substrates 2 and 3.
  • the connector 6 electrically connects the semiconductor elements 4 and 5 joined to the pair of ceramic substrates 2 and 3 and is joined to the first conductive layers 22A and 32A of at least one of the ceramic substrates 2 and 3.
  • the connector 6 of this embodiment is joined to the first conductive layer 22 ⁇ / b> A of the first ceramic substrate 2.
  • the connector 6 is made of a conductive material such as copper.
  • the connector 6 includes a band plate-shaped main body plate portion 61, an element joining portion 62 provided at a first end portion in the longitudinal direction of the main body plate portion 61 (right end portion in FIG. 1), and a main body plate portion 61. And a substrate bonding portion 63 provided at the second end (the left end in FIG. 1).
  • the element joint 62 is disposed between the element positioning recesses 23 and 33 of the pair of ceramic substrates 2 and 3 and is bonded to the pair of semiconductor elements 4 and 5 inserted into the element positioning recesses 23 and 33. .
  • the element joint portion 62 is formed in a block shape larger than the thickness dimension of the main body plate portion 61.
  • the element joint portion 62 of the present embodiment is formed to protrude on both sides in the thickness direction of the main body plate portion 61. Both protruding ends of the element bonding portion 62 are bonded to the main surfaces of the pair of semiconductor elements 4 and 5 facing each other by a conductive adhesive (not shown) such as solder. That is, the element junction 62 is sandwiched between the pair of semiconductor elements 4 and 5.
  • the substrate bonding portion 63 is bonded to the first conductive layer 22A of the first ceramic substrate 2 by a conductive adhesive (not shown) such as solder.
  • the substrate bonding portion 63 extends in the thickness direction of the main body plate portion 61 from the main body plate portion 61 toward the first ceramic substrate 2 side.
  • the substrate bonding portion 63 is formed by bending the second end portion of the main body plate portion 61.
  • the front end of the board bonding portion 63 in the extending direction is inserted into the connector positioning recess 24. In the illustrated example, there is no gap between the board joint 63 inserted in the connector positioning recess 24 and the inner surface of the connector positioning recess 24, but the present invention is not limited to this.
  • a conductive adhesive such as solder for bonding the substrate bonding portion 63 to the first conductive layer 22A is interposed. There may be.
  • the semiconductor elements 4, 5 and the connector 6 are inserted into the positioning recesses 23, 24, 25 of the ceramic substrates 2, 3, respectively. 5 and the connector 6 can be easily positioned with respect to the ceramic substrates 2 and 3. Therefore, the semiconductor module 1 can be manufactured efficiently.
  • the semiconductor elements 4, 5 and the connector 6 are positioned with respect to the ceramic substrates 2, 3 only by appropriately arranging the semiconductor elements 4, 5 and the connector 6 between the pair of ceramic substrates 2, 3.
  • solder reflow is performed in a state where the semiconductor elements 4 and 5 and the connector 6 are disposed between the pair of ceramic substrates 2 and 3, and the bonding between the ceramic substrates 2 and 3 and the semiconductor elements 4 and 5 is performed. Bonding between the elements 4 and 5 and the connector 6 and bonding between the ceramic substrates 2 and 3 and the connector 6 can be performed collectively.
  • the semiconductor module 1 is manufactured in comparison with the case where the semiconductor elements 4 and 5 and the connector 6 are positioned with respect to the pair of ceramic substrates 2 and 3 using a jig. It is possible to improve the manufacturing efficiency and the yield of the module 1. If it demonstrates concretely, when positioning the semiconductor elements 4 and 5 and the connector 6 with respect to the ceramic substrates 2 and 3 using a jig
  • the manufacture efficiency of a semiconductor module may fall. Furthermore, when the solder at the above-mentioned joining portion adheres to the jig, chip cracks may occur in the semiconductor elements 4 and 5 when the jig is removed, which leads to a decrease in the yield of the semiconductor module.
  • the above-described jig is not required when manufacturing the semiconductor module 1, so that attachment and detachment of the jig are not required, and the manufacturing efficiency of the semiconductor module 1 is improved. Can be planned. Further, when the semiconductor module 1 is manufactured, the chip crack does not occur, so that the yield of the semiconductor module 1 can be improved.
  • the semiconductor module 1 of the present embodiment since the semiconductor elements 4 and 5 are inserted into the element positioning recesses 23 and 33, the semiconductor module 1 can be thinned.
  • the semiconductor elements 4 and 5 inserted into the element positioning recesses 23 and 33 do not protrude from the surfaces of the first conductive layers 22A and 32A where the element positioning recesses 23 and 33 are opened. For this reason, the semiconductor module 1 can be further reduced in thickness.
  • the first conductive layers 22A and 32A are formed with the element positioning recesses 23 and 33, whereby the first conductive layer 22A in the junction region of the semiconductor elements 4 and 5 is formed.
  • 32A is thinner than the thickness of the first conductive layers 22A, 32A in the other regions. For this reason, the heat generated in the semiconductor elements 4 and 5 can be efficiently released to the ceramic plates 21 and 31. That is, the heat dissipation efficiency of the semiconductor elements 4 and 5 can be improved.
  • the pair of semiconductor elements 4 and 5 joined to the pair of ceramic substrates 2 and 3 are arranged side by side in the arrangement direction of the pair of ceramic substrates 2 and 3. For this reason, the heat of the semiconductor elements 4 and 5 can be efficiently released to both the pair of ceramic substrates 2 and 3.
  • the heat of the first semiconductor element 4 bonded to the first ceramic substrate 2 not only escapes to the first ceramic substrate 2 side but also passes through the second semiconductor element 5 bonded to the second ceramic substrate 3. It can also escape to the two ceramic substrate 3 side.
  • the heat dissipation path of the first semiconductor element 4 in the connector 6 interposed between the pair of semiconductor elements 4 and 5 is minimized, and the heat of the first semiconductor element 4 is also efficiently transferred to the second ceramic substrate 3 side. It is possible to escape well.
  • the first semiconductor element 4 bonded to the first ceramic substrate 2 has the first conductive layer 22A in which the first element positioning recess 23 of the first ceramic substrate 2 is opened. Does not protrude from the surface of For this reason, the height position of the connector 6 (particularly the main body plate portion 61) with respect to the surface of the first conductive layer 22A of the first ceramic substrate 2, that is, the loop height of the connector 6 can be set low. Therefore, the semiconductor module 1 can be further reduced in thickness.
  • the height position of the connector 6 (particularly the main body plate portion 61) with respect to the surface of the first conductive layer 22A of the first ceramic substrate 2 is lowered, so that the first ceramic element 2 to the first ceramic substrate 2 are firstly connected.
  • the length of the connector 6 reaching the conductive layer 22A can be set short. Therefore, the wiring resistance and parasitic inductance of the connector 6 can be reduced.
  • the semiconductor module 1A according to the present embodiment is configured in the same manner as the semiconductor module 1 of the first embodiment described above.
  • the semiconductor module 1 ⁇ / b> A of the present embodiment includes a spacer 7 that is sandwiched between the first conductive layers 22 ⁇ / b> A and 32 ⁇ / b> A of the pair of ceramic substrates 2 and 3.
  • only one spacer 7 is provided, but a plurality of spacers may be provided, for example.
  • the spacer 7 is formed in a rod shape such as a prism or a cylinder, a plate shape, or a block shape, for example.
  • the spacer 7 of this embodiment is a conductive component that electrically connects the first conductive layers 22 ⁇ / b> A and 32 ⁇ / b> A of the pair of ceramic substrates 2 and 3.
  • Examples of the conductive component include a wiring part, a resistor, and a capacitor.
  • the conductive component in the illustrated example is a capacitor having electrodes at both ends in the longitudinal direction.
  • the spacer 7 of this embodiment, which is a conductive component constitutes a circuit of the semiconductor module 1A together with the first conductive layers 22A and 32A, the semiconductor elements 4 and 5 and the connector 6 of the ceramic substrates 2 and 3.
  • the first conductive layers 22A and 32A of the pair of ceramic substrates 2 and 3 are formed with spacer positioning recesses 25 and 35 into which the end portions of the spacer 7 are inserted.
  • a conductive adhesive such as solder
  • each end of the spacer 7 is joined to both the bottom surface and the inner surface, which are the inner surfaces of the spacer positioning recesses 25 and 35.
  • the present invention is not limited to this.
  • the same effects as those of the first embodiment can be obtained. Further, according to the semiconductor module 1A of the present embodiment, since both end portions of the spacer 7 are inserted into the spacer positioning recesses 25 and 35 of the ceramic substrates 2 and 3, the positioning accuracy between the pair of ceramic substrates 2 and 3 is improved. Can be improved.
  • the dimension (length dimension) of the spacer 7 in the arrangement direction of the pair of ceramic substrates 2 and 3 is larger than the dimension of the connector 6 (particularly the element joint portion 62). Can be set.
  • the spacer 7 is more preferable than the connector 6. It expands and contracts greatly in the arranged direction. For this reason, the stress applied to the semiconductor elements 4 and 5 can be reduced based on the expansion and contraction of the connector 6 during the thermal shock test. That is, the semiconductor elements 4 and 5 can be protected even when the semiconductor module 1A is rapidly heated and cooled.
  • the spacer 7 is a conductive component constituting the circuit of the semiconductor module 1A. That is, the spacer 7 of the present embodiment has a function of positioning the pair of ceramic substrates 2 and 3 and a function of constituting a circuit of the semiconductor module 1A. For this reason, the number of components of the semiconductor module 1A can be reduced.
  • the spacer 7 is a conductive component
  • the conductive component mounting area on the ceramic substrates 2 and 3 can be set smaller than when the conductive component is mounted only on one of the ceramic substrates 2 and 3. Accordingly, the size of the ceramic substrates 2 and 3 can be reduced to reduce the size (shrink) of the semiconductor module 1A.
  • the spacer 7 when the spacer 7 is a wiring part or a resistor, there are two paths of current flowing between the pair of ceramic substrates 2 and 3.
  • the first current path is a path that passes through the pair of semiconductor elements 4 and 5 and the connector 6, and the second current path is a path that passes through the spacer 7 that is a conductive component.
  • the circuit of the semiconductor module 1A is set so that the directions of the currents flowing through the first current path and the second current path are opposite to each other, the inductance of the circuit of the semiconductor module 1A is reduced by the mutual inductance. Can also be planned.
  • the semiconductor module according to the present embodiment is configured similarly to the semiconductor module 1A of the second embodiment described above.
  • the elastic member 8 is provided between the bottom surfaces 25 a and 35 a of the spacer positioning recesses 25 and 35 and the end portions of the spacer 7. Yes.
  • the elastic member 8 may be a spring, for example, but may be a resin that can be easily elastically deformed, such as a silicone resin.
  • a liquid silicone resin may be poured into the spacer positioning recesses 25 and 35 and then cured in a gel state.
  • the dimension of the elastic member 8 is preferably set smaller than the depth dimension of the spacer positioning recesses 25 and 35 so that the end of the spacer 7 can be inserted into the spacer positioning recesses 25 and 35. In this case, the end of the spacer 7 inserted into the spacer positioning recesses 25 and 35 can be brought into contact with the inner side surfaces of the spacer positioning recesses 25 and 35. For this reason, even if the spacer 7 is a conductive component as in the illustrated example, the end portion of the spacer 7 and the first conductive layers 22A and 32A of the ceramic substrates 2 and 3 can be electrically connected.
  • the end of the spacer 7 and the inner surface of the spacer positioning recesses 25 and 35 are connected by a conductive adhesive (not shown) such as solder. It may be joined.
  • the same effects as those of the second embodiment can be obtained. Furthermore, according to the semiconductor module of this embodiment, the stress applied to the semiconductor elements 4 and 5 can be relieved by the elastic member 8 being elastically deformed even when pressurized during solder reflow. Specifically, during solder reflow, the semiconductor elements 4, 5 and the connector 6 are appropriately disposed between the pair of ceramic substrates 2, 3 and then between the pair of ceramic substrates 2, 3. A force for sandwiching the semiconductor elements 4 and 5 and the connector 6 is applied, that is, pressure is applied from the arrangement direction of the pair of ceramic substrates 2 and 3.
  • the elastic member 8 is provided between the bottom surfaces 25a and 35a of the spacer positioning recesses 25 and 35 and the end of the spacer 7, the elastic member 8 is elastically deformed by the applied pressure during solder reflow. It is possible to suppress an excessive force from being applied to the semiconductor elements 4 and 5.
  • the length dimension of the spacer 7 in the arrangement direction of the pair of ceramic substrates 2 and 3 is larger than the dimension of the connector 6, and the linear expansion coefficient of the connector 6 and the spacer 7 is larger.
  • the spacer 7 expands and contracts more in the arrangement direction than the connector 6.
  • the elastic member 8 is not provided, there is a possibility that a large stress is applied to the connection portion between the end portion of the spacer 7 and the first conductive layers 22A and 32A.
  • the elastic member 8 when the elastic member 8 is present, the elastic member 8 is elastically deformed as the spacer 7 expands and contracts, so that the stress applied to the joint portion between the end portion of the spacer 7 and the first conductive layers 22A and 32A. Can be relaxed. Therefore, deterioration of the spacer 7 and the first conductive layers 22A and 32A can be prevented.
  • the semiconductor module according to the present embodiment is configured similarly to the semiconductor module 1 of the first embodiment.
  • the molten solder 9 has its own surface tension. This facilitates the flow into the narrow gap between the bottom surfaces 23a, 33a of the element positioning recesses 23, 33 and the inner side surfaces 23b, 33b. That is, the melted solder 9 tends to wet and spread on the bottom surfaces 23 a and 33 a of the element positioning recesses 23 and 33. Thereby, the solder rise to the side surface of the semiconductor elements 4 and 5 can be suppressed. Therefore, it is possible to prevent the electrodes on both main surfaces of the semiconductor elements 4 and 5 from being short-circuited by the solder 9.
  • the configuration of the semiconductor module of the fourth embodiment is also applicable to the semiconductor modules of the second and third embodiments.
  • the semiconductor module 10 includes a pair of ceramic substrates 12 and 13, semiconductor elements 14 and 15, and connectors 16 and 17, as in the first embodiment.
  • the semiconductor elements 14 and 15 are bonded to at least one conductive layer 122 and 132 of a pair of ceramic substrates 12 and 13 described later. Similar to the first embodiment, the semiconductor elements 14 and 15 of the present embodiment are formed in a plate shape and have electrodes on both main surfaces. In the semiconductor elements 14 and 15 of this embodiment, two electrodes (source electrodes 14S and 15S and gate electrodes 14G and 15G) are provided on the first main surface, and one electrode (drain electrodes 14D and 15D) is provided on the second main surface. MOS-FET provided with In the present embodiment, the connectors 16 and 17 are also bonded to the conductive layers 122 and 132 of the pair of ceramic substrates 12 and 13 at least one by one.
  • the ceramic substrates 12 and 13 are configured by providing conductive layers 122 and 132 on both main surfaces of the ceramic plates 121 and 131, respectively.
  • the pair of ceramic substrates 12 and 13 are arranged at an interval in the thickness direction of the ceramic plates 121 and 131 so that the first conductive layers 122A and 132A face each other.
  • the first conductive layers 122A and 132A of the ceramic substrates 12 and 13 are formed as a wiring pattern constituting a circuit of the semiconductor module 10 together with the semiconductor elements 14 and 15 and the connectors 16 and 17.
  • Semiconductor elements 14 and 15 are bonded to the first conductive layers 122A and 132A of the pair of ceramic substrates 12 and 13, respectively. Specifically, one main surface of each of the semiconductor elements 14 and 15 is joined to the first conductive layers 122A and 132A of the ceramic substrates 12 and 13 by a conductive adhesive (not shown) such as solder. Thereby, the semiconductor elements 14 and 15 are electrically connected to the first conductive layers 122A and 132A of the ceramic substrates 12 and 13, respectively. In the present embodiment, the electrodes of the semiconductor elements 14 and 15 bonded to the ceramic substrates 12 and 13 are different from each other.
  • the semiconductor element 14 and the connector 16 bonded to the first conductive layer 122A of the lower ceramic substrate 12 are respectively referred to as the first semiconductor element 14 and the first connector 16. Also called.
  • the semiconductor element 15 and the connector 17 bonded to the first conductive layer 132A of the upper ceramic substrate 13 are referred to as the second semiconductor element 15 and the second connector 17, respectively.
  • Positioning recesses 123 and 124 into which the first semiconductor element 14 and the first connector 16 are individually inserted are formed in the first conductive layer 122A of the first ceramic substrate 12.
  • the element positioning recess 123 into which the first semiconductor element 14 is inserted is also referred to as an element positioning recess 123 or a first element positioning recess 123.
  • the connector positioning recess 124 into which the first connector 16 is inserted is also referred to as a first connector positioning recess 124.
  • the region where the first element positioning recess 123 is formed and the region where the first connector positioning recess 124 is formed are electrically independent from each other.
  • positioning recesses 133 and 134 into which the second semiconductor element 15 and the second connector 17 are individually inserted are formed in the first conductive layer 132A of the second ceramic substrate 13.
  • the element positioning recess 133 into which the second semiconductor element 15 is inserted is also referred to as an element positioning recess 133 or a second element positioning recess 133.
  • the connector positioning recess 134 into which the second connector 17 is inserted is also referred to as a second connector positioning recess 134.
  • the region where the second element positioning recess 133 is formed and the region where the second connector positioning recess 134 is formed are electrically independent from each other.
  • the semiconductor elements 14 and 15 are bonded to the bottom surfaces of the element positioning recesses 123 and 133 in the first conductive layers 122A and 132A.
  • the sizes of the element positioning recesses 123 and 133 are set so that the side portions of the semiconductor elements 14 and 15 do not contact the inner side surfaces of the element positioning recesses 123 and 133.
  • the gap between the side portions of the semiconductor elements 14 and 15 and the inner side surfaces of the element positioning recesses 123 and 133 is preferably as small as possible.
  • the depth dimensions of the element positioning recesses 123 and 133 are the same as those of the first embodiment, with the semiconductor elements 14 and 15 being joined to the bottom surfaces of the element positioning recesses 123 and 133.
  • the positioning recesses 123 and 133 are set so as not to protrude from the surfaces of the first conductive layers 122A and 132A that are opened.
  • the shape of the first element positioning recess 123 is This is the same as in the first embodiment.
  • the first main surface of the second semiconductor element 15 formed with two electrodes (the source electrode 15S and the gate electrode 15G) is joined to the bottom surface of the second element positioning recess 133.
  • the second element positioning recess 133 is formed with a groove 135 that is recessed from the bottom surface and reaches the ceramic plate 131. Two regions on the bottom surface of the second element positioning recess 133 where the two electrodes (the source electrode 15S and the gate electrode 15G) of the second semiconductor element 15 are joined are electrically independent from each other by the groove 135.
  • the pair of ceramic substrates 12 and 13 are arranged such that the first element positioning recess 123 and the second element positioning recess 133 are opposed to each other. That is, the pair of semiconductor elements 14 and 15 bonded to the pair of ceramic substrates 12 and 13 are arranged in the arrangement direction of the pair of ceramic substrates 12 and 13.
  • the first conductive layer 122 ⁇ / b> A of the first ceramic substrate 12 and the first semiconductor element 14 are electrically connected to the connectors 16 and 17 of the present embodiment and joined to the first conductive layer 122 ⁇ / b> A of the first ceramic substrate 12.
  • the semiconductor elements 14 and 15 bonded to the pair of ceramic substrates 12 and 13 are electrically connected to each other, and the first ceramic substrate 13 is connected to the first connector 16.
  • the first connector 16 includes a band plate-shaped main body plate portion 161, an element joint portion 162 provided at a first end portion in the longitudinal direction of the main body plate portion 161 (right end portion in FIG. 5), and a main body plate. And a substrate bonding portion 163 provided at a second end portion (left end portion in FIG. 5) of the portion 161.
  • the element joint 162 of the first connector 16 is joined to the first semiconductor element 14 inserted into the first element positioning recess 123 of the first ceramic substrate 12 by a conductive adhesive (not shown) such as solder. .
  • the element junction 162 is joined to the gate electrode 14G on the first main surface of the first semiconductor element 14.
  • the element bonding portion 162 extends in the thickness direction of the main body plate portion 161 from the main body plate portion 161 toward the first ceramic substrate 12 side.
  • the element joint portion 162 is formed by, for example, bending the first end portion of the main body plate portion 161.
  • the board joint 163 of the first connector 16 is joined to the first conductive layer 122A of the first ceramic board 12 by a conductive adhesive (not shown) such as solder.
  • the substrate bonding portion 163 extends in the thickness direction of the main body plate portion 161 from the main body plate portion 161 toward the first ceramic substrate 12 side.
  • the substrate bonding portion 163 is formed by bending the second end portion of the main body plate portion 161.
  • substrate junction part 163 is inserted in the positioning recessed part 124 for 1st connectors. In the illustrated example, there is no gap between the board joint 163 inserted into the first connector positioning recess 124 and the inner surface of the first connector positioning recess 124, but this is not restrictive.
  • a conductive adhesive such as solder for bonding the substrate bonding portion 163 to the first conductive layer 122A is interposed between the substrate bonding portion 163 and the inner surface of the first connector positioning recess 124. There may be a gap.
  • the second connector 17 includes a band plate-shaped main body plate portion 171, an element joint portion 172 provided at a first end portion in the longitudinal direction of the main body plate portion 171 (left end portion in FIG. 5), and a main body plate. And a substrate bonding portion 173 provided at the second end of the portion 171 (the right end in FIG. 5).
  • the element connecting portion 172 of the second connector 17 is disposed between the element positioning recesses 123 and 133 of the pair of ceramic substrates 12 and 13 and is inserted into the element positioning recesses 123 and 133. , 15.
  • the element joint portion 172 is formed in a block shape larger than the thickness dimension of the main body plate portion 171.
  • the element joint portion 172 is formed so as to protrude on both sides in the thickness direction of the main body plate portion 171.
  • One end of the element joining portion 172 in the protruding direction is joined to the source electrode 14S on the first main surface of the first semiconductor element 14 by a conductive adhesive (not shown) such as solder.
  • the other protruding end portion of the element bonding portion 172 is bonded to the drain electrode 15D on the second main surface of the second semiconductor element 15 by a conductive adhesive (not shown) such as solder.
  • the drain electrode 15D of the second semiconductor element 15 is larger than the source electrode 14S of the first semiconductor element 14.
  • the board joint portion 173 of the second connector 17 is joined to the first conductive layer 132A of the second ceramic board 13 by a conductive adhesive (not shown) such as solder.
  • the substrate bonding portion 173 extends in the thickness direction of the main body plate portion 171 from the main body plate portion 171 toward the second ceramic substrate 13 side.
  • the substrate bonding portion 173 is formed by bending the second end portion of the main body plate portion 171.
  • the front end of the board bonding portion 173 in the extending direction is inserted into the second connector positioning recess 134. In the illustrated example, there is no gap between the board joint portion 173 inserted into the second connector positioning recess 134 and the inner surface of the second connector positioning recess 134, but this is not restrictive.
  • a conductive adhesive such as solder for bonding the substrate bonding portion 173 to the first conductive layer 132A is interposed between the substrate bonding portion 173 and the inner surface of the second connector positioning recess 134. There may be a gap.
  • the semiconductor module 10 of this embodiment described above the same effects as those of the first embodiment can be obtained. That is, when manufacturing the semiconductor module 10, the semiconductor elements 14, 15 and the connectors 16, 17 are simply inserted into the positioning recesses 123, 124, 133, 134 of the ceramic substrates 12, 13, respectively. 15 and connectors 16 and 17 can be easily positioned with respect to the ceramic substrates 12 and 13, respectively. Therefore, the semiconductor module 10 can be manufactured efficiently.
  • the semiconductor module 10 can be thinned. Further, since the element positioning recesses 123 and 133 are formed in the first conductive layers 122A and 132A, the thickness of the first conductive layers 122A and 132A in the bonding region of the semiconductor elements 14 and 15 is the first in other regions. Since the thickness is smaller than that of the conductive layers 122A and 132A, the heat generated in the semiconductor elements 14 and 15 can be efficiently released to the ceramic plates 121 and 131.
  • the semiconductor module 10 of the present embodiment since the pair of semiconductor elements 14 and 15 are arranged in the arrangement direction of the pair of ceramic substrates 12 and 13, the heat of each semiconductor element 14 and 15 is paired. It is possible to efficiently escape to the ceramic substrates 12 and 13.
  • the semiconductor elements 14 and 15 bonded to the ceramic substrates 12 and 13 are formed from the surface of the first conductive layers 122A and 132A where the element positioning recesses 123 and 133 are opened. Does not protrude. Therefore, the height positions of the connectors 16, 17 (particularly the main body plate portions 161, 171) with respect to the surfaces of the first conductive layers 122A, 132A of the ceramic substrates 12, 13, that is, the loop heights of the connectors 16, 17 are as follows. Can be set low. Therefore, the semiconductor module 10 can be further reduced in thickness. Moreover, since the length of each connector 16, 17 can be set short by reducing the loop height of each connector 16, 17, the wiring resistance and parasitic inductance of each connector 16, 17 can be reduced. Can do.
  • the conductive layer of the ceramic substrate is not limited to being provided on both main surfaces of the ceramic plate, and may be provided only on one main surface of the ceramic plate.
  • a sealing resin for sealing the semiconductor element and the connector may be provided between the pair of ceramic substrates.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Combinations Of Printed Boards (AREA)

Abstract

La présent invention porte sur un module semi-conducteur qui comprend : une paire de substrats en céramique comprenant une couche conductrice au niveau de la surface primaire d'une plaque de céramique ; des éléments semi-conducteurs connectés aux premières couches conductrices mutuellement opposées de la paire de substrats en céramique ; et un connecteur qui connecte électriquement les éléments semi-conducteurs connectés à la paire de substrats en céramique, et est connecté à la première couche conductrice de l'un des substrats en céramique. Des indentations de positionnement destinées à insérer individuellement des éléments semi-conducteurs et le connecteur sont formées au niveau des premières couches conductrices.
PCT/JP2014/071318 2014-08-12 2014-08-12 Module semi-conducteur WO2016024333A1 (fr)

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PCT/JP2014/071318 WO2016024333A1 (fr) 2014-08-12 2014-08-12 Module semi-conducteur
JP2015504441A JP5930565B1 (ja) 2014-08-12 2014-08-12 半導体モジュール

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WO2019012679A1 (fr) * 2017-07-14 2019-01-17 新電元工業株式会社 Module électronique
NL2021620A (en) * 2017-09-14 2019-03-19 Shindengen Electric Mfg Electronic module and method for manufacturing electronic module
CN110199387A (zh) * 2017-02-20 2019-09-03 新电元工业株式会社 电子装置以及连接件
WO2022130889A1 (fr) * 2020-12-15 2022-06-23 ローム株式会社 Appareil à semi-conducteur
CN117476631A (zh) * 2023-12-26 2024-01-30 广东仁懋电子有限公司 一种氮化镓微波功率器件

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EP4261872A1 (fr) * 2022-04-11 2023-10-18 Nexperia B.V. Boîtier électronique moulé avec un composant électronique enrobé entre deux substrats avec un élément de ressort entre le composant électronique et un des substrats et son procédé de fabrication
KR20240106740A (ko) * 2022-12-29 2024-07-08 주식회사 아모그린텍 파워모듈용 세라믹 기판 및 이를 포함하는 파워모듈

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CN117476631B (zh) * 2023-12-26 2024-03-22 广东仁懋电子有限公司 一种氮化镓微波功率器件

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