JP6423147B2 - Power semiconductor device and manufacturing method thereof - Google Patents

Power semiconductor device and manufacturing method thereof Download PDF

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JP6423147B2
JP6423147B2 JP2013250011A JP2013250011A JP6423147B2 JP 6423147 B2 JP6423147 B2 JP 6423147B2 JP 2013250011 A JP2013250011 A JP 2013250011A JP 2013250011 A JP2013250011 A JP 2013250011A JP 6423147 B2 JP6423147 B2 JP 6423147B2
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solder
power semiconductor
semiconductor device
lead frame
chip
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JP2015109294A (en
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伸洋 浅地
伸洋 浅地
浩二 油布
浩二 油布
大輔 川端
大輔 川端
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Mitsubishi Electric Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/27011—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature
    • H01L2224/27013—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature for holding or confining the layer connector, e.g. solder flow barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
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    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
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    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83385—Shape, e.g. interlocking features
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    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

Description

本発明は、電力用半導体素子がはんだを用いてリードフレームの上に接合された構造を有する電力用半導体装置、およびその製造方法に関する。   The present invention relates to a power semiconductor device having a structure in which a power semiconductor element is bonded onto a lead frame using solder, and a method for manufacturing the power semiconductor device.

半導体チップの縮小化が続く中、一定の放熱性で一定の短絡耐量を得るため、はんだ接合においては、はんだ内部でのボイドの発生を防止することがますます要求されている。   As semiconductor chips continue to shrink, in order to obtain a certain short-circuit withstand capability with a certain heat dissipation, it is increasingly required to prevent the occurrence of voids inside the solder in solder joints.

ところで、ＩＧＢＴ、ダイオードなどの半導体チップが、はんだを用いてリードフレームの上に接合された電力用半導体装置が存在する。このとき、リードフレームの上に半導体チップをはんだ付けする方法として、例えば次の方法がある。すなわち、水素と窒素の混合ガスの還元雰囲気の炉内で、リードフレームの上にはんだを供給する。次に、はんだ攪拌ジグではんだを叩いてチップ面積（チップサイズ）程度の大きさに攪拌する。次に、吸着コレットを用いてウエハからチップをピックアップし、はんだの上に搭載する。   There is a power semiconductor device in which a semiconductor chip such as an IGBT or a diode is joined onto a lead frame using solder. At this time, as a method of soldering the semiconductor chip on the lead frame, for example, there is the following method. That is, solder is supplied onto the lead frame in a furnace in a reducing atmosphere of a mixed gas of hydrogen and nitrogen. Next, the solder is beaten with a solder agitation jig and agitated to the size of the chip area (chip size). Next, a chip is picked up from the wafer using an adsorption collet and mounted on the solder.

しかしこの方法では、還元雰囲気で除去し切れなかったはんだ表面の酸化膜の影響、はんだ攪拌時の雰囲気の巻き込みの影響などにより、チップ直下のはんだ内部にボイドが発生してしまう。このボイドの影響で、熱抵抗が高くなり、短絡耐量といったモジュールの熱特性が著しく低下する。   However, in this method, voids are generated in the solder directly under the chip due to the influence of the oxide film on the surface of the solder that cannot be completely removed in the reducing atmosphere, the influence of the entrainment of the atmosphere when the solder is stirred, and the like. Due to the influence of the voids, the thermal resistance is increased, and the thermal characteristics of the module such as the short circuit resistance are remarkably deteriorated.

これに対して、特許文献１には、はんだ内部に巻き込まれた雰囲気を外部へ排出するように構成されたはんだ攪拌ジグ（スパンカ）が開示されている。また、特許文献２には、余剰はんだを吸収するための溝が形成された金属性放熱部材を備えた半導体装置が開示されている。   On the other hand, Patent Document 1 discloses a solder stirring jig (spanker) configured to discharge the atmosphere entrained in the solder to the outside. Patent Document 2 discloses a semiconductor device including a metallic heat dissipation member in which a groove for absorbing excess solder is formed.

特開２００２−２７３５６６JP 2002-273666 特開２０１３−１２３０１６JP2013-123016

特許文献１の構成によれば、はんだ攪拌時のボイドの発生を防止できる可能性がある。しかし、チップ搭載時にも雰囲気を巻き込むことでボイドが発生する。このとき、はんだ攪拌の後に、はんだが例えばチップ面積程度に広がっていると、巻き込んだ雰囲気を排斥できず、やはりボイドの発生を防止できない。それゆえ、はんだ供給時のはんだの濡れ広がり面積をチップ面積以下にすることが望ましいが、特許文献１，２に記載の技術では、それについて考慮されていない。   According to the configuration of Patent Document 1, it may be possible to prevent the occurrence of voids during solder agitation. However, voids are generated when the atmosphere is involved even when the chip is mounted. At this time, if the solder spreads to, for example, the chip area after the solder agitation, the entrained atmosphere cannot be eliminated and the generation of voids cannot be prevented. For this reason, it is desirable that the solder wetting and spreading area at the time of supplying the solder be less than or equal to the chip area, but this is not considered in the techniques described in Patent Documents 1 and 2.

本発明の目的は、放熱性に優れ、短絡耐量の高い電力用半導体装置およびその製造方法を提供することである。   An object of the present invention is to provide a power semiconductor device having excellent heat dissipation and high short-circuit tolerance, and a method for manufacturing the same.

上記目的を達成するために、本発明に係る電力用半導体装置は、リードフレームと、リードフレームの上にはんだを用いて接合された電力用半導体素子とを備える。リードフレームの表面であって、平面視で電力用半導体素子の面内には、はんだで充填された凹状領域が設けられている。   In order to achieve the above object, a power semiconductor device according to the present invention includes a lead frame and a power semiconductor element joined to the lead frame using solder. A concave region filled with solder is provided on the surface of the lead frame in the plane of the power semiconductor element in plan view.

また、本発明に係る電力用半導体装置の製造方法は、リードフレームの表面に設けられた凹状領域に溶融はんだを供給する工程と、リードフレームの上に、凹状領域を覆うように電力用半導体素子を搭載する工程とを含む。凹状領域の外縁部には、供給された溶融はんだを塞き止める堤防部が設けられ、電力用半導体素子を搭載する工程では、塞き止められた状態の溶融はんだを前記堤防部の外側まで濡れ広げる。   The method for manufacturing a power semiconductor device according to the present invention includes a step of supplying molten solder to a concave region provided on a surface of a lead frame, and a power semiconductor element on the lead frame so as to cover the concave region. Including a step of mounting. The outer edge portion of the concave region is provided with a dyke portion that blocks the supplied molten solder, and in the step of mounting the power semiconductor element, the molten solder in the blocked state is wetted to the outside of the levee portion. spread.

本発明によれば、電力用半導体素子直下のはんだでボイドの発生が防止されることにより、放熱性に優れ、短絡耐量の高い電力用半導体装置およびその製造方法が実現される。   ADVANTAGE OF THE INVENTION According to this invention, generation | occurrence | production of a void is prevented with the solder directly under a power semiconductor element, Therefore The power semiconductor device excellent in heat dissipation and high short circuit tolerance, and its manufacturing method are implement | achieved.

（ａ）本発明の実施の形態１に係る電力用半導体装置の一製造工程を示し、（ｂ）製造された電力用半導体装置の断面図を示す。(A) One manufacturing process of the power semiconductor device which concerns on Embodiment 1 of this invention is shown, (b) Sectional drawing of the manufactured power semiconductor device is shown. 本発明の実施の形態１に係る電力用半導体装置の平面図を示す。1 is a plan view of a power semiconductor device according to a first embodiment of the present invention. 本発明の実施の形態１の第１変形例に係る電力用半導体装置を示す平面図である。It is a top view which shows the power semiconductor device which concerns on the 1st modification of Embodiment 1 of this invention. 本発明の実施の形態１の第２変形例に係る電力用半導体装置を示す断面図である。It is sectional drawing which shows the power semiconductor device which concerns on the 2nd modification of Embodiment 1 of this invention. （ａ）本発明の実施の形態２に係る電力用半導体装置の一製造工程での構造を示し、（ｂ）製造された電力用半導体装置の断面図を示す。(A) The structure in one manufacturing process of the power semiconductor device which concerns on Embodiment 2 of this invention is shown, (b) The sectional view of the manufactured power semiconductor device is shown. 本発明の実施の形態２に係る電力用半導体装置の平面図を示す。The top view of the semiconductor device for electric power which concerns on Embodiment 2 of this invention is shown. 本発明の実施の形態２の第１変形例に係る電力用半導体装置の平面図を示す。The top view of the semiconductor device for electric power which concerns on the 1st modification of Embodiment 2 of this invention is shown. （ａ）本発明の実施の形態２の第２変形例に係る電力用半導体装置の一製造工程での構造を示し、（ｂ）製造された電力用半導体装置の断面図を示す。(A) The structure in one manufacturing process of the power semiconductor device which concerns on the 2nd modification of Embodiment 2 of this invention is shown, (b) Sectional drawing of the manufactured power semiconductor device is shown. （ａ）本発明の実施の形態３に係る電力用半導体装置の一製造工程での構造を示し、（ｂ）製造された電力用半導体装置の断面図を示す。(A) The structure in one manufacturing process of the power semiconductor device which concerns on Embodiment 3 of this invention is shown, (b) The sectional view of the manufactured power semiconductor device is shown. 本発明の実施の形態３に係る電力用半導体装置の平面図を示す。The top view of the semiconductor device for electric power which concerns on Embodiment 3 of this invention is shown. 本発明の比較例に係る電力用半導体装置の断面図を示す。Sectional drawing of the semiconductor device for electric power which concerns on the comparative example of this invention is shown. 本発明の比較例に係る電力用半導体装置の製造工程を示しており、（ａ）〜（ｃ）は、はんだ供給工程、はんだ攪拌工程、チップ搭載工程にそれぞれ対応する。The manufacturing process of the semiconductor device for electric power which concerns on the comparative example of this invention is shown, (a)-(c) respond | corresponds to a solder supply process, a solder stirring process, and a chip mounting process, respectively.

以下、本発明の実施の形態に係る電力用半導体装置について、図面を参照しながら説明する。各図において、同一または同様の構成部分には同一の符号を付している。また、方向を表す用語「上」、「下」などは、図面中の方向を特定するための便宜的なものであり、使用時における装置の設置方向を限定するものではない。また、各断面図では、一部の部材についてハッチングを省略している。   Hereinafter, power semiconductor devices according to embodiments of the present invention will be described with reference to the drawings. In each figure, the same or similar components are denoted by the same reference numerals. Further, the terms “upper” and “lower” indicating the direction are for convenience in identifying the direction in the drawings, and do not limit the installation direction of the apparatus during use. In each sectional view, hatching is omitted for some members.

まず、図１１を用いて、本発明の比較例に係る電力用半導体装置について説明する。
比較例に係る電力用半導体装置では、リードフレーム１０１の上に半導体チップ１０３ａ，１０３ｂがはんだ１０２を用いて接合されている。チップ１０３ａと１０３ｂの間、チップ１０３ａ，１０３ｂとリードフレーム１０１の外部電極（図示せず）との間は、Ａｌ線１０５のような配線部材で接続されている。このようにして、電気回路が形成されている。 First, a power semiconductor device according to a comparative example of the present invention will be described with reference to FIG.
In the power semiconductor device according to the comparative example, the semiconductor chips 103 a and 103 b are bonded onto the lead frame 101 using the solder 102. A wiring member such as an Al wire 105 is connected between the chips 103a and 103b, and between the chips 103a and 103b and an external electrode (not shown) of the lead frame 101. In this way, an electric circuit is formed.

次に、図１２を用いて、比較例に係る電力用半導体装置の製造方法について説明する。
図１２（ａ）に示す工程Ｓ１では、水素と窒素の混合ガスの還元雰囲気の炉内で、リードフレーム１０１の上に溶融状態のはんだ（以下、溶融はんだという）１０２を供給する。具体的には、糸はんだをノズルから送り出し、熱板１１０の上で加熱されたリードフレーム１０１に接触させ、糸はんだの先端を溶融させてリードフレーム１０１を濡らす。次に、図１２（ｂ）に示す工程Ｓ２では、はんだ１０２を成形するために、はんだ攪拌ジグ１２０で叩いてはんだ１０２を攪拌する。ジグ１２０は先端が窪んでおり、はんだ１０２を叩くことで、窪んだ部分の体積だけはんだが濡れ広がるようになっている。はんだ１０２の面積をチップ１０３の面積と同等かそれ以上とすることで、はんだ１０２の濡れ広がり不足が解消する。次に、図１２（ｃ）に示す工程Ｓ３では、吸着コレット１３０を用いて、ウエハ（図示せず）からチップ１０３をピックアップしてはんだ１０２の上に搭載する。工程Ｓ３では、チップ１０３を吸着コレット１３０で押し込む際に、はんだ１０２が流動して濡れ広がる。 Next, a method for manufacturing a power semiconductor device according to a comparative example will be described with reference to FIG.
In step S1 shown in FIG. 12A, molten solder (hereinafter referred to as molten solder) 102 is supplied onto the lead frame 101 in a furnace in a reducing atmosphere of a mixed gas of hydrogen and nitrogen. Specifically, the thread solder is sent out from the nozzle, brought into contact with the lead frame 101 heated on the hot plate 110, the tip of the thread solder is melted, and the lead frame 101 is wetted. Next, in step S <b> 2 shown in FIG. 12B, the solder 102 is stirred by striking with a solder stirring jig 120 in order to form the solder 102. The jig 120 has a recessed tip, and when the solder 102 is struck, the solder spreads by the volume of the recessed portion. By setting the area of the solder 102 to be equal to or larger than the area of the chip 103, the insufficient wetting and spreading of the solder 102 is solved. Next, in step S <b> 3 shown in FIG. 12C, the chip 103 is picked up from a wafer (not shown) and mounted on the solder 102 using the suction collet 130. In step S3, when the chip 103 is pushed in by the suction collet 130, the solder 102 flows and spreads wet.

以下、工程Ｓ１をはんだ供給工程、工程Ｓ２をはんだ攪拌工程、工程Ｓ３をチップ搭載工程と呼ぶ。   Hereinafter, step S1 is referred to as a solder supply step, step S2 is referred to as a solder stirring step, and step S3 is referred to as a chip mounting step.

上記工程Ｓ１〜３を経て電力用半導体装置を製造した場合、還元雰囲気で除去し切れなかったはんだ表面の酸化膜の影響、工程Ｓ２，３での雰囲気の巻き込みの影響などにより、半導体チップ１０３の直下のはんだにボイドが発生する。ボイドが発生すると、放熱性が低下して熱抵抗が高くなるため、短絡耐量といったモジュールの熱特性が著しく低下してしまう。   When the power semiconductor device is manufactured through the steps S1 to S3, due to the influence of the oxide film on the solder surface that could not be completely removed in the reducing atmosphere, the influence of the entrainment of the atmosphere in the steps S2 and 3, etc. Voids are generated in the solder directly below. When voids are generated, the heat dissipation is reduced and the thermal resistance is increased, so that the thermal characteristics of the module, such as the short-circuit resistance, are significantly reduced.

ところで、工程Ｓ２，３ではんだ１０２内部に巻き込まれた雰囲気は、チップ搭載工程Ｓ３でのはんだ１０２の流動により、チップ１０３の接合面外に排斥することが有効である。ただし、はんだ攪拌工程Ｓ２の後に、はんだ１０２がチップ１０３の面積と同等かそれ以上に濡れ広がっていると、巻き込んだ雰囲気を排斥できず、ボイドの発生を防止できない。すなわち、はんだ１０２の流動によりボイドの発生を防止するためには、はんだ供給工程Ｓ１でのはんだ１０２の濡れ広がり面積をチップ面積以下にすることが望ましい。   By the way, it is effective that the atmosphere engulfed in the solder 102 in the steps S2 and S3 is discharged out of the bonding surface of the chip 103 by the flow of the solder 102 in the chip mounting step S3. However, if the solder 102 is wetted and spread over the area of the chip 103 or more after the solder stirring step S2, the entrained atmosphere cannot be eliminated, and the generation of voids cannot be prevented. In other words, in order to prevent the generation of voids due to the flow of the solder 102, it is desirable that the wet spreading area of the solder 102 in the solder supply step S1 is less than the chip area.

本発明者らは、以下のようにして、はんだ１０２内部に巻き込まれた雰囲気をチップ１０３の接合面外に排斥する方法が効果的であることを見いだした。すなわち、はんだ供給工程Ｓ１では、はんだ１０２を供給する面積をチップ面積以下とする。そして、はんだ攪拌工程Ｓ２を実施せず、はんだ１０２が供給された状態のままで、チップ搭載工程Ｓ３でのはんだの流動により、巻き込まれた雰囲気をチップ１０３の接合面外に排斥する。   The inventors of the present invention have found that the method of eliminating the atmosphere entrained in the solder 102 out of the bonding surface of the chip 103 is effective as follows. That is, in the solder supply step S1, the area for supplying the solder 102 is set to be equal to or less than the chip area. Then, without the solder agitation step S <b> 2 being performed, the entrained atmosphere is discharged out of the bonding surface of the chip 103 by the flow of the solder in the chip mounting step S <b> 3 while the solder 102 is supplied.

しかしこの方法では、さらに以下の課題が想定される。すなわち、はんだ供給工程Ｓ１では、はんだ１０２の供給位置に必然的に多少のバラツキが生じる。それゆえ、チップ搭載工程Ｓ３ではんだ１０２とチップ１０３との位置合わせ（中心合わせ）を正確に行うことは難しく、はんだの流動につられて平面内でチップ１０３が移動、回転する。例えば一定量以上チップ１０３が移動、回転すると、後の配線工程で配線できず、不良品となる。この現象は、特にチップ１０３が薄く、その面積が小さいほど発生しやすい。   However, this method further envisages the following problems. That is, in the solder supply step S1, there is inevitably some variation in the supply position of the solder 102. Therefore, it is difficult to accurately align (center) the solder 102 and the chip 103 in the chip mounting step S3, and the chip 103 moves and rotates in a plane as the solder flows. For example, if the chip 103 moves and rotates more than a certain amount, wiring cannot be performed in a later wiring process, resulting in a defective product. This phenomenon is more likely to occur as the chip 103 is thinner and its area is smaller.

以下で説明する、本発明の実施の形態に係る電力用半導体装置は、以上のような知見に基づいて構成されている。   The power semiconductor device according to the embodiment of the present invention described below is configured based on the above knowledge.

実施の形態１．
図１（ａ）は、本発明の実施の形態１に係る電力用半導体装置の一製造工程を示し、図１（ｂ）は、製造された電力用半導体装置の断面図を示す。図２は、当該電力用半導体装置の平面図を示す。図１（ｂ）は、図２のＡ−Ａ線断面図である。これは、図５と図６、図９と図１０でも同様である。
図１（ｂ）に示すように、電力用半導体装置１００は、リードフレーム１と、リードフレーム１の上にはんだ２を用いて接合された半導体チップ３と、リードフレーム１の上に設けられ、はんだ２中に取り込まれた堤防部材４などを備える。 Embodiment 1 FIG.
1A shows one manufacturing process of the power semiconductor device according to the first embodiment of the present invention, and FIG. 1B shows a cross-sectional view of the manufactured power semiconductor device. FIG. 2 is a plan view of the power semiconductor device. FIG.1 (b) is the sectional view on the AA line of FIG. The same applies to FIGS. 5 and 6 and FIGS. 9 and 10.
As shown in FIG. 1B, a power semiconductor device 100 is provided on a lead frame 1, a semiconductor chip 3 joined to the lead frame 1 using solder 2, and the lead frame 1. An embankment member 4 taken into the solder 2 is provided.

リードフレーム１は、例えば銅製である。さらに、銅などの母材に銀めっきを施した材料を用いてもよい。リードフレーム１は電力回路用のリードフレームを想定しているが、これに限定されず、例えば制御回路用のリードフレームであってもよい。はんだ２は、例えばＳｎ−Ａｇ系、Ｓｎ−Ｃｕ系の鉛フリーはんだである。半導体チップ３は、例えばＩＧＢＴ（絶縁ゲート型バイポーラトランジスタ）、ダイオード、ＭＯＳＦＥＴ（金属酸化膜半導体電界効果トランジスタ）のような電力用半導体素子である。   The lead frame 1 is made of, for example, copper. Furthermore, you may use the material which silver-plated to base materials, such as copper. The lead frame 1 is assumed to be a lead frame for a power circuit, but is not limited to this, and may be a lead frame for a control circuit, for example. The solder 2 is, for example, Sn-Ag-based or Sn-Cu-based lead-free solder. The semiconductor chip 3 is a power semiconductor element such as an IGBT (insulated gate bipolar transistor), a diode, or a MOSFET (metal oxide semiconductor field effect transistor).

図１（ｂ）では、リードフレーム１の上に搭載された１つの半導体チップのみを図示しているが、複数の半導体チップ３が搭載されていてもよい。比較例と同様に、例えば当該半導体チップ３どうしの間は、図示しないＡｌ線のような配線部材で接続されている。   In FIG. 1B, only one semiconductor chip mounted on the lead frame 1 is illustrated, but a plurality of semiconductor chips 3 may be mounted. Similar to the comparative example, for example, the semiconductor chips 3 are connected by a wiring member such as an Al wire (not shown).

図２に示すように、堤防部材４は、平面視で（ｚ方向から見て）半導体チップ３の面内に設けられている。すなわち、平面視で堤防部材４が内側方向に画定する面積は、半導体チップ３が画定する面積以下である。この堤防部材４により、リードフレーム１の表面にはんだ２で充填された凹状領域が画定される。図２では、凹状領域にハッチングを付している。後述するように、この凹状領域は、装置１００の製造時に溶融はんだ２を供給する領域である。堤防部材４は、はんだ２に対して濡れ性の良い材料で構成される。本明細書で、堤防部材４について濡れ性の良い（悪い）は、銅、銀めっきなどからなるリードフレーム１の表面の濡れ性に対しての相対的な評価である。当該濡れ性の良い材料は、はんだ２が上記鉛フリーはんだであれば、例えばＡｕ、Ａｇ、Ｃｕなどである。   As shown in FIG. 2, the bank member 4 is provided in the plane of the semiconductor chip 3 in a plan view (viewed from the z direction). That is, the area defined by the dike member 4 in the inner direction in plan view is equal to or smaller than the area defined by the semiconductor chip 3. The dike member 4 defines a concave region filled with the solder 2 on the surface of the lead frame 1. In FIG. 2, the concave region is hatched. As will be described later, this concave region is a region for supplying the molten solder 2 when the apparatus 100 is manufactured. The bank member 4 is made of a material having good wettability with respect to the solder 2. In this specification, the good (bad) wettability of the bank member 4 is a relative evaluation with respect to the wettability of the surface of the lead frame 1 made of copper, silver plating or the like. If the solder 2 is the lead-free solder, the material having good wettability is, for example, Au, Ag, Cu or the like.

また、図１，２から判るように、堤防部材４は枠状であり、その高さ（ｚ方向）は３０μｍから５０ｕｍ程度である。当該高さは、堤防部材４周囲でのはんだ２の厚さ以下であればよく、例えば当該はんだ２の厚さと等しい、または、ほぼ等しい。堤防部材４がはんだ２の厚さに等しいとき、堤防部材４は半導体チップ３に直接に接することになる。   As can be seen from FIGS. 1 and 2, the bank member 4 has a frame shape, and its height (z direction) is about 30 μm to 50 μm. The height may be equal to or less than the thickness of the solder 2 around the embankment member 4, for example, equal to or substantially equal to the thickness of the solder 2. When the bank member 4 is equal to the thickness of the solder 2, the bank member 4 comes into direct contact with the semiconductor chip 3.

この電力用半導体装置１００は、図１２の比較例のはんだ供給工程Ｓ１とチップ搭載工程Ｓ３（図１（ａ））とにより、はんだ攪拌工程Ｓ２を経ずに製造される。ただし、リードフレーム１の上の、はんだ２を供給する位置の周囲に、予め堤防部材４を設け、凹状領域を形成しておく。堤防部材４は、リードフレーム１表面の凹状領域に供給され、当該領域外に向けて流れる溶融はんだ２を塞き止める機能を有する。以下、本実施形態１により得られる効果について、製造工程中にはんだ２が濡れ広がる過程と併せて説明する。   This power semiconductor device 100 is manufactured without the solder stirring step S2 by the solder supply step S1 and the chip mounting step S3 (FIG. 1A) of the comparative example of FIG. However, an embankment member 4 is provided in advance around the position on the lead frame 1 where the solder 2 is supplied to form a concave region. The bank member 4 has a function of blocking the molten solder 2 that is supplied to the concave area on the surface of the lead frame 1 and flows toward the outside of the area. Hereinafter, the effects obtained by the first embodiment will be described together with the process in which the solder 2 spreads during the manufacturing process.

はんだ供給工程Ｓ１では、堤防部材４が半導体チップ３の面内に設けられていることにより、はんだ供給時の溶融はんだ２の濡れ広がり面積がチップ面積以下に制御される。   In the solder supply step S1, since the bank member 4 is provided in the surface of the semiconductor chip 3, the wet spread area of the molten solder 2 at the time of supplying the solder is controlled to be equal to or less than the chip area.

さらに、はんだ供給時のはんだ２の位置が定まることにより、半導体チップ３の移動、回転が抑制される。特に、リードフレーム１表面での凹状領域の面積は、はんだ供給時のはんだの濡れ広がり面積以下であることから、供給直後のはんだ２の中心が、凹状領域の中心となるように位置を制御できる。これにより、チップ３の移動、回転の抑制効果を高めることができる。換言すると、はんだ２の供給位置が、基準とする位置からずれた場合でも、はんだ２の中心（重心）が凹状領域の中心と一致するように、位置を制御できる。   Furthermore, movement and rotation of the semiconductor chip 3 are suppressed by determining the position of the solder 2 when supplying the solder. In particular, since the area of the concave region on the surface of the lead frame 1 is equal to or less than the wet spread area of the solder at the time of supplying the solder, the position can be controlled so that the center of the solder 2 immediately after supply is the center of the concave region. . Thereby, the effect of suppressing the movement and rotation of the chip 3 can be enhanced. In other words, even when the supply position of the solder 2 is deviated from the reference position, the position can be controlled so that the center (center of gravity) of the solder 2 coincides with the center of the concave region.

また、堤防部材４の高さを所望のはんだ２の厚さとほぼ同一とした場合、堤防部材４の高さによりはんだ２の厚さが決まるため、はんだ２の厚さを一定にする効果が得られる。はんだ２を所望の厚さで一定にすることで、はんだが薄くなることを防ぎ、熱履歴によるはんだクラックの発生を抑制して装置１００の信頼性を向上させることができる。   Further, when the height of the dike member 4 is substantially the same as the thickness of the desired solder 2, the thickness of the solder 2 is determined by the height of the dike member 4, so that the effect of making the thickness of the solder 2 constant is obtained. It is done. By making the solder 2 constant at a desired thickness, it is possible to prevent the solder from being thinned, to suppress the occurrence of solder cracks due to thermal history, and to improve the reliability of the apparatus 100.

また、比較例と同様にはんだ供給工程Ｓ１を還元雰囲気中で実施した場合、はんだ供給直後のはんだ２の濡れ広がりが促進され、堤防部材４が設けられたエリアまで、すなわち凹状領域の全体に確実にはんだ２が濡れ広がることになる。   Further, when the solder supply step S1 is performed in a reducing atmosphere as in the comparative example, the wetting and spreading of the solder 2 immediately after the supply of the solder is promoted, so that the area up to the area where the bank member 4 is provided, that is, the entire concave region is reliably obtained. The solder 2 spreads out.

チップ搭載工程Ｓ３では、リードフレーム１表面の凹状領域を覆うように、半導体チップ３をはんだ２の上に押し付ける。はんだ供給工程Ｓ１で濡れ広がり面積がチップ面積以下に制御されたはんだ２は、チップ搭載工程Ｓ３でのチップ３の押し付けにより、チップ面積を超えて濡れ広がることになり、その際のはんだ２の流動により、巻き込まれた雰囲気は半導体チップ３の接合面外に排斥されることになる。   In the chip mounting step S3, the semiconductor chip 3 is pressed onto the solder 2 so as to cover the concave area on the surface of the lead frame 1. The solder 2 whose wetting and spreading area is controlled to be equal to or less than the chip area in the solder supplying process S1 is spread over the chip area by pressing the chip 3 in the chip mounting process S3, and the flow of the solder 2 at that time As a result, the entrapped atmosphere is discharged out of the bonding surface of the semiconductor chip 3.

このようにして、半導体チップ３直下のはんだ２でボイドの発生が防止されることにより、放熱性に優れ、短絡耐量の高い電力用半導体装置１００が実現される。   In this way, the generation of voids is prevented by the solder 2 directly under the semiconductor chip 3, thereby realizing the power semiconductor device 100 having excellent heat dissipation and high short-circuit tolerance.

図３は、本発明の実施の形態１の第１変形例に係る電力用半導体装置を示す平面図である。
この変形例で、堤防部材４は、半導体チップ３の各辺と堤防部材４の外周（外縁部）とのクリアランス（間隔）が一定となるような形状を有する。換言すると、堤防部材４の外縁部は、平面視で、半導体チップ３の各辺から一定距離を隔てた辺で構成される。図３では、ｘ方向のクリアランスをＸで、ｙ方向のクリアランスをＹで示している。すなわち、この変形例ではＸの値とＹの値が等しい。それゆえ、はんだ２が各方向（ｘ方向、ｙ方向）へ濡れ広がる距離が一定となってはんだ２の流動のアンバランスが解消される。これにより、半導体チップ３の移動、回転の抑制効果を高めることができる。なお、図３のＸの値とＹの値が完全には一致しなくても、この変形例の効果をある程度得ることができる。 FIG. 3 is a plan view showing a power semiconductor device according to a first modification of the first embodiment of the present invention.
In this modification, the bank member 4 has a shape in which the clearance (interval) between each side of the semiconductor chip 3 and the outer periphery (outer edge portion) of the bank member 4 is constant. In other words, the outer edge portion of the dyke member 4 is constituted by sides that are spaced apart from each side of the semiconductor chip 3 in plan view. In FIG. 3, the clearance in the x direction is indicated by X, and the clearance in the y direction is indicated by Y. That is, in this modification, the value of X is equal to the value of Y. Therefore, the distance over which the solder 2 wets and spreads in each direction (x direction, y direction) becomes constant, and the flow imbalance of the solder 2 is eliminated. Thereby, the effect of suppressing the movement and rotation of the semiconductor chip 3 can be enhanced. Note that the effect of this modification can be obtained to some extent even if the values of X and Y in FIG. 3 do not completely match.

本実施形態１では、堤防部材４の枠の厚さもｘ方向、ｙ方向で一定であり、堤防部材４の内縁部、すなわち凹状領域の外縁部も、平面視で、半導体チップ３の各辺から一定距離を隔てた辺で構成される。   In the first embodiment, the thickness of the frame of the dyke member 4 is also constant in the x direction and the y direction, and the inner edge portion of the dyke member 4, that is, the outer edge portion of the concave region, is also seen from each side of the semiconductor chip 3 in plan view. It consists of sides separated by a certain distance.

図４は、本発明の実施の形態１の第２変形例に係る電力用半導体装置を示す平面図である。
この変形例で、堤防部材４は、半導体チップ３側でＲ面取りが施された形状を有する。他の面取り、例えばＣ面取りなどが施されてもよい。堤防部材４が面取りされた形状を有することにより、以下の効果が得られる。すなわち、チップ搭載工程Ｓ３によるはんだ２の濡れ広がり時に堤防部材４に塞き止められ、その内側に蓄積されてしまう可能性のある巻き込まれた雰囲気を、半導体チップ３の接合面外に排斥しやすくなる。 FIG. 4 is a plan view showing a power semiconductor device according to a second modification of the first embodiment of the present invention.
In this modification, the dyke member 4 has a shape that is chamfered on the semiconductor chip 3 side. Other chamfering, such as C chamfering, may be performed. The following effects are acquired by having the shape where the bank member 4 was chamfered. That is, the entangled atmosphere that may be blocked by the bank member 4 when the solder 2 spreads out in the chip mounting step S3 and accumulates inside thereof is easily discharged out of the bonding surface of the semiconductor chip 3. Become.

実施の形態２．
図５（ａ）は、本発明の実施の形態２に係る電力用半導体装置の一製造工程での構造を示し、図５（ｂ）は、製造された電力用半導体装置の断面図を示す。
本実施形態２に係る電力用半導体装置２００では、リードフレーム２１に溝部２１ａが形成されている。その他の基本的な構成は実施形態１と同様であり、説明を省略する。 Embodiment 2. FIG.
FIG. 5A shows a structure in one manufacturing process of the power semiconductor device according to the second embodiment of the present invention, and FIG. 5B shows a cross-sectional view of the manufactured power semiconductor device.
In the power semiconductor device 200 according to the second embodiment, a groove 21 a is formed in the lead frame 21. Other basic configurations are the same as those of the first embodiment, and a description thereof will be omitted.

図６に示すように、溝部２１ａは、平面視で半導体チップ３の面内に設けられている。すなわち、平面視で溝部２１ａが内側方向に画定する面積は、半導体チップ３が画定する面積以下である。この溝部２１ａにより、リードフレーム２１の表面に、はんだ２で充填された凹状領域が画定される。後述するように、この凹状領域は、装置２００の製造時に溶融はんだ２を供給する領域である。溝部２１ａの深さ（ｚ方向）は、３０μｍから５０ｕｍ程度である。   As shown in FIG. 6, the groove 21a is provided in the plane of the semiconductor chip 3 in plan view. That is, the area defined by the groove 21a in the inner direction in plan view is equal to or smaller than the area defined by the semiconductor chip 3. The groove 21 a defines a concave region filled with the solder 2 on the surface of the lead frame 21. As will be described later, this concave region is a region for supplying the molten solder 2 when the apparatus 200 is manufactured. The depth (z direction) of the groove 21a is about 30 μm to 50 μm.

この電力用半導体装置２００では、溝部２１ａの外縁の段差部２１ｂが、リードフレーム２１表面の凹状領域に供給され、当該領域外に向けて流れる溶融はんだ２を塞き止める「堤防部」としての機能を有する。製造工程中にはんだ２が濡れ広がる過程については、実施形態１と同様である。したがって、本実施形態２によれば、実施形態１で説明した効果と同様の効果が得られる。   In this power semiconductor device 200, the stepped portion 21 b at the outer edge of the groove 21 a is supplied to a concave region on the surface of the lead frame 21 and functions as a “bank” that blocks the molten solder 2 that flows toward the outside of the region. Have The process by which the solder 2 spreads out during the manufacturing process is the same as in the first embodiment. Therefore, according to the second embodiment, the same effects as those described in the first embodiment can be obtained.

図７は、本発明の実施の形態２の第１変形例に係る電力用半導体装置の平面図を示す。
この第１変形例で、溝部２１ａは、半導体チップ３の各辺と溝部２１ａの外縁部とのクリアランスが一定となるような形状を有する。すなわち、この変形例は、図３で説明した実施形態１の第１変形例と同様の構成であり、そこで説明した効果と同様の効果が得られる。 FIG. 7 is a plan view of a power semiconductor device according to a first modification of the second embodiment of the present invention.
In this first modification, the groove 21a has a shape such that the clearance between each side of the semiconductor chip 3 and the outer edge of the groove 21a is constant. That is, this modified example has the same configuration as that of the first modified example of the first embodiment described with reference to FIG. 3, and the same effect as described above can be obtained.

図８は、本発明の実施の形態２の第２変形例に係る電力用半導体装置の平面図を示す。
この第２変形例では、溝部２１ａの面方向の大きさが、半導体チップ３に向かって（＋ｚ方向に）テーパ状に大きくなるように形成されている。「面方向の大きさ」とは、例えば、平面視で長方形に形成された溝部２１ａでは長方形の面積である。これにより、チップ搭載工程Ｓ３によるはんだ２の濡れ広がり時に段差部２１ｂに塞き止められ、溝部２１に蓄積されてしまう可能性のある巻き込まれた雰囲気を、半導体チップ３の接合面外に排斥しやすくなるという効果が得られる。 FIG. 8 is a plan view of a power semiconductor device according to a second modification of the second embodiment of the present invention.
In the second modified example, the size of the groove 21a in the surface direction is formed to increase in a tapered shape toward the semiconductor chip 3 (in the + z direction). The “size in the surface direction” is, for example, a rectangular area in the groove portion 21a formed in a rectangular shape in plan view. As a result, the entangled atmosphere that may be blocked by the stepped portion 21b and accumulated in the groove portion 21 when the solder 2 spreads out in the chip mounting step S3 is discharged out of the bonding surface of the semiconductor chip 3. The effect that it becomes easy is acquired.

実施の形態３．
図９（ａ）は、本発明の実施の形態３に係る電力用半導体装置の一製造工程での構造を示し、図９（ｂ）は、製造された電力用半導体装置の断面図を示す。
本実施形態３に係る電力用半導体装置３００では、実施形態１と同様に枠状の堤防部材３４が設けられるところ、堤防部材３４の表面材料として、はんだ２に対して濡れ性の悪い材料を用いることが特徴である。その他の基本的な構成は実施形態１と同様であり、説明を省略する。 Embodiment 3 FIG.
FIG. 9A shows a structure in one manufacturing process of the power semiconductor device according to the third embodiment of the present invention, and FIG. 9B shows a cross-sectional view of the manufactured power semiconductor device.
In the power semiconductor device 300 according to the third embodiment, a frame-shaped dyke member 34 is provided as in the first embodiment. As the surface material of the dyke member 34, a material having poor wettability with respect to the solder 2 is used. It is a feature. Other basic configurations are the same as those of the first embodiment, and a description thereof will be omitted.

はんだ２として実施形態１で説明したような鉛フリーはんだを用い、リードフレーム１の表面に銅、銀めっきを用いた場合、はんだ２に対して濡れ性の悪い材料としては、Ｎｉ、Ａｌなどが挙げられる。堤防部材３４としては銅などの母材にＮｉ、Ａｌなどをメッキしたものを用いることができる。   When the lead-free solder as described in the first embodiment is used as the solder 2 and copper or silver plating is used on the surface of the lead frame 1, Ni, Al, etc. are examples of materials having poor wettability with respect to the solder 2. Can be mentioned. As the bank member 34, a base material such as copper plated with Ni, Al or the like can be used.

このように、本実施形態３では、はんだ２に対して濡れ性の悪い表面材料を用いることにより、例えば堤防部材３４の高さを小さくした場合でも、はんだ供給工程Ｓ１で供給された溶融はんだ２を塞き止める機能を担保させることができる。したがって、本実施形態３によれば、実施形態１で説明した効果と同様の効果が得られ、さらに、より自由度の高い構造が実現される。   As described above, in the third embodiment, by using a surface material having poor wettability with respect to the solder 2, for example, even when the height of the bank member 34 is reduced, the molten solder 2 supplied in the solder supply step S <b> 1. Can be secured. Therefore, according to the third embodiment, the same effects as those described in the first embodiment can be obtained, and a structure with a higher degree of freedom can be realized.

なお、例えば堤防部材３４の表面粗さを大きくした場合にも、本実施形態３による効果を得ることができる。濡れ性の悪い材料からなる表面、表面粗さの大きい表面は、それぞれ「はんだに対する非濡れ性表面」の一例である。   For example, even when the surface roughness of the bank member 34 is increased, the effect of the third embodiment can be obtained. A surface made of a material having poor wettability and a surface having a large surface roughness are examples of a “non-wettable surface with respect to solder”.

このように、上記の「リードフレーム１表面の凹状領域に供給され、当該領域外に向けて流れる溶融はんだ２を塞き止める」堤防部材３４（４）の機能は、堤防部材３４（４）の表面の材料と粗さ、形状（高さ）などを調整することにより達成される。   As described above, the function of the dyke member 34 (4) “blocks the molten solder 2 supplied to the concave region on the surface of the lead frame 1 and flowing toward the outside of the region” is the function of the dyke member 34 (4). This is achieved by adjusting the surface material, roughness, shape (height) and the like.

以上で説明した実施の形態では、フラックスレスの鉛フリーはんだを使用することを想定したが、これに限定されることなく、錫入り、フラックス入りのはんだを用いた場合にも、もちろん本発明による効果は得られる。また、はんだ２に対して濡れ性の良い材料、濡れ性の悪い材料は、当業者により適宜選択される。   In the embodiment described above, it is assumed that a flux-less lead-free solder is used. However, the present invention is not limited to this. The effect is obtained. A material having good wettability and poor wettability to the solder 2 is appropriately selected by those skilled in the art.

また、以上で説明した各実施の形態および各変形例の構成は、自由に組み合わせ、あるいは変形、省略されてもよい。例えば、実施形態３に実施形態１の第１変形例（図３）を適用してもよい。   Further, the configurations of the embodiments and the modifications described above may be freely combined, modified, or omitted. For example, the first modification (FIG. 3) of the first embodiment may be applied to the third embodiment.

１，２１ リードフレーム、 ２ はんだ、 ３ 半導体チップ、 ４，３４ 堤防部材、 ２１ａ 溝部、 ２１ｂ 段差部、 ３０ 吸着コレット、 １００，２００，３００ 電力用半導体装置。   1, 21 Lead frame, 2 Solder, 3 Semiconductor chip, 4,34 Levee member, 21a Groove part, 21b Step part, 30 Adsorption collet, 100, 200, 300 Power semiconductor device.

Claims (3)

リードフレームの表面に設けられた凹状領域に溶融はんだを供給する工程と、
前記リードフレームの上に、前記凹状領域を覆うように電力用半導体素子を搭載する工程とを含み、
前記凹状領域は、前記リードフレームに形成された溝部によって画定され、
前記溝部の外縁部には、供給された溶融はんだを塞き止める段差部が設けられ、
前記溝部の段差部は、該溝部の面方向の大きさが前記電力用半導体素子に向かってテーパ状に大きくなるように形成され、
前記溝部の段差部は、平面視で前記電力用半導体素子の外縁部の内側に位置し、
前記電力用半導体素子を搭載する工程では、塞き止められた状態の溶融はんだを前記段差部の外側まで濡れ広げることを特徴とする、電力用半導体装置の製造方法。 Supplying molten solder to a concave region provided on the surface of the lead frame;
Mounting a power semiconductor element on the lead frame so as to cover the concave region,
The concave region is defined by a groove formed in the lead frame;
The outer edge portion of the groove portion is provided with a stepped portion that blocks the supplied molten solder,
The step portion of the groove is formed so that the size of the groove in the surface direction increases in a tapered shape toward the power semiconductor element,
The step portion of the groove portion is located inside the outer edge portion of the power semiconductor element in a plan view,
In the step of mounting the power semiconductor element, a method of manufacturing a power semiconductor device is characterized in that molten solder in a closed state is wetted to the outside of the stepped portion. 前記リードフレームの表面での凹状領域の面積は、前記溶融はんだを供給する工程で溶融はんだが濡れ広がる面積以下であることを特徴とする、請求項１に記載の電力用半導体装置の製造方法。 The area of the recessed areas on the surface of the lead frame, characterized in that said at most area spreads the molten solder in the process for supplying the molten solder, method of manufacturing the power semiconductor device according to claim 1. 前記溶融はんだを供給する工程および前記電力用半導体素子を搭載する工程は、還元雰囲気中で実施することを特徴とする、請求項１または２に記載の電力用半導体装置の製造方法。 Process, which comprises carrying out in a reducing atmosphere, method of manufacturing the power semiconductor device according to claim 1 or 2 for mounting step and the power semiconductor element for supplying the molten solder.
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