JP2015138970A - semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which can prevent poor connection caused by a short circuit between neighboring conductive posts when bonding a semiconductor chip and the conductive posts.SOLUTION: A semiconductor device comprises: an insulating substrate; semiconductor chips 11A, 11B arranged on one surface of the insulating substrate; electrode pads 11a, 11b provided on a surface of the semiconductor chip on the side opposite to the insulating substrate; a plurality of conductive posts 18a, 18b with one ends being bonded to the electrode pads by a bonding material; and a printed circuit board which is arranged to face one surface of the semiconductor chip and has an electric wiring part to which the other end of each conductive post is bonded, in which a heat resistant insulating resin layer 31 is formed around bonding material arrangement regions of the conductive posts on the semiconductor chip.

Description

  The present invention relates to a semiconductor device that electrically and mechanically joins an electrode pad of a semiconductor chip disposed on an insulating substrate to a printed circuit board through a conductive post.

In power converters, uninterruptible power supplies, machine tools, industrial robots, etc., semiconductor devices equipped with power semiconductor elements such as IGBTs (Insulated Gate Bipolar Transistors) and power FETs (Field Effect Transistors) are used.
In Patent Document 1, as this semiconductor device, a copper block is arranged on the front and back of an insulating substrate with a copper pattern, an IGBT chip and a diode chip are arranged on the front copper block, and the IGBT chip, the diode chip and the printed board are arranged. And a plurality of implant pins (hereinafter referred to as conductive posts).

  In Patent Document 2, metal particles protected with an organic coating are applied to at least one of the bonding surfaces of the front surface electrode and the post electrode of the semiconductor chip, and the front surface electrode and the post electrode of the semiconductor chip are applied. A method of manufacturing a semiconductor device is described in which a metal electrode is exposed by pressurizing and heating between the two to expose the metal particles and actively bond the metal particles to bond the front electrode and the post electrode. Has been.

JP 2011-142124 A JP 2012-74433 A

However, in the conventional example described in Patent Document 1, the connection of the conductive posts connecting the semiconductor chip and the printed board to the semiconductor chip is fixed by soldering.
As described above, when the conductive posts are joined by solder, in the joining process such as reflow processing, when the solder is melted, the solder wets and spreads, so that a solder bridge is formed between the adjacent conductive posts. There is an unsolved problem that a connection failure occurs due to a short circuit.

Further, even when a solid diffusion bonding material such as a metal particle represented by nano Ag is used as a bonding material for bonding a semiconductor chip and a conductive post described in Patent Document 2, pressurization during bonding Since the bonding material may spread to a horizontal plane due to the process such as the above, there is an unresolved problem that the bonding material on each electrode pad of the semiconductor chip is in contact with the solder as in the case of the solder, and a connection failure may occur due to a short circuit. is there.
Accordingly, the present invention has been made paying attention to the above-described unsolved problems of the conventional example, and prevents a connection failure between the semiconductor chip and the conductive post due to a short circuit between adjacent conductive posts. An object of the present invention is to provide a semiconductor device.

  In order to achieve the above object, one embodiment of a semiconductor device according to the present invention includes an insulating substrate, a semiconductor chip disposed on one surface of the insulating substrate, and a surface of the semiconductor chip opposite to the insulating substrate. Electrode pads, a plurality of conductive posts whose one ends are bonded to the electrode pads with a bonding material, and arranged opposite to one surface of the semiconductor chip, and the other ends of the respective conductive posts are bonded. And a printed circuit board on which an electrical wiring portion is formed. A heat-resistant insulating resin layer is formed around the bonding material arrangement region of the conductive posts in the semiconductor chip.

  According to the present invention, when a plurality of conductive posts are bonded to an electrode pad provided on one surface of a semiconductor chip with a bonding material, a short circuit between adjacent conductive posts is arranged to dispose the bonding material of the conductive posts. This can be prevented by a heat-resistant insulating resin layer formed around the region. Therefore, the mounting quality of the semiconductor chip can be improved.

It is a circuit diagram which shows the example of the equivalent circuit in the semiconductor device of this invention. 1 is a cross-sectional view of a semiconductor device according to a first embodiment of the present invention. 1 is a plan view of a semiconductor chip according to a first embodiment of the present invention. It is a top view in the state where the conductive post of the semiconductor chip of the 1st embodiment of the present invention was joined. It is an expanded sectional view of a semiconductor chip. It is process drawing in the case of forming a heat resistant insulating resin layer by the drawing process which uses an inkjet printer. It is process drawing in the case of forming a heat resistant insulating resin layer by a photolithography process. It is a figure explaining the manufacturing method of the semiconductor device of the 1st Embodiment of this invention. It is a top view of the semiconductor chip which shows the modification of the 1st Embodiment of this invention. It is a top view of the state which joined the conductive post of the semiconductor chip which shows the 2nd Embodiment of this invention. It is sectional drawing similar to FIG. 2 which shows the modification of the power semiconductor module as a semiconductor device which concerns on this invention.

Hereinafter, an example of an embodiment of the present invention will be described with reference to the drawings.
FIG. 1 is a circuit diagram showing an example of an equivalent circuit in a semiconductor device of the present invention. This semiconductor device includes a first transistor Q1, a first diode D1, a second transistor Q2, a second diode D2, a first collector terminal C1, a first gate terminal G1, a second gate terminal G2, an intermediate terminal C2 / E1, Two emitter terminals E2 are provided.

The first gate terminal G1 is electrically connected to the gate of the first transistor Q1. The collector of the first transistor Q1 and the cathode of the first diode D1 are electrically connected, and these are electrically connected to the first collector terminal C1.
The second gate terminal G2 is electrically connected to the gate of the second transistor Q2. The emitter of the second transistor Q2 and the anode of the second diode D2 are electrically connected, and these are electrically connected to the second emitter terminal E2.

The emitter of the first transistor Q1, the anode of the first diode D1, the collector of the second transistor Q2, and the cathode of the second diode D2 are electrically connected, and these are electrically connected to the intermediate terminal C2 / E1. Connected to.
In the semiconductor device of the present embodiment, a switching device such as an IGBT or a power MOSFET is used as the first transistor Q1 and the second transistor Q2. The first diode D1 and the second diode D2 are used as free wheeling diodes.

FIG. 2 is a cross-sectional view of the semiconductor device according to the first embodiment of the present invention. In a transistor for a power semiconductor device having a large rated current, a semiconductor chip having a small rated current is used in parallel to increase the rated current as a whole. FIG. 2 shows a portion of the first transistor and the first collector terminal C1 indicated by broken lines in FIG. 1, and includes two semiconductor chips 11A and 11B and two pin-like conductors 20 for external connection, respectively. It shows what was formed in parallel.
The insulating substrate 12 includes a ceramic substrate 15 made of alumina or the like having good heat conductivity, and copper plates 16a and 16b individually attached to the front and back surfaces of the ceramic substrate 15.
On the copper plate 16a on the front surface side of the insulating substrate 12, a predetermined wiring pattern for connecting a plurality of power devices arranged on the copper plate 16a is formed.

As shown in FIG. 3, a first electrode pad 11a and a second electrode pad 11b are formed on the front surfaces of the semiconductor chips 11A and 11B, respectively. The first electrode pad 11a constitutes an emitter electrode pad that becomes a main electrode pad. The second electrode pad 11b constitutes a gate electrode pad that serves as a control electrode pad.
As shown in FIG. 2, third electrode pads 11c are formed on the back surfaces of the semiconductor chips 11A and 11B, respectively. The third electrode pad 11c constitutes a collector electrode pad that becomes a main electrode pad.

The copper plate 16 a of the insulating substrate 12 is electrically connected to each third electrode pad 11 c on the back surface of the semiconductor chips 11 A and 11 B via the solder 17. The semiconductor chips 11A and 11B may be formed of a silicon substrate or may be formed of a SiC substrate.
The pin-shaped conductor 20 (first collector terminal C1) is electrically connected to the copper plate 16a of the insulating substrate 12 with solder (not shown).
Above the semiconductor chips 11A and 11B, a printed circuit board 14 having an electrical wiring portion is provided at a predetermined distance from the upper surfaces of the semiconductor chips 11A and 11B.

As shown in FIG. 4, the plurality of first conductive posts 18 a electrically and mechanically connect the first electrode pads 11 a and the wiring circuit of the printed circuit board 14 via solder 19, respectively.
The second conductive post 18 b electrically and mechanically connects the second electrode pad 11 b and the electric wiring portion of the printed board 14 via the solder 19.
As shown in FIGS. 2 to 4, the resin sealing material 24 is such that one end of the pin-like conductor 20 (first collector terminal C1) and the lower surface of the copper plate 16b on the back surface of the insulating substrate 12 are exposed to the outside. The insulating substrate 12, the semiconductor chips 11A and 11B, the first electrode pad 11a, the second electrode pad 11b, the pin-shaped conductor 20 (first collector terminal C1), the first conductive post 18a, and the second conductive post 18b. And the printed circuit board 14 and the like are sealed.

  In FIG. 2, the semiconductor chips 11A and 11B constituting the first transistor Q1 and the semiconductor chip (not shown) constituting the first diode D1 are arranged in the front-rear direction on the copper plate 16a of the insulating substrate 12. It shows the state that was done. That is, the first transistor Q1 and the first diode D1 are connected in antiparallel by the copper plate 16a of the insulating substrate 12 and the printed circuit board 14.

As described above, a plurality of first conductive posts 18a and one second conductive post 18b are disposed on the printed circuit board 14 so as to extend downward from the back surface serving as one surface. The pin-shaped conductor 20 (first collector terminal C1) is disposed upward on the insulating substrate 12, and penetrates the printed circuit board 14 and is led out to the outside.
2, the semiconductor chips 11A and 11B can be arranged side by side in the front-rear direction without being arranged on the copper plate 16a of the insulating substrate 12 in the left-right direction.

  As shown in FIG. 3, in the semiconductor chips 11A and 11B, a first electrode pad 11a having a relatively large area is formed on the front surface side, and a predetermined width is formed on the first electrode pad 11a. A second electrode pad 11b having a relatively small area with an insulating distance is formed. Here, as shown in an enlarged view in FIG. 5, the first electrode pad 11a and the second electrode pad 11b are connected to the semiconductor chip 11A in order to join the first conductive post 18a and the second conductive post 18b by soldering. , 11B is formed on the front surface of the electrode film 11d such as aluminum (Al) by plating or vapor deposition to form a metal film 11e that improves the wettability of copper (Au) or silver (Ag) solder. Has been.

  FIG. 4 illustrates the arrangement of the first conductive posts 18a on the first electrode pads 11a and the second conductive posts 18b on the second electrode pads 11b. In FIG. 4, four first conductive posts 18a and one second conductive post 18b are used. The first electrode pad 11a is electrically connected to a pin-like conductor (pin terminal) constituting an external connection terminal (emitter terminal E1) (not shown) via the printed board 14.

As shown in FIG. 4, on the first electrode pad 11a, for example, a rectangular bonding material arrangement region 30 in which solder as a bonding material is arranged around the plurality of first conductive posts 18a is formed. A heat-resistant insulating resin layer 31 having a height and a width capable of suppressing the spreading of the solder is formed around the arrangement region. Here, as shown in FIG. 5, the heat-resistant insulating resin layer 31 is formed relatively wide at the peripheral portion of the metal film 11e that improves the wettability of the solder so as to overcoat the peripheral portion. In addition, between the adjacent bonding material arrangement regions 30, for example, the width is about 100 μm, the side surface is inclined about 15 degrees with respect to the vertical surface, and the height is about 5 μm.
The heat-resistant insulating resin layer 31 is formed by forming polyimide resin (PI) on the front surfaces of the semiconductor chips 11A and 11B by a drawing process using an inkjet printer.

  As shown in FIG. 6, in order to form the heat-resistant insulating resin layer 31 by a drawing process using an ink jet printer, first, a wafer surface process is performed in which the wafer front surfaces of the semiconductor chips 11A and 11B are cleaned and then dried. Perform (step S1). Next, the polyimide resin is drawn around the bonding material arrangement region 30 using an ink jet printer (step S2). Next, pre-baking is performed (step S3), and finally a final cure is performed to form the heat resistant insulating resin layer 31 (step S4). In this drawing process, the time required to form the heat-resistant insulating resin layer 31 is about 10 hours, and the formation time of the heat-resistant insulating resin layer 31 can be shortened.

According to the drawing process using this ink jet printer, the mountain-shaped heat-resistant insulating resin layer 31 can be easily and reliably formed in a short time.
The formation of the heat resistant insulating resin layer 31 is not limited to the drawing process using the ink jet printer of FIG. 6, but the time required for forming the heat resistant insulating resin layer 31 is lengthened. The heat resistant insulating resin layer 31 may be formed by photolithography shown in FIG.

  That is, in the photolithography process, first, the wafer front surfaces of the semiconductor chips 11A and 11B are cleaned and then dried (step S11). Next, a polyimide resin is applied to the entire area of the wafer front surface of the semiconductor chips 11A and 11B and then prebaked (step S12). Next, a resist is applied on the pre-baked polyimide resin and then pre-baked (step S13). Next, the pre-baked resist is exposed (step S14). Next, the exposed resist is developed to remove an unnecessary polyimide resin layer, and then prebaked (step S15). Next, post-baking is performed (step S16), and then the resist is peeled off (step S17). Finally, final curing is performed to form the heat-resistant insulating resin layer 31 (step S18). In this photolithography process, it takes about 19 hours to form the heat resistant insulating resin layer 31.

In this way, after the heat-resistant insulating resin layer 31 is formed around the bonding material arrangement region 30 for bonding the conductive posts 18a in the first electrode pads 11a of the semiconductor chips 11A and 11B, the bonding material is formed in the bonding material arrangement region 30. For example, lead-free solder is applied, and the first conductive post 18a is erected on the lead-free solder. Similarly, for example, lead-free solder as a bonding material is applied to the bonding material arrangement region 32 for bonding the conductive post 18b in the second electrode pad 11b, and the second conductive post is erected on the lead-free solder. To do.
In this state, the conductive posts 18a and 18b can be joined to the first electrode pad 11a and the second electrode pad 11b by performing a reflow process at about 280 ° C., for example.

  Each component of the power semiconductor module 10 is molded and protected by a resin sealing material 24 made of, for example, an epoxy resin material of a thermosetting resin. As a result, the outer shape of the power semiconductor module 10 is formed as a rectangular parallelepiped molded body 25 having a rectangular shape in plan view as a whole. At this time, the lower surface of the copper plate 16b on the back surface side of the insulating substrate 12 protrudes slightly from the bottom surface of the molded body 25 or slightly from the bottom surface.

Next, a method for manufacturing the power semiconductor module of the present embodiment having the above configuration will be described with reference to FIG. The first electrode pad 11a and the second electrode pad 11b are not shown in FIG. 8, but are described in the following text.
First, as shown in FIG. 8A, the semiconductor chips 11A and 11B are mounted on the copper plate 16a of the insulating substrate 12 by the bonding material 17 such as solder.

Next, as illustrated in FIG. 8B, in the semiconductor chips 11 </ b> A and 11 </ b> B mounted on the insulating substrate 12, the bonding material 21 is disposed in the bonding material arrangement region 30 surrounded by the heat-resistant insulating resin layer 31 in the first electrode pad 11 a. And the bonding material 21 is applied to the bonding material arrangement region 32 of the second electrode pad 11b.
For example, when using paste-like solder (joining material) 21 for liquid phase joining as the joining material 21, the paste-like solder (joining material) 21 is partially applied using a dispenser or the like. The amount of paste solder 21 applied is the volume corresponding to a predetermined solder thickness after the first conductive post 18a and the second conductive post 18b are bonded onto the first electrode pad 11a and the second electrode pad 11b, respectively. Apply so that

As a solder used for manufacturing a semiconductor device using a wide band gap (WBG) device, a high temperature lead-free solder is used in order to cope with a high temperature operation of the wide band gap (WBG) device. Specifically, SnAg solder such as SnAgCuNiGe solder, Sn3.5% Ag solder, SnSb solder such as Sn5% Sb solder, SnAgCu solder, SnAgBi solder, SnCuBi solder, SnCu solder, SnAu solder , AuSi solder, AgSi solder, AgGe solder, and the like.
As a feature of these high-temperature lead-free solders, there is a concern about the decrease in wettability. However, the wettability exceeding the heat-resistant insulating resin layer 31 can be achieved by arranging in the bonding material arrangement region 30 surrounded by the heat-resistant insulating resin layer 31. Spreading can be prevented.

Next, as shown in FIG. 8C, a pin-like conductor (pin terminal) 20 as an external connection terminal (collector terminal C1) is fitted into the fitting hole 22 formed in the copper plate 16a of the insulating substrate 12. Let Next, the pin-like conductor 20 is inserted into the through hole 14a formed in the printed board 14, and the printed board 14 is lowered from above the semiconductor chips 11A and 11B using the pin-like conductor 20 as a guide.
Then, the first conductive post 18a and the second conductive post 18b fixed to the printed circuit board 14 are introduced into a reflow furnace while being in contact with the paste-like solder 21, and are subjected to a reflow process. Accordingly, the first conductive post 18a and the second conductive post 18b are joined to the first electrode pad 11a and the second electrode pad 11b, respectively.

At this time, the solder is melted by the reflow process, but since the periphery of the solder is surrounded by the heat-resistant insulating resin layer 31, the molten solder exceeds the heat-resistant insulating resin layer 31 and is adjacent to the bonding material. Movement between the placement areas 30 and 32 is reliably prevented. For this reason, a fillet generated by wetting during soldering between the first conductive post 18a joined to the first electrode pad 11a and the second conductive post 18b adjacent to the first conductive post 18a. Can be prevented from being connected to each other. Therefore, it is possible to reliably prevent the fillet formed on the first conductive post 18a and the fillet formed on the second conductive post 18b closest to the first conductive pad 18a from being in a bridge state. The short circuit between 11a and the 2nd electrode pad 11b can be prevented reliably.
Thereafter, the bonded insulating substrate 12, semiconductor chips 11A and 11B, and printed circuit board 14 are molded by a resin sealing material 24 made of an epoxy resin material of a thermosetting resin, and the power semiconductor module 10 as a semiconductor device is formed. It is formed.

As described above, according to the first embodiment, when the plurality of electrode pads 11a and 11b are formed on one surface of the semiconductor chips 11A and 11B, the first conductive posts 18a are joined to each other. A heat resistant insulating resin layer 31 is formed around a bonding material arrangement region 30 where a bonding material formed around the electrode pad 11a is arranged. Therefore, when a bonding material made of solder is applied to the bonding material arrangement region 30 surrounded by the heat-resistant insulating resin layer 31, and the reflow process is performed in a state where the first conductive post 18a is arranged in the bonding material. Further, it is possible to reliably suppress the molten bonding material from spreading over the heat-resistant insulating resin layer 31. Therefore, it is possible to reliably prevent the solder fillet from being bridged between the first conductive post 18a and the second conductive post 18b.
Further, since the heat-resistant insulating resin layer 31 is overcoated over the periphery of the metal film 11e at the periphery of the metal film 11e on the front surface side that forms the first electrode pad 11a, it is in close contact with the electrode film 11d. It is possible to prevent the peripheral edge of the metal film 11e having unstable properties from being peeled off and the occurrence of cracks.

Therefore, it is possible to surely prevent a bridge from being formed due to the coupling of the fillet between the first conductive post 18a and the second conductive post 18b, and a short circuit between the electrode pad 11a and the electrode pad 11b. Can be reliably prevented, and the occurrence of poor connection can be avoided. Thereby, the mounting quality of each semiconductor chip of the power semiconductor module 10 can be improved, and the reliability of the power semiconductor module 10 can be ensured.
In the first embodiment, the case where the heat-resistant insulating resin layer 31 is formed so as to surround the bonding material arrangement region 30 for bonding the conductive post 18a in the first electrode pad 11a has been described. However, the present invention is not limited to this, and the heat-resistant insulating resin layer 31 may be disposed so as to surround the periphery of the bonding material arrangement region 32 to be bonded to the second conductive post 18b in the second electrode pad 11b.

  In the first embodiment, the electrode pads 11a and 11b of the semiconductor chips 11A and 11B and the first conductive posts 18a and the second conductive posts 18b fixed to the printed circuit board 14 are soldered, respectively. Although described, there is nothing limited thereto. That is, a solid phase diffusion bonding material using metal particles typified by nano Ag instead of solder can be used as the bonding material.

  As described above, when a solid phase diffusion bonding material is applied as the bonding material, as shown in FIG. 9, for example, a circular shape for bonding the first conductive post 18a and the second conductive post 18b of the semiconductor chips 11A and 11B. The heat-resistant insulating resin layer 31 is formed around the bonding material arrangement regions 30 and 32, and the solid-phase diffusion bonding material is partially applied to the bonding material arrangement regions 30 and 32 surrounded by the heat-resistant insulating resin layer 31 by a dispenser or the like. Apply. Then, the first conductive post 18a and the second conductive post 18b fixed to the printed circuit board 14 are brought into contact with each other on the solid phase diffusion bonding material by heating and pressurizing. The second conductive post 18b is electrically and mechanically bonded to the electrode pads 11a and 11b via a solid phase diffusion bonding material.

  Thus, also in the manufacturing method of the power semiconductor module 10 using the solid phase diffusion bonding material, the heat-resistant insulating resin layer 31 is formed on the semiconductor chips 11A and 11B. For this reason, when the solid phase diffusion bonding material spreads in a horizontal plane by a process such as pressure heating bonding, the solid phase diffusion bonding material applied on different electrode pads on the respective semiconductor chips 11A and 11B may come into contact. In addition, connection failure due to a short circuit of the bonding material can be avoided.

Next, a second embodiment of the present invention will be described with reference to FIG.
In the second embodiment, the first electrode pad 11a that joins the plurality of first conductive posts 18a is formed with a short-circuit prevention region that prevents a short circuit between the joining materials between the second conductive posts 18b. It is a thing.
That is, in the second embodiment, as shown in FIG. 10, the first electrode pad 11a of each of the semiconductor chips 11A and 11B is in a region near the second conductive post 18b joined to the second electrode pad 11b. For example, the short-circuit prevention region As for prohibiting the joining of the semicircular conductive post centered on the center of the second conductive post 18b in the state where the second conductive post 18b is joined to the center of the second electrode pad 11b is provided. Is set.

  The short-circuit prevention region As is a fillet for the first conductive post 18a and the second conductive post 18b adjacent to each other when the first conductive post 18a and the second conductive post 18b are joined by, for example, solder as a bonding material. Is formed in a semicircular shape having a radius equal to or larger than a radius that can prevent the two fillets from being combined with each other to form a bridge. Preferably, the relative positional deviation in the horizontal plane between the installation position of the semiconductor chips 11A and 11B on the copper plate 16a of the insulating substrate 12 and the installation position of the printed board 14 having the first conductive post 18a and the second conductive post 18b. Is set to a radius at which the fillets formed on the second conductive post 18b and the first conductive post 18a closest to the second conductive post 18b are not coupled to each other. Yes.

Accordingly, the first conductive posts 18a fixed to the printed circuit board 14 are arranged outside the short-circuit prevention area As of the semiconductor chips 11A and 11B of the first electrode pad 11a and along the peripheral edge of the first electrode pad 11a. As described above, the printed circuit board 14 is positioned and fixed by a joining member such as solder.
That is, as shown in FIG. 10, the first conductive post 18a is joined to the first electrode pad 11a so that the central portion and the second electrode pad 11b are opened. Are arranged and fixed to the printed circuit board 14 in a reversed U shape, for example, when viewed from above.

Then, the heat-resistant insulating resin layer 31 is formed on the entire front surface of the semiconductor chips 11A and 11B except for the bonding material arrangement region 30 of each first conductive post 18a and the bonding material arrangement region 32 of the second conductive post 18b. Has been.
According to the second embodiment, the entire front surface of the semiconductor chips 11A and 11B is heat resistant except for the bonding material arrangement regions 30 and 32 around the first conductive post 18a and the second conductive post 18b. Since it is covered with the insulating resin layer 31, the same short-circuit prevention effect as that in the first embodiment described above can be obtained.

  Furthermore, in the second embodiment, a short-circuit prevention region As is set in the first electrode pad 11a, and the first conductive post 18a is not disposed in the short-circuit prevention region As. For this reason, when the first conductive post 18a and the second conductive post 18b are soldered to the electrode pads 11a and 11b, the first conductive post 18a and the second conductive post 18b adjacent thereto are interposed. Sufficient intervals can be ensured so that the fillets formed during soldering are not coupled.

  Accordingly, the first conductive post 18a of the first electrode pad 11a is formed around the first conductive post 18a and the second conductive post 18b closest to the second conductive post 18b of the second electrode pad 11b. Even when the bonding material arranged in the bonding material arrangement regions 30 and 32 surrounded by the heat-resistant insulating resin layer 31 climbs over the heat-resistant insulating resin layer 31, the first conductive post 18a and the second conductive post 18b Thus, it is possible to reliably prevent the fillet from being bonded to each other to form a bridge state. For this reason, the short circuit between the 1st electrode pad 11a and the 2nd electrode pad 11b can be prevented reliably, and generation | occurrence | production of a connection failure can be avoided. Thereby, the mounting quality of each semiconductor chip of the power semiconductor module 10 can be improved, and the reliability of the power semiconductor module 10 can be ensured.

In addition, since the number of the second conductive posts 18b in the peripheral portion is set larger than the number of the second conductive posts in the central portion, the central portion of the semiconductor chip that is easily affected by heat in the power cycle reliability test. Deterioration due to cracks or the like can be avoided, and a long-life power semiconductor module can be provided.
In the second embodiment, the case where the first conductive posts 18a are arranged in a U-shape has been described. However, the present invention is not limited to this, and the first conductive post 18a is outside the short-circuit prevention region As. The conductive posts 18a can be arbitrarily arranged.

Moreover, in the said 1st Embodiment and 2nd Embodiment, although the case where the joining material arrangement | positioning area | regions 30 and 32 formed in the circumference | surroundings of an electroconductive post was made into square or circular was demonstrated, it is limited to these Instead, the bonding material arrangement region can be formed in an arbitrary shape such as a triangle, a pentagon or more polygon, or an ellipse.
In the first and second embodiments, the case where the insulating substrate 12 and the printed circuit board 14 on which the semiconductor chips 11A and 11B are mounted is molded with the resin sealing material 24 has been described. However, the present invention is not limited to the above configuration, and can also be applied to the power semiconductor module 44 having the configuration shown in FIG.

  That is, in the power semiconductor module 44, the insulating substrate 12 on which the semiconductor chips 11A and 11B are mounted is disposed on the metallic heat dissipation base 41, and the first conductive posts 18a formed on the semiconductor chips 11A and 11B and the printed circuit board 14 and The second conductive post 18 b is electrically joined by solder 19. In this joined state, the power semiconductor module 44 is formed by covering the outside with a resin case 42 and filling the resin case 42 with a gel insulating sealing material 43.

DESCRIPTION OF SYMBOLS 10 ... Power semiconductor module 11A, 11B ... Semiconductor chip 11a ... 1st electrode pad 11b ... 2nd electrode pad 11c ... 3rd electrode pad 12 ... Insulating substrate 14 ... Printed circuit board 14a ... Through-hole 15 ... Ceramic substrate 16a, 16b ... Copper plate 17 ... Solder (joining material)
18a ... 1st conductive post 18b ... 2nd conductive post 19 ... Solder (joining material)
20 ... Pin-shaped conductor 21 ... Paste solder (joining material)
22 ... fitting hole 24 ... resin sealing material 25 ... molded product 30, 32 ... bonding material arrangement region 31 ... heat resistant insulating resin layer 41 ... heat dissipation base 42 ... resin case 43 ... gel-like insulating sealing material 44 ... power Semiconductor module As ... short-circuit prevention region Q1 ... first transistor D1 ... first diode Q2 ... second transistor D2 ... second diode C1 ... first collector terminal G1 ... first gate terminal G2 ... second gate terminal C2 / E1 ... intermediate Terminal E2 ... Second emitter terminal

Claims (6)

An insulating substrate;
A semiconductor chip disposed on one surface of the insulating substrate;
An electrode pad provided on a surface of the semiconductor chip opposite to the insulating substrate;
A plurality of conductive posts having one end bonded to the electrode pad with a bonding material;
A printed circuit board formed with an electrical wiring portion disposed opposite to one surface of the semiconductor chip and joined to the other end of each conductive post;
A semiconductor device, wherein a heat-resistant insulating resin layer is formed around a bonding material arrangement region of the conductive post in the semiconductor chip. The electrode pad includes a first electrode pad to which a first conductive post that is separated from each other is bonded and a second electrode pad to which a second conductive post is bonded.
The semiconductor device according to claim 1, wherein the heat-resistant insulating resin layer is formed around the bonding material arrangement region in one of the first electrode pad and the second electrode pad.   The second conductive post adjacent to the first conductive post avoids a short-circuit prevention region at a distance where the bonding material of the first conductive post and the bonding material of the second conductive post are not coupled. The semiconductor device according to claim 2, wherein the heat-resistant insulating resin layer is formed in a region that is arranged and includes the short-circuit prevention region of the semiconductor chip and excludes the bonding material arrangement region.   The semiconductor device according to claim 1, wherein the heat-resistant insulating resin layer is formed of a polyimide resin.   The semiconductor device according to claim 4, wherein the heat-resistant insulating resin layer is formed of a polyimide resin by a photolithography process.   5. The semiconductor device according to claim 4, wherein the heat-resistant insulating resin layer is formed by printing a polyimide resin around a bonding material arrangement region with an ink jet printer and performing a final cure after pre-baking.

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