JP7025181B2 - Power modules and their manufacturing methods, graphite plates, and power supplies - Google Patents

Description

The present embodiment relates to a power module and its manufacturing method, a graphite plate, and a power supply device.

As one of the power modules, a power module in which the outer periphery of a semiconductor device including a power element (chip) such as an insulated gate bipolar transistor (IGBT) is molded with a resin has been conventionally known. ..

Since the semiconductor device generates heat in the operating state, it is common to dissipate heat by arranging a radiator such as a heat sink or fins on the back surface side of the substrate to cool the semiconductor device.

In particular, in recent years, thick copper substrates and double-sided cooling structures have also been used in order to reduce thermal resistance.

However, there is a concern about reliability in thickening the substrate, and although the double-sided cooling structure is excellent in cooling performance, it is more expensive to manufacture than the single-sided cooling structure from the viewpoint of productivity.

Under such circumstances, the possibility of applying graphite plates with anisotropic thermal conductivity to power modules is being investigated.

In addition, since semiconductor devices generate heat during operation, it is important to ensure the reliability of wire connection against high temperatures, especially in inverter modules for high temperature operation.

Furthermore, an insulating substrate is used as the substrate used for the power module. Thick copper substrates and the like have been developed for further lowering the thermal resistance. However, there is a concern about reliability in thickening the substrate, and although the double-sided cooling structure is excellent in cooling performance, it is more expensive to manufacture than the single-sided cooling structure from the viewpoint of productivity.

In order to further reduce the thermal resistance of this thick copper substrate, the possibility of applying a graphite plate having an anisotropic thermal conductivity to a power module is being investigated.

Furthermore, in recent years, with the spread of hybrid vehicles and EVs (Electric Cars), the demand for power modules has also increased. Since the power module generates heat in the operating state, a water cooling system is used in the power module used in the vehicle. Currently, a single-sided water cooling system is generally used, but a double-sided water cooling system has been developed in order to further reduce the thermal resistance. Meanwhile, the possibility of applying graphite plates with anisotropic thermal conductivity to power modules is also being investigated.

Japanese Unexamined Patent Publication No. 2007-019130 Japanese Unexamined Patent Publication No. 2005-210035 Japanese Unexamined Patent Publication No. 2013-118336 Japanese Unexamined Patent Publication No. 2016-4996 International Publication No. 2015/076257

Yasushi Yamada, Atsushi Kuno, Seito Sawaki, Yasunori Narita, Katsuhiro Takema, "Applicability of Carbon-based Heterogeneous Heat Transfer Materials to Power Semiconductor Modules" Bulletin of Daido University Vol. 50 (2014) pp. 133-pp. 135

However, the double-sided water cooling system requires two water cooling machines, and it is difficult to design the flow path. Moreover, it is difficult to reduce the cost because the water cooler is expensive.

In addition, when a large current is passed through an inverter module using a SiC MOSFET (Silicon Carbide Metal Oxide Semiconductor Field Effect Transistor), heat is generated by the current flowing through the FET, and the source pad electrode is used to directly input the control signal. The bonding portion of the source sense wire bonded above was also hot.

Therefore, the bonding portion of the source sense wire becomes hot to the same extent as the junction temperature, so that the wire is liable to break in the conventional case type power module in which the particle size of the wire tends to be coarse.

On the other hand, in the case of a mold type power module, the grain size of the wire is unlikely to be coarsened, but there is a concern that the wire may break at the interface due to thermal stress.

In both cases, the deterioration was caused by heat, and it was necessary to take measures for wire connection to increase the heat resistance.

This embodiment provides a power module that is inexpensive, can exhibit cooling performance comparable to that of a double-sided cooling structure, and can reduce stress.

Further, the present embodiment provides an inexpensive power module and a graphite plate having a cooling capacity close to that of double-sided cooling in one cooler.

Further, the present embodiment provides a power module and a method for manufacturing the same, which can reduce the influence of heat due to high temperature operation, increase the heat resistance to wire connection, and improve the reliability.

Furthermore, the present embodiment provides a power module and a power supply device capable of reducing thermal resistance.

According to one aspect of the present embodiment, an insulating substrate, a power device arranged on the insulating substrate and having electrodes on the front surface side and the back surface side thereof, and one end thereof are connected to the front surface side of the power device. The other end is provided with an anisotropic thermal conductivity connected to the insulating substrate, and is provided with a graphite wiring having a second orientation in which the thermal conductivity is higher in the thickness direction than in the surface direction, and is provided on the surface side of the power device. A power module is provided that transfers heat to the insulating substrate via the graphite wiring.

According to another aspect of the present embodiment, the insulating substrate, the first electrode pattern and the second electrode pattern arranged on the first surface of the substrate, and the second surface facing the first surface. An insulating substrate having an arranged third electrode pattern, a power device arranged on the first electrode pattern and having electrodes on the front surface side and the back surface side thereof, and heat dissipation arranged on the third electrode pattern. A device, a block electrode arranged on the second electrode pattern, a graphite wiring having an anisotropic thermal conductivity, a first wiring pattern arranged on the first main surface of the graphite wiring, and the first one. A second wiring pattern arranged on a second main surface facing the main surface is provided, one end side is connected to the front surface side of the power device, and the other end side at a position separated from the one end side on the same plane is. The graphite wiring includes a wiring lead portion connected to the second electrode pattern via the block electrode, and the graphite wiring has a second orientation having a higher thermal conductivity in the thickness direction than in the plane direction, and the second orientation . Provided is a power module having a plate structure in which a plurality of graphite sheets having the above-mentioned orientation are laminated, and transferring heat on the surface side of the power device to the insulating substrate via the graphite wiring.

According to another aspect of the present embodiment, the insulating substrate, the first electrode pattern and the second electrode pattern arranged on the first surface of the substrate, and the second surface facing the first surface. An insulating substrate having an arranged third electrode pattern, a power device arranged on the first electrode pattern and having electrodes on the front surface side and the back surface side thereof, and heat dissipation arranged on the third electrode pattern. A device, a graphite wiring having an anisotropic thermal conductivity, and an arrangement on the first main surface of the graphite wiring, one end side of which is connected to the surface side of the power device and in the same plane as the one end side. The graphite wiring is provided with a wiring lead portion having a first wiring pattern having an L-shaped cross-sectional shape in which the thickness of the wiring pattern is partially different so that the other end side at a distant position is connected to the second electrode pattern. Has a second orientation having a higher thermal conductivity in the thickness direction than in the plane direction, and has a plate structure in which a plurality of graphite sheets having the second orientation are laminated, and is provided on the surface side of the power device. A power module is provided that transfers heat to the insulating substrate via the graphite wiring.

According to another aspect of the present embodiment, an insulating substrate, a graphite substrate having anisotropy in thermal expansion coefficient arranged on the substrate, and a surface side thereof arranged on the graphite substrate. A power device having an electrode on the back surface side and a graphite wiring having an anisotropic thermal conductivity connected to the front surface side of the power device are provided, and heat on the front surface side of the power device is transferred through the graphite wiring. A power module that transmits to the substrate is provided.

According to another aspect of the present embodiment, the graphite insulating substrate including the insulating substrate, the graphite substrate having an anisotropic heat expansion coefficient arranged on the substrate, and the graphite insulating substrate. A power device arranged and having electrodes on the front surface side and the back surface side thereof, and a graphite wiring having an anisotropic thermal conductivity connected to the front surface side of the power device, the surface side of the power device. A power module is provided that transfers heat to the substrate via the graphite wiring.

According to another aspect of the present embodiment, a substrate which is connected in series between a first power supply terminal and a second power supply terminal and has a first surface and a second surface facing the first surface. It has a power device arranged on the first surface and a cooler arranged on the second surface side of the substrate, and is configured to connect a connection point of the power device to an output terminal. A power module, the power device having a first surface and a second surface facing the first surface, the second surface side of the substrate of the cooler and the second surface of the power device. A power module is provided that includes a graphite plate that thermally connects to the surface side, and the graphite plate has a structure in which two types of graphite plates having different thermal conduction orientations are bonded together in a direction having a high thermal conductivity.

According to another aspect of this embodiment, a graphite plate included in the power module is provided.

According to another aspect of the present embodiment, a substrate having a first main electrode pattern and a signal wiring pattern, a semiconductor device having a main pad electrode on the surface and arranged on the substrate, and the main pad electrode. The lead frame connected between the lead frame and the first main electrode pattern, and the first junction between the lead frame and the main pad electrode are separated from each other, and the lead frame and the first main electrode pattern are separated from each other. A first bonding wire connected between a junction and the second junction and the signal wiring pattern , one end of which is connected to the signal wiring pattern and the other end of the lead of the second junction. The second bonding portion includes a first bonding wire connected to the frame, and the second bonding portion is provided with a power module whose temperature during operation of the semiconductor device is relatively lower than that of the first bonding portion.

According to another aspect of the present embodiment, an insulating substrate including an insulating substrate and a first main electrode pattern, a second main electrode pattern, a signal wiring pattern, and a control signal wiring pattern arranged on the substrate. A semiconductor device having a main pad electrode and a control pad electrode on the front surface side and a main electrode on the back surface side and arranged face-up on the second main electrode pattern, and the main pad electrode and the first. The lead frame connected between the 1 main electrode pattern and the first joint portion between the lead frame and the main pad electrode are separated from each other, and the temperature during operation of the semiconductor device is relative to that of the first joint portion. Between the second bonding portion between the lead frame and the first main electrode pattern, the first bonding wire connected between the signal wiring pattern, and the control pad electrode and the control signal wiring pattern. The first bonding wire is connected to the signal wiring pattern at one end and the first main electrode pattern at the second bonding portion at the other end. A power module is provided.

According to another aspect of the present embodiment, the insulating substrate and the first main electrode pattern, the second main electrode pattern, the signal wiring pattern, the control signal wiring pattern, and the wiring electrode pattern arranged on the substrate. A semiconductor device having a main pad electrode and a control pad electrode on the front surface thereof, and having a main electrode on the back surface and arranged face-up on the second main electrode pattern, and the main pad electrode. And the lead frame connected between the first main electrode pattern and the connection end side with the main pad electrode extended and connected to the wiring electrode pattern, and the lead frame and the main pad electrode. A second junction between the lead frame and the first main electrode pattern, which is separated from the first junction and whose temperature during operation of the semiconductor device is relatively lower than that of the first junction. A third junction between the lead frame and the wiring electrode pattern, which has a relatively lower temperature during operation of the semiconductor device than the first junction, and one end thereof are connected to the signal wiring pattern and other. A first bonding wire whose end is connected to the third bonding portion and a second bonding wire connected between the control pad electrode and the control signal wiring pattern are provided, and the other end of the first bonding wire is provided. However, a power module connected to the lead frame of the third joint or the connection electrode pattern is provided.

According to another aspect of the present embodiment, a conductive substrate, a main electrode pattern, a signal wiring pattern and a control signal wiring pattern arranged on the substrate via an insulating layer, and a main pad electrode on the surface thereof. A semiconductor device arranged on the substrate, a lead frame connected between the main pad electrode and the main electrode pattern, and a first joint portion between the lead frame and the main pad electrode. A second bonded portion between the lead frame and the main electrode pattern, which is separated and whose temperature during operation of the semiconductor device is relatively lower than that of the first bonding portion, and the signal wiring pattern. A power module comprising one bonding wire is provided.

According to another aspect of the present embodiment, an insulating substrate having an insulating substrate and a first main electrode pattern, a second main electrode pattern, a signal wiring pattern, and a control signal wiring pattern arranged on the substrate. A step of arranging a semiconductor device having a main pad electrode and a control pad electrode on the front surface side and having a main electrode on the back surface side face-up on the second main electrode pattern, and the main pad electrode and the first. The step of connecting the lead frame to the main electrode pattern and the first junction between the lead frame and the main pad electrode are separated from each other, and the temperature at the time of operation of the semiconductor device is relative to that of the first junction. In the step of connecting the first bonding wire between the second joint portion between the lead frame and the first main electrode pattern, which is relatively low, and the signal wiring pattern, one end of the first bonding wire is connected. The step of connecting to the signal wiring pattern and connecting the other end of the first bonding wire to the lead frame of the second bonding portion, and the second bonding wire between the control pad electrode and the control signal wiring pattern. A method of manufacturing a power module having a step of connecting the electrodes is provided.

According to another aspect of the present embodiment, a substrate, a graphite substrate having an anisotropic thermal conductivity arranged on the first surface of the substrate, and a second surface facing the first surface of the substrate. A plurality of semiconductors arranged side by side on the graphite substrate via the first electrode pattern arranged on the surface, the second electrode pattern arranged on the graphite substrate, and the second electrode pattern, and generate heat during operation. The graphite substrate is provided with a device, and the graphite substrate has an orientation in which the thermal conductivity is relatively higher in the thickness direction than in the plane direction, and the direction in which the plurality of semiconductor devices are arranged on the substrate surface of the graphite substrate is the graphite. A power module having a temperature of −45 degrees or more and +45 degrees or less based on an orientation direction in which the thermal conductivity of the substrate is relatively low is provided.

According to another aspect of the present embodiment, an insulating layer, a graphite substrate arranged on the insulating layer and having an anisotropic thermal conductivity, and a semiconductor arranged on the graphite substrate and generating heat during operation. The graphite substrate is provided with a device, and the graphite substrate is provided with a power module having a surface electrode layer of the graphite substrate on the surface thereof.

According to another aspect of the present embodiment, the first switching device and the second switching device are connected in series between the first power supply and the second power supply, and the voltage at the connection point is output. Each of the switching devices is composed of a plurality of chips and is arranged side by side on a graphite substrate. The distance between the chips in the arrangement direction of the plurality of chips is the distance between the chips and the graphite substrate. A power supply device that is shorter than the respective distances to both end faces in the longitudinal direction of the power supply is provided.

According to the present embodiment, it is possible to provide a power module that is inexpensive, can exhibit cooling performance comparable to that of a double-sided cooling structure, and can reduce stress.

Further, according to the present embodiment, it is possible to provide an inexpensive power module and a graphite plate having a cooling capacity close to that of double-sided cooling with one cooler.

Further, according to the present embodiment, it is possible to provide a power module capable of reducing the influence of heat due to high temperature operation, increasing heat resistance to wire connection, and improving reliability, and a method for manufacturing the power module.

Furthermore, according to the present embodiment, it is possible to provide a power module and a power supply device capable of reducing thermal resistance.

(A) Schematic plane pattern configuration diagram showing a schematic configuration of the power module according to the first embodiment, (b) Schematic cross-sectional structure diagram along the line II of FIG. 1 (a). The schematic cross-sectional structure diagram which shows the schematic structure of the power module which concerns on the comparative example 1 in 1st Embodiment. The schematic cross-sectional structure diagram which shows the schematic structure of the power module which concerns on the comparative example 2 in 1st Embodiment. The thermal resistance characteristics of the power module (PM1) according to the first embodiment are compared with Comparative Example 1 (PM11) in the first embodiment and Comparative Example 2 (PM12) in the first embodiment. The figure which shows. FIG. 3 is a schematic bird's-eye view configuration diagram of a laminated structure of graphite sheets constituting a graphite plate applicable to the power module according to the first embodiment. An example of a graphite plate applicable to the power module according to the first embodiment is a schematic bird's-eye view configuration diagram illustrating (a) an XY-oriented graphite plate, and (b) an XZ-oriented graphite plate. Schematic bird's-eye view configuration diagram. (A) Schematic plane pattern configuration diagram showing a schematic configuration of the power module according to the second embodiment, (b) Schematic cross-sectional structure diagram along line II-II of FIG. 7 (a). A schematic bird's-eye view configuration diagram showing a schematic configuration of a power module according to a second embodiment. (A) Schematic bird's-eye view configuration diagram, (b) Schematic front configuration diagram of the upper wiring provided with the graphite plate applied to the power module according to the second embodiment. A schematic bird's-eye view configuration diagram showing a schematic configuration of a power module according to a modified example of the second embodiment. (A) Schematic plane pattern configuration diagram showing a schematic configuration of a power module according to a third embodiment, (b) Schematic cross-sectional structure diagram along lines III-III of FIG. 11 (a). (A) Schematic bird's-eye view configuration diagram, (b) Schematic front configuration diagram of the upper wiring provided with the graphite plate applied to the power module according to the third embodiment. (A) Schematic plane pattern configuration diagram showing a schematic configuration of the power module according to the fourth embodiment, (b) Schematic cross-sectional structure diagram along the IV-IV line of FIG. 13 (a). Taking the power module according to the fourth embodiment as an example, (a) a characteristic diagram for explaining the relationship between the width of the upper wiring and the thermal resistance (No. 1), (b) the width and the thermal resistance of the upper wiring. Characteristic diagram for explaining the relationship (No. 2). Taking the power module according to the fourth embodiment as an example, (a) a characteristic diagram for explaining the relationship between the thickness of the upper wiring and the thermal resistance (No. 1), (b) the thickness and the thermal resistance of the upper wiring. (Part 2), (c) A characteristic diagram for explaining the relationship between the thickness of the upper wiring and the thermal resistance (No. 3). (A) A schematic cross-sectional structure diagram showing a stress relaxation structure of a power module according to a fifth embodiment, and (b) an enlarged view showing an enlarged portion of display A in FIG. 16 (a). FIG. 5 is a characteristic diagram for explaining a stress relaxation structure by taking the power module according to the fifth embodiment as an example. (A) Schematic plane pattern configuration diagram showing a schematic configuration of the power module according to the sixth embodiment, (b) Schematic cross-sectional structure diagram along the VV line of FIG. 18 (a). In the power module according to the embodiment, (a) a schematic plan plan configuration diagram illustrating the arrangement direction of the graphite substrate and the IGBT, taking as an example a case where a graphite substrate having anisotropy in the coefficient of thermal expansion is applied, ( b) Schematic plane pattern configuration diagram illustrating the arrangement direction of the graphite substrate and the SiC MOSFET. (A) Schematic plane pattern configuration of (a) simulation model MD for simulating the stress applied to the joint when a graphite substrate having anisotropy in the coefficient of thermal expansion is applied to the power module according to the embodiment. FIG. (B) is a schematic cross-sectional structure diagram along the VI-VI line of FIG. 20 (a). In the simulation model shown in FIG. 20, the figure which shows an example of the thickness of each part which has the lowest thermal resistance. The figure which shows the result (the whole warping shape) at the time of performing the simulation about the stress applied to the joint part using the simulation model shown in FIG. (A) for performing simulation by changing the shape of the device (simulation models MD1 to MD5), taking as an example a case where a graphite substrate having an anisotropic thermal expansion coefficient is applied to the power module according to the embodiment. Schematic planar pattern configuration diagram of simulation model MD2, (b) Schematic planar pattern configuration diagram of simulation model MD3, (c) Schematic planar pattern configuration diagram of simulation model MD4, (d) Schematic planar pattern of simulation model MD5 Diagram. (A) Edge when simulation is performed by changing the shape of the device (simulation models MD1 to MD5) in the case of applying a graphite substrate having anisotropy in the coefficient of thermal expansion in the power module according to the embodiment. A characteristic diagram for explaining the relationship between the distance (Y) from and the Mieses stress, and (b) a characteristic diagram for explaining the relationship between the simulation model MD and the Mieses stress ratio. (A) Schematic plane pattern configuration of simulation model MD1 for simulating the stress applied to the joint when a graphite substrate having anisotropy in the coefficient of thermal expansion is applied to the power module according to the embodiment. FIG. (B) is a schematic cross-sectional structure diagram along the line VII-VII of FIG. 25 (a). (A) Edge when simulation is performed by changing the shape of the device (simulation models MD1 to MD3) in the case where a graphite substrate having anisotropy in the thermal expansion coefficient is applied in the power module according to the embodiment. A characteristic diagram for explaining the relationship between the distance (X) from and the Mises stress, and (b) a characteristic diagram for explaining the relationship between the simulation model MD and the Mises stress ratio. A diagram showing the results of (a) simulation using the simulation model MD1 as an example in the case where a graphite substrate having anisotropy in the coefficient of thermal expansion is applied to the power module according to the embodiment, (b). ) A diagram showing the results when simulation is performed using the simulation model MD2, and (c) a diagram showing the results when simulation is performed using the simulation model MD3. FIG. 6 is a schematic circuit representation diagram of a SiC MOSFET of a one-in-one (1 in 1) module, which is a power module according to an embodiment. FIG. 6 is a detailed circuit representation diagram of a 1 in 1 module SiC MOSFET, which is a power module according to an embodiment. FIG. 6 is a schematic circuit representation diagram of a SiC MOSFET of a two-in-one (2 in 1) module, which is a power module according to an embodiment. FIG. 6 is a schematic cross-sectional structural view of a SiC MOSFET including a source pad electrode SP and a gate pad electrode GP, which is an example of a semiconductor device applicable to the power module according to the embodiment. FIG. 6 is a schematic cross-sectional structural view of an IGBT, which is an example of a semiconductor device applicable to a power module according to an embodiment, and includes an emitter pad electrode EP and a gate pad electrode GP. An example of a semiconductor device applicable to a power module according to an embodiment, and is a schematic cross-sectional structure diagram of a SiC DI (Double Implanted) MOSFET. An example of a semiconductor device applicable to a power module according to an embodiment, and is a schematic cross-sectional structure diagram of a SiC T (Trench) MOSFET. An example of a circuit configuration in which a SiC MOSFET is applied as a semiconductor device and a snubber capacitor is connected between a power supply terminal PL and a ground terminal NL in a circuit configuration of a three-phase AC inverter configured by using the power module according to the embodiment. FIG. 3 is a circuit configuration diagram of a three-phase AC inverter to which a SiC MOSFET is applied as a semiconductor device in a circuit configuration of a three-phase AC inverter configured by using the power module according to the embodiment. The schematic cross-sectional structure view of the power module which concerns on the comparative example in 7th Embodiment. The schematic cross-sectional structure view of the power module which concerns on the comparative example in 7th Embodiment. The schematic cross-sectional structure view of the power module which concerns on the comparative example in 7th Embodiment. FIG. 6 is a schematic cross-sectional structural view of the power module according to the seventh embodiment. FIG. 6 is a schematic cross-sectional structural view of a graphite plate applicable to the power module according to the seventh embodiment. FIG. 6 is a schematic cross-sectional structural diagram showing a structural model of thermal resistance simulation of a power module according to a comparative example in the seventh embodiment. FIG. 4 is a schematic top view of the SiC chip of the structural model shown in FIGS. 42, 44, and 45 when viewed from above. FIG. 6 is a schematic cross-sectional structural diagram showing a structural model of thermal resistance simulation of a power module according to a comparative example in the seventh embodiment. The schematic cross-sectional structure diagram which shows the structural model of the thermal resistance simulation of the power module which concerns on 7th Embodiment. (A) Schematic plane pattern configuration diagram showing a specific example of the power module according to the seventh embodiment, (b) Schematic cross-sectional structure diagram along the line VIII-VIII of FIG. 46 (a), (c). FIG. 4 is a schematic right side sectional view of the power module shown in 46 (a). (A) Schematic cross-sectional structure diagram of the power module according to the seventh embodiment, (b) Enlarged cross-sectional structure diagram of the portion of display A in FIG. 47 (a). FIG. 6 is a schematic cross-sectional structural view showing a modified example of the graphite plate included in the power module according to the seventh embodiment. Schematic cross-sectional structural view of a power module using the graphite plate shown in FIG. 48. Schematic cross-sectional structural view of another power module using the graphite plate shown in FIG. 48. FIG. 6 is a schematic cross-sectional structure diagram showing a modified example of the power module according to the seventh embodiment. (A) Schematic plane pattern configuration diagram showing a modified example of the power module according to the seventh embodiment, (b) Schematic cross-sectional structure diagram along the IX-IX line of FIG. 52 (a). A detailed cross-sectional structural view of the power module according to the seventh embodiment. A detailed cross-sectional structural view of another power module according to the seventh embodiment. FIG. 6 is a schematic cross-sectional structure diagram of a one-in-one (1 in 1) module to which a SiC MOSFET is applied as a semiconductor device, which is a power module according to a basic technique which is a basis of the eighth to fourteenth embodiments. FIG. 6 is a schematic circuit representation diagram of a 1-in-1 module to which a SiC MOSFET is applied as a semiconductor device, which is a power module according to the basic technology which is the basis of the 8th to 14th embodiments. (A) Schematic plane pattern configuration diagram of a two-in-one (2 in 1) module to which a SiC MOSFET is applied as a semiconductor device, which is a power module according to a basic technique which is a basis of the eighth to fourteenth embodiments. (B) An enlarged view showing an enlarged main part (display 11A part) of FIG. 57 (a). A schematic cross-sectional structure diagram and a schematic circuit representation diagram of (a) a schematic cross-sectional structure diagram and (b) a schematic circuit representation diagram of a 1-in-1 module which is a power module according to an eighth embodiment and to which a SiC MOSFET is applied as a semiconductor device. The schematic plane pattern block diagram of the semiconductor device applicable to the power module which concerns on 8th Embodiment. A schematic circuit diagram for explaining (a) switching loss due to parasitic inductance at the time of turn-on, taking as an example a 1 in 1 module to which a SiC MOSFET is applied as a semiconductor device, which is a power module according to the eighth embodiment. , (B) Schematic circuit diagram for explaining switching loss due to parasitic inductance at turn-off. FIG. 6 is a schematic bird's-eye view pattern configuration diagram of a 2 in 1 module (module with a built-in half bridge) to which a SiC MOSFET is applied as a semiconductor device, which is a power module according to a ninth embodiment. A power module according to a ninth embodiment, which is a module with a built-in half bridge to which a SiC MOSFET is applied as a semiconductor device, (a) a schematic planar pattern configuration diagram, and (b) a main part of FIG. 62 (a). Display 1A part) enlarged view. FIG. 6 is a schematic circuit representation diagram of a power module according to a ninth embodiment, which is a module with a built-in half bridge to which a SiC MOSFET is applied as a semiconductor device. FIG. 6 is a schematic bird's-eye view configuration diagram of a module with a built-in half bridge after resin molding as a mold type module, which is a power module according to a ninth embodiment. 9 is a power module according to a ninth embodiment, and is a schematic side enlarged view showing the configuration of a main part from the direction of arrow B in FIG. 62 (b). FIG. 6 is a schematic planar pattern configuration diagram of a 1-in-1 module to which a SiC MOSFET is applied as a semiconductor device, which is a power module according to a tenth embodiment. It is a figure which shows the simulation result about the thermal diffusivity at the time of heat generation, taking a 1 in 1 module which applied the SiC MOSFET as a semiconductor device as an example, which is the power module which concerns on the tenth embodiment. FIG. 6 is a schematic cross-sectional structural view of a 1-in-1 module to which a SiC MOSFET is applied as a semiconductor device, which is a power module according to the eleventh embodiment. FIG. 6 is a schematic bird's-eye view pattern configuration diagram of a six-in-one (6 in 1) module, which is a power module according to a twelfth embodiment. (A) Schematic plane pattern configuration diagram, (b) Schematic cross-sectional structure diagram along the XI-XI line of FIG. 70 (a) of the power module according to the thirteenth embodiment. (A) Schematic plane pattern configuration diagram, (b) Schematic cross-sectional structure diagram along line XII-XII of FIG. 71 (a) of the power module according to the fourteenth embodiment. (A) Schematic plane pattern configuration diagram showing a schematic configuration of the power module according to the fifteenth embodiment, (b) Schematic cross-sectional structure diagram along the line XIII-XIII of FIG. 72 (a). (A) A power module according to a modification 1 of the fifteenth embodiment, which is a schematic cross-sectional structure diagram along the line XIII-XIII having a schematic planar pattern configuration similar to that of FIG. 72 (a), (b). FIG. 6 is a schematic cross-sectional structure diagram along line XIII-XIII having a schematic planar pattern configuration similar to that of FIG. 72 (a), which is a power module according to the second modification of the fifteenth embodiment. (A) Schematic cross-sectional structure diagram of the power module according to Comparative Example 1 in the fifteenth embodiment, (b) Schematic cross-sectional structure diagram of the power module according to Comparative Example 2 in the fifteenth embodiment. A schematic cross-sectional structure applied to a thermal resistance simulation, wherein (a) an example of a power module according to a fifteenth embodiment, and (b) an example of a power module according to a modification one of the fifteenth embodiment. (C) An example of a power module according to a modification 2 of the fifteenth embodiment. A schematic cross-sectional structure applied to a thermal resistance simulation, wherein (a) an example of a power module according to Comparative Example 1 in the fifteenth embodiment, and (b) a power according to Comparative Example 2 in the fifteenth embodiment. Module example. Heat between the power module according to the fifteenth embodiment (E1) and its modifications 1 and 2 (E2 and E3) and the power module according to the comparative examples 1 to 4 (C1 to C4) in the fifteenth embodiment. Comparison result of resistance simulation. Thermal resistance simulation results using a ceramic substrate (Al ₂ O ₃ / Si ₃ N ₄ / Al N) in the power module according to the fifteenth embodiment. In the power module according to the first modification of the fifteenth embodiment, the combination of the heat conductive layer (heat conductive sheet layer / solder layer / silver fired layer) and the ceramic substrate (Al ₂ O ₃ / Si ₃ N ₄ / Al N). Thermal resistance simulation results by. In the power module according to the second modification of the fifteenth embodiment, the combination of the heat conductive layer (heat conductive sheet layer / solder layer / silver fired layer) and the ceramic substrate (Al ₂ O ₃ / Si ₃ N ₄ / Al N). Thermal resistance simulation results by. An example of a graphite substrate applicable to the power module according to the fifteenth embodiment, (a) a schematic bird's-eye view configuration diagram illustrating an application example of a graphite substrate with YZ orientation, and (b) a device for YZ orientation. A diagram illustrating the alignment direction, (c) a schematic bird's-eye view configuration diagram illustrating an application example of an XZ-oriented graphite substrate, and (d) a diagram illustrating the arrangement direction of the devices with respect to the XZ orientation. The figure explaining the thermal resistance characteristic of the power module which concerns on 15th Embodiment by the case of (a) XZ orientation as an example, and (b) the figure explaining the case of YZ orientation as an example. (A) A schematic bird's-eye view pattern configuration diagram showing a schematic configuration of a power module according to a sixteenth embodiment, and (b) a schematic plane pattern configuration diagram. In the power module according to the fifteenth to eighteenth embodiments, (a) a schematic cross-sectional view, (b) FIG. 84 (a) for explaining the heat interference effect by taking the case where the distance between devices is widened as an example. ) Corresponding schematic plan view. In the power module according to the fifteenth to eighteenth embodiments, (a) a schematic cross-sectional view, (b) FIG. 85 (a) for explaining the heat interference effect by taking the case where the distance between devices is narrowed as an example. ) Corresponding schematic plan view. In the power module according to the fifteenth to eighteenth embodiments, in order to explain the heat interference effect, (a) a schematic cross-sectional view showing an example of a case where the graphite substrate is thickened, and (b) the graphite substrate being thinned. The schematic cross-sectional view which shows the case as an example. In the power module according to the fifteenth to eighteenth embodiments, examples of device arrangement are shown, in which (a) an example in which a plurality of devices are linearly arranged, and (b) a plurality of devices are arranged at a predetermined angle. An example in which the devices are arranged diagonally, and (c) an example in which a plurality of devices are arranged in a staggered pattern. In the power module according to the fifteenth to eighteenth embodiments, in order to explain the relationship between the amount of deviation of the device arrangement and the thermal resistance, (a) a schematic plan view of the simulation model used in the simulation, (b). A characteristic diagram showing the standardized simulation results, and (c) a schematic diagram showing an allowable range of deviation amount. In the power module according to the fifteenth to eighteenth embodiments, a schematic plan view showing another example of the simulation model for explaining the relationship between the amount of deviation of the device arrangement and the thermal resistance. A schematic bird's-eye view pattern configuration diagram and (b) a schematic plane pattern configuration diagram showing a schematic configuration of a power module according to a seventeenth embodiment. The schematic plan view which shows the schematic structure of the power module which concerns on 18th Embodiment. (A) Results of simulation using simulation model MD1 in the case of applying a graphite substrate having an anisotropic coefficient of thermal expansion in the power module according to the fifteenth to eighteenth embodiments. (B) A diagram showing the results when simulation is performed using the simulation model MD2, and (c) A diagram showing the results when simulation is performed using the simulation model MD3.

Next, the present embodiment will be described with reference to the drawings. In the description of the drawings described below, the same or similar parts are designated by the same or similar reference numerals. However, it should be noted that the drawings are schematic and the relationship between the thickness of each component and the plane dimensions is different from the actual one. Therefore, the specific thickness and dimensions should be determined in consideration of the following explanation. In addition, it goes without saying that parts of the drawings having different dimensional relationships and ratios are included.

Further, the embodiments shown below exemplify devices and methods for embodying the technical idea, and do not specify the material, shape, structure, arrangement, etc. of each component. This embodiment can be modified in various ways within the scope of the claims.

In the following description, for convenience, the height (thickness) direction (the height (thickness) direction of the module) orthogonal to the rectangular paper surface is Z, and the direction along one side of the paper surface (one orthogonal to the height direction Z) is The direction) is defined as X, and the direction along the other side orthogonal to one side (other direction) is defined as Y, but the present invention is not limited to this, and X, Y, and Z can be arbitrarily set.

[First Embodiment]
(Basic configuration)
The schematic plane pattern configuration of the power module (PM; Power Module) 1 according to the first embodiment is shown as shown in FIG. 1 (a), and is a schematic along the line II of FIG. 1 (a). The cross-sectional structure is represented as shown in FIG. 1 (b). In addition, in FIG. 1A and FIG. 1B, the case where it is applied to PM1 of a 1 in 1 (one-in-one) module type is illustrated.

Here, in FIG. 1, the upper side of the insulating substrate 20 is defined as the UP (U) side, and the lower side of the insulating substrate 20 is defined as the DOWN (D) side. This definition applies to all drawings shown below.

As shown in FIGS. 1A and 1B, the PM1 according to the first embodiment is, for example, a Cu foil provided on the upper surface (first surface) of the SiN-based ceramic substrate 21. The drain electrode pattern (first electrode pattern) 23U1 and the source electrode pattern (second electrode pattern) 23U2, and the back surface electrode pattern (third electrode pattern) such as Cu foil provided on the lower surface (second surface) of the ceramic substrate 21. The insulating substrate 20 having the 23D, the semiconductor device (power device) 10 of the power element system arranged on the drain electrode pattern 23U1, and the radiator 41 arranged on the back electrode pattern 23D of the insulating substrate 20 are different. A conductive graphite plate (graphite wiring) 18GP having a directional thermal conductivity and a Cu wiring pattern 16 as a first wiring pattern are provided on the lower surface (first main surface), and a source pad electrode (shown) of the semiconductor device 10 is provided. The upper wiring (wiring lead portion) 30 for connecting the source electrode pattern 23U2 and the source electrode pattern 23U2 is provided.

That is, the PM1 according to the first embodiment has an insulating substrate 20, a semiconductor device 10 arranged on the insulating substrate 20 and having electrodes on the front surface side and the back surface side thereof, and one end on the front surface side of the semiconductor device 10. It is provided with a graphite plate 18GP having an anisotropic thermal conductivity whose other end is connected to the insulating substrate 20 and transfers heat on the surface side of the semiconductor device 10 to the insulating substrate 20 via the graphite plate 18GP.

The graphite plate 18GP has, for example, a length GL composed of one end side connected to the semiconductor device 10 and the other end side at a position separated from the one end side in the same plane, and a direction orthogonal to the length GL in a plan view. The width GW is wider than the width CW of the semiconductor device 10. This makes it easy to secure high thermal conductivity (heat diffusivity) of the graphite plate 18GP.

The semiconductor device 10 is arranged so that the U side is the source electrode and the D side is the drain electrode. The same applies to other semiconductor devices described later.

In the upper wiring 30, the lower Cu wiring pattern 16 is connected to the source electrode pattern 23U2 via the block electrode 29.

The block electrode 29 is made of, for example, Cu (metal column), and is joined to the Cu wiring pattern 16 of the upper wiring 30 and to the source electrode pattern 23U2, respectively, via the silver fired portion 27.

The semiconductor device 10 is joined to the Cu wiring pattern 16 of the upper wiring 30 and to the drain electrode pattern 23U1 via a silver firing portion 27, respectively.

Here, although the illustration is omitted except for PM1 shown in FIG. 16, in reality, the Al electrode portion 61 and the Ni plating layer 63 are sequentially formed on the upper surface of the semiconductor device 10, and the Al electrode portion 61 and the Al electrode portion 61 are formed. The semiconductor device 10 and the Cu wiring pattern 16 are bonded to each other via the Ni plating layer 63 and the silver fired portion 27, but from the viewpoint of heat, the Al electrode 61 on the semiconductor device 10 is thin. Therefore, it can be almost ignored.

The radiator 41 is joined to the back surface electrode pattern 23D by a joining member 26 made of SnAgCu-based solder or the like.

The radiator 41 may be an Al heat sink that absorbs heat generated from the semiconductor device 10 and dissipates heat, a heat radiation fin or a heat dissipation pin, or a cooler that cools heat generated from the semiconductor device 10.

In the case of a cooler, for example, water or a mixture of water and ethylene glycol at a ratio of 50% or a cooling gas (cold air) having good thermal conductivity is used as the cooling water. Be done.

The upper wiring 30 is bonded so as to expose the gate pad electrode to the upper surface of the semiconductor device 10 for wire bonding with the gate pad electrode (not shown).

The semiconductor device 10 is not limited to a power device, and may include an FRD such as a diode, for example, or is a module in which the outer periphery of one or a plurality of chips is sealed with a mold resin or a case. There may be.

For example, an AMB (Active Metal Brazed, Active Metal Bond) substrate can be applied to the insulating substrate 20, but a DBC (Direct Bonding Copper) substrate, a DBA (Direct Brazed Aluminum) substrate, or the like can also be applied.

The PM1 according to the first embodiment can be expected to have a heat diffusion effect in the upper wiring 30 by adopting the graphite plate 18GP, which is a high thermal conductive material, for the upper wiring 30 in the one-sided cooling + upper wiring structure.

[Comparative example in the first embodiment]
(Comparative Example 1 in the First Embodiment)
PM11 according to Comparative Example 1 in the first embodiment has a single-sided cooling + wire bonding structure, and has an insulating substrate 20 having a drain electrode pattern 23U provided on the ceramic substrate 21 as shown in FIG. , The power-based semiconductor device 10 arranged on the drain electrode pattern 23U via the silver firing portion 27, and the insulating substrate 20 via the bonding member 26 on the back surface electrode pattern 23D on the facing surface side of the drain electrode pattern 23U. The radiator 41 is provided with a radiator 41, and a source bonding wire SW for connecting the source pad electrode and the source electrode pattern of the semiconductor device 10 (not shown).

(Comparative Example 2 in the First Embodiment)
PM12 according to Comparative Example 2 in the first embodiment has a double-sided cooling structure, and as shown in FIG. 3, has a lower insulating substrate 20D having electrode patterns 23D and 24D provided on both sides of the ceramic substrate 21D. The power-based semiconductor device 10 arranged on the electrode pattern 24D via the silver firing unit 27 and the semiconductor device 10 are arranged facing the semiconductor device 10 via the silver firing unit 27 and provided on both sides of the ceramic substrate 21U. The upper insulating substrate 20U having the electrode patterns 23U and 24U, the lower radiator 41D arranged on the electrode pattern 23D of the lower insulating substrate 20D via the joining member 26, and the joining member on the electrode pattern 23U of the upper insulating substrate 20U. It is provided with an upper radiator 41U arranged via 26.

[Heat resistance characteristics]
The results (thermal resistance characteristics) of the thermal simulation performed on PM1 and PM11 (Comparative Example 1) and PM12 (Comparative Example 2) according to the first embodiment are shown in FIG.

As shown in FIG. 4, since the PM12 according to Comparative Example 2 in the first embodiment has a double-sided cooling structure having excellent cooling performance, it is about 40 more than PM11 according to Comparative Example 1 in the first embodiment. It is possible to reduce the thermal resistance by%.

On the other hand, PM1 according to the first embodiment does not reach PM12 according to Comparative Example 2 in the first embodiment, but has higher thermal resistance than PM11 according to Comparative Example 1 in the first embodiment. Can be reduced by about 20%.

That is, by adopting a structure in which the Cu wiring pattern 16 is bonded to the graphite plate 18GP of a high thermal conductivity material having an anisotropic thermal conductivity as the upper wiring 30, in PM1 according to the first embodiment. , Improvement of cooling performance (heat diffusion effect) in the upper wiring 30 can be expected.

The dimensions (thickness) of each part of PM1, PM11, and PM12 used in the above thermal simulation are as follows, and the temperature of the back surface of the radiator 41 was fixed at 65 ° C.

For example, the radiator 41, 41D, 41U has a thickness of 1.0 mm, the joining member 26 has a thickness of 0.2 mm, the ceramic substrate 21, 21D, 21U has a thickness of 0.25 mm, and the electrode patterns 23D, 23U1, 23U2, 23U, etc. The 24D and 24U were 1.0 mm thick, and the semiconductor device 10 was a 350 μm thick SiC MOSFET. The silver fired portion 27 was 60 μm thick, the block electrode 29 was 350 μm thick, the Cu wiring pattern 16 was 0.2 mm thick, and the graphite plate 18GP was 0.7 mm thick.

According to PM1 according to the first embodiment, a single-sided cooling structure is used as a basic structure, and a Cu wiring pattern 16 is attached to a graphite plate 18GP having an anisotropic thermal conductivity as an upper wiring 30 on a semiconductor device 10. By applying the combined graphite upper wiring structure (graphite structure), cooling performance comparable to that of the double-sided cooling structure can be exhibited.

Further, in PM1 according to the first embodiment, it is possible to reduce stress at the same time by applying the graphite plate 18GP to the upper wiring 30.

Therefore, it is possible to provide a power module which is excellent in reliability and productivity, is inexpensive as compared with the double-sided cooling structure, can exhibit cooling performance not inferior to the double-sided cooling structure, and can simultaneously reduce stress.

(Graphite plate 18GP)
(Basic configuration)
In PM1 according to the first embodiment, it is possible to use two types of graphite plates having different orientations as the graphite plate 18GP.

A schematic configuration (example of laminated structure) of the graphite sheet (graphene) GS constituting the graphite plate 18GP is shown as shown in FIG.

The graphite plate 18GP has an XY orientation (first orientation) having a higher thermal conductivity in the plane direction than the thickness direction, and an XZ orientation having a higher thermal conductivity in the thickness direction than the plane direction. There is a graphite plate 18GP (XZ) with (second orientation), the graphite plate 18GP (XY) is represented as shown in FIG. 6 (a), and the graphite plate 18GP (XZ) is shown in FIG. 6 (b). It is expressed as shown in.

As shown in FIG. 5, the graphite sheets GS1, GS2, GS3, ..., GSn on each surface composed of n layers have a large number of hexagonal covalent bonds in one laminated crystal structure, and each surface has a covalent bond. The graphite sheets GS1, GS2, GS3, ..., and GSn are bonded by a van der Waals force.

That is, graphite, which is a carbon-based anisotropic heat transfer material, is a layered crystal having a hexagonal network structure of carbon atoms, and has anisotropy in heat conduction. Graphite sheets GS1, GS2, shown in FIG. GS3 ..... GSn has a higher thermal conductivity (high thermal conductivity) in the crystal plane direction (on the XY plane) than in the thickness direction of the Z axis.

Therefore, as shown in FIG. 6A, the graphite plate 18GP (XY) having an XY orientation has, for example, X = 1500 (W / mK), Y = 1500 (W / mK), Z = 5 (W /). It has a thermal conductivity of mK).

On the other hand, as shown in FIG. 6B, the graphite plate 18GP (XZ) having the XZ orientation has, for example, X = 1500 (W / mK), Y = 5 (W / mK), Z = 1500 (W /). It has a thermal conductivity of mK).

Both the graphite plates 18GP (XY) and 18GP (XZ) have a density of 2.2 (g / cm ³ ), a thickness of 2 mm to 10 mm, and a size of 40 mm × 40 mm or less.

[Second Embodiment]
(Rough configuration)
The schematic planar pattern configuration of PM1 according to the second embodiment is shown in FIG. 7 (a), and the schematic cross-sectional structure along the line II-II of FIG. 7 (a) is shown in FIG. 7 (b). ). Further, the schematic bird's-eye view configuration of PM1 according to the second embodiment is shown as shown in FIG. It should be noted that FIGS. 7 (a), 7 (b) and 8 show examples of application to PM1 of the 1 in 1 module type.

Here, as shown in FIGS. 7 (a), 7 (b) and 8, the PM1 according to the second embodiment is the first PM1 except for the configuration of the upper wiring (wiring lead portion) 30A. It has almost the same configuration as PM1 according to the embodiment.

As shown in FIGS. 7 (a), 7 (b) and 8, the PM1 according to the second embodiment is arranged on the insulating ceramic substrate 21 and the upper surface (first surface) of the ceramic substrate 21. The drain electrode pattern (first electrode pattern) 23U1 and the source electrode pattern (second electrode pattern) 23U2, and the back surface electrode pattern (third electrode pattern) 23D arranged on the lower surface (second surface) of the ceramic substrate 21. A semiconductor device (power device) 10 arranged on the drain electrode pattern 23U1 and having electrodes (not shown) on the front surface side and the back surface side thereof, and heat dissipation arranged on the back surface electrode pattern 23D. The vessel 41, the block electrode 29 arranged on the source electrode pattern 23U2, the graphite plate (graphite wiring) 18GP having an anisotropic thermal conductivity, and the lower surface (first main surface) of the graphite plate 18GP are arranged. It is provided with a Cu wiring pattern (first wiring pattern) 16D and a Cu wiring pattern (second wiring pattern) 16U arranged on the upper surface (second main surface), and one end side thereof is a source pad electrode on the front surface side of the semiconductor device 10. It also includes an upper wiring (wiring lead portion) 30A that is connected and the other end side at a position separated from one end side in the same plane is connected to the source electrode pattern 23U2 via the block electrode 29.

In PM1 according to the second embodiment, the schematic bird's-eye view configuration of the upper wiring 30A is shown as shown in FIG. 9A, and the schematic front (side surface) configuration is shown in FIG. 9B. It is expressed as.

In PM1 according to the second embodiment, as shown in FIGS. 9A and 9B, the upper wiring 30A is, for example, a graphite plate 18GP (XY) having an XY orientation and a graphite plate 18GP (XY). ) Is provided with a Cu wiring pattern 16D bonded to the lower surface (first main surface) and a Cu wiring pattern 16U bonded to the upper surface (second main surface) of the graphite plate 18GP (XY). The Cu wiring pattern 16D in the lower layer has a substantially I-shaped cross-sectional shape formed separately from the block electrode 29 with respect to the XZ surface.

That is, the PM1 according to the second embodiment faces the upper surface of the insulating ceramic substrate 21, the drain electrode pattern 23U1 and the source electrode pattern 23U2 arranged on the upper surface (first surface) of the ceramic substrate 21. An insulating substrate 20 having a back surface electrode pattern 23D arranged on the lower surface (second surface), a semiconductor device 10 arranged on the drain electrode pattern 23U1 and having a source electrode on the front surface side and a drain electrode on the back surface side. A radiator 41 arranged on the back surface electrode pattern 23D, a block electrode 29 arranged on the source electrode pattern 23U2, a graphite plate 18GP having an anisotropic thermal conductivity, and a lower surface of the graphite plate 18GP (first). It is provided with a Cu wiring pattern 16D arranged on the main surface) and a Cu wiring pattern 16U arranged on the upper surface (second main surface) facing the lower surface, and one end side is connected to the front surface side of the semiconductor device 10 and one end is connected. The other end side of the position distant from the side is provided with the upper wiring 30A connected to the Cu electrode pattern 23U2 via the block electrode 29, and the graphite plate 18GP has higher thermal conductivity in the surface direction than in the thickness direction. A plate structure (18GP (XY)) or XY, which has either an XY orientation or an XZ orientation having a higher thermal conductivity in the thickness direction than the plane direction, and is formed by laminating a plurality of graphite sheets GS having the XY orientation. A plate structure (18GP (XZ)) formed by laminating a plurality of oriented graphite sheets GS is provided, and heat on the surface side of the semiconductor device 10 is transferred to the insulating substrate 20 via the graphite plate 18GP.

The graphite plate 18GP (XY) having an XY orientation has, for example, a thermal conductivity of X = 1500 (W / mK), Y = 1500 (W / mK), and Z = 5 (W / mK).

Therefore, the upper wiring 30A to which the graphite plate 18GP (XY) is applied can be expected to have a higher heat diffusion effect on the XY surface, and is provided with the Cu wiring pattern 16U in the upper layer, so that the warp (stress) is simultaneously obtained. Can be effectively suppressed.

(Modification example)
The schematic bird's-eye view configuration of PM1 according to the modified example of the second embodiment is shown as shown in FIG.

Here, the PM1 according to the modified example of the second embodiment is arranged so that the direction of the semiconductor device 10 is different from that of the PM1 according to the second embodiment, for example, as shown in FIG. This is an example of the case, and since it has almost the same configuration as PM1 according to the second embodiment except for the orientation of the semiconductor device 10, detailed description thereof will be omitted.

That is, as in PM1 according to the modified example of the second embodiment, the semiconductor device 10 is arranged so that the direction of the gate pad electrode (not shown) is orthogonal to the extension direction of the upper wiring 30A. It is also possible.

The upper wiring 30A is bonded so as to expose the gate pad electrode (bonding surface GB of the gate wire) to the upper surface of the semiconductor device 10 for wire bonding with the gate pad electrode (not shown).

Although detailed description will be omitted, the configuration of PM1 according to the modified example of the second embodiment shown in FIG. 10 can be similarly applied to PM1 having the configuration according to another embodiment.

[Third Embodiment]
The schematic planar pattern configuration of PM1 according to the third embodiment is shown in FIG. 11 (a), and the schematic cross-sectional structure along the line III-III in FIG. 11 (a) is shown in FIG. 11 (b). ). In addition, in FIG. 11A and FIG. 11B, the case where it is applied to PM1 of a 1 in 1 module type is exemplified.

Here, as shown in FIGS. 11A and 11B, the PM1 according to the third embodiment is the second embodiment except for the configuration of the upper wiring (wiring lead portion) 30B. It has almost the same configuration as PM1 according to the above.

That is, as shown in FIGS. 11A and 11B, the PM1 according to the third embodiment includes the ceramics substrate 21 and the drain electrodes arranged on the upper surface (first surface) of the ceramics substrate 21. An insulating substrate including a pattern (first electrode pattern) 23U1 and a source electrode pattern (second electrode pattern) 23U1 and a back surface electrode pattern (third electrode pattern) 23D arranged on the lower surface (second surface) of the ceramic substrate 21. 20 and a semiconductor device (power device) 10 arranged on the drain electrode pattern 23U1 and having a source pad electrode (not shown) on the front surface, and a radiator 41 arranged on the back surface electrode pattern 23D are anisotropic. A graphite plate (graphite wiring) 18GP having thermal conductivity and a lower surface (first main surface) of the graphite plate 18GP are arranged, one end side is connected to the source pad electrode of the semiconductor device 10, and the other end side is a source electrode pattern. Upper wiring (wiring lead) having a Cu wiring pattern (first wiring pattern) 16D1 connected to 23U2 and a Cu wiring pattern (second wiring pattern) 16U provided on the upper surface (second main surface) of the graphite plate 18GP. Part) 30B and the like.

In PM1 according to the third embodiment, the schematic bird's-eye view configuration of the upper wiring 30B is shown as shown in FIG. 12 (a), and the schematic front (side surface) configuration is shown in FIG. 12 (b). It is expressed as.

That is, in PM1 according to the third embodiment, as shown in FIGS. 12 (a) and 12 (b), the upper wiring 30B is, for example, a graphite plate 18GP (XY) having an XY orientation and a graphite plate 18GP. A Cu wiring pattern 16D1 bonded to the lower surface of (XY) and a Cu wiring pattern 16U bonded to the upper surface of the graphite plate 18GP (XY) are provided. The Cu wiring pattern 16D1 in the lower layer has a substantially L-shaped cross-sectional shape integrally formed with a block-shaped connection electrode portion (block electrode) with respect to the XZ surface.

Therefore, the upper wiring 30B to which the graphite plate 18GP is applied can be used in combination with the Cu wiring pattern 16U in the upper layer while integrally forming the Cu wiring pattern in the lower layer and the block electrode as in the Cu wiring pattern 16D1. On the other hand, a higher thermal diffusion effect can be expected, and warpage (stress) can be reduced more effectively.

According to PM1 according to the third embodiment, when the single-sided cooling structure is adopted from the viewpoint of productivity by adopting the upper wiring 30B in which the Cu wiring patterns 16U and 16D1 are attached to both the upper and lower surfaces of the graphite plate 18GP. However, it is possible to secure cooling performance that is not inferior to the double-sided cooling structure.

At the same time, a relaxation effect on stress can be expected (for example, by laminating a graphite plate and a Cu wiring pattern, a reduction of about 50% is possible as compared with the case of using only the Cu wiring pattern).

Further, the combined use of the Cu wiring pattern 16D1 does not impair the electrical conductivity of the upper wiring 30B.

Although detailed description is omitted, the configuration (upper wiring structure) of PM1 according to the third embodiment is similarly the same as PM1 having the configuration according to other embodiments such as the first embodiment. Applicable.

That is, the upper wiring 30B has a configuration in which the Cu wiring pattern 16U is provided on the upper surface of the graphite plate 18GP, but the Cu wiring pattern 16U in the upper layer is not an indispensable configuration requirement, and the Cu wiring pattern 16U may be omitted. It is possible.

Further, in PM1 according to any of the embodiments, the graphite plate 18GP is not limited to the graphite plate 18GP (XY) having XY orientation, and for example, the graphite plate 18GP (XZ) having XZ orientation can be applied. ..

That is, the PM1 according to the third embodiment is arranged on the insulating ceramic substrate 21, the drain electrode pattern 23U1 and the source electrode pattern 23U2 arranged on the upper surface of the ceramic substrate 21, and the lower surface facing the upper surface. An insulating substrate 20 having a back surface electrode pattern 23D, a semiconductor device 10 arranged on the drain electrode pattern 23U1 and having electrodes on the front surface side and the back surface side thereof, and a radiator 41 arranged on the back surface electrode pattern 23D. , The graphite wiring 18GP having an anisotropic thermal conductivity, and the other end located on the lower surface of the graphite wiring 18GP, one end side connected to the front surface side of the semiconductor device 10 and the other end in the same plane as the one end side and distant from each other. The graphite wiring 18GP is provided with an upper wiring 30B having a Cu wiring pattern 16D1 having an L-shaped cross-sectional shape in which the thickness of the wiring pattern is partially different so that the side is connected to the source electrode pattern 23U2, and the graphite wiring 18GP is a surface rather than a thickness direction. A plate structure (18GP) in which a plurality of graphite sheets GS having either XY orientation having high thermal conductivity in the direction or XZ orientation having higher thermal conductivity in the thickness direction than the plane direction and having XY orientation are laminated. (XY)) or a plate structure (18GP (XZ)) formed by laminating a plurality of graphite sheets GS having XZ orientation, and heat on the surface side of the semiconductor device 10 is transferred to the insulating substrate 20 via the graphite wiring 18GP. introduce.

[Heat resistance characteristics]
Next, the result (relationship between the upper wiring and the thermal resistance) when the simulation is performed using PM1 according to the fourth embodiment as a model will be described.

[Fourth Embodiment]
(Rough configuration)
The schematic planar pattern configuration of PM1 according to the fourth embodiment is shown in FIG. 13 (a), and the schematic cross-sectional structure along the IV-IV line in FIG. 13 (a) is shown in FIG. 13 (b). ). In addition, in FIG. 13A and FIG. 13B, the case where it is applied to PM1 of a 1 in 1 module type is exemplified.

Here, as shown in FIGS. 13 (a) and 13 (b), the PM1 according to the fourth embodiment is substantially the same as the PM1 according to the first embodiment except for the block electrode 29A. It has a configuration.

That is, in the PM1 according to the fourth embodiment, as shown in FIGS. 13 (a) and 13 (b), the Cu wiring pattern 16 is bonded to the lower surface (first main surface) of the graphite plate 18GP. The upper wiring 30 is provided.

In the upper wiring 30, for example, the thickness t of the graphite plate 18GP is 0.7 mm, and the thickness tc of the Cu wiring pattern 16 is 0.2 mm. Further, the width (length in the Y direction) of the upper wiring 30 is d.

The graphite plate 18GP has an XY orientation and has, for example, a thermal conductivity of X = 1500 (W / mK), Y = 1500 (W / mK), and Z = 5 (W / mK).

In PM1 according to the fourth embodiment, the insulating substrate 20 has, for example, a SiN-based ceramic substrate 21 having a thickness of 0.25 mm, and the upper drain electrode pattern 23U1 and the source electrode pattern 23U2 having a thickness of 1.0 mm. Cu foil was formed in a size of 15 mm × 15 mm.

For the back surface electrode pattern 23D of the lower layer, for example, a Cu foil having a thickness of 1.0 mm was used.

As the semiconductor device 10, for example, a SiC MOSFET having a thickness of 350 μm and a size of 5 mm × 5 mm was used.

The silver fired portion 27 had a thickness of 60 μm.

For the block electrode 29A, for example, a Cu foil having a thickness of 0.35 mm was formed in a size of 3.2 mm × 3.2 mm.

The block electrode 29A is arranged substantially at the center of the upper wiring 30 in the Y direction, and the distance from the edge of the upper wiring 30 in the X direction is set to e.

Using PM1 with such a configuration as a simulation model, the thermal resistance (° C./W) when the width d of the upper wiring 30 is d1 = 3.2 mm, d2 = 7.5 mm, d3 = 10 mm, and d4 = 15 mm is simulated. The results are shown in FIGS. 14 (a) and 14 (b).

Note that FIG. 14A shows the results when the distance e from the edge of the upper wiring 30 of the block electrode 29A in the X direction is 0, 2.5 mm, 5 mm, 7.5 mm, and 10 mm, and is shown in FIG. 14 (a). b) is the result when the distance e is set to 0.

As is clear from FIG. 14A, the heat diffusion region of the upper wiring 30 increases as the width d increases, so that the thermal resistance is reduced (up to a decrease of about 6%).

Further, the width d of the upper wiring 30 is effectively within 20 mm (the distance e from the block electrode 29 to the edge is up to about 5 mm) as shown by an arrow in FIG. 14 (b).

15 (a) to 15 (c) show the relationship between the upper wiring 30 and the thermal resistance as a result of the simulation, and FIG. 15 (a) shows the thickness ct (tk) of the Cu wiring pattern 16. = 5 mm or less) and thermal resistance, FIG. 15 (b) shows the relationship between the thickness ct (tc = 10 mm or less) of the Cu wiring pattern 16 and thermal resistance, and FIG. 15 (c) shows the graphite plate. The relationship between the thickness t of 18GP (thickness tc of Cu wiring pattern 16 = 0.2 mm) and the thermal resistance is shown.

FIG. 15A shows a case where the thickness t of the graphite plate 18GP is t = 3 mm and a case where t = 0 (Cu wiring pattern 16 alone), and FIG. 15B shows. , The case where the thickness t of the graphite plate 18GP is t = 0.7 mm and the case where t = 0 is shown.

As shown by an arrow in FIG. 15B, the upper wiring 30 can reduce the thermal resistance when the thickness ct of the Cu wiring pattern 16 is about 9 mm or less as compared with the case where the Cu wiring pattern 16 is used alone. ..

As shown by an arrow in FIG. 15 (c), if the thickness t of the graphite plate 18GP is about 1 mm, the effect of reducing the thermal resistance can be sufficiently expected.

[Stress relaxation structure]
Next, the stress relaxation structure of PM by applying the graphite structure will be described using PM1 according to the fifth embodiment as a model.

[Fifth Embodiment]
(Rough configuration)
A schematic cross-sectional structure of a model for performing a simulation of the stress relaxation structure of PM1 according to the fifth embodiment is shown as shown in FIG. 16 (a). Note that FIG. 16B is an enlarged view showing an enlarged portion of the display A in FIG. 16A.

Here, due to the thermal expansion coefficient (CTE) of the graphite plate 18GP, the location where the Mises stress is acquired in PM1 is represented by the display B shown in FIG. 16 (b).

In PM1 shown in FIGS. 16A and 16B, for example, regarding the size in the X direction, the length of the back surface electrode pattern 23D x 1 = 28 mm, the length of the drain electrode pattern 23U1 x 2 = 15 mm, and the drain electrode pattern. Distance (length) x3 = 5 mm from the edge of 23U1 to the semiconductor device 10, length x4 = 5 mm of the semiconductor device 10, distance (length) x5 = 0 from the edge of the back surface electrode pattern 23D to the edge of the ceramic substrate 21. .5 mm, length of Al electrode portion 61 on device x6 = 4.94 mm, length of Ni plating layer 63 and silver fired portion 27 on device x7 = 2.5 mm, length of source electrode pattern 23U2 x8 = 12.5 mm The distance (length) between the two electrode patterns 23U1 and 23U2 (length) x9 = 0.5 mm, and the length of the block electrode 29 x10 = 2.5 mm.

On the other hand, regarding the size (thickness) of PM1 in the Z direction, for example, the thickness of the silver fired portion 27 is t1 · t6 = 0.1 mm (0.01 in Mesh), and the thickness of the Ni plating layer 63 on the device is t2. = 3 μm (0.0005 in Mesh), thickness t3 of Al electrode portion 61 on device t3 = 0.005 mm (0.0005 in Mesh), thickness t4 of semiconductor device 10 = 0.35 mm, firing of silver under device The thickness of the portion 27 is t5 = 0.05 mm, the thickness of the electrode patterns 23U1 and 23U2 is t7 = 0.5 mm, the thickness of the ceramic substrate 21 is t8 = 0.32 mm, and the thickness of the back surface electrode pattern 23D is t9 = 0.5 mm. (The interface between the silver fired part and the Al electrode part is Mesh, 0.0001).

The CTE of the graphite plate 18GP is X = 0.1 ppm / K, Y = 0.1 ppm / K, Z = 25 ppm / K, and the CTE of the Cu wiring pattern 16U / 16D is 17 ppm / K. Further, the CTE when the thickness t8 = 0.3 mm of the SiN-based ceramic substrate 21 is 3 ppm / K, and the thickness t7 = t9 = 0.3 mm of the electrode patterns 23U1, 23U2, and 23D. The CTE is 17 ppm / K, and the total CTE is adjusted to be about 8 ppm / K to 9 ppm / K.

Then, the thickness t of the graphite plate 18GP of the upper wiring 30 is 0.1 mm, 0.3 mm, 0.5 mm, 0.7 mm, and the thickness ct of the Cu wiring pattern 16D / 16U is 0.1 mm, 0. The cases of 0.3 mm and 0.5 mm were examined.

In order to see the effect of the anisotropy (CTE X = 0.1 ppm / K, Y = 0.1 ppm / K, Z = 25 ppm / K) of the graphite plate 18GP, the elastic modulus (Von Mises stress) GPa is Cu. It was set to 120 GPa, which is the same as the above.

FIG. 17 shows the relationship between CTE (ppm) and von Mises stress (von Mises stress ratio of graphite structure), and is the Mises stress ratio when CTE 17 ppm is 100. In FIG. 17, Cu and INV were used to simulate the graphite structure.

Here, the Mises stress is one of the equivalent stresses used to indicate the stress state generated inside the object with a single value. The definition formula of Mises stress is shown below. In the definition formula, σ1 is the maximum principal stress, σ2 is the intermediate principal stress, and σ3 is the minimum principal stress. Here, each of the principal stresses σ1, σ2, and σ3 is selected from the principal stress in the X direction, the principal stress in the Y direction, and the principal stress in the Z direction acting on the silver fired portion 27.

In FIG. 17, Cu is a case where the simulation model is a simple substance of Cu, Super Invar is a case where a simple substance of INV is used, and CIC1 has a thickness ratio of Cu, INV, and Cu of 1: 1. In the case of CIC3, the thickness ratio of Cu, INV, and Cu is 1: 3: 1.

As is clear from FIG. 17, the graphite structure can reduce the Mises stress ratio by about 50%.

That is, the Mises stress ratio in the simulation model can be reduced by changing the CTE of Cu and INV. This is because the change in the Mises stress of the Al electrode portion 61 is small even if the thickness of the Cu wiring pattern 16 is changed, but the Mises stress applied to the Al electrode portion 61 is greatly improved by changing the CTE of the upper wiring 30. Suggest the possibility of doing so.

Therefore, the upper wiring 30 having a graphite structure in which the Cu wiring patterns 16D and 16U are bonded to the graphite plate 18GP can have an excellent structure in terms of stress.

In FIG. 17, when the Mises stress ratio exceeds 80 (CTE of about 10 ppm or more), the model is broken.

[Sixth Embodiment]
(Rough configuration)
The schematic planar pattern configuration of PM1 according to the sixth embodiment is shown in FIG. 18 (a), and the schematic cross-sectional structure along the VV line of FIG. 18 (a) is shown in FIG. 18 (b). ). In addition, in FIG. 18A and FIG. 18B, the case where it is applied to PM1 of a 1 in 1 module type is exemplified.

Here, as shown in FIGS. 18A and 18B, the PM1 according to the sixth embodiment is the PM1 according to the first embodiment except for the configuration of the graphite substrates 18GH1 and 18GH2. It has almost the same configuration as.

As shown in FIGS. 18A and 18B, PM1 according to the sixth embodiment has an anisotropic coefficient of thermal expansion arranged on the upper surface (first surface) of the ceramic substrate 21. The graphite substrates 18GH1 and 18GH2 to be provided are further provided, a drain electrode pattern (first electrode pattern) 22U1 to which a semiconductor device (power device) 10 is bonded is bonded to the graphite substrate 18GH1, and a block electrode 29 is bonded to the graphite substrate 18GH2. The source electrode pattern (second electrode pattern) 22U2 to be formed is arranged respectively.

That is, PM1 according to the sixth embodiment includes an insulating ceramic substrate 21, graphite substrates 18GH1 and 18GH2 having an anisotropic thermal expansion coefficient arranged on the ceramic substrate 21, and graphite substrates 18GH1 and 18GH2. The semiconductor device 10 is provided with a semiconductor device 10 arranged on the surface and having electrodes on the front surface side and the back surface side thereof, and a graphite wiring 30 having an anisotropic thermal conductivity connected to the front surface side of the semiconductor device 10. The heat on the surface side of the above is transferred to the ceramic substrate 21 via the graphite wiring 30.

Further, PM1 according to the sixth embodiment is a graphite insulating substrate 20A including an insulating ceramic substrate 21 and graphite substrates 18GH1 and 18GH2 having an anisotropic thermal expansion coefficient arranged on the ceramic substrate 21. A semiconductor device 10 arranged on the graphite insulating substrate 20A and having electrodes on the front surface side and the back surface side thereof, and a graphite wiring 30 having an anisotropic thermal conductivity connected to the front surface side of the semiconductor device 10. The heat on the surface side of the semiconductor device 10 is transferred to the ceramic substrate 21 via the graphite wiring 30.

In PM1 according to the sixth embodiment, in addition to the heat diffusion effect due to the graphite structure, the joint portion (direction and vertical / horizontal size) of the semiconductor device 10 bonded on the drain electrode pattern 22U1 is changed. It is possible to reduce the stress applied to the silver fired portion 27 and the Al electrode portion 61).

When a device (module) such as a square is bonded on the graphite substrate 18GH1, the thermal conductivity and the coefficient of thermal expansion are anisotropic on the graphite substrate 18GH1, so in the direction where the coefficient of thermal expansion is large, both coefficients of thermal expansion A large stress is generated at the joint due to the difference between the above, but the stress applied to the joint can be reduced by matching the shape of the device with the coefficient of thermal expansion of the graphite substrate 18GH1.

Hereinafter, the stress applied to the joint portion will be described by taking as an example the case where the graphite substrate 18GH1 having anisotropy in the coefficient of thermal expansion is applied in PM1 according to the sixth embodiment.

A schematic planar pattern configuration (PMa) illustrating an arrangement with respect to the graphite substrate 18GH1 using FRD SC1 and IGBT SC2 as an example is shown as shown in FIG. 19A, and with SiC MOSFET SC3 as an example, with respect to the graphite substrate 18GH1. A schematic planar pattern configuration (PMb) illustrating the arrangement is represented as shown in FIG. 19 (b).

The semiconductor device 10 is actually bonded to the drain electrode pattern 22U1 on the graphite substrate 18GH1, but is not shown here in the description.

In the case of an IGBT including a diode or the like, as shown in FIG. 19A, the FRD SC1 and the IGBT SC2 are bonded as the semiconductor device 10 on the graphite substrate 18GH1.

In the case of the SiC MOSFET, as shown in FIG. 19B, the SiC MOS SC3 is bonded as the semiconductor device 10 on the graphite substrate 18GH1.

Here, when the orientation of the coefficient of thermal expansion of the graphite substrate 18GH1 is, for example, X = 0.5 ppm / K, Y = 25 ppm / K, z = 0.5 ppm / K, it is used as FRD SC1, IGBT SC2, SiC MOS SC3. All use a rectangular device (H1> C1) having a longitudinal (X) direction H1 and a lateral (Y) direction C1, and each lateral direction C1 corresponds to an orientation (Y) having a large coefficient of thermal expansion. Let me. This makes it possible to reduce the stress applied to the joint as well as the heat diffusion effect of the graphite substrates 18GH1 and 18GH2.

The configuration of PM1 according to the sixth embodiment can be similarly applied to PM1 having the configuration according to another embodiment.

[Stress reduction effect]
Hereinafter, the stress reducing effect by applying the graphite substrate in the PM according to the first to sixth embodiments will be further described.

(Example 1)
The schematic plane pattern configuration of the simulation model MD for simulating the stress applied to the joint is shown in FIG. 20 (a), taking as an example the case where a graphite substrate having anisotropy in the coefficient of thermal expansion is applied. The schematic cross-sectional structure along the VI-VI line of FIG. 20 (a) is represented by FIG. 20 (b).

Here, in the simulation model MD having the configurations shown in FIGS. 20 (a) and 20 (b), the lower surface Cu foil (back surface electrode pattern 23D) / Si _{3N 4 substrate} (ceramics substrate 21) / graphite plate (graphite substrate). A laminated substrate structure composed of 18GH1 and 18GH2) / upper surface Cu foil (electrode patterns 22U1 and 22U2) is referred to as a graphite insulating substrate.

Since the graphite plate of the graphite insulating substrate has anisotropy in thermal conductivity and coefficient of thermal expansion, when a device such as a square is die-bonded, the difference in the coefficient of thermal expansion causes the joint to be formed in the direction where the coefficient of thermal expansion is large. Although a large amount of stress is generated, it is possible to reduce the stress applied to the joint by matching the shape of the device with the coefficient of thermal expansion of the graphite plate.

In the simulation model MD, as shown in FIGS. 20 (a) and 20 (b), for example, a SiN-based ceramic substrate 21 of 10 mm (GX) × 21 mm (LY1) is used, and the semiconductor device 10 is bonded. As the source electrode pattern 22U2 to which the drain electrode pattern 22U1 and the block electrode (not shown) are joined, a Cu foil of 10 mm (GX) × 10 mm (LY) was used.

The drain electrode pattern 22U1 and the source electrode pattern 22U2 are separated by a distance LY2 = 1 mm.

The back surface electrode pattern 23D has the same dimensions (10 mm × 21 mm) as the ceramic substrate 21.

The graphite substrates 18GH1 and 18GH2 have the same dimensions (10 mm × 21 mm) as the drain electrode pattern 22U1 and the source electrode pattern 22U2.

As the semiconductor device 10, a square SiC MOSFET having 5 mm (H1) × 5 mm (C1) is used (H1 = C1), and the distance from the edge of the drain electrode pattern 22U1 is X1 (2.5 mm) and Y1 (2.5 mm). ), The silver fired portion 27 was used to bond the drain electrode pattern 22U1 to the substantially central portion.

The orientation of the coefficient of thermal expansion of the graphite substrates 18GH1 and 18GH2 was, for example, X = 25 ppm / K, Y = 0.1 ppm / K, and Z = 0.1 ppm / K.

As shown in FIG. 21, the thickness (mm) of each part is optimized so that the thermal resistance is the lowest. In the case of this simulation model MD, for example, the semiconductor device 10 is about 0.35 mm thick, the graphite substrates 18GH1 and 18GH2 are about 1.5 mm thick, the ceramic substrate 21 is about 0.32 mm thick, and the drain electrode patterns 22U1 and 22U2 are about 0. The thickness of the back electrode pattern 23D is about 0.2 mm, the thickness of the silver fired portion 27 is about 0.05 mm, and the thickness is optimized.

In such a configuration, for example, the stress applied to the silver calcined portion 27 can be obtained by calculating the Mises stress at 25 ° C., where no stress is set to 200 ° C.

In the simulation model MD having the configuration shown in FIG. 20, the orientation of the coefficient of thermal expansion of the graphite substrates 18GH1 and 18GH2 is set to, for example, X = 25ppm / K, Y = 0.5ppm / K, Z = 0.5ppm / K. FIG. 22 shows the result (overall warped shape) when a simulation was performed on the stress applied to the silver fired portion 27 in the case of the above.

The warp of the simulation model MD was 26.322 μm at the maximum value and 0.079 μm at the minimum value.

Next, simulation models with different configurations will be described. In the simulation model MD having the configuration shown in FIG. 20, the case where the square semiconductor devices 10 are joined is referred to as the simulation model MD1.

FIG. 23A illustrates a case (simulation model MD2) in which vertically long semiconductor devices (H2 × C2, H2> C2) 10a are joined in the simulation model MD having the configuration shown in FIG. 20. As the semiconductor device 10a, a rectangular SiC MOSFET having 6.25 mm (H2) × 4 mm (C2) is used, and the drain electrode pattern 22U1 is drained by the distances X2 (1.875 mm) and Y2 (3 mm) from the edge. It is joined to the substantially central portion on the electrode pattern 22U1.

FIG. 23 (b) illustrates a case (simulation model MD3) in which horizontally long semiconductor devices (H3 × C3, H3 <C3) 10b are joined in the simulation model MD having the configuration shown in FIG. 20. As the semiconductor device 10b, a rectangular SiC MOSFET having 4 mm (H3) × 6.25 mm (C3) is used, and the drain electrode pattern 22U1 is drained by the distance X3 (3 mm) and Y3 (1.875 mm) from the edge. It is joined to the substantially central portion on the electrode pattern 22U1.

FIG. 23 (c) illustrates a case (simulation model MD4) in which vertically long semiconductor devices (H4 × C4, H4 >> C4) 10c are joined in the simulation model MD having the configuration shown in FIG. 20. As the semiconductor device 10c, a rectangular SiC MOSFET having 8.33 mm (H4) × 3 mm (C4) is used, and the distance from the edge of the drain electrode pattern 22U1 is X4 (0.835 mm) and Y4 (3.5 mm). , Joined approximately in the center of the drain electrode pattern 22U1.

FIG. 23 (d) illustrates a case (simulation model MD5) in which horizontally long semiconductor devices (H5 × C5, H5 << C5) 10d are joined in the simulation model MD having the configuration shown in FIG. 20. As the semiconductor device 10d, a rectangular SiC MOSFET having 3 mm (H5) × 8.33 mm (C5) is used, and the distance from the edge of the drain electrode pattern 22U1 is X5 (3.5 mm) and Y5 (0.835 mm). , Joined approximately in the center of the drain electrode pattern 22U1.

FIG. 24A shows a case where a graphite substrate having an anisotropy in the coefficient of thermal expansion is applied in the power module according to the first to sixth embodiments, and simulations are performed using the simulation models MD1 to MD5. It is a characteristic diagram for explaining the relationship between the distance (Y1 to Y5) from the edge (EDG in FIGS. 20 (a) and 20 (b)) and the Mises stress (GPa) at that time, and is a characteristic diagram in FIG. 24 (. b) is a characteristic diagram for explaining the relationship between the simulation models MD1 to MD5 and the Mises stress ratio.

In FIGS. 24 (a) and 24 (b), the orientation of the coefficient of thermal expansion of the graphite substrate 18GH1 is, for example, X = 25 ppm / K, Y = 0.5 ppm / K, and Z = 0.5 ppm / K. As an example of the case, FIG. 24 (a) shows the Mises stress applied to the silver firing portion 27, and FIG. 24 (b) shows the case of the simulation model MD1 as 1 GPa.

From FIGS. 24 (a) and 24 (b), assuming that the Mieses stress ratio of the simulation model MD1 is 1, the Mieses stress ratio of the simulation models MD2 and MD4 is 1.05, and the Mieses stress ratio of the simulation model MD3 is 0.83. , The Mieses stress ratio of the simulation model MD5 is 0.84.

That is, a simulation model when the orientation of the coefficient of thermal expansion of the graphite substrate 18GH1 is, for example, X = 25 ppm / K, Y = 0.5 ppm / K, Z = 0.5 ppm / K, and the stress-free state is 200 ° C. The stress (at 25 ° C.) applied to the silver fired portions 27 of MD1 to MD5 can be reduced by reducing the size of the direction (X) having a large coefficient of thermal expansion like the semiconductor devices 10b and 10d of the models MD3 and MD5. Will be.

(Example 2)
Next, the stress applied to the silver fired portion 27 will be described by taking the case where there is no source electrode pattern as an example.

The schematic planar pattern configuration of the simulation model MD1 in the absence of the source electrode pattern is represented as shown in FIG. 25 (a), and the schematic cross-sectional structure along the VII-VII line of FIG. 25 (a) is shown. It is represented as shown in FIG. 25 (b).

The orientation of the coefficient of thermal expansion of the graphite substrate 18GH1 is, for example, X = 0.1ppm / K, Y = 25ppm / K, Z = 0.1ppm / K, and the thickness of each part (10.18GH1.21.22U1.27). (Mm) is optimized to have the lowest thermal resistance, as shown in FIG.

The simulation models MD2 and MD3 are almost the same except that the shapes of the semiconductor devices 10a and 10b are different.

FIG. 26A shows a case where a graphite substrate having an anisotropy in the coefficient of thermal expansion is applied in the power module according to the first to sixth embodiments, and simulations are performed using simulation models MD1 to MD3. FIG. 26 (b) is a characteristic diagram for explaining the relationship between the distance (X1 to X3) from the edge (EDG in FIGS. 25 (a) and 25 (b)) and the Mises stress at the time. , Is a characteristic diagram for explaining the relationship between the simulation models MD1 to MD3 and the Mises stress ratio.

In FIGS. 26 (a) and 26 (b), the orientation of the coefficient of thermal expansion of the graphite substrate 18GH1 is, for example, X = 0.5 ppm / K, Y = 25 ppm / K, and Z = 0.5 ppm / K. As an example of the case, FIG. 26A shows the Mises stress applied to the silver firing portion 27, and FIG. 26B shows the case of the simulation model MD1 as 1.

From FIGS. 26 (a) and 26 (b), assuming that the von Mises stress ratio of the simulation model MD1 is 1, the von Mises stress ratio of the simulation model MD2 is 0.96 and the von Mises stress ratio of the simulation model MD3 is 1.02. ..

That is, a simulation model when the orientation of the coefficient of thermal expansion of the graphite substrate 18GH1 is, for example, X = 0.5 ppm / K, Y = 25 ppm / K, Z = 0.5 ppm / K, and the stress-free state is 200 ° C. The stress (at 25 ° C.) applied to the silver fired portions 27 of MD1 to MD3 can be reduced by reducing the size of the direction (Y) having a large coefficient of thermal expansion like the semiconductor device 10a of the model MD2.

In the simulation models MD1 to MD3 having the configuration shown in FIG. 25, when the orientation of the coefficient of thermal expansion of the graphite substrate 18GH1 is, for example, X = 0.1 ppm / K, Y = 25 ppm / K, Z = 0.1 ppm / K. The results (overall warped shape) of the above when the stress applied to the silver fired portion 27 was simulated are shown in FIGS. 27 (a) to 27 (c).

The maximum value of the warp of the simulation model MD1 is 22.599 μm and the minimum value is 0.128 μm, and the maximum value of the warp of the simulation model MD2 is 22.313 μm and the minimum value is 0.146 μm. The maximum value of the warp was 22.972 μm and the minimum value was 0.322 μm.

In PM1 according to the first to sixth embodiments, the case where it is applied to the 1 in 1 module type as a semiconductor device has been described, but the present invention is not limited to this, and for example, a 2 in 1 (two-in-one) module type. PM, 4 in 1 (four-in-one) module type PM, 6 in 1 (six-in-one) module type PM, and 7 in 1 (seven-in-one) module type PM equipped with a snubber capacitor in the 6 in 1 module. , 8 in 1 (eight-in-one) module type PM, 12 in 1 (twelve-in-one) module type PM, 14 in 1 (fourteen-in-one) module type PM, and the like.

(Specific examples of semiconductor devices)
The schematic circuit representation of the SiC MOSFET of the 1 in 1 module 50 of PM1 according to the first to sixth embodiments, which is applicable as a semiconductor device, is shown as shown in FIG. 28.

FIG. 28 shows a diode DI connected in antiparallel to MOSFET Q. The main electrode of MOSFET Q is represented by a drain terminal DT and a source terminal ST. Further, it is also possible to realize (not shown) an IGBT of the 1 in 1 module 50 which is PM1 according to the first to sixth embodiments and can be applied as a semiconductor device.

Further, the detailed circuit representation of the SiC MOSFET of the 1 in 1 module 50 of PM1 according to the first to sixth embodiments, which is applicable as a semiconductor device, is shown as shown in FIG. 29.

In PM1 according to the first to sixth embodiments, for example, the semiconductor device has a configuration of a 1 in 1 module 50. That is, one MOSFET Q is built in one module. As an example, 5 chips (MOSFETs × 5) can be mounted, and up to 5 MOSFETs Q can be connected in parallel. It is also possible to mount a part of the five chips for diode DI.

More specifically, as shown in FIG. 29, sense MOSFETs Qs are connected in parallel with MOSFET Qs. The sense MOSFET Qs are formed as fine transistors in the same chip as the MOSFET Q.

In FIG. 29, SS is a source sense terminal, CS is a current sense terminal, and G is a gate signal terminal. Also in the first to sixth embodiments, the sense MOSFET Qs may be formed as fine transistors in the same chip in the semiconductor device Q.

(Circuit configuration)
Next, in PM1 according to the first to sixth embodiments, a circuit configuration example of the semiconductor device will be described more specifically.

Here, a module applicable as a semiconductor device of PM1 according to the first to sixth embodiments, a semiconductor package device in which two semiconductor devices Q1 and Q4 are sealed in one mold resin. A so-called 2 in 1 type module will be described.

The circuit configuration of the 2 in 1 module 130A to which the SiC MOSFET is applied as the semiconductor devices Q1 and Q4 is shown, for example, as shown in FIG.

That is, as shown in FIG. 30, the 2 in 1 module 130A includes a half-bridge built-in module in which two SiC MOSFETs Q1 and Q4 are built in as one module.

Here, the module can be regarded as one large transistor, but the built-in transistor may be one chip or a plurality of chips. That is, there are 1 in 1, 2 in 1, 4 in 1, 6 in 1 modules, etc. For example, a module containing two transistors (chips) on one module is 2 in 1, A module containing two sets of 2 in 1 is called 4 in 1, and a module containing three sets of 2 in 1 is called 6 in 1.

As shown in FIG. 30, the 2 in 1 module 130A contains two SiC MOSFETs Q1 and Q4 and diodes DI1 and DI4 connected in antiparallel to the SiC MOSFETs Q1 and Q4 as one module.

In FIG. 30, G1 is a lead terminal for the gate signal of the SiC MOSFET Q1, and S1 is a lead terminal for the source signal of the SiC MOSFET Q1. Similarly, G4 is a lead terminal for the gate signal of the SiC MOSFET Q4, and S4 is a lead terminal for the source signal of the SiC MOSFET Q4.

Further, P is a positive power input terminal electrode, N is a negative power input terminal electrode, and O is an output terminal electrode.

Further, a module applicable as a semiconductor device of PM1 according to the first to sixth embodiments, in which a 2 in 1 module (not shown) to which an IGBT is applied is realized as the semiconductor devices Q1 and Q4. You can also.

The same applies to the semiconductor devices Q2 and Q5 and the semiconductor devices Q3 and Q6 applicable to PM1 according to the first to sixth embodiments.

(Device structure)
An example of the semiconductor devices Q1 and Q4 applicable to PM1 according to the first to sixth embodiments, the schematic cross-sectional structure of the SiC MOSFET 130A including the source pad electrode SP and the gate pad electrode GP is shown in FIG. 31. It is expressed as shown in.

As shown in FIG. 31, the SiC MOSFET 130A is formed on the surface of the semiconductor layer 31 composed of the n-high resistance layer, the p-body region 32 formed on the surface side of the semiconductor layer 31, and the p-body region 32. In the source region 33, the gate insulating film 34 arranged on the surface of the semiconductor layer 31 between the p body regions 32, the gate electrode 35 arranged on the gate insulating film 34, and the source region 33 and the p body region 32. It includes a connected source electrode 36, an n + drain region 37 arranged on the back surface opposite to the front surface of the semiconductor layer 31, and a drain electrode 38 connected to the n + drain region 37.

The gate pad electrode GP is connected to the gate electrode 35 arranged on the gate insulating film 34, and the source pad electrode SP is connected to the source electrode 36 connected to the source region 33 and the p body region 32. Further, as shown in FIG. 31, the gate pad electrode GP and the source pad electrode SP are arranged on the passive interlayer insulating film 39 covering the surface of the SiC MOSFET 130A.

Although not shown, a transistor structure having a fine structure may be formed in the semiconductor layer 31 below the gate pad electrode GP and the source pad electrode SP.

Further, as shown in FIG. 31, in the transistor structure in the central portion, the source pad electrode SP may be extended and arranged on the passive interlayer insulating film 39.

In FIG. 31, the SiC MOSFET 130A is composed of a planar gate type n-channel vertical SiC MOSFET, and as shown in FIG. 34 described later, a trench gate type n-channel vertical SiC T (Trench) MOSFET 130C. It may be composed of such as.

Alternatively, as the semiconductor devices Q1 and Q4 applicable to PM1 according to the first to sixth embodiments, a GaN-based FET or the like can be adopted instead of the SiC MOSFET 130A.

The same applies to the semiconductor devices Q2 and Q5 and the semiconductor devices Q3 and Q6 applicable to PM1 according to the first to sixth embodiments.

Further, the semiconductor devices Q1 to Q6 applicable to PM1 according to the first to sixth embodiments include semiconductors having a bandgap energy of, for example, 1.1 eV to 8 eV, which is called a wide bandgap type. Can be used.

Similarly, in the example of the semiconductor devices Q1 and Q4 applicable to PM1 according to the first to sixth embodiments, the schematic cross-sectional structure of the IGBT 130B including the emitter pad electrode EP and the gate pad electrode GP is It is represented as shown in FIG.

As shown in FIG. 32, the IGBT 130B has a semiconductor layer 31 composed of an n-high resistance layer, a p-body region 32 formed on the surface side of the semiconductor layer 31, and an emitter formed on the surface of the p-body region 32. Connected to the region 33E, the gate insulating film 34 arranged on the surface of the semiconductor layer 31 between the p-body regions 32, the gate electrode 35 arranged on the gate insulating film 34, and the emitter region 33E and the p-body region 32. The emitter electrode 36E is provided, a p + collector region 37P arranged on the back surface opposite to the front surface of the semiconductor layer 31, and a collector electrode 38C connected to the p + collector region 37P.

The gate pad electrode GP is connected to the gate electrode 35 arranged on the gate insulating film 34, and the emitter pad electrode EP is connected to the emitter electrode 36E connected to the emitter region 33E and the p body region 32. Further, as shown in FIG. 32, the gate pad electrode GP and the emitter pad electrode EP are arranged on the passive interlayer insulating film 39 covering the surface of the IGBT 130B.

Although not shown, an IGBT structure having a fine structure may be formed in the semiconductor layer 31 below the gate pad electrode GP and the emitter pad electrode EP.

Further, as shown in FIG. 32, even in the central IGBT structure, the emitter pad electrode EP may be extended and arranged on the passive interlayer insulating film 39.

In FIG. 32, the IGBT 130B is composed of a planar gate type n-channel vertical IGBT, but may be composed of a trench gate type n-channel vertical IGBT or the like.

The same applies to the semiconductor devices Q2 and Q5 and the semiconductor devices Q3 and Q6 applicable to PM1 according to the first to sixth embodiments.

As the semiconductor devices Q1 to Q6, a SiC power device such as a SiC DI MOSFET or a SiC T MOSFET, or a GaN power device such as a GaN high electron mobility transistor (HEMT) can be applied. In some cases, power devices such as Si-based MOSFETs and IGBTs can also be applied.

―SiC DI MOSFET―
An example of a semiconductor device applicable to PM1 according to the first to sixth embodiments, the schematic cross-sectional structure of the SiC DI MOSFET 130D is represented as shown in FIG. 33.

The SiC DI MOSFET 130D shown in FIG. 33 has a semiconductor layer 31 composed of an n-high resistance layer, a p-body region 32 formed on the surface side of the semiconductor layer 31, and n + formed on the surface of the p-body region 32. In the source region 33, the gate insulating film 34 arranged on the surface of the semiconductor layer 31 between the p body regions 32, the gate electrode 35 arranged on the gate insulating film 34, and the source region 33 and the p body region 32. It includes a connected source electrode 36, an n + drain region 37 arranged on the back surface opposite to the front surface of the semiconductor layer 31, and a drain electrode 38 connected to the n + drain region 37.

In FIG. 33, in the SiC DI MOSFET 130D, a p-body region 32 and an n + source region 33 formed on the surface of the p-body region 32 are formed by double ion implantation (DII), and the source pad electrode SP is a source. It is connected to the source electrode 36 connected to the region 33 and the p-body region 32.

The gate pad electrode GP (not shown) is connected to the gate electrode 35 arranged on the gate insulating film 34. Further, as shown in FIG. 33, the source pad electrode SP and the gate pad electrode GP are arranged on the passive interlayer insulating film 39 so as to cover the surface of the SiC DI MOSFET 130D.

As shown in FIG. 33, the SiC DI MOSFET 130D is a junction type because a depletion layer as shown by a broken line is formed in a semiconductor layer 31 composed of an n-high resistance layer sandwiched between p body regions 32. A channel resistance R _JFET is formed due to the FET (JFET) effect. Further, as shown in FIG. 33, a body diode BD is formed between the p-body region 32 and the semiconductor layer 31.

―SiC T MOSFET―
An example of a semiconductor device applicable to PM1 according to the first to sixth embodiments, a schematic cross-sectional structure of a SiC T MOSFET is represented as shown in FIG. 34.

The SiC T MOSFET 130C shown in FIG. 34 has a semiconductor layer 31N composed of n layers, a p-body region 32 formed on the surface side of the semiconductor layer 31N, and an n + source region 33 formed on the surface of the p-body region 32. The trench gate electrode 35TG formed through the p-body region 32 and formed through the gate insulating film 34 and the interlayer insulating films 39U / 39B in the trench formed up to the semiconductor layer 31N, and the source region 33 and the p-body region. It includes a source electrode 36 connected to 32, an n + drain region 37 arranged on the back surface opposite to the front surface of the semiconductor layer 31N, and a drain electrode 38 connected to the n + drain region 37.

In FIG. 34, the SiC T MOSFET 130C penetrates the p-body region 32, and the trench gate electrode 35TG is formed in the trench formed up to the semiconductor layer 31N via the gate insulating film 34 and the interlayer insulating films 39U / 39B. The source pad electrode SP is connected to the source electrode 36 connected to the source region 33 and the p body region 32.

The gate pad electrode GP (not shown) is connected to the trench gate electrode 35TG arranged on the gate insulating film 34. Further, as shown in FIG. 34, the source pad electrode SP and the gate pad electrode GP are arranged on the passive interlayer insulating film 39U so as to cover the surface of the SiC T MOSFET 130C.

In the SiC T MOSFET 130C, the channel resistance R _JFET associated with the junction FET (JFET) effect such as the SiC DI MOSFET 130D is not formed. Further, a body diode BD is formed between the p-body region 32 and the semiconductor layer 31N, as in FIG. 33.

(Application example)
It is a three-phase AC inverter 40A configured by using PM1 according to the first to sixth embodiments, a SiC MOSFET is applied as a semiconductor device, and a snubber capacitor C is connected between a power supply terminal PL and a ground terminal NL. An example of the circuit configuration is shown in FIG. 35.

Similarly, an IGBT can be applied as a semiconductor device to realize a three-phase AC inverter (not shown) in which a snubber capacitor C is connected between the power supply terminal PL and the ground terminal NL.

When the PM1 is connected to the power supply E and the switching operation is performed, the switching speed of the SiC MOSFET or the IGBT is high due to the inductance L of the connection line, so that a large surge voltage Ldi / dt is generated. For example, if the current change di = 300A and the time change dt = 100nsec accompanying switching, then di / dt = 3 × 10 ⁹ (A / s).

The value of the surge voltage Ldi / dt changes depending on the value of the inductance L, but the surge voltage Ldi / dt is superimposed on the power supply E. This surge voltage Ldi / dt can be absorbed by the snubber capacitor C connected between the power supply terminal PL and the ground terminal NL.

(Concrete example)
Next, with reference to FIG. 36, a three-phase AC inverter 42A configured by applying a SiC MOSFET as a semiconductor device and using PM1 according to the first to sixth embodiments will be described.

As shown in FIG. 36, the three-phase AC inverter 42A includes a power module unit 130 connected to the gate driver (GD) 180, a three-phase AC motor unit 51, a power supply or storage battery (E) 53, and a converter 55. To prepare for. The power module unit 130 is connected to a U-phase, V-phase, and W-phase inverter corresponding to the U-phase, V-phase, and W-phase of the three-phase AC motor unit 51.

Here, the GD180 is connected to the SiC MOSFETs Q1 and Q4, the SiC MOSFETs Q2 and Q5, and the SiC MOSFETs Q3 and Q6.

The power module unit 130 is connected between the positive terminal (+) P and the negative terminal (-) N of the converter 55 to which the power supply or the storage battery (E) 53 is connected, and is connected to the SiC MOSFETs Q1, Q4, and Q2 having an inverter configuration. -Provides Q5 and Q3 / Q6. Further, freewheel diodes DI1 to DI6 are connected in antiparallel between the source and drain of the SiC MOSFETs Q1 to Q6, respectively.

Further, although not shown, it is also possible to apply an IGBT as a semiconductor device and realize a three-phase AC inverter configured by using PM1 according to the first to sixth embodiments.

As described above, according to the first to sixth embodiments, PM is realized which is inexpensive, can exhibit cooling performance not inferior to the double-sided cooling structure, and can simultaneously reduce stress. can.

In the PM according to the first to sixth embodiments, the module applicable as a semiconductor device may be, for example, a molded power module having a 4-terminal electrode structure or the like.

Further, the semiconductor device applicable to the PM according to the first to sixth embodiments is not limited to the SiC-based power device, but is a power called a wide bandgap type such as a GaN-based power device or a Si-based power device. Devices can also be adopted.

Further, it can be applied not only to a resin-molded mold-type power module but also to a power module packaged by a case-type package.

[Comparative example in the seventh embodiment]
First, the power module according to the comparative example in the seventh embodiment will be described. Here, as one of the power modules, a power module in which the outer circumference of a power device (semiconductor device) including a power element (chip) such as an IGBT is molded with a resin is exemplified.

(Single-sided cooling structure: air cooling)
The schematic cross-sectional structure of the power module according to the comparative example in the seventh embodiment is shown as shown in FIG. 37. The power module according to the comparative example in the seventh embodiment employs a single-sided cooling structure (air cooling). Specifically, as shown in FIG. 37, the heat sink 105 is arranged on the lower surface of the power module 107 via the bonding material 106. Due to the single-sided cooling structure (air cooling), the cooling capacity is low. Such power modules are used for industrial machine power modules and the like.

(Single-sided cooling structure: water cooling)
The schematic cross-sectional structure of the power module according to the comparative example in the seventh embodiment is shown as shown in FIG. 38. The power module according to the comparative example in the seventh embodiment employs a single-sided cooling structure (water cooling). Specifically, as shown in FIG. 38, the water cooler 111 is arranged on the lower surface of the power module 113 via the bonding material 112. Due to the single-sided cooling structure (water cooling), the cooling capacity is higher than that of the single-sided cooling structure (air cooling), but inferior to that of the double-sided cooling structure (water cooling). Such power modules are used in today's general in-vehicle modules.

(Double-sided cooling structure: water cooling)
The schematic cross-sectional structure of the power module according to the comparative example in the seventh embodiment is shown as shown in FIG. 39. The power module according to the comparative example in the seventh embodiment employs a double-sided cooling structure (water cooling). Specifically, as shown in FIG. 39, the water cooler 121 is arranged on the lower surface of the power module 123 via the bonding material 122A. Further, a water cooler 124 is arranged on the upper surface of the power module 123 via the bonding material 122B. Since it is water-cooled on both sides, the cooling capacity is very high, but since it requires two coolers, it is difficult to assemble and it is very expensive. Such power modules will be used in next-generation in-vehicle modules.

[7th Embodiment]
Next, the power module according to the seventh embodiment will be described. Here, too, the power module 1 in which the outer circumference of the power device is molded with resin is illustrated.

(Basic structure)
The schematic cross-sectional structure of the power module according to the seventh embodiment is shown as shown in FIG. 40. Further, the schematic cross-sectional structure of the graphite plate 18GP included in the power module shown in FIG. 40 is represented as shown in FIG. 41. The arrows in the figure indicate the direction of high thermal conductivity in the graphite plate 18GP.

As shown in FIGS. 40 and 41, the power module according to the seventh embodiment has a lower surface (first surface) and an upper surface (second surface) facing the lower surface, and is used during an operation as described later. A power module 1 that encloses a semiconductor circuit that generates heat, one side of which is a surface to which a water cooling cooler 28 arranged on the lower surface side of the power module 1 and a lower surface of the power module 1 of the cooler 28 are joined. A graphite plate 18GP with the other surface bonded to the upper surface of the power module 1 is provided, and the power module 1 is arranged between the second graphite plates 18GP (XZ) 1 and 18GP (XZ) 2. .. The graphite plate 18GP has a structure in which two types of graphite plates 18GP having different thermal conductivity orientations are bonded together in a direction having high thermal conductivity.

Although the details will be described later, the graphite plate 18GP has a structure in which the second graphite plates 18GP (XZ) 1 and 18GP (XZ) 2 are bonded to the first graphite plate 18GP (XY) in orthogonal directions. There is. The orthogonality referred to here may be substantially orthogonal and may include some error.

Further, the first graphite plate 18GP (XY) has an XY orientation (first orientation) in which the thermal conductivity is higher in the plane direction than in the thickness direction.

Further, the first graphite plate 18GP (XY) may have a plate structure in which a plurality of graphite sheets GS having XY orientation are laminated (see FIG. 6).

Further, the second graphite plates 18GP (XZ) 1 and 18GP (XZ) 2 may have an XZ orientation (second orientation) in which the thermal conductivity is higher in the thickness direction than in the plane direction.

Further, the second graphite plates 18GP (XZ) 1 and 18GP (XZ) 2 have a plate structure in which a plurality of graphite sheets GS having XZ orientation are laminated (see FIG. 6).

Further, the upper surface (one side) of the second graphite plates 18GP (XZ) 1, 18GP (XZ) 2 is bonded to the first graphite plate 18GP (XY), and the second graphite plates 18GP (XZ) 1, The lower surface (the other surface) of 18GP (XZ) 2 is joined to the cooler 28.

Further, a plurality of second graphite plates 18GP (XZ) 1, 18GP (XZ) 2 may be bonded to the same surface of one first graphite plate 18GP (XY).

In addition, a plurality of power modules 1 ₁ , 1 ₂ and 1 ₃ are built in, and a second graphite plate 18GP (XZ) 3, 18GP (XZ) is connected to each of the plurality of power modules 1 ₁ , 1 ₂ and 1 ₃ . 4 may be arranged (see FIG. 52).

Further, a metal layer such as the Cu layer 5 may be formed on both sides of at least a part of the graphite plate 18GP (see FIGS. 49 and 52).

Further, the power module 1 has a power terminal P, N, an output terminal O, and a signal unit terminal RT, and is covered with a mold resin except for a part of each terminal P, N, O (see FIG. 46).

Further, the upper electrode 1I may be exposed from the upper surface of the mold resin, and the lower electrode 1A may be exposed from the lower surface of the mold resin (see FIG. 53).

Further, although solder or silver firing is used as the bonding material 3D of the upper electrode 1I and the graphite plate 18GP, other bonding materials having good thermal conductivity may be used (see FIG. 53).

Further, although solder or silver firing is used as the bonding material 3A between the lower electrode 1A and the cooler 28, other bonding materials having good thermal conductivity may be used (see FIG. 53).

Further, the radiator F may be arranged on the surface of the graphite plate 18GP opposite to the joint surface with the upper surface of the power module 1 (see FIG. 52).

Further, the cooler 28 is a water cooler in which a coolant WR flows inside, and as the coolant WR, for example, water or a mixed solution of water and ethylene glycol mixed at a ratio of 50% each is used.

Further, the power module 1 includes a power semiconductor of any one of a Si-based or SiC-based IGBT, a diode, a MOSFET, and a GaN-based FET.

Further, the power module 1 may be configured as any one of a one-in-one module, a two-in-one module, a four-in-one module, a six-in-one module, a seven-in-one module, an eight-in-one module, a twelve-in-one module, or a fourteen-in-one module.

Further, the power module 1 may be configured as an inverter or a converter by using a six-in-one module type.

Further, a substrate (for example, a lower insulating substrate) which is connected in series between the first power supply terminal P and the second power supply terminal N and has an upper surface (first surface) and a lower surface (second surface) facing the upper surface. 20D) has a power device 1E arranged on the upper surface and a cooler 28 arranged on the lower surface side of the substrate, and is configured to connect the connection point of the power device 1E to the output terminal O. In the module 1, the power device 1E has a lower surface (first surface) and an upper surface (second surface) facing the lower surface, and has a lower surface side of the substrate of the cooler 28 and an upper surface side of the power device 1E. A graphite plate 18GP that is thermally connected is provided, and the graphite plate 18GP has a structure in which two types of graphite plates 18GP having different thermal conduction orientations are bonded together in a direction having high thermal conductivity (see FIG. 53).

The joining surfaces 7A and 7B of the first graphite plate 18GP (XY) and the second graphite plates 18GP (XZ) 1, 18GP (XZ) 2 shown in FIG. 41 are joined by brazing. Other bonding methods with good thermal conductivity may be used.

(Graphite plate)
In the power module according to the seventh embodiment, two types of graphite plates having different orientations are used as the graphite plate 18GP.

A schematic configuration (example of laminated structure) of the graphite sheet (graphene) GS constituting the graphite plate 18GP is shown as shown in FIG.

The graphite plate 18GP has a first graphite plate 18GP (XY) having an XY orientation (first orientation) having a higher thermal conductivity in the plane direction than the thickness direction, and the graphite plate 18GP has a thermal conductivity in the thickness direction rather than the plane direction. There is a second graphite plate 18GP (XZ) with a high XZ orientation (second orientation), the first graphite plate 18GP (XY) is represented as shown in FIG. 6 (a) and the second The graphite plate 18GP (XZ) is represented as shown in FIG. 6 (b).

As shown in FIG. 5, the graphite sheets GS1, GS2, GS3, ..., GSn on each surface composed of n layers have a large number of hexagonal covalent bonds in one laminated crystal structure, and each surface has a covalent bond. The graphite sheets GS1, GS2, GS3, ..., and GSn are bonded by a van der Waals force.

That is, graphite, which is a carbon-based anisotropic heat transfer material, is a layered crystal having a hexagonal network structure of carbon atoms, and has anisotropy in heat conduction. Graphite sheets GS1, GS2, shown in FIG. GS3 ..... GSn has a higher thermal conductivity (high thermal conductivity) in the crystal plane direction (on the XY plane) than in the thickness direction of the Z axis.

Therefore, as shown in FIG. 6A, the first graphite plate 18GP (XY) having XY orientation is, for example, X = 1500 (W / mK), Y = 1500 (W / mK), Z. It has a thermal conductivity of about 5 (W / mK).

On the other hand, as shown in FIG. 6B, the second graphite plate 18GP (XZ) having the XZ orientation has, for example, X = 1500 (W / mK), Y = 5 (W / mK), Z. = It has a thermal conductivity of about 1500 (W / mK).

Both the first graphite plate 18GP (XY) and the second graphite plate 18GP (XZ) have a density of about 2.2 (g / cm ³ ) and a thickness of about 0.7 mm to 10 mm. Yes, the size is about 40 mm × 40 mm or less.

[Comparison of thermal resistance]
Next, the relationship between the cooling structure and the thermal resistance will be described.

(Single-sided cooling structure)
A schematic cross-sectional structure showing a structural model of thermal resistance simulation of a power module having a single-sided cooling structure according to a comparative example in the seventh embodiment is shown as shown in FIG. 42. Further, a schematic upper surface configuration when the SiC chip 113E of the structural model shown in FIG. 42 is viewed from above is shown as shown in FIG. 43.

In the thermal resistance simulation of this single-sided cooling structure, for example, as shown in FIG. 42, the thickness of the SiC chip 113E is 0.35 mm, the thickness of the silver firing portion 113D is 0.06 mm, and the thickness of the Cu layer 113C is 1. 0.0 mm, Si ₃ N ₄ layer 113B thickness is 0.25 mm, Cu layer 113A thickness is 1.0 mm, SnAg solder 112 thickness is 0.2 mm, cooler (Al layer) 111 thickness is It was set to 1.0 mm. Further, as shown in FIG. 43, for example, the size of the SiC chip 113E is 5 mm × ₅ mm, the size of the Si 3N ₄ layer 113B is 15 mm × 15 mm, and the size of the cooler (Al layer) 111 is 25 mm × 25 mm. When such a single-sided cooling structure is adopted, for example, the thermal resistance is 0.304 (° C./W).

(Double-sided cooling structure)
The schematic cross-sectional structure showing the structural model of the thermal resistance simulation of the power module of the double-sided cooling structure according to the comparative example in the seventh embodiment is shown as shown in FIG. 44. Here, too, a schematic upper surface configuration when the SiC chip 123E is viewed from above will be described with reference to FIG. 43.

In the thermal resistance simulation of this double-sided cooling structure, as shown in FIG. 44, for example, the thickness of the cooler (Al layer) 124 is 1.0 mm, the thickness of the SnAg solder 122B is 0.2 mm, and the thickness of the Cu layer 123I. The solder is 1.5 mm, the thickness of the Si 3N ₄ layer _123H is 0.25 mm, the thickness of the Cu layer 123G is 1.5 mm, the thickness of the silver fired portion 123F is 0.06 mm, and the thickness of the SiC chip 123E is The thickness of the silver fired portion 123D is 0.06 mm, the thickness of the Cu layer 123C is 1.0 mm, the thickness of the Si _{3N 4 layer} 123B is 0.25 mm, and the thickness of the Cu layer 123A is 1. The thickness of the 0 mm, SnAg solder 122A was 0.2 mm, and the thickness of the cooler (Al layer) 121 was 1.0 mm. Further, as shown in FIG. 43, for example, the size of the SiC chip 123E is 5 mm × ₅ mm, the size of the Si 3N ₄ layer 123B is 15 mm × 15 mm, and the size of the cooler (Al layer) 121 is 25 mm × 25 mm. Further, although not shown, the size of the joint portion (silver fired portion 123F) on the SiC chip 123E is set to 3 mm × 3 mm, for example. When such a double-sided cooling structure is adopted, for example, the thermal resistance is 0.184 (° C./W), which is about 40% lower than that of the single-sided cooling structure.

(Half-sided cooling structure)
The schematic cross-sectional structure showing the structural model of the thermal resistance simulation of the power module of the half-sided cooling structure according to the seventh embodiment is shown as shown in FIG. 45. Here, too, a schematic upper surface configuration when the SiC chip 1E is viewed from above will be described with reference to FIG. 43.

In the thermal resistance simulation of this half-sided cooling structure, for example, as shown in FIG. 45, the thickness of the first graphite plate 18GP (XY) is 1.0 mm, and the width of the second graphite plate 18GP (XZ) is 2 mm. , SnAg solder _3D has a thickness of 0.2 mm, Cu layer 1I has a thickness of 1.5 mm, Si 3N ₄ layer 1H has a thickness of 0.25 mm, Cu layer 1G has a thickness of 1.5 mm, and is fired with silver. The thickness of the portion 1F is 0.06 mm, the thickness of the SiC chip 1E is 0.35 mm, the thickness of the silver fired portion 1D is 0.06 mm, the thickness of the Cu layer 1C is 1.0 mm, and the thickness of the Si _{3N 4 layer} 1B. The thickness of the Cu layer 1A was 1.0 mm, the thickness of the SnAg solders 3A, 3B, and 3C was 0.2 mm, and the thickness of the cooler (Al layer) 2 was 1.0 mm. .. Further, as shown in FIG. 43, for example, the size of the SiC chip 1E is 5 mm × 5 mm, the size of the Si _{3N 4 layer} 1B is 15 mm × 15 mm, and the size of the cooler (Al layer) 2 is 25 mm × 25 mm. Further, although not shown, the size of the joint portion (silver fired portion 1F) on the SiC chip 1E is, for example, 3 mm × 3 mm. When such a half-sided cooling structure is adopted, for example, the thermal resistance is 0.209 (° C./W), which is about 32% lower than that of the single-sided cooling structure. That is, it was found that one cooler has a cooling capacity close to that of double-sided cooling.

As described above, in the power module according to the seventh embodiment, two graphite plates 18GP having different orientations are bonded together by utilizing the anisotropic thermal conductivity of graphite, and the roles of the two coolers for double-sided cooling are used. Is fulfilled only by the cooler (water cooler) 2. Therefore, for example, heat is spread in the XY direction with a high thermal conductivity of about 1500 W / m · K, and the temperature of the cooler 28 reaches almost the upper part of the power module with a high thermal conductivity of about 1500 W / m · K. .. This makes it possible for one cooler 28 to have a cooling capacity comparable to that of a double-sided cooler in a simulated manner.

The bonding materials 3A, 3B, 3C, and 3D are not limited to solder and silver firing, and may be compounds or grease. However, when a compound or grease is used, the thermal resistance increases, so it is desirable to use solder or silver firing.

[Concrete example]
Next, a specific example of the power module according to the seventh embodiment will be described.

A schematic plane pattern configuration showing a specific example of the power module according to the seventh embodiment is shown as shown in FIG. 46 (a). Further, the schematic cross-sectional structure along the line VIII-VIII of FIG. 46 (a) is represented as shown in FIG. 46 (b). Further, the schematic right side configuration of the power module shown in FIG. 46 (a) is represented as shown in FIG. 46 (c). The "right side" here is the side seen from the side without terminals.

In this power module, a 2 in 1 module type power module shown in FIG. 30 is adopted as a power device. Specifically, as shown in FIG. 46, a power module 1 in which a power device is sealed is provided, and power terminals P and N for supplying power to the power device and output terminals O for outputting power from the power device. It has a signal unit terminal RT that controls the operation of the power device. The signal unit terminal RT is bent and connected to the gate drive. The power terminals P and N, the output terminal O, and a part of the signal unit terminal RT may be covered with a mold resin.

In this example, the first graphite plate 18GP (XY) has a size larger than the upper surface of the power module 1, and the second graphite plates 18GP (XZ) 1, 18GP (XZ) 2 have the same size as the power module 1. It is said to be the height of. According to such a graphite plate 18GP, it is possible to effectively cool the upper surface side of the power module 1.

Further, the second graphite plates 18GP (XZ) 1 and 18GP (XZ) 2 are bonded to both ends of the first graphite plate 18GP (XY). As a result, a loop-shaped graphite plate 18GP joined to the cooler 28 is configured, and the power module 1 can be arranged inside the loop. According to such a graphite plate 18GP, it is possible to spread heat in the XY and XZ directions with high thermal conductivity and exhibit high cooling capacity.

Of course, the size, number, shape, positional relationship, etc. of the first graphite plate 18GP (XY) and the second graphite plates 18GP (XZ) 1, 18GP (XZ) 2 can be appropriately changed. For example, as shown in FIG. 46 (b), both ends of the first graphite plate 18GP (XY) in the X direction are outward from the second graphite plates 18GP (XZ) 1, 18GP (XZ) 2. It may project slightly toward the surface, or the end face of the second graphite plate 18GP (XZ) may be flush with the outer surface of the first graphite plate 18GP (XY).

[Modification example]
Next, a modification of the power module according to the seventh embodiment will be described.

(Stress reduction structure)
The schematic cross-sectional structure of the power module according to the seventh embodiment is shown in FIG. 47 (a). Further, an enlarged cross-sectional structure obtained by enlarging the portion of the display A in FIG. 47 (a) is shown as shown in FIG. 47 (b).

The synthetic thermal expansion rate (CTE) of the power module 1 itself is dominated by the resin of the mold, so that the portion of display B shown in FIG. 47 (b) is most stressed. The portion of the display B is a joint portion (hereinafter, simply referred to as “joint portion”) of the bonding material 3D that joins the power module 1 and the graphite plate 18GP with the graphite plate 18GP. The Mises stress applied to the joint can be obtained by the following definition formula.

Here, the Mises stress is one of the equivalent stresses used to indicate the stress state generated inside the object with a single value. In the definition formula, σ1 is the maximum principal stress, σ2 is the intermediate principal stress, and σ3 is the minimum principal stress. Here, each of the principal stresses σ1, σ2, and σ3 is selected from the principal stress in the X direction, the principal stress in the Y direction, and the principal stress in the Z direction acting on the joint portion.

A schematic cross-sectional structure showing a modification of the graphite plate 18GP included in the power module according to the seventh embodiment is shown as shown in FIG. 48. As shown in FIG. 48, Cu layers 5 thinner than the graphite plate 18GP are formed on both sides of the graphite plate 18GP. Here, the Cu layer 5 is illustrated, but other metals, ceramics, and the like may be used instead of Cu.

The schematic cross-sectional structure of the power module using the graphite plate 18GP shown in FIG. 48 is represented as shown in FIG. As shown in FIG. 49, the Cu layer 5A is formed on the upper surface and the lower surface of the first graphite plate 18GP (XY). Further, Cu layers 5B1, 5C1 are formed on the side surfaces of the second graphite plates 18GP (XZ) 1, 18GP (XZ) 2. This makes it possible to reduce the Mises stress applied to the joint portion by matching it with the synthetic CTE of the power module 1.

The schematic cross-sectional structure of another power module using the graphite plate 18GP shown in FIG. 48 is represented as shown in FIG. The difference from FIG. 49 is that Cu layers 5B2, 5C2 are formed on the upper surface and the lower surface of the second graphite plates 18GP (XZ) 1, 18GP (XZ) 2. In this case as well, it is possible to reduce the Mises stress applied to the joint portion by adjusting to the synthetic CTE of the power module 1.

(Heat sink)
A schematic cross-sectional structure showing a modification of the power module according to the seventh embodiment is shown as shown in FIG. 52. As shown in FIG. 52, a radiator (fin) F made of metal, ceramic, graphite or the like may be arranged on the first graphite plate 18GP (XY). As a result, heat can be dissipated from the upper surface of the first graphite plate 18GP (XY), so that the cooling capacity can be further increased.

(6in1 module)
A schematic plane pattern configuration showing a modification of the power module according to the seventh embodiment is shown as shown in FIG. 52 (a). Further, the schematic cross-sectional structure along the IX-IX line of FIG. 52 (a) is represented as shown in FIG. 52 (b).

In this power module, a 6 in 1 (six-in-one) module type power module is adopted as a power device. Specifically, as shown in FIG. 52, power terminals (P 1, N 1), which include power modules 1 ₁ , _{1 2} and 13 in which the power device is sealed and supply power to the power device, (P ₁ , N ₁ ), ( P ₂ , N ₂ ), (P ₃ , N ₃ ), output terminals O ₁ , O ₂ , O ₃ that output from the power device, and signal terminal RT ₁ , RT ₂ that controls the operation of the power device. , RT ₃ and. The signal terminals RT ₁ , RT ₂ , and RT ₃ are bent and connected to the gate drive circuit. One of the power terminals (P ₁ , N ₁ ), (P ₂ , N ₂ ), (P ₃ , N ₃ ), output terminals O ₁ , O ₂ , O ₃ and signal terminal RT ₁ , RT ₂ , RT ₃ Except for the part, it is covered with mold resin.

In such a 6 in 1 module type, the first graphite plate 18GP (XY) becomes longer in the X direction. Therefore, not only the second graphite plates 18GP (XZ) 1, 18GP (XZ) 2 are bonded to both ends of the first graphite plate 18GP (XY), but also the power modules 1 ₁ , 1 ₂ and 1 ₃ are respectively. It is desirable to attach the second graphite plates 18GP (XZ) 3 and 18GP (XZ) 4 to the connecting portion as well. As a result, heat is conducted through the four second graphite plates 18GP (XZ) 1,18GP (XZ) 2,18GP (XZ) 3,18GP (XZ) 4, so that it is cooler than the 2 in 1 module type. The ability does not decrease. Further, since the second graphite plates 18GP (XZ) 3, 18GP (XZ) 4 are bonded to the connecting portions of the power modules 1 ₁ , 1 ₂ and 1 ₃ , each power module 1 ₁ and 1 ₂ are attached. ， 1 ₃ can be cooled evenly. Such a power module is preferably applied to an inverter circuit such as an air conditioner or a converter circuit such as a power supply device.

In the power module according to the seventh embodiment, the case where the power device is applied to the 2 in 1 module type and the 6 in 1 module type has been described, but the present invention is not limited to this, and for example, 1 in 1 (one). In-one module type power module, 4 in 1 (four-in-one) module type power module, 7 in 1 (seven-in-one) module type power module equipped with a snubber capacitor in 6 in 1 module, 8 in 1 (8 in 1) It can also be applied to an eight-in-one module type power module, a 12-in-1 (twelve-in-one) module type power module, a 14-in-1 (fourteen-in-one) module type power module, and the like.

[Detailed cross-sectional structure example]
Next, a detailed cross-sectional structure example of the power module according to the seventh embodiment will be described. In the following, each part corresponding to the power module shown in FIG. 45 will be described with reference to the same reference numerals.

(Detailed cross-sectional structure example 1)
The detailed cross-sectional structure of the power module according to the seventh embodiment is shown in FIG. 53. As shown in FIG. 53, the power module according to the seventh embodiment has a lower insulating substrate 20D having electrode patterns 1A and 1C provided on both sides of the ceramic substrate 1B, and a bonding material 1D on the electrode pattern 1C. The power device 1E arranged via the power device 1E, the metal 1J arranged on the power device 1E via the bonding material 1F, and the metal 1J arranged facing the metal 1J via the bonding material 1K are provided on both sides of the ceramic substrate 1H. The upper insulating substrate 20U having the electrode patterns 1G and 1I, the cooler 28 arranged on the electrode pattern 1A of the lower insulating substrate 20D via the bonding material 3A, and the electrode pattern 1I of the upper insulating substrate 20U are bonded. The first graphite plate 18GP (XY) arranged via the material 3D and the upper surface are bonded in a direction orthogonal to the first graphite plate 18GP (XY), and the lower surface is a cooler via the bonding materials 3B and 3C. A second graphite plate 18GP (XZ) 1, 18GP (XZ) 2 joined to 28 is provided, an electrode pattern (upper electrode) 1I is exposed from the upper surface of the mold resin 6, and an electrode pattern is exposed from the lower surface of the mold resin 6. (Lower electrode) 1A is exposed. That is, since the metal is exposed from the upper surface and the lower surface of the mold resin 6, it is firmly bonded to the first graphite plate 18GP (XY) and the cooler 28 by using the bonding materials 3D and 3A such as solder and silver firing. be able to.

The ceramic substrates 1B and 1H are, for example, a SiN layer and an AlN layer. The electrode patterns 1A, 1C, 1G, and 1I are, for example, a Cu layer and an Al layer. The power device 1E is, for example, a SiC chip, an IGBT made of Si, or the like. The metal 1J is, for example, a Cu layer, a CuMo layer, or the like.

(Detailed cross-sectional structure example 2)
The detailed cross-sectional structure of another power module according to the seventh embodiment is shown in FIG. 54. The difference from FIG. 53 is that the Cu layer 5A is formed on both sides of the first graphite plate 18GP (XY). As described above, other metals, ceramics, and the like may be used instead of Cu. According to such a power module, it is possible to reduce the Mises stress applied to the joint portion by matching the synthetic CTE of the power module 1.

Of course, even in such a power module, as described with reference to FIG. 49, even if the Cu layers 5B1, 5C1 are formed on the side surfaces of the second graphite plates 18GP (XZ) 1, 18GP (XZ) 2. good. Further, as described with reference to FIG. 52, Cu layers 5B2, 5C2 may be formed on the upper surface and the lower surface of the second graphite plates 18GP (XZ) 1, 18GP (XZ) 2.

[Specific examples of semiconductor devices]
The schematic circuit representation of the SiC MOSFET of the 1 in 1 module 50, which is the power module according to the seventh embodiment and can be applied as a semiconductor device (power device), is shown as shown in FIG. 28.

FIG. 28 shows a diode DI connected in antiparallel to MOSFET Q. The main electrode of MOSFET Q is represented by a drain terminal DT and a source terminal ST. Further, it is also possible to realize (not shown) an IGBT of 1 in 1 module 50, which is a power module according to the seventh embodiment and can be applied as a semiconductor device.

Further, a detailed circuit representation of the SiC MOSFET of the 1 in 1 module 50, which is the power module according to the seventh embodiment and can be applied as a semiconductor device, is shown as shown in FIG. 29.

The power module according to the seventh embodiment includes, for example, a configuration in which a plurality of semiconductor devices are 1 in 1 module 50. That is, a plurality of MOSFET Q chips of one type are connected in parallel to one module and built in. As an example, 5 chips (MOSFETs × 5) can be mounted, and up to 5 MOSFETs Q can be connected in parallel. It is also possible to mount a part of the five chips for diode DI.

More specifically, as shown in FIG. 29, sense MOSFETs Qs are connected in parallel with MOSFET Qs. The sense MOSFET Qs are formed as fine transistors in the same chip as the MOSFET Q.

In FIG. 29, SS is a source sense terminal, CS is a current sense terminal, and G is a gate signal terminal. Also in the seventh embodiment, the sense MOSFET Qs may be formed as fine transistors in the same chip in the semiconductor device Q.

(Circuit configuration)
Next, in the power module according to the seventh embodiment, a circuit configuration example of the semiconductor device will be described more specifically.

Here, it is a module applicable as a semiconductor device of the power module according to the seventh embodiment, and is a semiconductor package device in which two types of semiconductor devices Q1 and Q4 are sealed in one mold resin, so-called 2. An in 1 type module will be described.

The circuit configuration of the 2 in 1 module 130A to which the SiC MOSFET is applied as the semiconductor devices Q1 and Q4 is shown, for example, as shown in FIG.

That is, in the 2 in 1 module 130A, as shown in FIG. 30, two types of SiC MOSFETs Q1 and Q4 are connected in series with the power terminals P and N that supply power to each power device, and the connection points thereof are connected. It includes a half-bridge built-in module that is connected to the output terminal O and is built in as one module so that signals for controlling the operation of each power device are connected to the signal unit terminals G1 and G2.

Here, the module can be regarded as one large transistor, but a transistor chip in which a plurality of transistor cells are connected in parallel in one chip may connect one chip or a plurality of chips in parallel. That is, there are 1 in 1, 2 in 1, 4 in 1, 6 in 1 modules, etc. For example, a module containing two transistors (chips) on one module is 2 in 1, A module containing two sets of 2 in 1 is called 4 in 1, and a module containing three sets of 2 in 1 is called 6 in 1.

As shown in FIG. 30, the 2 in 1 module 130A contains two SiC MOSFETs Q1 and Q4 and diodes DI1 and DI4 connected in antiparallel to the SiC MOSFETs Q1 and Q4 as one module.

In FIG. 30, G1 is a lead terminal for the gate signal of the SiC MOSFET Q1, and S1 is a lead terminal for the source signal of the SiC MOSFET Q1. Similarly, G4 is a lead terminal for the gate signal of the SiC MOSFET Q4, and S4 is a lead terminal for the source signal of the SiC MOSFET Q4.

Further, P is a positive power input terminal electrode, N is a negative power input terminal electrode, and O is an output terminal electrode.

Further, it is a module applicable as a semiconductor device of the power module according to the seventh embodiment, and it is also possible to realize a 2 in 1 module (not shown) to which an IGBT is applied as the semiconductor devices Q1 and Q4. ..

Further, P is a positive power input terminal electrode, N is a negative power input terminal electrode, and O is an output terminal electrode.

The same applies to the semiconductor devices Q2 and Q5 and the semiconductor devices Q3 and Q6 applicable to the power module according to the seventh embodiment.

(Device structure)
An example of the semiconductor devices Q1 and Q4 applicable to the power module according to the seventh embodiment, the schematic cross-sectional structure of the SiC MOSFET 130A including the source pad electrode SP and the gate pad electrode GP is shown in FIG. 31. It is expressed as.

As shown in FIG. 31, the SiC MOSFET 130A is formed on the surface of the semiconductor layer 31 composed of the n-high resistance layer, the p-body region 32 formed on the surface side of the semiconductor layer 31, and the p-body region 32. In the source region 33, the gate insulating film 34 arranged on the surface of the semiconductor layer 31 between the p body regions 32, the gate electrode 35 arranged on the gate insulating film 34, and the source region 33 and the p body region 32. It includes a connected source electrode 36, an n + drain region 37 arranged on the back surface opposite to the front surface of the semiconductor layer 31, and a drain electrode 38 connected to the n + drain region 37.

The gate pad electrode GP is connected to the gate electrode 35 arranged on the gate insulating film 34, and the source pad electrode SP is connected to the source electrode 36 connected to the source region 33 and the p body region 32. Further, as shown in FIG. 31, the gate pad electrode GP and the source pad electrode SP are arranged on the passive interlayer insulating film 39 covering the surface of the SiC MOSFET 130A.

Although not shown, a transistor structure having a fine structure may be formed in the semiconductor layer 31 below the gate pad electrode GP and the source pad electrode SP.

Further, as shown in FIG. 31, in the transistor structure in the central portion, the source pad electrode SP may be extended and arranged on the passive interlayer insulating film 39.

In FIG. 31, the SiC MOSFET 130A is composed of a planar gate type n-channel vertical SiC MOSFET, and as shown in FIG. 34 described later, a trench gate type n-channel vertical SiC T (Trench) MOSFET 130C. It may be composed of such as.

Alternatively, as the semiconductor devices Q1 and Q4 applicable to the power module according to the seventh embodiment, a GaN-based FET or the like can be adopted instead of the SiC MOSFET 130A.

The same applies to the semiconductor devices Q2 and Q5 and the semiconductor devices Q3 and Q6 applicable to the power module according to the seventh embodiment.

Further, for the semiconductor devices Q1 to Q6 applicable to the power module according to the seventh embodiment, semiconductors having a bandgap energy of, for example, 1.1 eV to 8 eV, which is called a wide bandgap type, are used. Can be done.

Similarly, an example of the semiconductor devices Q1 and Q4 applicable to the power module according to the seventh embodiment, the schematic cross-sectional structure of the IGBT 130B including the emitter pad electrode EP and the gate pad electrode GP is shown in FIG. 32. It is expressed as shown in.

As shown in FIG. 32, the IGBT 130B has a semiconductor layer 31 composed of an n-high resistance layer, a p-body region 32 formed on the surface side of the semiconductor layer 31, and an emitter formed on the surface of the p-body region 32. Connected to the region 33E, the gate insulating film 34 arranged on the surface of the semiconductor layer 31 between the p-body regions 32, the gate electrode 35 arranged on the gate insulating film 34, and the emitter region 33E and the p-body region 32. The emitter electrode 36E is provided, a p + collector region 37P arranged on the back surface opposite to the front surface of the semiconductor layer 31, and a collector electrode 38C connected to the p + collector region 37P.

The gate pad electrode GP is connected to the gate electrode 35 arranged on the gate insulating film 34, and the emitter pad electrode EP is connected to the emitter electrode 36E connected to the emitter region 33E and the p body region 32. Further, as shown in FIG. 32, the gate pad electrode GP and the emitter pad electrode EP are arranged on the passive interlayer insulating film 39 covering the surface of the IGBT 130B.

Although not shown, an IGBT structure having a fine structure may be formed in the semiconductor layer 31 below the gate pad electrode GP and the emitter pad electrode EP.

Further, as shown in FIG. 32, even in the central IGBT structure, the emitter pad electrode EP may be extended and arranged on the passive interlayer insulating film 39.

In FIG. 32, the IGBT 130B is composed of a planar gate type n-channel vertical IGBT, but may be composed of a trench gate type n-channel vertical IGBT or the like.

The same applies to the semiconductor devices Q2 and Q5 and the semiconductor devices Q3 and Q6 applicable to the power module according to the seventh embodiment.

As the semiconductor devices Q1 to Q6, a SiC-based power device such as a SiC DI MOSFET or a SiC T MOSFET, or a GaN-based power device such as a GaN-based HEMT can be applied. In some cases, power devices such as Si-based MOSFETs and IGBTs can also be applied.

―SiC DI MOSFET―
An example of a semiconductor device applicable to the power module according to the seventh embodiment, the schematic cross-sectional structure of the SiC DI MOSFET 130D is represented as shown in FIG. 33.

The SiC DI MOSFET 130D shown in FIG. 33 has a semiconductor layer 31 composed of an n-high resistance layer, a p-body region 32 formed on the surface side of the semiconductor layer 31, and n + formed on the surface of the p-body region 32. In the source region 33, the gate insulating film 34 arranged on the surface of the semiconductor layer 31 between the p body regions 32, the gate electrode 35 arranged on the gate insulating film 34, and the source region 33 and the p body region 32. It includes a connected source electrode 36, an n + drain region 37 arranged on the back surface opposite to the front surface of the semiconductor layer 31, and a drain electrode 38 connected to the n + drain region 37.

In FIG. 33, in the SiC DI MOSFET 130D, a p-body region 32 and an n + source region 33 formed on the surface of the p-body region 32 are formed by double ion implantation (DII), and the source pad electrode SP is a source. It is connected to the source electrode 36 connected to the region 33 and the p-body region 32.

The gate pad electrode GP (not shown) is connected to the gate electrode 35 arranged on the gate insulating film 34. Further, as shown in FIG. 33, the source pad electrode SP and the gate pad electrode GP are arranged on the passive interlayer insulating film 39 so as to cover the surface of the SiC DI MOSFET 130D.

As shown in FIG. 33, the SiC DI MOSFET 130D is a junction type because a depletion layer as shown by a broken line is formed in a semiconductor layer 31 composed of an n-high resistance layer sandwiched between p body regions 32. A channel resistance R _JFET is formed due to the FET (JFET) effect. Further, as shown in FIG. 33, a body diode BD is formed between the p-body region 32 and the semiconductor layer 31.

―SiC T MOSFET―
An example of a semiconductor device applicable to the power module according to the seventh embodiment, the schematic cross-sectional structure of the SiC T MOSFET is represented as shown in FIG. 34.

The SiC T MOSFET 130C shown in FIG. 34 has a semiconductor layer 31N composed of n layers, a p-body region 32 formed on the surface side of the semiconductor layer 31N, and an n + source region 33 formed on the surface of the p-body region 32. The trench gate electrode 35TG formed through the p-body region 32 and formed through the gate insulating film 34 and the interlayer insulating films 39U / 39B in the trench formed up to the semiconductor layer 31N, and the source region 33 and the p-body region. It includes a source electrode 36 connected to 32, an n + drain region 37 arranged on the back surface opposite to the front surface of the semiconductor layer 31N, and a drain electrode 38 connected to the n + drain region 37.

In FIG. 34, the SiC T MOSFET 130C penetrates the p-body region 32, and the trench gate electrode 35TG is formed in the trench formed up to the semiconductor layer 31N via the gate insulating film 34 and the interlayer insulating films 39U / 39B. The source pad electrode SP is connected to the source electrode 36 connected to the source region 33 and the p body region 32.

The gate pad electrode GP (not shown) is connected to the trench gate electrode 35TG arranged on the gate insulating film 34. Further, as shown in FIG. 34, the source pad electrode SP and the gate pad electrode GP are arranged on the passive interlayer insulating film 39U so as to cover the surface of the SiC T MOSFET 130C.

In the SiC T MOSFET 130C, the channel resistance R _JFET associated with the junction FET (JFET) effect such as the SiC DI MOSFET 130D is not formed. Further, a body diode BD is formed between the p-body region 32 and the semiconductor layer 31N, as in FIG. 33.

(Application example)
A circuit of a three-phase AC inverter 40A configured by using the power module according to the seventh embodiment, in which a SiC MOSFET is applied as a semiconductor device and a snubber capacitor C is connected between a power supply terminal PL and a ground terminal NL. The configuration example is shown as shown in FIG. 35.

Similarly, an IGBT can be applied as a semiconductor device to realize a three-phase AC inverter (not shown) in which a snubber capacitor C is connected between the power supply terminal PL and the ground terminal NL.

When the power module is connected to the power supply E and the switching operation is performed, the switching speed of the SiC MOSFET or the IGBT is high due to the inductance L of the connection line, so that a large surge voltage Ldi / dt is generated. For example, if the current change di = 300A and the time change dt = 100nsec accompanying switching, then di / dt = 3 × 10 ⁹ (A / s).

The value of the surge voltage Ldi / dt changes depending on the value of the inductance L, but the surge voltage Ldi / dt is superimposed on the power supply E. This surge voltage Ldi / dt can be absorbed by the snubber capacitor C connected between the power supply terminal PL and the ground terminal NL.

(Concrete example)
Next, with reference to FIG. 36, a three-phase AC inverter 42A configured by applying a SiC MOSFET as a semiconductor device and using the power module according to the seventh embodiment will be described.

As shown in FIG. 36, the three-phase AC inverter 42A includes a power module unit 130 connected to the gate driver (GD) 180, a three-phase AC motor unit 51, a power supply or storage battery (E) 53, and a converter 55. To prepare for. The power module unit 130 is connected to the U-phase, V-phase, and W-phase inverters corresponding to the U-phase, V-phase, and W-phase of the three-phase AC motor unit 51.

Here, the GD180 is connected to the SiC MOSFETs Q1 and Q4, the SiC MOSFETs Q2 and Q5, and the SiC MOSFETs Q3 and Q6.

The power module unit 130 is connected between the positive terminal (+) P and the negative terminal (-) N of the converter 55 to which the power supply or the storage battery (E) 53 is connected, and is connected to the SiC MOSFETs Q1, Q4, and Q2 having an inverter configuration. -Provides Q5 and Q3 / Q6. Further, freewheel diodes DI1 to DI6 are connected in antiparallel between the source and drain of the SiC MOSFETs Q1 to Q6, respectively.

Further, although not shown, it is also possible to apply an IGBT as a semiconductor device and realize a three-phase AC inverter configured by using the power module according to the seventh embodiment.

As described above, according to the seventh embodiment, it is possible to provide an inexpensive power module and a graphite plate having a cooling capacity close to double-sided cooling with one cooler.

In the power module according to the seventh embodiment, the module applicable as a semiconductor device may be, for example, a molded power module having a 4-terminal electrode structure or the like.

Further, the semiconductor device applicable to the power module according to the seventh embodiment is not limited to the SiC-based power device, but also a Si-based power device and a power device called a wide bandgap type such as a GaN-based power device. It can be adopted.

Further, it can be applied not only to a resin-molded mold-type power module but also to a power module packaged by a case-type package.

[Basic technology in the 8th to 14th embodiments]
Before explaining the power module according to the 8th to 14th embodiments, the basic basic technique will be briefly described. Here, a case where a SiC MOSFET is applied as a semiconductor device (power device) of a power element system will be described as an example.

The PM11 according to the basic technology which is the basis of the power module (PM) 11 according to the eighth to the fourteenth embodiments, and the schematic cross-sectional structure of the 1 in 1 module to which the SiC MOSFET Q1 is applied to the semiconductor device is. It is represented as shown in FIG. 55, and the schematic circuit configuration of PM11 is represented as shown in FIG. 56.

Further, FIG. 57 (a) shows a schematic planar pattern configuration of a 2 in 1 module to which the SiC MOSFETs Q1 and Q4 are applied as semiconductor devices in PM11 according to the basic technology of the 8th to 14th embodiments. It is represented as shown, and the enlarged configuration of the display 11A portion (main part) of FIG. 57 (a) is represented as shown in FIG. 57 (b).

Since the basic configuration is almost the same for both the 2 in 1 module and the 1 in 1 module, a specific description will be given here with reference to the 1 in 1 module shown in FIG. 55, and the 2 in 1 module will be described. Just a brief explanation.

As shown in FIG. 55, the 1 in 1 module type PM11 according to the basic technique includes a ceramic substrate 21, a drain electrode pattern 25D1 and a source electrode pattern 25S1 provided on the upper surface side of the ceramic substrate 21, and a source signal electrode pattern SL1. Further, an insulating substrate 20 having a gate signal electrode pattern GL1 and a back surface electrode pattern 23R provided on the lower surface side of the ceramic substrate 21 is provided.

Here, in FIG. 55, the upper side of the insulating substrate 20 is defined as the U (UP) side, and the lower side of the insulating substrate 20 is defined as the D (DOWN) side. This definition applies to all drawings shown below.

As shown in FIG. 55, the 1-in-1 module type PM11 includes a SiC MOSFET Q1 arranged face-up on the drain electrode pattern 25D1 as a semiconductor device. The SiC MOSFET Q1 has a source pad electrode SP1, a source sense pad electrode SSP1 and a gate pad electrode GP1 on the front surface side, and has a drain electrode 38 on the back surface side.

Further, as shown in FIG. 55, the 1 in 1 module type PM11 is connected between the source pad electrode SP1 of the SiC MOSFET Q1 and the source electrode pattern 25S1 and serves as the main wiring for the source power line wiring. The frame SM1 is provided.

Further, in the 1 in 1 module type PM11, as shown in FIG. 55, the source sense bonding wire SSW1 for connecting the source sense pad electrode SSP1 to the source signal electrode pattern SL1 and the gate pad electrode GP1 are connected to the gate signal electrode pattern GL1. It is provided with a bonding wire GW1 for a gate signal to be connected to.

In the 1 in 1 module type PM11, the position of the wire bonding portion on the SiC MOSFET Q1 of the source sense bonding wire SSW1 connected to the source signal electrode pattern SL1 is on the source sense pad electrode SSP1 of the SiC MOSFET Q1. It has become. That is, in PM11 according to the basic technique, as shown in FIG. 56, the source sense bonding wire SSW1 is connected to the inside of the lead frame SM1 which is closer to the SiC MOSFET Q1.

Therefore, as a semiconductor device, for example, in PM11 to which the SiC MOSFET Q1 is applied, the temperature of the source sense pad electrode SSP1 rises significantly due to the influence of heat due to the operation of the SiC MOSFET Q1 to become high in temperature, and the source sense pad electrode SSP1 and the source sense pad electrode SSP1. The connectivity of the source sense bonding wire SSW1 is deteriorated due to stress concentration on the bonding interface with the source sense bonding wire SSW1 and local particle size change in the source sense bonding wire SSW1.

In the case of the bonding wire GW1 for the gate signal, there is basically no cell having a MOSFET structure directly under the gate pad electrode GP1 to be bonded, and the temperature rise there is larger than that of the source sense pad electrode SSP1. Since there is no such thing, deterioration is suppressed.

Similarly, in the case of the 2 in 1 module type PM11 according to the basic technique, as shown in FIGS. 57 (a) and 57 (b), the source sense bonding wire SSW1 connected to the source signal electrode patterns SL1 and SL4. The position of the wire bonding portion of the SSW4 on the SiC MOSFETs Q1 and Q4 is on the source sense pad electrode SSP1 (not shown) in the SiC MOSFET Q1 and the source sense pad electrode SSP4 in the SiC MOSFET Q4. Since it is above, deterioration of the connectivity of the source sense bonding wires SSW1 and SSW4 is a problem.

As described above, in the PM11 in which the SiC MOSFET Q operating at a high temperature is mounted as a semiconductor device, deterioration of the connectivity of the bonding wire SSW for source sense becomes a problem.

[Eighth Embodiment]
The schematic cross-sectional structure of PM1 according to the eighth embodiment is shown as shown in FIG. 58 (a), and the schematic circuit configuration of PM1 is shown as shown in FIG. 58 (b). Further, a schematic planar pattern configuration of the semiconductor device applicable to PM1 according to the eighth embodiment is shown as shown in FIG. 59.

Here, a 1-in-1 module to which the SiC MOSFET Q1 is applied will be described as an example as a power device-based semiconductor device (power device).

As shown in FIGS. 58 (a) and 58 (b), the PM1 according to the eighth embodiment has a SiN-based ceramic substrate 21 and a Cu foil provided on the upper surface (U) side of the ceramic substrate 21. Drain electrode pattern (second main electrode pattern) 25D1, source electrode pattern (first main electrode pattern) 25S1, source signal electrode pattern (signal wiring pattern) SL1, gate signal electrode pattern (control signal wiring pattern) GL1 and the like. An insulating substrate 20 having a back surface electrode pattern 23R such as a Cu foil provided on the lower surface (D) side of the ceramic substrate 21 is provided.

Here, as shown in FIG. 58 (b), the source sense terminal SS1 (SST1) is connected to the source signal electrode pattern SL1, and the gate terminal G1 (GT1) is connected to the gate signal electrode pattern GL1. ..

Further, the PM1 according to the eighth embodiment includes a SiC MOSFET Q1 arranged on the drain electrode pattern 25D1 as a semiconductor device. As shown in FIG. 59, for example, the SiC MOSFET Q1 has two source pad electrodes (main pad electrodes) SP1 and one gate pad electrode (control pad electrode) GP1 and one on the surface of the SiC MOSFET Q1. A current sense pad electrode CS1 and one source sense pad electrode SSP1 are provided, and a gate finger electrode GF is arranged in a peripheral portion and a central portion.

A surface protective film PE formed of polyimide resin or the like is arranged on the surface of the SiC MOSFET Q1 excluding the surfaces of the source pad electrode SP1, the gate pad electrode GP1, the current sense pad electrode CS1, and the source sense pad electrode SSP1. ing.

Further, although not shown in FIG. 59, a drain electrode (main electrode) 38 is provided on the back surface side of the SiC MOSFET Q1 facing the front surface side.

As another configuration example, two source pad electrodes SP1 are not always required, and a configuration including one source pad electrode SP1 may be used. Further, the source sense pad electrode SSP1 can be omitted.

As shown in FIG. 58A, the SiC MOSFET Q1 is face-up on the insulating substrate 20 by bonding the drain electrode 38 to the drain electrode pattern 25D1 using a bonding member 27 such as silver firing or solder. It has been implemented.

Further, the PM1 according to the eighth embodiment includes a lead frame SM1 which is connected between the source pad electrode SP1 of the SiC MOSFET Q1 and the source electrode pattern 25S1 and is the main wiring for the source power line wiring. The lead frame SM1 includes a parasitic inductance Lsm and a parasitic resistance Rsm.

The lead frame SM1 includes any of Cu, Al, a clad material (for example, a Cu / Invar / Cu laminate), or CuMo.

A joining member 27 is used for the connection of the lead frame SM1 with the source electrode pattern 25S1 and the connection of the lead frame SM1 with the source pad electrode SP1.

In the following description, the junction between the source pad electrode SP1 and the lead frame SM1 is defined as the device-side junction (first junction) DC, separated from the device-side junction DC, and generates more heat than the device-side junction DC. The joint portion between the lead frame SM1 and the source electrode pattern 25S1 which are less affected by the above and have a relatively low temperature is referred to as a land side joint portion (second joint portion) SC.

As shown in FIG. 58 (a), in the case of PM1 according to the eighth embodiment, the drain electrode pattern 25D1 is located between the source electrode pattern 25S1 and the source signal electrode pattern SL1, and the drain electrode pattern 25D1 is located from the land side junction SC. Also, the device-side junction DC is arranged close to the source signal electrode pattern SL1.

The PM1 according to the eighth embodiment has a source sense bonding wire (first bonding wire) SSW1 for connecting the lead frame SM1 to the source signal electrode pattern SL1 on the land side bonding portion SC side, and a device side bonding portion DC. On the side, a gate signal bonding wire (second bonding wire) GW1 for connecting the gate pad electrode GP1 to the gate signal electrode pattern GL1 is provided.

That is, in PM1 according to the eighth embodiment, as shown in FIG. 58 (b), the source sense bonding wire SSW1 is farther from the SiC MOSFET Q1 on the land side junction SC side (SiC MOSFET of the lead frame SM1). It is connected to (outside when viewed from Q1).

The bonding wire SSW1 for source sense and the bonding wire GW1 for gate signal include Al, Cu, a clad material, or an alloy having one or more of them.

The source sense bonding wire SSW1 is wedge-bonded with a wire diameter of about φ = 150 μm, and the gate signal bonding wire GW1 is wedge-bonded with a wire diameter of about φ = 150 μm.

Then, in the PM1 according to the eighth embodiment, the outer periphery of the SiC MOSFET Q1 is entirely sealed (resin-molded) with a mold resin and housed in a mold-type package type power module or a case. It is a case type package type power module.

In the PM1 according to the eighth embodiment described above, the source sense bonding wire SSW1 is connected to the lead frame SM1 on the land side joint SC side, but the source sense bonding wire SSW1 is a source electrode. It may be connected to the pattern 25S1 (the same applies to other embodiments described later).

That is, the PM1 according to the eighth embodiment has a ceramics substrate 21 having a source electrode pattern 25S1 and a source signal electrode pattern SL1 and a source pad electrode SP1 on the surface thereof, and is a SiC MOSFET arranged on the ceramics substrate 21. The lead frame SM1 connected between the Q1 and the source pad electrode SP1 and the source electrode pattern 25S1 and the device-side junction DC between the lead frame SM1 and the source pad electrode SP1 are separated from each other, and the lead frame SM1 and the source electrode pattern are separated. A land-side junction SC with 25S1 and a source sense bonding wire SSW1 connected between the land-side junction SC and the source signal electrode pattern SL1 are provided, and the land-side junction SC is a device-side junction DC. The temperature during operation of the semiconductor device is relatively lower than that of the above.

Further, PM1 according to the eighth embodiment includes an insulating ceramic substrate 21, a source electrode pattern 25S1 arranged on the ceramic substrate 21, a drain electrode pattern 25D1, a source signal electrode pattern SL1, and a gate signal electrode pattern GL1. An insulating substrate 20 having a source pad electrode SP1 and a gate pad electrode GP1 on the front surface side, and a drain electrode 38 on the back surface side, and a SiC MOSFET Q1 arranged face-up on the drain electrode pattern 25D1. , The lead frame SM1 connected between the source pad electrode SP1 and the source electrode pattern 25S1 and the device-side junction DC between the lead frame SM1 and the source pad electrode SP1 are separated from each other, and the semiconductor device is more than the device-side junction DC. The source sense bonding wire SSW1 connected between the land-side junction SC between the lead frame SM1 and the source electrode pattern 25S1 whose temperature during operation is relatively low, the source signal electrode pattern SL1, and the gate pad electrode GP1. The gate signal bonding wire GW1 connected between the gate signal electrode pattern GL1 and the gate signal electrode pattern GL1 is provided, and one end of the source sense bonding wire SSW1 is connected to the source signal electrode pattern SL1 and the other end is connected to the land side. It is connected to the lead frame SM1 of the unit SC or the source electrode pattern 25S1.

For example, an AMB substrate can be applied to the insulating substrate 20, but a DBC substrate, a DBA substrate, or the like can also be applied.

Further, in order to enhance the cooling effect, a radiator (not shown) such as a heat sink or a cooler may be arranged on the back electrode pattern 23R of the insulating substrate 20.

(Production method)
The PM1 according to the eighth embodiment has, for example, a ceramics substrate 21, a source electrode pattern 25S1 arranged on the ceramics substrate 21, a drain electrode pattern 25D1, a source signal electrode pattern SL1, and a gate signal electrode pattern GL1. A process of arranging a SiC MOSFET Q1 having a source pad electrode SP1 and a gate pad electrode GP1 on the front surface side and a drain electrode 38 on the back surface side face-up on the drain electrode pattern 25D1 of the insulating substrate 20 and a source pad. The step of connecting the lead frame SM1 between the electrode SP1 and the source electrode pattern 25S1 and the device-side junction DC between the lead frame SM1 and the source pad electrode SP1 are separated from each other, and the temperature is relatively higher than the device-side junction DC. The process of connecting the source sense bonding wire SSW1 between the land-side junction SC of the lead frame SM1 and the source electrode pattern 25S1 and the source signal electrode pattern SL1, and the gate pad electrode GP1 and the gate signal electrode pattern. It has a step of connecting the bonding wire GW1 for a gate signal to the GL1.

-Explanation of the role of the source sense terminal from the viewpoint of switching loss-
Here, in PM1 according to the eighth embodiment, the switching loss due to the parasitic inductance of the lead frame SM will be described by taking a SiC power module to which a SiC MOSFET is applied as an example as a semiconductor device.

As shown in FIGS. 60 (a) and 60 (b), in the SiC power module SPM1 to which the SiC MOSFET Q1 is applied as a semiconductor device, the current Id flowing between the drain (D1) and the source (S1) of the SiC MOSFET Q1. On the other hand, due to the parasitic inductance Lsm of the lead frame SM1, an electric current is generated by −Lsm · d (Id) / dt. The electromotive voltage Es of the gate (G1) is assumed to be, for example, Lg · (di / dt). However, di is a change in current due to switching, and dt is a change in time due to switching.

Then, at the time of current rise at the time of turn-on, as shown in FIG. 60 (a), the electromotive voltage Es is generated in the direction of suppressing the increase of the voltage applied to the parasitic capacitance between the gate (G1) and the source (S1). .. Therefore, the accumulation time until the applied voltage of the gate-source parasitic capacitance required for passing the load current is reached becomes long, and as a result, the switching time becomes long and the switching loss increases.

On the other hand, when the current rises at the time of turn-off, as shown in FIG. 60 (b), the electromotive voltage Es is generated in the direction of suppressing the decrease of the voltage applied to the gate-source parasitic capacitance. Therefore, the discharge time until the value falls below the gate threshold becomes long, and as a result, the switching time becomes long and the switching loss increases.

On the other hand, since the loss of the three-phase bridge circuit (module) in the motor drive is mainly conduction loss, the position of the wire bonding portion of the source sense bonding wire SSW1 is changed to the land side bonding portion SC side. The effect on the increase in overall loss is small, and there are merits such as high heat resistance of wire connection and ensuring reliability for high temperature operation without a large trade-off.

In particular, in the SiC power module SPM1 for motors that do not require high-speed switching operation (high-frequency drive), for example, low-frequency drive of about 5 kHz to 10 kHz and inverters (which operate even at high temperatures), the position of the wire bonding section is changed. The effect of increased inductance on the generated loss is small.

In this way, by applying the lead frame SM1 instead of the thin wire to the main wiring for the source power line wiring, the parasitic inductance (Ls) is reduced, and a large current flows in a concentrated manner, resulting in high temperature due to heat generation. By connecting the source sense bonding wire SSW1 to the land-side junction SC side, which avoids the region (device-side junction DC), has a smaller effect of heat generation, and has a relatively lower temperature than the device-side junction DC. Since the increase in switching loss due to the parasitic inductance Ls can be suppressed, it can be introduced without a large trade-off.

That is, in the SiC power module SPM1 for an inverter, which tends to have a high temperature, the temperature of the source sense bonding wire SSW1 required for signal detection does not become higher than that of the device-side bonding portion DC even during the operation of the SiC power module SPM1. Wire bonding to the land side joint SC side is effective.

The change in the position of the wire bonding portion of the source sense bonding wire SSW1 to the land side bonding portion SC can be applied to both the case and mold type modules.

Therefore, even if the source pad electrode SP1 becomes hot to the same extent as the junction temperature due to the large current flowing through the SiC MOSFET Q1, the wire SSW1 is broken in the case type module in which the grain size of the wire tends to be coarsened. Further, it is possible to avoid breakage of the wire SSW1 at the joint surface (intersection) due to thermal stress in the mold type module.

As described above, according to PM1 according to the eighth embodiment, the lead frame SM1 is applied to the main wiring for the source power line wiring, and the temperature at the time of operation of the SiC MOSFET Q1 is higher than that of the device-side junction DC. By connecting the source sense bonding wire SSW1 to the relatively low land side joint SC side, the influence of heat on the wire connection due to the operation of high temperature can be reduced, and the heat resistance and reliability for the wire connectivity can be improved. It will be possible to improve.

As the SiC MOSFET Q1, a SiC-based power device such as a SiC DI MOSFET or a SiC T MOSFET, or a GaN-based power device such as a GaN-based HEMT can be applied. In some cases, power devices such as Si-based MOSFETs, Si-based IGBTs, and SiC-based IGBTs can also be applied.

Further, the SiC MOSFET Q1 is not limited to one consisting of one chip (device), and may be configured by connecting a plurality of chips in parallel.

When the SiC MOSFET Q1 is configured by connecting a plurality of chips in parallel, the lead frame SM1 and the source sense bonding wire SSW1 are commonly connected to the plurality of chips.

[9th embodiment]
In PM1 according to the ninth embodiment, a schematic bird's-eye view pattern configuration before the resin mold is shown as shown in FIG. Here, as a power device-based semiconductor device (power device), a 2 in 1 module type half-bridge built-in module to which SiC MOSFETs Q1 and Q4 are applied will be described as an example.

Further, the schematic plane pattern configuration of the half-bridge built-in module to which the SiC MOSFETs Q1 and Q4 are applied in the PM1 according to the ninth embodiment is shown in FIG. 62A, and is shown in FIG. 62. The enlarged configuration of the display 1A portion (main part) of (a) is shown as shown in FIG. 62 (b).

Further, the circuit configuration of the half-bridge built-in module to which the SiC MISFETs Q1 and Q4 are applied in the PM1 according to the ninth embodiment is shown as shown in FIG. 63.

The PM1 according to the ninth embodiment, as a mold type module, has a schematic bird's-eye view configuration after resin molding of the module with a built-in half bridge, as shown in FIG. 64.

In PM1 according to the ninth embodiment, the schematic side surface configuration of the main part seen from the direction of arrow B in FIG. 62B is shown as shown in FIG. 65.

That is, the PM1 according to the ninth embodiment has a configuration of a half-bridge built-in module in which two SiC MOSFETs Q1 and Q4 connected in series are built in one module.

As shown in FIG. 64, PM1 according to the ninth embodiment is a positive power input terminal electrode (positive power terminal) arranged on the first side of the ceramic substrate 21 coated with the resin mold layer 115. P and negative power input terminal electrode (negative power terminal) N, gate terminal (gate) GT1 and source sense terminal SST1 arranged on the second side adjacent to the first side, and on the first side It includes an output terminal electrode (output terminal) O arranged on the third side facing each other, and a gate terminal GT4 and a source sense terminal SST4 arranged on the fourth side facing the second side.

The PM1 according to the ninth embodiment is a power module having a four-power terminal structure including two output terminals O.

Here, as shown in FIGS. 61 to 65, the gate terminal GT1 and the source sense terminal SST1 are connected to the gate signal electrode pattern GL1 and the source signal electrode pattern SL1 of the SiC MOSFET Q1 and are connected to the gate terminal GT4 and the source sense terminal SST4. Is connected to the gate signal electrode pattern GL4 and the source signal electrode pattern SL4 of the SiC MOSFET Q4.

As shown in FIGS. 61 to 65, gate terminals GT1 and GT4 for external extraction and source sense terminals SST1 and SST4 are connected to the gate signal electrode patterns GL1 and GL4 and the source signal electrode patterns SL1 and SL4 by soldering or the like. Will be done.

As shown in FIGS. 61 to 65, the gate signal electrode patterns GL1 and GL4 and the source signal electrode patterns SL1 and SL4 are arranged on the signal boards 261, 264, and the signal boards 261, 264 are soldered on the ceramic board 21. It is connected by soldering.

The signal substrates 261, 264 can be formed of a ceramic substrate. The ceramic substrate may be formed of, for example, Al ₂ O ₃ , AlN, SiN, AlSiC, or at least an insulating SiC on the surface.

Further, although not shown in FIGS. 61 to 65, diodes may be connected in antiparallel between D1 and S1 and between D4 and S4 of the SiC MOSFETs Q1 and Q4.

The positive power terminal P / negative power terminal N, the gate terminals GT1 / GT4 for external extraction, and the source sense terminals SST1 / SST4 can be formed by, for example, Cu.

The electrode patterns 25D1, 25D4, and 25DN, which are the main wiring conductors, can be formed by, for example, Cu.

Here, in the examples shown in FIGS. 61 to 65, in the module with a built-in half bridge of the 2 in 1 module type, the electrode pattern 25D1 functions as a drain electrode pattern for the high side device (SiC MOSFET Q1). do.

Further, the electrode pattern 25D4 functions as a drain electrode pattern for the low side device (SiC MOSFET Q4) and also functions as a source electrode pattern (25S1) for the high side device. That is, the drain electrode pattern 25D4 is a drain electrode of the SiC MOSFET Q4 and at the same time a source electrode of the SiC MISFET Q1.

Further, the electrode pattern 25DN connected to the negative power terminal N also functions as a source electrode pattern (25S4) for the row side device.

That is, in PM1 according to the ninth embodiment, as shown in FIGS. 61 to 65, the SiC MOSFET Q1 is mounted on the electrode pattern 25D1, the drain D1 is connected to the electrode pattern 25D1, and the source is connected. S1 is connected to the electrode pattern 25D4 via the lead frame SM1. Similarly, the SiC MOSFET Q4 is mounted on the electrode pattern 25D4, the drain D4 is connected to the electrode pattern 25D4, and the source S4 is connected to the electrode pattern 25DN via the lead frame SM4.

Further, as shown in FIGS. 61 to 65, in the PM1 according to the ninth embodiment, the source sense bonding for connecting the lead frame SM1 to the source signal electrode pattern SL1 on the land side bonding portion SC side. A gate signal bonding wire (second bonding wire) that connects the gate pad electrode GP1 to the gate signal electrode pattern GL1 on the device-side bonding portion DC side facing the wire (first bonding wire) SSW1 and the land-side bonding portion SC. It is equipped with GW1.

Similarly, on the land-side bonding portion SC side, the source sense bonding wire (first bonding wire) SSW4 for connecting the lead frame SM4 to the source signal electrode pattern SL4 and the device-side bonding portion DC facing the land-side bonding portion SC. On the side, a gate signal bonding wire (second bonding wire) GW4 for connecting the gate pad electrode GP4 to the gate signal electrode pattern GL4 is provided.

That is, as shown in FIG. 63, the lead frames SM1 and SM4 or the source electrode patterns 25S1 and 25S4 are connected to the source signal electrode patterns SL1 and SL4 of the SiC MOSFETs Q1 and Q4 on the land side junction SC side. The source sense bonding wires SSW1 and SSW4 are wedge-bonded.

Other configurations, manufacturing methods, and the like are substantially the same as in the case of the eighth embodiment.

As described above, also by PM1 according to the ninth embodiment, the lead frames SM1 and SM4 are applied to the main wiring for the source power line wiring, and the SiC MOSFETs Q1 and Q4 are operated rather than the device-side junction DC. By connecting the source sense bonding wires SSW1 and SSW4 to the land side joint SC side where the temperature is relatively low, the influence of heat on the wire connection due to the operation of high temperature can be reduced, and the heat resistance to the wire connectivity is high. It is possible to improve the reliability and reliability.

According to the ninth embodiment, the 2 in 1 module is a PM capable of reducing the influence of heat on the wire connection due to the operation of high temperature, increasing the heat resistance of the wire connection, and improving the reliability. It will be possible to provide a type of module with a built-in half bridge.

[10th Embodiment]
The schematic planar pattern configuration of PM1 according to the tenth embodiment is shown as shown in FIG. 66. Further, the simulation result regarding the temperature diffusion (temperature distribution) at the time of heat generation of PM1 according to the tenth embodiment is shown as shown in FIG. 67.

Here, as shown in FIG. 66, the PM1 according to the tenth embodiment includes a device-side junction DC which is a junction between the source pad electrode SP1 and the lead frame SM1, and the lead frame SM1 and the source electrode pattern 25S1. Except for the difference in the arrangement of the land-side joint SC, which is the joint with the PM1, the configuration is substantially the same as that of PM1 according to the eighth embodiment.

That is, the PM1 according to the tenth embodiment includes the ceramics substrate 21, the drain electrode pattern (second main electrode pattern) 25D1 provided on the upper surface (U) side of the ceramics substrate 21, and the source electrode pattern (first main electrode). An insulating substrate 20 having an electrode pattern) 25S1, a source signal electrode pattern (signal wiring pattern) SL1, and a back surface electrode pattern 23R arranged on the lower surface (D) side of the ceramic substrate 21, and face-up on the drain electrode pattern 25D1. A power element-based semiconductor device (SiC MOSFET) Q1 having a source pad electrode (main pad electrode) SP1 on the surface, and a source power line connected between the source pad electrode SP1 and the source electrode pattern 25S1. It includes a lead frame SM1 that is the main wiring for wiring, and a source sense bonding wire SSW1 that connects between the land side junction SC and the source signal electrode pattern SL1.

In the case of PM1 according to the tenth embodiment, the source electrode pattern 25S1 is located between the drain electrode pattern 25D1 and the source signal electrode pattern SL1, and is closer to the source signal electrode pattern SL1 than the device-side junction DC. The land side joint SC is arranged.

In FIGS. 66 and 67, the gate pad electrode (GP1) on the SiC MOSFET Q1, the gate signal electrode pattern (GL1) on the ceramic substrate 21, and the gate pad electrode (GP1) and the gate signal electrode pattern (GL1) are shown. The gate signal bonding wire (GW1) and the package (resin mold layer 115) connecting between them are not shown.

Further, the BE shown in FIG. 67 is a block electrode made of a metal column for connecting the lead frame SM1 to the source electrode pattern 25S1. The block electrode BE can be formed of Cu or the like. The block electrode BE may be integrally formed as a part of the lead frame SM1.

The simulation result regarding the temperature diffusion (temperature distribution) at the time of heat generation of PM1 according to the tenth embodiment is shown as shown in FIG. 67. Note that FIG. 67 corresponds to the cross section along the X-ray line of FIG. 66, and the lighter the color, the higher the temperature. In addition, this simulation result shows the saturation time in which the temperature does not change any more after a certain time has passed from the operation of the SiC MOSFET Q1.

As is clear from FIG. 67, the temperature rises due to the operation of the SiC MOSFET Q1 almost in the vicinity of the device-side junction DC, up to the region shown by display 1C in the figure (near the land-side junction SC). The heat does not rise significantly.

Therefore, even if the source pad electrode SP1 becomes hot to the same level as the junction temperature due to a large current flowing through the SiC MOSFET Q1 and operating at a high temperature, the source sense bonding wire SSW1 may be broken or the source sense bonding wire may be broken. It is possible to avoid breakage of the SSW1 at the joint surface.

The PM1 shown in the tenth embodiment is also applicable to other power modules shown in the tenth embodiment.

[Eleventh Embodiment]
The schematic cross-sectional structure of PM1 according to the eleventh embodiment is represented as shown in FIG. 68.

Here, as shown in FIG. 68, the PM1 according to the eleventh embodiment has substantially the same configuration as the PM1 according to the eighth embodiment except for the configuration of the lead frame SM1. Therefore, avoid duplicate explanations and explain different parts.

That is, as shown in FIG. 68, PM1 according to the eleventh embodiment is an example in which a wiring lead portion (lead frame) 30SM is adopted as the main wiring for source power line wiring instead of the lead frame SM1. The wiring lead portion 30SM is a graphite plate (graphite wiring) 18GP (XZ) having an anisotropic thermal conductivity and thermal expansion coefficient, and a lower Cu arranged on the lower surface side of the graphite plate 18GP (XZ). It is provided with a wiring pattern 16D and an upper Cu wiring pattern 16U arranged on the upper surface side, one end side is connected to the source pad electrode SP1 of the semiconductor device (SiC MOSFET) Q1, and the other end side is ceramics via a block electrode BE. It is connected to the source electrode pattern 25S1 on the substrate 21.

The graphite plate 18GP (XZ) has an XZ orientation having a relatively high thermal conductivity in the thickness direction rather than the plane direction. The XZ orientation substantially coincides with the direction of the illustrated XZ plane orthogonal to the illustrated Y direction, which is the extension direction of the wiring lead portion 30SM. That is, the graphite wiring 18GP (XZ) has an orientation having a relatively low thermal conductivity in the plane direction and an XZ orientation having a relatively high thermal conductivity in the thickness direction rather than the plane direction.

Then, on the land side bonding portion SC side, the source sense bonding wire SSW1 for connecting the wiring lead portion 30SM or the source electrode pattern 25S1 to the source signal electrode pattern SL1 is wedge-bonded.

Here, the graphite plate 18GP (XZ) will be briefly described. The schematic configuration (laminated structure example) of the graphite sheet (graphene) GS constituting the graphite plate is shown as shown in FIG.

The graphite plates include a graphite plate 18GP (XY) having an XY orientation having a higher thermal conductivity in the plane direction than a thickness direction, and a graphite plate 18GP (XZ) having an XZ orientation having a higher thermal conductivity in the thickness direction than the plane direction. ), The graphite plate 18GP (XY) is represented as shown in FIG. 6 (a), and the graphite plate 18GP (XZ) is represented as shown in FIG. 6 (b).

As shown in FIG. 5, the graphite sheets GS1, GS2, GS3, ..., GSn on each surface composed of n layers have a large number of hexagonal covalent bonds in one laminated crystal structure, and each surface has a covalent bond. Graphite sheets GS1, GS2, GS3, ..., GSn are bonded by van der Waals force.

That is, graphite, which is a carbon-based anisotropic heat transfer material, is a layered crystal having a hexagonal network structure of carbon atoms, and has anisotropy in heat conduction. Graphite sheets GS1, GS2, shown in FIG. GS3 ..... GSn has a higher thermal conductivity (high thermal conductivity) in the crystal plane direction (on the XY plane) than in the thickness direction of the Z axis.

Therefore, as shown in FIG. 6A, the graphite plate 18GP (XY) having an XY orientation has, for example, X = 1500 (W / mK), Y = 1500 (W / mK), Z = 5 (W /). It has a thermal conductivity of mK).

On the other hand, as shown in FIG. 6B, the graphite plate 18GP (XZ) having the XZ orientation has, for example, X = 1500 (W / mK), Y = 5 (W / mK), Z = 1500 (W /). It has a thermal conductivity of mK).

Both the graphite plates 18GP (XY) and 18GP (XZ) have a density of about 2.2 (g / cm ³ ), a thickness of about 0.7 mm to 10 mm, and a size of 40 mm × 40 mm. It is below the degree.

According to PM1 according to the eleventh embodiment, due to the adoption of the graphite plate 18GP (XZ), the heat generated on the device side junction DC side due to the operation of the SiC MOSFET Q1 at a high temperature causes the wiring lead portion 30SM. Through this, it becomes possible to suppress transmission to the land side joint SC side.

Therefore, also in the PM1 according to the eleventh embodiment, the graphite plate 18GP (XZ) is adopted as the lead frame SM1 for the main wiring for the source power line wiring, and the operation of the SiC MOSFET Q1 is performed rather than the device-side bonding portion DC. By connecting the source sense bonding wire SSW1 to the land side joint SC side where the temperature is relatively low at the time, the influence of heat on the wire connection due to the operation of high temperature can be reduced more effectively, and the wire connectivity can be reduced. It is possible to improve the heat resistance and reliability of the wire.

Further, by adopting the graphite plate 18GP for the wiring lead portion 30SM as in PM1 according to the eleventh embodiment, it is possible to further suppress the common Ls (resistance) that increases by the amount of the wiring lead portion 30SM. Will be.

The PM1 shown in the eleventh embodiment can be applied to other power modules shown in the embodiment.

[Twelfth Embodiment]
In PM2 according to the twelfth embodiment, the schematic bird's-eye view pattern configuration of the six-in-one (6 in 1) module is represented as shown in FIG. 69.

The PM2 according to the twelfth embodiment is an example in which, for example, three PM1s shown in FIG. 59 are arranged in parallel on a common ceramic substrate 21A to form a 6 in 1 module type switching module. Is.

Here, in the case of a 6 in 1 module type switching module, the basic structure is the same as that of the 1 in 1 module type PM and the 2 in 1 module type PM. That is, in the PM2 according to the twelfth embodiment, the 6 in 1 module type switching module includes the 2 in 1 module type PM1 ₁ , 1, ₂ , and 1 ₃ as shown in FIG. 69.

PM1 ₁ is equipped with, for example, SiC MOSFETs _Q1 and Q4 as semiconductor devices, PM1 ₂ is equipped with, for example, SiC MOSFETs Q2 and Q5, and PM1 ₃ is equipped with, for example, SiC MOSFETs Q3 and Q6. ₂・ 1 ₃ is the same as PM1, and detailed description thereof will be omitted.

In the PM2 according to the twelfth embodiment, the 6 in 1 module type switching module is, for example, a 2 in 1 module type PM1 ₁ , 1, ₂ , 1 ₃ which is a common mold resin (not shown). Alternatively, it has a configuration in which it is integrally sealed by a case.

That is, in the 6 in 1 module type switching module (PM2 according to the twelfth embodiment), PM1 ₁ , 1, ₂ , and 1 ₃ are arranged in parallel on a common ceramic substrate 21A to form an integrated package (integrated package). It is possible to seal as a resin mold layer (not shown) and to standardize (integrate) the back surface electrode pattern 23R.

Alternatively, 2 in 1 module type PM1 ₁ , 1 ₂ and 1 ₃ sealed separately by individual mold resin or case are further arranged in parallel on a common ceramic substrate 21A to form a 6 in 1 module type. It is also possible to use the switching module of.

Even when the PM2 configuration (6 in 1 module type switching module) according to the twelfth embodiment is used, as shown in FIG. 69, the source pad electrodes are set in PM1 ₁・ 1 ₂・ 1 ₃ . Connected between SP1 / SP4, SP2 / SP5, SP3 / SP6 and the source electrode patterns 25S1 (25D4) / 25S4 (25DN), 25S2 (25D5) / 25S5 (25DN), 25S3 (25D6) / 25S6 (25DN). Lead frames SM1 / SM4, SM2 / SM5, SM3 / SM6, and lead frames SM1 / SM4, SM2 / SM5, SM3 / SM6 of the land side junction SC and source signal electrode patterns SL1 / SL4, SL2 / SL5, SL3. By providing the source sense bonding wires SSW1 / SSW4, SSW2 / SSW5, and SSW3 / SSW6 for connecting to the SL6, the influence of heat on the wire connection due to the operation of high temperature can be reduced, and the wire connectivity is high. It is possible to improve heat resistance and reliability.

The source sense bonding wires SSW1 / SSW4, SSW2 / SSW5, SSW3 / SSW6 have source electrode patterns 25S1 (25D4) / 25S4 (25DN), 25S2 (25D5) / 25S5 (25DN) on the land side bonding portion SC side. , 25S3 (25D6) and 25S6 (25DN) may be connected.

[13th Embodiment]
In PM1 according to the thirteenth embodiment, the schematic plane pattern configuration of the 1 in 1 module is represented as shown in FIG. 70 (a), and is along the XI-XI line of FIG. 70 (a). The schematic cross-sectional structure is represented as shown in FIG. 70 (b).

Here, as shown in FIGS. 70 (a) and 70 (b), the PM1 according to the thirteenth embodiment is almost the same as the PM1 according to the eighth embodiment except for the configuration of the lead frame SM. Since it has the same configuration, duplicate explanations will be avoided and different parts will be explained.

As shown in FIGS. 70 (a) and 70 (b), PM1 according to the thirteenth embodiment is an example in which an extended lead frame (lead frame) SML1 is adopted as the main wiring for the source power line wiring. In the extended lead frame SML1, one end side is connected to the source electrode pattern 25S1 on the ceramic substrate 21, and the other end side connected to the source pad electrode SP1 of the SiC MOSFET (semiconductor device) Q1 is extended to extend the source electrode. It is connected to an electrode pattern (wiring electrode pattern) 25K1 different from the pattern 25S1.

Then, on the SB side of the second land-side junction (third junction) with another electrode pattern 25K1, the extension lead frame SML1 or another electrode pattern 25K1 transmits a source signal via the source sense bonding wire SSW1. It is connected to the electrode pattern SL1.

That is, the PM1 according to the thirteenth embodiment includes the ceramic substrate 21, the drain electrode pattern 25D1 arranged on the ceramic substrate 21, the source electrode pattern 25S1, the source signal electrode pattern SL1, the gate signal electrode pattern GL1, and the electrodes. An insulating substrate 20 having a pattern 25K1 and a SiC MOSFET Q1 having a source pad electrode SP1 and a gate pad electrode GP1 on the front surface and a drain electrode 38 on the back surface and arranged face-up on the drain electrode pattern 25D1. , An extended lead frame SML1 connected between the source pad electrode SP1 and the source electrode pattern 25S1 and having an extended connection end side with the source pad electrode SP1 connected to the electrode pattern 25K1, an extended lead frame SML1 and a source. The land side of the extended lead frame SML1 and the source electrode pattern 25S1, which are separated from the device-side junction DC and the device-side junction DC with the pad electrode SP1 and whose temperature during device operation is relatively lower than that of the device-side junction DC. The second land-side joint SB of the extended lead frame SML1 and the electrode pattern 25K1 whose temperature during device operation is relatively lower than that of the joint SC and the device-side joint DC, and one end of the source signal electrode pattern SL1. Bonding for gate signal connected between the source sense bonding wire SSW1 whose other end is connected to the second land side joint SB and the gate pad electrode GP1 and the gate signal electrode pattern GL1. A wire GW1 is provided, and the other end of the source sense bonding wire SSW1 is connected to the extension lead frame SML1 or the electrode pattern 25K1 of the second land-side joint SB.

Even in such a configuration, the source sense bonding wire SSW1 should be connected to the second land-side junction SB, which has a relatively lower temperature during operation of the SiC MOSFET Q1 than the device-side junction DC. Therefore, it is possible to reduce the influence of heat on the wire connection due to the operation of high temperature, and it is possible to improve the heat resistance and reliability of the wire connection.

According to PM1 according to the thirteenth embodiment, although the module (resin mold layer (not shown) becomes longer according to the length of the extended lead frame SML1, the gate signal electrode pattern GL1 and the source signal electrode pattern SL1 are bonded. Since it exists between the SB and DC, the wire lengths of the source sense bonding wire SSW1 and the gate signal bonding wire GW1 can both be shortened.

The PM1 shown in the thirteenth embodiment is also applicable to other power modules shown in the thirteenth embodiment.

[14th Embodiment]
In PM1 according to the fourteenth embodiment, the schematic plane pattern configuration of the 1 in 1 module is represented as shown in FIG. 71 (a) and is along the XII-XII line of FIG. 71 (a). The schematic cross-sectional structure is represented as shown in FIG. 71 (b).

Here, as shown in FIGS. 71 (a) and 71 (b), the PM1 according to the 14th embodiment is almost the same as the PM1 according to the 8th embodiment except for the configuration of the insulating substrate 20. Since it has the same configuration, duplicate explanations will be avoided and different parts will be explained.

In PM1 according to the fourteenth embodiment, as shown in FIGS. 71 (a) and 71 (b), a conductive metal plate (for example, a thick copper substrate) 45 is provided. A SiC MOSFET (semiconductor device) Q1 is arranged on the upper surface (U) side of the thick copper substrate 45 via the solder layer 29.

Further, since the thick copper substrate 45 cannot maintain the insulating state by itself, the adhesive insulating layers 43 and 44 made of an inorganic adhesive or the like are arranged on both sides of the SiC MOSFET Q1 on the U side of the thick copper substrate 45. Has been done. The source signal electrode pattern SL1 and the gate signal electrode pattern GL1 are arranged on the adhesive insulating layer 43. The source electrode pattern 25S1 is arranged on the adhesive insulating layer 44.

A water-cooled (liquid-cooled) cooler 49 may be arranged on the lower surface (D) side of the thick copper substrate 45 via an insulating layer (for example, an insulating substrate, an insulating resin sheet, etc.) 47. In the case of the cooler 49, as the refrigerant, for example, water having good thermal conductivity, a mixed liquid in which water and ethylene glycol are mixed at a ratio of 50% each, or a cooling gas (cold air) is used. ..

That is, the PM1 according to the fourteenth embodiment has a conductive thick copper substrate 45, a source electrode pattern 25S1 arranged on the thick copper substrate 45 via the adhesive insulating layers 43 and 44, and a source signal electrode pattern. The SL1 and the gate signal electrode pattern GL1, the SiC MOSFET Q1 having the main pad electrode on the surface and arranged on the substrate, and the lead frame SM1 connected between the source pad electrode SP1 and the source electrode pattern 25S1. , The land-side junction between the lead frame SM1 and the source electrode pattern 25S1, which is separated from the device-side junction DC between the lead frame SM1 and the source pad electrode SP1 and whose temperature during device operation is relatively lower than that of the device-side junction DC. A source sense bonding wire SSW1 connected between the unit SC and the source signal electrode pattern SL1 is provided.

One end of the source sense bonding wire SSW1 is connected to the source signal electrode pattern SL1, and the other end is connected to the lead frame SM1 or the source electrode pattern 25S1 on the land side bonding portion SC side.

In the PM1 according to the fourteenth embodiment, the gate pad electrode GP1 on the surface of the SiC MOSFET Q1 and the gate signal electrode pattern GL1 are connected by a gate signal bonding wire GW1.

Also in PM1 according to the fourteenth embodiment, the lead frame SM1 is applied to the main wiring for the source power line wiring, and the land side where the temperature during operation of the SiC MOSFET Q1 is relatively lower than that of the device side junction DC. By connecting the source sense bonding wire SSW1 to the joint SC side, it is possible to reduce the influence of heat on the wire connection due to the operation of high temperature, and it is possible to improve the heat resistance and reliability of the wire connectivity. Become.

Further, according to PM1 according to the fourteenth embodiment, the adoption of the thick copper substrate 45 makes it possible to reduce the warp of the entire substrate at low cost.

The PM1 shown in the 14th embodiment can be applied to other power modules shown in the 8th to 14th embodiments.

(Specific example of power module)
Hereinafter, specific examples of PM according to the eighth to fourteenth embodiments will be described. Of course, also in the PM described below, the lead frame SM which is the main wiring for the source power line wiring is adopted, and the land side junction SC / SB of the lead frame SM and the source signal electrode pattern SL are connected. A bonding wire SSW for source sense is provided. The main wiring for the source power line wiring may be a wiring lead portion 30SM or an extension lead frame SML.

Although a SiC MOSFET has been described as an example as a semiconductor device in some of the above-described eighth to fourteenth embodiments, a power element (switching element) arranged in the PM has been described as an example. May be an element other than the SiC MOSFET.

For example, the switching element may be a SiC-IGBT, a SiC-IGBT, a SiC-bipolar transistor, a SiC-JFET, or the like.

In FIG. 32, when the switching element is a SiC-IGBT, the source pad electrode SP, the drain electrode 38, the gate pad electrode GP, and the source sense pad electrode SSP are the emitter pad electrode, collector electrode, and gate of the SiC-IGBT, respectively. Corresponds to pad electrodes and emitter sense pad electrodes.

When the switching element is a SiC-bipolar transistor, the source pad electrode SP, the drain electrode 38, the gate pad electrode GP, and the source sense pad electrode SSP are the emitter pad electrode, collector electrode, and base of the SiC-bipolar transistor, respectively. Corresponds to pad electrodes and emitter sense pad electrodes (not shown).

The PM according to the eighth to fourteenth embodiments is not limited to the 1 in 1 module type, the 2 in 1 module type, and the 6 in 1 module type PM, and is not limited to, for example, a 4 in 1 (four-in-one) module type. PM, 7 in 1 (seven in one) module type PM equipped with a snubber capacitor in 6 in 1 module, 8 in 1 (eight in one) module type PM, 12 in 1 (twelve in one) module type PM , 14 in 1 (fourteen in one) It can also be applied to module type PM.

(Specific examples of semiconductor devices)
Schematic circuit representations of the 1 in 1 module type PM50 SiC MOSFETs of the PMs according to the eighth to fourteenth embodiments, which are applicable as semiconductor devices, are shown as shown in FIG. 28.

FIG. 28 shows a diode DI connected in antiparallel to the SiC MOSFET Q. The main electrode of the SiC MOSFET Q is represented by a drain terminal DT and a source terminal ST. Further, it is also possible to realize (not shown) the IGBT of the 1 in 1 module 50 which is the PM according to the 8th to 14th embodiments and can be applied as a semiconductor device.

Further, the detailed circuit representation of the 1 in 1 module type PM50 SiC MOSFET which is the PM according to the 8th to 14th embodiments and can be applied as a semiconductor device is shown as shown in FIG. 29.

The PM according to the eighth to fourteenth embodiments includes, for example, a PM50 in which the semiconductor device is a 1 in 1 module type. That is, a SiC MOSFET Q in which a plurality of MOSFET cells are connected in parallel is built in one module. Further, a plurality of SiC MOSFET chips can be mounted in one module, and as an example, 5 chips (MOSFETs × 5) can be connected in parallel. It is also possible to mount a part of the five chips for diode DI.

More specifically, as shown in FIG. 29, sense MOSFETs Qs are connected in parallel with the SiC MOSFET Q. The sense MOSFET Qs are formed as fine transistors in the same chip as the SiC MOSFET Q.

In FIG. 29, SS is a source sense terminal, CS is a current sense terminal, and G is a gate terminal. Also in the eighth to fourteenth embodiments, the sense MOSFET Qs may be formed as fine transistors in the same chip in the SiC MOSFET Q.

(Circuit configuration)
Next, in PM according to the 8th to 14th embodiments, a circuit configuration example of a semiconductor device will be described more specifically.

Here, it is a module applicable as a semiconductor device of PM according to the 8th to 14th embodiments, and is a PM in which two semiconductor devices are sealed in one mold resin, a so-called 2 in 1 module. The type of PM will be described.

The circuit configuration of the 2 in 1 module type PM (2 in 1 module) 130A to which the SiC MOSFETs Q1 and Q4 are applied as the semiconductor device is shown, for example, as shown in FIG.

That is, as shown in FIG. 30, the 2 in 1 module 130A includes a half-bridge built-in module in which two SiC MOSFETs Q1 and Q4 are built in as one module.

Here, the module can be regarded as one large transistor, but the built-in transistor may be one chip or a plurality of chips. That is, there are 1 in 1, 2 in 1, 4 in 1, 6 in 1 modules, etc. For example, a module containing two transistors (chips) on one module is 2 in 1, A module containing two sets of 2 in 1 is called 4 in 1, and a module containing three sets of 2 in 1 is called 6 in 1.

As shown in FIG. 30, the 2 in 1 module 130A contains two SiC MOSFETs Q1 and Q4 and diodes DI1 and DI4 connected in antiparallel to the SiC MOSFETs Q1 and Q4 as one module. The diodes DI1 and DI4 can be omitted by using a parasitic diode.

In FIG. 30, G1 is a lead terminal (so-called gate terminal) for the gate signal of the SiC MOSFET Q1, and S1 is a lead terminal (so-called source sense terminal) for the source signal of the SiC MOSFET Q1. Similarly, G4 is a lead terminal for the gate signal of the SiC MOSFET Q4, and S4 is a lead terminal for the source signal of the SiC MOSFET Q4.

Further, P is a positive power input terminal electrode, N is a negative power input terminal electrode, and O is an output terminal electrode.

Further, it is a module applicable as a semiconductor device of the power module according to the 8th to 14th embodiments, and realizes a 2 in 1 module (not shown) to which an IGBT is applied as the semiconductor devices Q1 and Q4. You can also do it.

Further, P is a positive power input terminal electrode, N is a negative power input terminal electrode, and O is an output terminal electrode.

The same applies to the semiconductor devices (Q2 and Q5) and the semiconductor devices (Q3 and Q6) applicable to PM2 according to the twelfth embodiment shown in FIG. 69.

(Device structure)
An example of the semiconductor devices (Q1 and Q4) applicable to the PM according to the eighth to fourteenth embodiments, the schematic cross-sectional structure of the SiC MOSFET 130A including the source pad electrode SP and the gate pad electrode GP is as follows. It is represented as shown in FIG.

As shown in FIG. 31, the SiC MOSFET 130A is formed on the surface of the semiconductor layer 31 composed of the n-high resistance layer, the p-body region 32 formed on the surface side of the semiconductor layer 31, and the p-body region 32. In the source region 33, the gate insulating film 34 arranged on the surface of the semiconductor layer 31 between the p body regions 32, the gate electrode 35 arranged on the gate insulating film 34, and the source region 33 and the p body region 32. It includes a connected source electrode 36, an n + drain region 37 arranged on the back surface opposite to the front surface of the semiconductor layer 31, and a drain electrode 38 connected to the n + drain region 37.

The gate pad electrode GP is connected to the gate electrode 35 arranged on the gate insulating film 34, and the source pad electrode SP is connected to the source electrode 36 connected to the source region 33 and the p body region 32. Further, as shown in FIG. 31, the gate pad electrode GP and the source pad electrode SP are arranged on the passive interlayer insulating film 39 covering the surface of the SiC MOSFET 130A.

Although not shown, a transistor structure having a fine structure may be formed in the semiconductor layer 31 below the gate pad electrode GP and the source pad electrode SP.

Further, as shown in FIG. 31, in the transistor structure in the central portion, the source pad electrode SP may be extended and arranged on the passive interlayer insulating film 39.

In FIG. 31, the SiC MOSFET 130A is composed of a planar gate type n-channel vertical SiC MOSFET, but as shown in FIG. 34 described later, it is configured by a trench gate type n-channel vertical SiC T MOSFET 130C or the like. It may have been done.

Alternatively, as the semiconductor device applicable to the PM according to the eighth to fourteenth embodiments, a GaN-based FET or the like can be adopted instead of the SiC MOSFET 130A.

The same applies to the semiconductor devices (Q2 / Q5, Q3 / Q6) applicable to the PM according to the eighth to fourteenth embodiments.

Further, the semiconductor devices Q1 to Q6 applicable to the PM according to the eighth to fourteenth embodiments include semiconductors having a bandgap energy of, for example, 1.1 eV to 8 eV, which is called a wide bandgap type. Can be used.

Similarly, it is an example of semiconductor devices (Q1 and Q4) applicable to PM according to the eighth to fourteenth embodiments, and is a schematic cross-sectional structure of an IGBT 130B including an emitter pad electrode EP and a gate pad electrode GP. Is represented as shown in FIG.

As shown in FIG. 32, the IGBT 130B has a semiconductor layer 31 composed of an n-high resistance layer, a p-body region 32 formed on the surface side of the semiconductor layer 31, and an emitter formed on the surface of the p-body region 32. Connected to the region 33E, the gate insulating film 34 arranged on the surface of the semiconductor layer 31 between the p-body regions 32, the gate electrode 35 arranged on the gate insulating film 34, and the emitter region 33E and the p-body region 32. The emitter electrode 36E is provided, a p + collector region 37P arranged on the back surface opposite to the front surface of the semiconductor layer 31, and a collector electrode 38C connected to the p + collector region 37P.

The gate pad electrode GP is connected to the gate electrode 35 arranged on the gate insulating film 34, and the emitter pad electrode EP is connected to the emitter electrode 36E connected to the emitter region 33E and the p body region 32. Further, as shown in FIG. 32, the gate pad electrode GP and the emitter pad electrode EP are arranged on the passive interlayer insulating film 39 covering the surface of the IGBT 130B.

Although not shown, an IGBT structure having a fine structure may be formed in the semiconductor layer 31 below the gate pad electrode GP and the emitter pad electrode EP.

Further, as shown in FIG. 32, even in the central IGBT structure, the emitter pad electrode EP may be extended and arranged on the passive interlayer insulating film 39.

In FIG. 32, the IGBT 130B is composed of a planar gate type n-channel vertical IGBT, but may be composed of a trench gate type n-channel vertical IGBT or the like.

The same applies to the semiconductor devices (Q2 / Q5, Q3 / Q6) applicable to the PM according to the eighth to fourteenth embodiments.

As the semiconductor devices Q1 to Q6, a SiC-based power device such as a SiC DI MOSFET or a SiC T MOSFET, or a GaN-based power device such as a GaN-based HEMT can be applied. In some cases, power devices such as Si-based MOSFETs and IGBTs can also be applied.

―SiC DI MOSFET―
An example of a semiconductor device applicable to PM according to the eighth to fourteenth embodiments, the schematic cross-sectional structure of the SiC DI MOSFET 130D is represented as shown in FIG. 33.

The SiC DI MOSFET 130D shown in FIG. 33 has a semiconductor layer 31 composed of an n-high resistance layer, a p-body region 32 formed on the surface side of the semiconductor layer 31, and n + formed on the surface of the p-body region 32. In the source region 33, the gate insulating film 34 arranged on the surface of the semiconductor layer 31 between the p body regions 32, the gate electrode 35 arranged on the gate insulating film 34, and the source region 33 and the p body region 32. It includes a connected source electrode 36, an n + drain region 37 arranged on the back surface opposite to the front surface of the semiconductor layer 31, and a drain electrode 38 connected to the n + drain region 37.

In FIG. 33, in the SiC DI MOSFET 130D, a p-body region 32 and an n + source region 33 formed on the surface of the p-body region 32 are formed by double ion implantation (DII), and the source pad electrode SP is a source. It is connected to the source electrode 36 connected to the region 33 and the p-body region 32.

The gate pad electrode GP (not shown) is connected to the gate electrode 35 arranged on the gate insulating film 34. Further, as shown in FIG. 33, the source pad electrode SP and the gate pad electrode GP are arranged on the passive interlayer insulating film 39 so as to cover the surface of the SiC DI MOSFET 130D.

As shown in FIG. 33, the SiC DI MOSFET 130D is a junction type because a depletion layer as shown by a broken line is formed in a semiconductor layer 31 composed of an n-high resistance layer sandwiched between p body regions 32. A channel resistance R _JFET is formed due to the FET (JFET) effect. Further, as shown in FIG. 33, a body diode BD is formed between the p-body region 32 and the semiconductor layer 31.

―SiC T MOSFET―
An example of a semiconductor device applicable to the PM according to the eighth to fourteenth embodiments, the schematic cross-sectional structure of the SiC T MOSFET is represented as shown in FIG. 34.

The SiC T MOSFET 130C shown in FIG. 34 has a semiconductor layer 31N composed of n layers, a p-body region 32 formed on the surface side of the semiconductor layer 31N, and an n + source region 33 formed on the surface of the p-body region 32. The trench gate electrode 35TG formed through the p-body region 32 and formed through the gate insulating film 34 and the interlayer insulating films 39U / 39B in the trench formed up to the semiconductor layer 31N, and the source region 33 and the p-body region. It includes a source electrode 36 connected to 32, an n + drain region 37 arranged on the back surface opposite to the front surface of the semiconductor layer 31N, and a drain electrode 38 connected to the n + drain region 37.

In FIG. 34, the SiC T MOSFET 130C penetrates the p-body region 32, and the trench gate electrode 35TG is formed in the trench formed up to the semiconductor layer 31N via the gate insulating film 34 and the interlayer insulating films 39U / 39B. The source pad electrode SP is connected to the source electrode 36 connected to the source region 33 and the p body region 32.

The gate pad electrode GP (not shown) is connected to the trench gate electrode 35TG arranged on the gate insulating film 34. Further, as shown in FIG. 34, the source pad electrode SP and the gate pad electrode GP are arranged on the passive interlayer insulating film 39U so as to cover the surface of the SiC T MOSFET 130C.

In the SiC T MOSFET 130C, the channel resistance R _JFET associated with the junction FET (JFET) effect such as the SiC DI MOSFET 130D is not formed. Further, a body diode BD is formed between the p-body region 32 and the semiconductor layer 31N, as in FIG. 33.

(Application example)
It is a three-phase AC inverter 40A configured by using PM according to the eighth to fourteenth embodiments, a SiC MOSFET is applied as a semiconductor device, and a snubber capacitor C is connected between a power supply terminal PL and a ground terminal NL. An example of the circuit configuration is shown in FIG. 35.

Similarly, an IGBT can be applied as a semiconductor device to realize a three-phase AC inverter (not shown) in which a snubber capacitor C is connected between the power supply terminal PL and the ground terminal NL.

When the PM is connected to the power supply E and the switching operation is performed, since the switching speed of the SiC MOSFET or the IGBT is high, a large surge voltage −Ldi / dt is generated by the inductance L of the connection line. For example, if the current change di = 300A and the time change dt = 100nsec accompanying switching, then di / dt = 3 × 10 ⁹ (A / s).

The value of the surge voltage −Ldi / dt changes depending on the value of the inductance L, but the surge voltage −Ldi / dt is superimposed on the power supply E. The snubber capacitor C connected between the power supply terminal PL and the ground terminal NL is provided for the purpose of reducing the value of the inductance L that affects the magnitude of the surge voltage −Ldi / dt.

(Concrete example)
Next, with reference to FIG. 36, a three-phase AC inverter 42A configured by applying a SiC MOSFET as a semiconductor device and using PM according to the eighth to fourteenth embodiments will be described.

As shown in FIG. 36, the three-phase AC inverter 42A includes a power module unit 130 connected to the gate driver (GD) 180, a three-phase AC motor unit 51, a power supply, or a storage battery (E) 53, and a converter 55. And prepare. The power module unit 130 is connected to a U-phase, V-phase, and W-phase inverter corresponding to the U-phase, V-phase, and W-phase of the three-phase AC motor unit 51.

The power module unit 130 is connected between the positive terminal (+) P and the negative terminal (-) N of the converter 55 to which the power supply or the storage battery (E) 53 is connected, and the SiC MOSFET Q1 with an inverter configuration. It includes Q4, Q2 / Q5, and Q3 / Q6, and the control signal from the GD180 is supplied to the gates of the SiC MOSFETs Q1 / Q4, the SiC MOSFETs Q2 / Q5, and the SiC MOSFETs Q3 / Q6, respectively. Further, freewheel diodes DI1 to DI6 are connected in antiparallel between the source and drain of the SiC MOSFETs Q1 to Q6, respectively.

Further, although not shown, it is also possible to apply an IGBT as a semiconductor device and realize a three-phase AC inverter configured by using the power module according to the eighth to fourteenth embodiments.

As described above, according to the eighth to fourteenth embodiments, it is possible to reduce the influence of heat on the wire connection due to the operation at a high temperature, and to improve the heat resistance and reliability of the wire connection. PM and its manufacturing method can be realized.

In the PM according to the eighth to fourteenth embodiments, the module applicable as a semiconductor device may be, for example, a power module having a three-power terminal structure.

Further, the semiconductor device applicable to the PM according to the 8th to 14th embodiments is not limited to the SiC-based power device, but is a power called a wide bandgap type such as a GaN-based power device or a Si-based power device. Devices can also be adopted.

Further, the PM according to each of the 8th to 14th embodiments is not limited to the 1 in 1 module, the 2 in 1 module, or the 6 in 1 module, and all of them are the 4 in 1 module type PM and the 7 in. It can also be applied to 1-module type PM, 8 in 1 module type PM, 12 in 1 module type PM, 14 in 1 module type PM, and the like.

[Fifteenth Embodiment]
(Basic configuration)
The schematic planar pattern configuration of the power module (PM) 1 according to the fifteenth embodiment is shown as shown in FIG. 72 (a), and has a schematic cross-sectional structure along the line XIII-XIII of FIG. 72 (a). Is represented as shown in FIG. 72 (b). In addition, in FIG. 72 (a) and FIG. 72 (b), the case where three semiconductor devices (modules) Q11, Q12, and Q13 are mounted is exemplified as an example of a plurality of semiconductor devices (power transistor devices) Q. ing.

As shown in FIG. 72B, PM1 according to the fifteenth embodiment includes an insulating layer 21, a graphite substrate 18GH arranged on the insulating layer 21 and having an anisotropic thermal conductivity, and a graphite substrate. It includes semiconductor devices Q11, Q12, and Q13 that are arranged on 18GH and generate heat during operation.

The graphite substrate 18GH is provided with a surface electrode layer 23 of the graphite substrate on the surface thereof. That is, the graphite substrate 18GH may include a composite material having one surface bonded to a metal.

The semiconductor devices Q11, Q12, and Q13 may be bonded to each other via the surface electrode layer 23 and the silver fired layer 27.

Further, the graphite of the graphite substrate 18GH is oriented with high thermal conductivity in the thickness direction.

The insulating layer 21 may include a ceramic substrate. Further, the copper foil layer 22 may be arranged on the back surface of the ceramic substrate. That is, the insulating layer 21 may include a ceramic substrate and a metal composite material.

(Modification 1)
FIG. 73 (a) shows PM1 according to the first modification of the fifteenth embodiment, and the schematic cross-sectional structure along the line XIII-XIII having the same schematic planar pattern configuration as that of FIG. 72 (a). It is expressed as. In addition, in FIG. 73A, as an example of a plurality of semiconductor devices (power transistor devices) Q, for example, a case where three semiconductor devices (modules) Q11, Q12, and Q13 are mounted is exemplified.

As shown in FIG. 73A, the PM1 according to the first modification of the fifteenth embodiment is arranged on the insulating layer 21, the graphite substrate 18GH arranged on the insulating layer 21, and the graphite substrate 18GH. The semiconductor devices Q11, Q12, and Q13 are provided.

The graphite substrate 18GH is provided with a surface electrode layer 23 of the graphite substrate on the surface thereof. Further, the graphite substrate 18GH is provided with a back surface electrode layer 24 of the graphite substrate on the back surface. That is, the graphite substrate 18GH may include a composite material in which both the front surface and the back surface are bonded to a metal.

The semiconductor devices Q11, Q12, and Q13 may be bonded to each other via the surface electrode layer 23 and the silver fired layer 27.

The graphite of the graphite substrate 18GH is oriented with high thermal conductivity in the thickness direction.

Further, as shown in FIG. 73A, the insulating layer 21 and the graphite substrate 18GH are in contact with each other via the heat conductive layer 25.

The insulating layer 21 may include a ceramic substrate. Further, the ceramic substrate may be provided with the back surface electrode layer 22 of the ceramic substrate on the back surface. That is, the insulating layer 21 may include a ceramic substrate and a metal composite material.

The heat conductive layer 25 may include any of a heat conductive sheet layer, a solder layer, and a silver fired layer.

The ceramic substrate may include any of Al ₂ O ₃ , Si ₃ N ₄ , or Al N.

(Modification 2)
FIG. 73 (b) shows PM1 according to the second modification of the fifteenth embodiment, and the schematic cross-sectional structure along the line XIII-XIII having the same schematic planar pattern configuration as that of FIG. 72 (a). It is expressed as. In addition, in FIG. 73B, as an example of a plurality of semiconductor devices (power transistor devices) Q, for example, a case where three semiconductor devices (modules) Q11, Q12, and Q13 are mounted is exemplified.

As shown in FIG. 73B, PM1 according to the second modification of the fifteenth embodiment is arranged on the insulating layer 21, the graphite substrate 18GH arranged on the insulating layer 21, and the graphite substrate 18GH. The semiconductor devices Q11, Q12, and Q13 are provided.

The graphite substrate 18GH is provided with a surface electrode layer 23 of the graphite substrate on the surface thereof. Further, the graphite substrate 18GH is provided with a back surface electrode layer 24 of the graphite substrate on the back surface. That is, the graphite substrate 18GH may include a composite material in which both the front surface and the back surface are bonded to a metal.

The semiconductor devices Q11, Q12, and Q13 may be bonded to each other via the surface electrode layer 23 and the silver fired layer 27.

The graphite of the graphite substrate 18GH is oriented with high thermal conductivity in the thickness direction.

Further, as shown in FIG. 73 (b), the insulating layer 21 and the graphite substrate 18GH are in contact with each other via the heat conductive layer 25.

The insulating layer 21 may include a ceramic substrate. Further, the front surface electrode layer 36 of the ceramic substrate may be arranged on the front surface of the ceramic substrate, and the back surface electrode layer 22 of the ceramic substrate may be arranged on the back surface. As a result, the insulating layer 21 includes a ceramic substrate and a metal composite material, and may include a DBC substrate.

The heat conductive layer 25 may include any of a heat conductive sheet layer, a solder layer, and a silver fired layer.

The ceramic substrate may include any of Al ₂ O ₃ , Si ₃ N ₄ , or Al N.

The PM1 according to the fifteenth embodiment and the first and second modifications thereof has a laminated structure of a graphite substrate 18GH and an insulating layer (ceramic substrate).

The PM1 according to the fifteenth embodiment and the modifications 1 and 2 thereof has a power module structure using a low-cost ceramic substrate, for example, a DBC substrate to which Al ₂ O ₃ is bonded to a graphite plate. May be. Further, as a bonding method, a vertical structure may be provided such that the carbon sheet, the solder layer, or the silver fired layer is used for bonding. As a result, a substrate structure that ensures low cost and reliability can be obtained. Further, it may have a vertical structure in which a graphite plate and an Al ₂ O ₃ ceramic substrate are joined by brazing or the like.

(Comparative Example 1 in the Fifteenth Embodiment)
The schematic cross-sectional structure of PM1A according to Comparative Example 1 in the fifteenth embodiment is shown as shown in FIG. 74 (a). Note that FIG. 74 (a) shows, for example, a case where three semiconductor devices (modules) Q11, Q12, and Q13 are mounted as an example of a plurality of semiconductor devices (power transistor devices) Q.

As shown in FIG. 74 (a), PM1A according to Comparative Example 1 in the fifteenth embodiment has an insulating layer 21N, a thick copper layer 22U arranged on the surface of the insulating layer 21N, and a back surface of the insulating layer 21N. The thick copper layer 22D arranged in the above, and the semiconductor devices Q11, Q12, and Q13 arranged on the thick copper layer 22U via the solder layer 27S are provided. As a result, the thick copper insulating substrate is composed of the thick copper layer 22U / the insulating layer 21N / the thick copper layer 22D. As the insulating layer 21N, for example, a SiN-based ceramic layer or the like can be applied.

(Comparative Example 2 in the Fifteenth Embodiment)
The schematic cross-sectional structure of PM1A according to Comparative Example 2 in the fifteenth embodiment is shown as shown in FIG. 74 (b). Similar to FIG. 74 (a), FIG. 74 (b) shows a case where, for example, three semiconductor devices (modules) Q11, Q12, and Q13 are mounted as an example of a plurality of semiconductor devices (power transistor devices) Q. Has been done.

As shown in FIG. 74B, PM1A according to Comparative Example 2 in the fifteenth embodiment has an insulating layer 21S, a thick copper layer 22U arranged on the surface of the insulating layer 21S, and a back surface of the insulating layer 21S. The copper foil layer 22C arranged in the above and the semiconductor devices Q11, Q12, and Q13 arranged on the thick copper layer 22U via the solder layer 27S are provided. The thick copper layer 22U / insulating layer 21S / copper foil layer 22C constitutes a thick copper insulating sheet substrate composed of thick copper + an insulating sheet as a result. As the insulating layer 21S, for example, an epoxy resin, a sheet layer of a semi-curing material using a polyimide resin as a base resin, or the like can be applied.

(Thermal resistance simulation)
In the thermal resistance simulation, the boundary conditions were 65 ° C. on the back surface, heat transfer coefficient = 5000 (W / m ² K), and the calorific value of the SiC semiconductor device Q was 100 W.

The back surface of 65 ° C. is assumed to be fixed at 65 ° C. as a boundary condition on the lower surface of the cooler 28. Assuming a water-cooled type, the heat transfer coefficient is set to 5000 (W / m ² K). That is, in the aluminum cooler 28, the cooling water temperature is fixed at 65 ° C. The heat transfer coefficient is the ease with which heat is transferred through the contact surfaces of two objects, and is different from the thermal conductivity.

The thermal resistance Rthjw (° C./W) represents the thermal resistance between Tj (junction temperature) and Tw (cooling water temperature) of the SiC semiconductor device Q.

-Fifteenth embodiment-
The schematic cross-sectional structure applied to the thermal resistance simulation of PM1 according to the fifteenth embodiment is shown as shown in FIG. 75 (a), and a heat conductive layer 25T and a cooler 28 are added. The material / thickness of each layer applied to the thermal resistance simulation is as follows. That is, the semiconductor device Q (SiC / 0.25 mm), the silver fired layer 27 (silver / 0.03 mm), the surface electrode layer 23 (Cu / 1 mm) of the graphite substrate 18GH, the graphite substrate 18GH (graphite / 3 mm), and the ceramic substrate. 21 (Al ₂ O ₃ / 0.32 mm), back electrode layer 22 (Cu / 0.5 mm) of ceramic substrate 21, heat conductive layer 25T (carbon sheet / 0.2 mm), cooler 28 (Al / 1 mm). be.

An example in which a ceramic substrate (Si ₃ N ₄ ) is applied as the insulating layer 21 is as follows. That is, the semiconductor device Q (SiC / 0.25 mm), the silver fired layer 27 (silver / 0.08 mm), the surface electrode layer 23 (Cu / 1 mm) of the graphite substrate 18GH, the graphite substrate 18GH (graphite / 3 mm), and the ceramic substrate. 21 (Si ₃ N ₄ / 0.32 mm), back electrode layer 22 (Cu / 0.5 mm) of ceramic substrate 21, heat conductive layer 25T (carbon sheet / 0.2 mm), cooler 28 (Al / 1 mm). be.

-Modification example 1-
The schematic cross-sectional structure applied to the thermal resistance simulation of PM1 according to the first modification of the fifteenth embodiment is shown as shown in FIG. 75 (b), and the heat conductive layer 25T and the cooler 28 are added. There is. The material / thickness of each layer applied to the thermal resistance simulation is as follows. That is, the semiconductor device Q (SiC / 0.25 mm), the silver fired layer 27 (silver / 0.03 mm), the surface electrode layer 23 (Cu / 0.7 mm) of the graphite substrate 18GH, the graphite substrate 18GH (graphite / 3 mm), and the like. Back electrode layer 24 (Cu / 0.7 mm) of graphite substrate 18GH, heat conductive layer 25 (carbon sheet / 0.2 mm), ceramic substrate 21 (Al ₂ O ₃ / 0.32 mm), back electrode layer of ceramic substrate 21 22 (Cu / 0.1 mm), heat conductive layer 25T (carbon sheet / 0.2 mm), cooler 28 (Al / 1 mm).

-Modification example 2-
The schematic cross-sectional structure applied to the thermal resistance simulation of PM1 according to the second modification of the fifteenth embodiment is shown as shown in FIG. 75 (c), and the heat conductive layer 25T and the cooler 28 are added. There is. The material / thickness of each layer applied to the thermal resistance simulation is as follows. That is, the semiconductor device Q (SiC / 0.25 mm), the silver fired layer 27 (silver / 0.03 mm), the surface electrode layer 23 (Cu / 0.7 mm) of the graphite substrate 18GH, the graphite substrate 18GH (graphite / 3 mm), and the like. Back electrode layer 24 (Cu / 0.7 mm) of graphite substrate 18GH, heat conductive layer 25 (carbon sheet / 0.2 mm), front electrode layer 36 (Cu / 0.1 mm) of ceramic substrate 21, ceramic substrate 21 (Al). ₂ O ₃ / 0.32 mm), the back electrode layer 22 (Cu / 0.1 mm) of the ceramic substrate 21, the heat conductive layer 25T (carbon sheet / 0.2 mm), and the cooler 28 (Al / 1 mm).

-Comparative Example 1 in the Fifteenth Embodiment-
The schematic cross-sectional structure applied to the thermal resistance simulation of PM1A according to Comparative Example 1 in the fifteenth embodiment is shown in FIG. 76 (a). The material / thickness of each layer applied to the thermal resistance simulation is as follows. That is, the semiconductor device Q (SiC / 0.25 mm), the solder layer 27S (solder / 0.15 mm), the thick copper layer 22U (Cu / 1.5 mm), the insulating layer 21N (Si ₃ N ₄ / 0.32 mm), The thick copper layer 22D (Cu / 1.5 mm), the heat conductive layer 25T (carbon sheet / 0.2 mm), and the cooler 28 (Al / 1 mm).

-Comparative Example 2 in the Fifteenth Embodiment-
The schematic cross-sectional structure applied to the thermal resistance simulation of PM1A according to Comparative Example 2 in the fifteenth embodiment is shown in FIG. 76 (b). That is, the material / thickness of each layer applied to the thermal resistance simulation is as follows. Semiconductor device Q (SiC / 0.25 mm), solder layer 27S (solder / 0.15 mm), thick copper layer 22U (Cu / 3 mm), insulating layer 21S (resin sheet / 0.1 mm), copper foil layer 22C (Cu). /0.3 mm), heat conductive layer 25T (carbon sheet / 0.2 mm), cooler 28 (Al / 1 mm).

(Comparison result of thermal resistance simulation)
The comparison result of the thermal resistance simulation between PM1 according to the fifteenth embodiment and the modified examples 1 and 2 and PM1A according to the comparative examples 1 to 4 in the fifteenth embodiment is shown as shown in FIG. 77. To.

C1 of FIG. 77 corresponds to an example in which the solder layer 27S is applied as the chip bottom bonding layer in Comparative Example 1 in the fifteenth embodiment, as shown in FIG. 76 (a).

C2 of FIG. 77 corresponds to an example in which the solder layer 27S is applied as the chip bottom bonding layer in Comparative Example 2 in the fifteenth embodiment, as shown in FIG. 76 (b).

C3 in FIG. 77 represents Comparative Example 3 in the fifteenth embodiment, and corresponds to the example in which the silver fired layer 27 is applied as the subchip bonding layer in Comparative Example 1 in the fifteenth embodiment.

C4 in FIG. 77 represents Comparative Example 4 in the fifteenth embodiment, and corresponds to the example in which the silver fired layer 27 is applied as the subchip bonding layer in Comparative Example 2 in the fifteenth embodiment.

According to the thermal resistance simulation results of PM1A according to Comparative Examples 1 to 4 in the fifteenth embodiment, the value of the thermal resistance Rthjw (° C./W) is about 0. 85 (° C./W)/0.83 (° C./W)/0.75 (° C./W)/0.73 (° C./W) has been obtained.

E1 of FIG. 77 corresponds to a structural example of Cu (23) / graphite substrate (18GH) / ceramic substrate 21 (Al ₂ O ₃ ) / Cu (22) in the fifteenth embodiment.

E2 of FIG. 77 shows Cu (23) / graphite substrate (18GH) / Cu (24) / heat conductive layer (carbon sheet: 25) / ceramic substrate 21 (Al ₂ O) in the first modification of the fifteenth embodiment. ₃ ) / Cu (22) corresponds to the structural example.

E3 of FIG. 77 shows Cu (23) / graphite substrate (18GH) / Cu (24) / heat conductive layer (carbon sheet: 25) / Cu (36) / ceramic substrate in the second modification of the fifteenth embodiment. It corresponds to the structural example of 21 (Al ₂ O ₃ ) / Cu (22).

According to the thermal resistance simulation results of PM1 according to the fifteenth embodiment and the modified examples 1 and 2, the value of the thermal resistance Rthjw (° C./W) is about 0.73 with respect to E1 / E2 / E3. (° C./W) /0.74 (° C./W)/0.74 (° C./W) is obtained.

In PM1A according to Comparative Examples 1 and 2 in the fifteenth embodiment, Comparative Examples 3.4 (when the bottom of the chip is joined with a silver firing layer) in the fifteenth embodiment, or the fifteenth embodiment and Compared with PM1 according to the modified examples 1 and 2, the result that the thermal resistance is relatively high is obtained.

On the other hand, in Comparative Examples 3 and 4 (when the bottom of the chip is joined with a silver fired layer) in the 15th embodiment, the thermal resistance is about the same as that of PM1 according to the 15th embodiment and its modifications 1 and 2. Simulation results are obtained. However, Comparative Example 3 and 4 in the 15th embodiment in which the solder layer 27S of PM1A according to Comparative Examples 1 and 2 in the 15th embodiment was replaced with the silver fired layer 27 (the bottom of the chip is bonded with the silver fired layer). If this is the case), the reliability will decrease. The reason for this is as follows.

In the case of the structures of Comparative Examples 1 to 4 in the fifteenth embodiment, since a copper plate having a thickness of 2 mm or more is used for the substrate, the solder layer 27S whose thermal stress is a joint due to a temperature change due to the environmental temperature or heat generation of the device. It is applied to the silver fired layer 27. At this time, since the linear expansion coefficient of copper (Cu) and SiC (the elongation rate of the material with respect to the temperature change) is significantly different (the linear expansion coefficient of copper is, for example, about 16.5 ppm / K, and the linear expansion coefficient of SiC is For example, about 3 ppm / K), the reliability of PM1A according to Comparative Examples 3 and 4 in the fifteenth embodiment having a joint portion made of a fired silver layer is lowered. The reason why the solder layer can maintain the reliability more than the silver fired layer is that the elastic modulus is low. However, solder has a low melting point and is not suitable for driving a SiC device at a high temperature. Here, ppm represents 10 ^-6 . The same applies hereinafter.

On the other hand, in PM1 according to the fifteenth embodiment shown in FIG. 77 and the modified examples 1 and 2 thereof, reliability can be maintained when the bottom of the chip is joined with a silver firing layer. The reason for this is as follows. That is, graphite has anisotropy of, for example, about 25.2 ppm / K in the low heat conduction direction and about -0.6 ppm / K in the high heat conduction direction, and if it is a composite substrate with copper (Cu / graphite / Cu), The synthetic linear expansion coefficient is lower than that of copper. Further, since the elastic modulus of the material is as soft as 50 GPa as compared with 120 GPa of copper, the thermal stress applied to the joint under the chip can be reduced. As a result, in PM1 according to the fifteenth embodiment and the modified examples 1 and 2, the silver firing joint is performed as compared with the comparative examples 3.4 (when the bottom of the chip is bonded with the silver firing layer) in the fifteenth embodiment. The reliability of the department will be maintained. That is, in PM1 according to the fifteenth embodiment and the modified examples 1 and 2, the thermal resistance is relatively low and high reliability can be obtained.

(Fifteenth Embodiment: Dependence on Ceramic Substrate)
The thermal resistance simulation result when the material of the ceramic substrate 21 is changed to Al ₂ O ₃ / Si ₃ N ₄ / Al N in PM1 according to the fifteenth embodiment is shown in FIG. 78. In FIG. 78, E11 / E12 / E13 correspond to an example in which Al ₂ O ₃ / Si ₃ N ₄ / Al N is used as the ceramic substrate 21. According to the thermal resistance simulation result, the value of thermal resistance Rthjw (° C./W) is about 0.73 (° C./W)/0.67 (° C./W)/0.64 (° C./W) /0.64 (° C./W) /0.64 (° C./W) /0.64 (° C./W) /0.64 (° C./W) ° C / W) has been obtained.

In the example of FIG. 78, the material / thickness of each layer applied to the thermal resistance simulation is as follows. That is, the semiconductor device Q (SiC / 0.25 mm), the silver fired layer 27 (silver / 0.03 mm), the surface electrode layer 23 (Cu / 1 mm) of the graphite substrate, the graphite substrate 18GH (graphite / 3 mm), and the ceramic substrate 21. (Al ₂ O ₃ / Si ₃ N ₄ / AlN 0.32 mm), back electrode layer 22 (Cu / 1 mm) of ceramic substrate, heat conductive layer 25T (carbon sheet / 0.2 mm), cooler 28 (Al / 1 mm) ).

(Variation Example 1: Dependency of Combination between Thermal Conductive Layer and Ceramic Substrate)
In PM1 according to the first modification of the fifteenth embodiment, the heat conductive layer 25 (heat conductive sheet layer / solder layer / silver fired layer) and the ceramic substrate 21 (Al ₂ O ₃ / Si ₃ N ₄ / Al N) The thermal resistance simulation result by the combination is shown as shown in FIG. 79.

E21 in FIG. 79 corresponds to the heat conductive sheet layer / Al ₂ O ₃ as a combination of the heat conductive layer 25 / ceramic substrate 21.

E22 in FIG. 79 corresponds to the solder layer / Al ₂ O ₃ as a combination of the heat conductive layer 25 / the ceramic substrate 21.

E23 in FIG. 79 corresponds to the silver fired layer / Al ₂ O ₃ as a combination of the heat conductive layer 25 / ceramic substrate 21.

E24 in FIG. 79 corresponds to the heat conductive sheet layer / Si ₃ N ₄ as a combination of the heat conductive layer 25 / ceramic substrate 21.

E25 in FIG. 79 corresponds to the solder layer / Si ₃ N ₄ as a combination of the heat conductive layer 25 / ceramic substrate 21.

E26 in FIG. 79 corresponds to the silver fired layer / Si ₃ N ₄ as a combination of the heat conductive layer 25 / ceramic substrate 21.

E27 in FIG. 79 corresponds to the heat conductive sheet layer / AlN as a combination of the heat conductive layer 25 / ceramic substrate 21.

E28 in FIG. 79 corresponds to the solder layer / AlN as a combination of the heat conductive layer 25 / ceramic substrate 21.

E29 in FIG. 79 corresponds to the silver fired layer / AlN as a combination of the heat conductive layer 25 / ceramic substrate 21.

In the example of FIG. 79, the material / thickness of each layer applied to the thermal resistance simulation is as follows. That is, the semiconductor device Q (SiC / 0.25 mm), the silver fired layer 27 (silver / 0.03 mm), the surface electrode layer 23 (Cu / 0.8 mm) of the graphite substrate 18GH, the graphite substrate 18GH (graphite / 3 mm), and the like. Backside electrode layer 24 (Cu / 0.8 mm) of graphite substrate 18GH, heat conductive layer 25 (heat conductive sheet layer / 0.2 mm / solder layer / silver fired layer), ceramic substrate 21 (Al ₂ O ₃ / 0.32 mm) / Si ₃ N ₄ / AlN) The back surface electrode layer 22 (Cu / 0.1 mm) of the ceramic substrate 21, the heat conductive layer 25T (carbon sheet / 0.2 mm), and the cooler 28 (Al / 1 mm).

In PM1 according to the first modification of the fifteenth embodiment, the heat conductive layer 25 (heat conductive sheet layer / solder layer / silver fired layer) and the ceramic substrate 21 (Al ₂ O ₃ / Si ₃ N ₄ / Al N) According to the thermal resistance simulation result by the combination, the value of the thermal resistance Rthjw (° C./W) is about 0.75 (° C./W) with respect to E21 / E22 / E23 / E24 / E25 / E26 / E27 / E28 / E29. W) /0.73 (° C./W)/0.72 (° C./W)/0.70 (° C./W)/0.68 (° C./W)/0.67 (° C./W) /0. 68 (° C./W)/0.66 (° C./W)/0.65 (° C./W) has been obtained.

(Variation Example 2: Dependency of Combination of Thermal Conductive Layer and Ceramic Substrate in Fifteenth Embodiment)
In PM1 according to the second modification of the fifteenth embodiment, the combination of the heat conductive layer (heat conductive sheet layer / solder layer / silver fired layer) and the ceramic substrate (Al ₂ O ₃ / Si ₃ N ₄ / Al N) is used. The thermal resistance simulation result is shown in FIG. 80.

E31 in FIG. 80 corresponds to the heat conductive sheet layer / Al ₂ O ₃ as a combination of the heat conductive layer 25 / ceramic substrate 21.

E32 in FIG. 80 corresponds to the solder layer / Al ₂ O ₃ as a combination of the heat conductive layer 25 / the ceramic substrate 21.

E33 in FIG. 80 corresponds to the silver fired layer / Al ₂ O ₃ as a combination of the heat conductive layer 25 / ceramic substrate 21.

E34 in FIG. 80 corresponds to the heat conductive sheet layer / Si ₃ N ₄ as a combination of the heat conductive layer 25 / ceramic substrate 21.

E35 in FIG. 80 corresponds to the solder layer / Si ₃ N ₄ as a combination of the heat conductive layer 25 / ceramic substrate 21.

E36 in FIG. 80 corresponds to the silver fired layer / Si ₃ N ₄ as a combination of the heat conductive layer 25 / ceramic substrate 21.

E37 in FIG. 80 corresponds to the heat conductive sheet layer / AlN as a combination of the heat conductive layer 25 / ceramic substrate 21.

E38 in FIG. 80 corresponds to the solder layer / AlN as a combination of the heat conductive layer 25 / ceramic substrate 21.

E39 in FIG. 80 corresponds to the silver fired layer / AlN as a combination of the heat conductive layer 25 / ceramic substrate 21.

In the example of FIG. 80, the material / thickness of each layer applied to the thermal resistance simulation is as follows. That is, the semiconductor device Q (SiC / 0.25 mm), the silver fired layer 27 (silver / 0.03 mm), the surface electrode layer 23 (Cu / 0.8 mm) of the graphite substrate 18GH, the graphite substrate 18GH (graphite / 3 mm), and the like. Backside electrode layer 24 (Cu / 0.8 mm) of graphite substrate 18GH, heat conduction layer 25 (heat conduction sheet layer / 0.2 mm / solder layer / silver fired layer), surface electrode layer 36 (Cu / 0) of ceramics substrate 21 .1 mm), ceramic substrate 21 (Al ₂ O ₃ / 0.32 mm / Si ₃ N ₄ / AlN), back electrode layer 22 (Cu / 0.1 mm) of the ceramic substrate 21, heat conductive layer 25T (carbon sheet / 0). .2 mm), cooler 28 (Al / 1 mm).

In PM1 according to the second modification of the fifteenth embodiment, the heat conductive layer 25 (heat conductive sheet layer / solder layer / silver fired layer) and the ceramic substrate 21 (Al ₂ O ₃ / Si ₃ N ₄ / Al N) According to the results of the thermal resistance simulation by the combination, the value of the thermal resistance Rthjw (° C./W) is about 0.75 (° C./E39) with respect to E31 / E32 / E33 / E34 / E35 / E36 / E37 / E38 / E39. W) /0.73 (° C./W)/0.72 (° C./W)/0.70 (° C./W)/0.68 (° C./W)/0.67 (° C./W) /0. 68 (° C./W)/0.66 (° C./W)/0.65 (° C./W) has been obtained.

As shown in FIGS. 72 (a) and 72 (b), PM1 according to the fifteenth embodiment is, for example, conductive graphite provided on the upper surface (first surface) of the SiN-based ceramic substrate 21. The substrate (graphite plate) 18GH, the back surface electrode pattern (first electrode pattern) 22 such as Cu foil provided on the lower surface (second surface) of the ceramic substrate 21, and the Cu foil arranged on the graphite substrate 18GH. It includes a graphite insulating substrate 20 having a surface electrode pattern (second electrode pattern) 23, and three semiconductor devices Q11, Q12, and Q13 arranged side by side along the X direction of the illustrated arrow on the surface electrode pattern 23.

Although not shown, PM1 according to the fifteenth embodiment is a mold-type package type power module in which the outer periphery of the semiconductor devices Q11, Q12, and Q13 is entirely sealed (resin-molded) with a mold resin. Alternatively, it is housed in a case and becomes a case-type package type power module.

The graphite substrate 18GH has a plate-type structure that is thicker than the ceramic substrate 21 and has a substantially uniform thickness.

In PM1 according to the fifteenth embodiment, the graphite substrate 18GH has an anisotropic heat conductivity in the thickness direction (XZ plane, YZ plane) rather than the plane direction (XY plane) as the graphite thermal conductivity orientation. It has thermal conductivity.

That is, the graphite substrate 18GH has an orientation direction in which heat diffusion is most favorable with respect to the arrangement direction (plane direction) of the semiconductor devices Q11, Q12, and Q13.

In the graphite substrate 18GH, the orientation direction in which the heat diffusion is the best is the direction in which the thermal conductivity is relatively high. For example, when the direction of arrangement of the semiconductor devices Q11, Q12, and Q13 is the X direction, X is used. The YZ direction is substantially perpendicular to the direction (YZ plane substantially orthogonal to the X direction).

The orientation direction is expressed as GH (XZ) when the orientation of the graphite substrate 18GH is in the XZ direction, and is expressed as GH (YZ) when the orientation is in the YZ direction.

That is, the PM1 according to the fifteenth embodiment is arranged side by side on the graphite substrate 18GH having an anisotropic thermal conductivity and the graphite substrate 18GH, and three semiconductor devices Q11, Q12, and Q13 that generate heat during operation. The direction of alignment of the semiconductor devices Q11, Q12, and Q13 on the plane of the graphite substrate 18GH is -45 degrees with respect to the X direction (alignment direction) in which the thermal conductivity of the graphite substrate 18GH is relatively low. The range is +45 degrees or less (allowable deviation amount: see FIG. 81).

Further, PM1 according to the fifteenth embodiment includes a ceramic substrate 21, a graphite substrate 18GH having an anisotropic thermal conductivity arranged on the upper surface of the ceramic substrate 21, and a lower surface facing the upper surface of the ceramic substrate 21. Three semiconductor devices arranged side by side on the graphite substrate 18GH via the back electrode pattern 22 arranged on the graphite substrate 18GH, the surface electrode pattern 23 arranged on the graphite substrate 18GH, and the surface electrode pattern 23, and generating heat during operation. With Q11, Q12, and Q13, the graphite substrate 18GH has an orientation in which the thermal conductivity is relatively higher in the thickness direction than in the plane direction, and three semiconductor devices Q11, Q12, and Q13 are provided on the plane of the graphite substrate 18GH. The direction of arrangement is in the range of −45 degrees or more and +45 degrees or less with respect to the orientation direction in which the heat conductivity of the graphite substrate 18GH is relatively low.

Alternatively, PM1 according to the fifteenth embodiment includes a graphite insulating substrate 20 including a ceramic substrate 21 and a graphite substrate 18GH having an anisotropic thermal conductivity arranged on the upper surface of the ceramic substrate 21, and a graphite substrate. The graphite substrate 18GH has three semiconductor devices Q11, Q12, and Q13 that are arranged side by side on the 18GH and generate heat during operation, and the graphite substrate 18GH has an orientation in which the thermal conductivity is relatively higher in the thickness direction than in the plane direction, and graphite. The direction of arrangement of the three semiconductor devices Q11, Q12, and Q13 on the plane of the substrate 18GH is in the range of -45 degrees or more and +45 degrees or less with respect to the orientation direction in which the thermal conductivity of the graphite substrate 18GH is relatively low. Will be done.

In PM1 according to the fifteenth embodiment, the semiconductor devices Q11, Q12, and Q13 are respectively bonded to the surface electrode pattern 23 via the silver firing layer 27. In addition to silver firing, SnAgCu-based solder or the like can also be used for joining the semiconductor devices Q11, Q12, and Q13. That is, by arranging the surface electrode pattern 23 on the graphite substrate 18GH, not only solder bonding but also bonding by silver firing is possible.

In PM1 according to the fifteenth embodiment shown in FIGS. 72 (a) and 72 (b), for example, the thickness of the ceramic substrate 21 is about 0.32 mm and the thickness (H) of the graphite substrate 18GH is about 0.32 mm. Approximately 2.5 mm, the thickness of the back surface electrode pattern 22 is approximately 0.2 mm, the thickness of the front surface electrode pattern 23 is approximately 0.3 mm, the thickness of the silver fired layer 27 is approximately 60 μm, and the semiconductor devices Q11, Q12, and Q13. The thickness is said to be about 350 μm.

The heat transfer coefficient of the back surface electrode pattern 22 is about 30,000 (W / m ² K).

Further, the semiconductor devices Q11, Q12, and Q13 have a size (C1 × L1) of about 5 mm × 5 mm in the X direction and the Y direction. In the semiconductor devices Q11, Q12, and Q13, the distance from each edge of the surface electrode pattern 23 is X1 and the distance between the semiconductor devices Q11, Q12, and Q13 is X2 in the X direction, and the distance between the semiconductor devices Q11, Q12, and Q13 is X2. Therefore, the distance from each edge of the surface electrode pattern 23 is set to Y1.

In PM1 according to the fifteenth embodiment, the distance X2 in the direction of arrangement of the semiconductor devices Q11, Q12, and Q13 is shorter than the distance Y1 from the semiconductor devices Q11, Q12, and Q13 to the edge of the graphite substrate 18GH.

The semiconductor devices Q11, Q12, and Q13 are not limited to power transistor devices such as SiC MOSFETs and IGBTs, and may include, for example, FRD (Fast Recovery Diode), Schottky barrier diode, or the like. A module type in which the outer periphery of a plurality of chips is sealed with a molding resin or a case may be used.

In the case of a SiC MOSFET, the upper side is a source electrode and the lower side is a drain electrode. In the case of an IGBT, the upper side is an emitter electrode and the lower side is a collector electrode. The same applies to other semiconductor devices described later.

Further, although not shown, a heat sink made of Al as a radiator, a radiator fin, a radiator pin, or a cooler may be joined to the back surface electrode pattern 22. In the case of the liquid cooling (water cooling) type, as a refrigerant, for example, water, a mixed liquid in which water and ethylene glycol are mixed at a ratio of 50% each, or a cooling gas (cold air) has good thermal conductivity. Things are used.

According to PM1 according to the fifteenth embodiment, in the modular structure when a plurality of semiconductor devices Q are arranged side by side, the orientation direction of the graphite substrate 18GH is approximated to the direction in which the heat diffusion is the best (substantially). By making them match), it is possible to further reduce the thermal resistance.

It should be noted that the plurality of semiconductor devices Q are not limited to three, and are not limited to the case where they are arranged side by side.

Further, the graphite insulating substrate 20 may be configured such that an insulating substrate or the like is arranged on the upper surface of the graphite substrate 18GH, and is provided with a graphite plate, for example, an AMB substrate, a DBC substrate, a DBA substrate, or the like. Insulation substrate can be applied.

(Graphite plate)
(Basic configuration)
In PM1 according to the fifteenth embodiment, it is possible to use two types of graphite plates having different orientations as the graphite substrate 18GH.

The schematic configuration (laminated structure example) of the graphite sheet (graphene) GS constituting the graphite plate applicable as the graphite substrate 18GH is shown as shown in FIG.

The graphite substrate 18GH includes a graphite plate 18GH (XZ) having an XZ orientation having a higher thermal conductivity in the thickness direction than a plane direction and a graphite plate 18GH having a YZ orientation having a higher thermal conductivity in the thickness direction than the plane direction (XZ). YZ) is applicable, the graphite plate 18GH (YZ) is represented as shown in FIG. 81 (a), and the graphite plate 18GH (XZ) is represented as shown in FIG. 81 (b).

As shown in FIG. 73, the graphite sheets GS1, GS2, GS3, ..., GSn on each surface composed of n layers have a large number of hexagonal covalent bonds in one laminated crystal structure, and each surface has a covalent bond. The graphite sheets GS1, GS2, GS3, ..., and GSn are bonded by a van der Waals force.

That is, graphite, which is a carbon-based anisotropic heat transfer material, is a layered crystal having a hexagonal network structure of carbon atoms, and has anisotropy in heat conduction. Graphite sheets GS1, GS2, shown in FIG. GS3 ..... GSn has a higher thermal conductivity (high thermal conductivity) in the crystal plane direction (on the XY plane) than in the thickness direction of the Z axis.

On the other hand, as shown in FIG. 81 (a), in the case of a graphite plate 18GH (YZ) having a GH (YZ) orientation, for example, X = 5 (W / mK), Y = 1500 (W / mK), Z. = 1500 (W / mK) with thermal conductivity.

On the other hand, as shown in FIG. 81 (b), in the case of the graphite plate 18GH (XZ) having the GH (XZ) orientation, for example, X = 1500 (W / mK) and Y = 5 (W / mK). ), Z = 1500 (W / mK).

Both the graphite plates 18GH (XZ) and 18GH (YZ) have a density of about 2.2 (g / cm ³ ), a thickness of about 0.7 mm to 10 mm, and a size of 40 mm × 40 mm. It is about the following.

Here, in PM1 according to the fifteenth embodiment in which the graphite plate 18GH (YZ) is applied as the graphite substrate 18GH, as shown in FIGS. 81A and 81B, the semiconductor devices Q11 and Q12. The graphite substrate 18GH has a relatively low thermal conductivity that is substantially orthogonal to the GH (YZ) orientation direction TD of the graphite substrate 18GH, where the orientation PD1 of the arrangement of Q13 almost coincides with the X direction. On the plane (board surface) of the above, a range of an angle θ of about −45 degrees or more and +45 degrees or less, preferably a range of an angle θ of about −30 degrees or more and +30 degrees or less in the clockwise direction.

On the other hand, in PM1 according to the fifteenth embodiment in which the graphite plate 18GH (XZ) is applied as the graphite substrate 18GH, the semiconductor devices Q11, Q12, and Q13 are shown in FIGS. 81 (c) and 81 (d). The graphite substrate 18GH has a relatively low thermal conductivity that is substantially orthogonal to the GH (XZ) orientation orientation direction TD of the graphite substrate 18GH, in which the arrangement direction PD1 almost coincides with the Y direction. On the plane (board surface) of the above, the range of the angle θ of about −45 degrees or more and +45 degrees or less in the clockwise direction, preferably the range of the angle θ of about −30 degrees or more and +30 degrees or less.

(Simulation of thermal resistance by orientation direction)
The results of simulating the thermal resistance characteristics of PM1 according to the fifteenth embodiment using GH (XZ) orientation as an example are shown in FIG. 82 (a), and GH (YZ) orientation is an example. The result of the simulation is shown in FIG. 82 (b).

In both simulations, in PM1 shown in FIGS. 72 (a) and 72 (b), the thermal resistance (° C./W) when X1 is 2 mm and Y1 is 2 mm, 4 mm, 6 mm, 8 mm, and 10 mm. ) Is 2 mm (shown (a)), 4 mm (shown (b)), 6 mm (shown (c)), 8 mm (shown (d)), and 10 mm (shown (e)). did.

As is clear from FIGS. 82 (a) and 82 (b), in the modular structure in which a plurality of semiconductor devices Q are arranged, if the graphite substrate 18GH is oriented in GH (XZ), the distance (X2) in the X direction is extended. The thermal resistance decreases as the distance (Y1) in the Y direction increases in the case of GH (YZ) orientation.

Further, from the above results, it was found that thermal interference can be prevented if there is a certain distance (for example, X2 · Y1 = about 4 mm or more) in the orientation direction with low thermal conductivity.

That is, as shown in FIGS. 82 (a) and 82 (b), in PM1 in which a plurality of semiconductor devices Q are arranged in the X direction, a GH (YZ) oriented graphite substrate 18GH is used to reduce thermal resistance. Is more effective, and in PM1 in which a plurality of semiconductor devices Q are arranged in the Y direction, the GH (XZ) oriented graphite substrate 18GH is more effective for lowering the thermal resistance.

According to PM1 according to the fifteenth embodiment, the graphite insulating substrate 20 using the graphite plates 18GH (XZ) and 18GH (YZ) which are anisotropic but have high thermal conductivity is used, and the graphite substrate 18GH is used. In the module structure when a plurality of semiconductor devices Q are arranged side by side, the Y direction of the plurality of semiconductor devices Q is set as the orientation direction TD of the graphite plates 18GH (XZ) and 18GH (YZ) orientations that have the best heat diffusion. -By making the arrangement substantially perpendicular to the X direction, it is possible to provide a power module having good thermal diffusivity, structurally simple, inexpensive, and capable of lowering thermal resistance.

[16th Embodiment]
(Rough configuration)
In PM1 according to the sixteenth embodiment, the schematic bird's-eye view pattern configuration before the resin mold is shown as shown in FIG. 83 (a), and the schematic plane pattern configuration is shown as shown in FIG. 83 (b). It is represented by. Note that FIGS. 83 (a) and 83 (b) show specific examples of the arrangement of semiconductor devices in PM1, and are 2 in 1 module types to which SiC MOSFETs Q1 and Q4 are applied as the semiconductor device Q. A module with a built-in half bridge is illustrated.

That is, in the PM1 according to the 16th embodiment, for example, as shown in FIG. 30A, two SiC MOSFETs Q1 and Q4 connected in series are included in one module of a half-bridge built-in module. It has a configuration.

The PM1 according to the sixteenth embodiment includes a positive power input terminal electrode (positive power terminal) P and a negative power supply arranged on the first side of a ceramics substrate 21 coated with a resin mold layer (not shown). On the first side of the input terminal electrode (negative power terminal) N, the gate terminal GT1 (gate G1) and the source sense terminal SST1 (source S1) arranged on the second side adjacent to the first side. The output terminal electrode (output terminal) O arranged on the third side facing each other, and the gate terminal GT4 (gate G4) and the source sense terminal SST4 (source S4) arranged on the fourth side facing the second side. ) And.

The PM1 according to the 16th embodiment is a power module having a 4-power terminal structure provided with two output terminals O.

Here, as shown in FIGS. 83 (a) and 83 (b), the two SiC MOSFETs Q1 and Q4 each include three devices (chips), and each chip of the SiC MOSFET Q1 has a gate terminal GT1. -Commonly connected to the source sense terminal SST1, each chip of the SiC MOSFET Q4 is commonly connected to the gate terminal GT4 and the source sense terminal SST4.

The gate terminal GT1 and the source sense terminal SST1 are connected to the gate signal electrode pattern GL1 and the source signal electrode pattern SL1 of the SiC MOSFET Q1, and the gate terminal GT4 and the source sense terminal SST4 are the gate signal electrode pattern GL4 and the source of the SiC MOSFET Q4. It is connected to the signal electrode pattern SL4.

As shown in FIGS. 83 (a) and 83 (b), the gate signal electrode patterns GL1 and GL4 and the source signal electrode patterns SL1 and SL4 have gate terminals GT1 and GT4 for external extraction and source sense terminals SST1 and SST4. Is connected by soldering or the like.

As shown in FIGS. 83 (a) and 83 (b), the gate signal electrode patterns GL1 and GL4 and the source signal electrode patterns SL1 and SL4 are arranged on the signal boards 261, 264, and the signal boards 261, 264 It may be connected to the ceramic substrate 21 by soldering or the like.

The signal substrates 261, 264 can be formed of a ceramic substrate. The ceramic substrate may be formed of, for example, Al ₂ O ₃ , AlN, SiN, AlSiC, or at least an insulating SiC on the surface.

Although not shown in FIGS. 83 (a) and 83 (b), diodes (DI1) are arranged in antiparallel between the drain D1 and the source S1 of the SiC MOSFETs Q1 and Q4 and between the drain D4 and the source S4. -DI4) may be connected.

The positive power terminal P / negative power terminal N, the gate terminals GT1 / GT4 for external extraction, and the source sense terminals SST1 / SST4 can be formed by, for example, Cu.

The surface electrode pattern 23 (23D1, 23D4, 23DN) which is the main wiring conductor can be formed by, for example, Cu.

Here, in the example shown in FIGS. 83 (a) and 83 (b), in the module with a built-in half bridge of the 2 in 1 module type, the surface electrode pattern 23D1 is the high side device (SiC MOSFET Q1). Functions as a drain electrode pattern for.

Further, the surface electrode pattern 23D4 functions as a drain electrode pattern for the low side device (SiC MOSFET Q4) and also functions as a source electrode pattern (23S1) for the high side device. That is, the drain electrode pattern 23D4 is a drain electrode of the SiC MOSFET Q4 and at the same time a source electrode of the SiC MISFET Q1.

Further, the surface electrode pattern 23DN connected to the negative power terminal N functions as a source electrode pattern (23S4) for the row side device.

That is, in the PM1 according to the sixteenth embodiment, as shown in FIGS. 83A and 83B, the SiC MOSFET Q1 is mounted on the surface electrode pattern 23D1 and the drain D1 is a surface electrode pattern. Along with being connected to the 23D1, the source S1 is connected to the surface electrode pattern 23D4 via a bonding wire (bonding wire for a source signal (not shown)).

Similarly, the SiC MOSFET Q4 is mounted on the surface electrode pattern 23D4, the drain D4 is connected to the surface electrode pattern 23D4, and the source S4 is connected to the surface electrode via a bonding wire (bonding wire for a source signal (not shown)). It is connected to the pattern 23DN.

Further, in PM1 according to the 16th embodiment, although not shown, a source sense bonding wire for connecting the source sense pad electrode of the SiC MOSFET Q1 to the source signal electrode pattern SL1 and a gate pad electrode are provided. A bonding wire for a gate signal connected to the gate signal electrode pattern GL1 is provided.

Similarly, although not shown, a source sense bonding wire that connects the source sense pad electrode of the SiC MOSFET Q4 to the source signal electrode pattern SL4 and a gate signal bonding wire that connects the gate pad electrode to the gate signal electrode pattern GL4. And.

That is, a source sense bonding wire for connecting the source sense pad electrode is wedge-bonded to the source signal electrode patterns SL1 and SL4 of the SiC MOSFETs Q1 and Q4.

Other configurations and the like are substantially the same as in the case of the fifteenth embodiment, and a graphite insulating substrate is formed on the upper surface of the ceramic substrate 21 and on the lower surface of the surface electrode patterns 23D1, 23D4, 23DN. YZ) A graphite substrate 18GH with orientation is arranged.

That is, as shown in FIGS. 83 (a) and 83 (b), the PM1 according to the sixteenth embodiment includes the ceramic substrate 21 and the graphite substrate arranged on the upper surface (first surface) of the ceramic substrate 21. 18GH, a surface electrode pattern (second electrode pattern) 23D1, 23D4, 23DN arranged on the graphite substrate 18GH, and a back surface electrode pattern (first electrode pattern) arranged on the lower surface (second surface) of the ceramic substrate 21. It is provided with a graphite insulating substrate (not shown) and a plurality of SiC MOSFETs Q1 and Q4 arranged side by side along the X direction of the illustrated arrow on the surface electrode patterns 23D1 and 23D4.

In PM1 according to the sixteenth embodiment, the GH (YZ) orientation of the graphite substrate 18GH is an orientation direction TD that is substantially orthogonal to the X direction of the arrangement of the plurality of SiC MOSFETs Q1 and Q4 and substantially coincides with the Y direction. Orthogonal. That is, the allowable amount of deviation (allowable deviation amount) of the alignment direction PD1 of the SiC MOSFETs Q1 and Q4 arranged side by side in the X direction with respect to the orientation direction TD of GH (YZ) is the orientation direction corresponding to the X direction. A range of an angle θ of about −45 degrees or more and +45 degrees or less in the clockwise direction, preferably a range of an angle θ of about -30 degrees or more and +30 degrees or less on the plane (board surface) of the graphite substrate 18GH with reference to PD. It is said that.

In FIGS. 83A and 83B, when the semiconductor device Q is a SiC MOSFET, the GT1 and GT4 are lead terminals (so-called gate terminals) for the gate signals of the SiC MOSFETs Q1 and Q4. The SST1 and SST4 are lead terminals (so-called source sense terminals) for the source signals of the SiC MOSFETs Q1 and Q4.

On the other hand, in the case of the IGBT, the GT1 and GT4 are lead terminals for the gate signal of the IGBT Q1 and Q4 (so-called gate terminals G1 and G4 in FIG. 30B), and the SST1 and SST4 are IGBT Q1. The lead terminals for the emitter signal of Q4 (so-called emitter sense terminals E1 and E4 in FIG. 30B) are used.

According to PM1 according to the sixteenth embodiment, by adopting the graphite insulating substrate to which the graphite substrate 18GH is applied, the direction PD1 of the arrangement of the plurality of semiconductor devices Q can be set to GH (XZ) and GH (YZ) of the graphite substrate 18GH. ) Orientation direction A high thermal diffusion effect can be expected by approximating the orientation direction PD, which has a relatively low thermal conductivity and is substantially orthogonal to the TD.

That is, the PM1 according to the 16th embodiment can also be a power module having good thermal diffusivity, structurally simple, inexpensive, and capable of lowering thermal resistance.

The 2 in 1 module type PM1 can be applied to a structure having a source electrode pattern above the semiconductor devices Q1 and Q4, and is limited to a 2 in 1 module type PM1. do not have.

(Heat interference)
Hereinafter, the heat interference action in PM according to the fifteenth to eighteenth embodiments will be described.

In PM, if the semiconductor device Q is arranged close to each other for miniaturization, or if the graphite substrate 18GH is made thicker than necessary in order to obtain a high heat diffusion effect, heat interference is likely to occur.

In the PM according to the fifteenth to eighteenth embodiments, the schematic cross-sectional structure for explaining the heat interference action is described by taking as an example the case where the distance between devices (for example, X2 in FIG. 72 (a)) is widened. , As shown in FIG. 84 (a), and the schematic planar configuration corresponding to FIG. 84 (a) is represented as shown in FIG. 84 (b). The cross-sectional structure of FIG. 84 (a) corresponds to the cross-section along the XIV-XIV line of FIG. 84 (b).

Here, assuming that the heat from the semiconductor devices QA and QB diffuses downward at an angle of about 45 degrees, the thickness (H) of the graphite substrate 18GH is shown in FIGS. 84 (a) and 84 (b). When H1 mm is set and the distance between devices is X2a (X2a> X2) mm, there is almost no region where the heat T1 from the semiconductor device QA and the heat T1 from the semiconductor device QB interfere with each other in the graphite substrate 18GH.

That is, the distance X2a in the X direction of the arrangement of the semiconductor devices QA / QB is the distance (H) from the semiconductor devices QA / QB to the lower surface (second surface) side facing the upper surface (first surface) of the graphite substrate 18GH. It is desirable that it is at least twice as long as).

On the other hand, in the PM according to the fifteenth to eighteenth embodiments, the schematic cross-sectional structure for explaining the heat interference effect is shown in FIG. 85, taking as an example the case where the distance between devices (X2) is narrowed. Represented as shown in a), the schematic planar configuration corresponding to FIG. 85 (a) is represented as shown in FIG. 85 (b). The cross-sectional structure of FIG. 85 (a) corresponds to the cross-section along the XV-XV line of FIG. 85 (b).

As shown in FIGS. 85 (a) and 85 (b), when the thickness (H) of the graphite substrate 18GH is H1 mm and the distance between devices is X2b (X2b <X2) mm, the heat from the semiconductor device QA A region T3 is formed in which T2 and heat T2 from the semiconductor device QB interfere with each other in the graphite substrate 18GH. The region T3 is not desirable because it causes an increase in thermal resistance.

As shown in FIG. 86 (a), when the distance between devices is X2a (X2a> X2) mm, the thickness (H) of the graphite substrate 18GH is H2 (H2) in anticipation of a high heat diffusion effect. When the thickness is increased to> H1) mm, a region T3 is formed in which the heat T1 from the semiconductor device QA and the heat T1 from the semiconductor device QB interfere with each other in the graphite substrate 18GH.

On the contrary, as shown in FIG. 86 (b), when the distance between devices is X2b (X2b <X2) mm, the thickness (H) of the graphite substrate 18GH is changed to H3 (H3) at the expense of the heat diffusion effect. When the thickness is reduced to <H1) mm, there is almost no region where the heat T1 from the semiconductor device QA and the heat T1 from the semiconductor device QB interfere with each other in the graphite substrate 18GH.

As described above, since there is a trade-off relationship between the thickness (H) of the graphite substrate 18GH and the device-to-device distance (X2) of the semiconductor devices QA and QB, the orientation direction TD of the graphite substrate 18GH is set. By approximating (substantially matching) the direction in which the heat diffusion is the best, the heat resistance can be reduced more effectively.

It should be noted that when the semiconductor devices QA and QB are arranged diagonally with a predetermined angle, the distance between the devices can be slightly increased as compared with the case where the semiconductor devices are arranged linearly on the same straight line. Although it becomes difficult to form a region where heat interferes with each other, it is difficult to completely suppress it.

(Semiconductor device placement example)
87 (a) to 87 (c) show an arrangement example of the semiconductor devices Q11, Q12, and Q13 in the PM according to the fifteenth to eighteenth embodiments.

In the semiconductor devices Q11, Q12, and Q13, for example, as shown in FIG. 87 (a), the orientation PDA of the arrangement arrangement on the substrate surface of the graphite substrate 18GH is substantially linear along the orientation direction PD corresponding to the X direction. Placed in.

Further, as shown in FIG. 87 (b), for example, the semiconductor devices Q11, Q12, and Q13 are predetermined with respect to the orientation direction PD along the X direction corresponding to one side of the graphite substrate 18GH on the substrate surface of the graphite substrate 18GH. It may be arranged substantially linearly in the direction PDB of the arrangement inclined in the minus (-) direction by the angle of.

Further, in the semiconductor devices Q11, Q12, and Q13, for example, as shown in FIG. 87 (c), the semiconductor device Q11 is oriented in the X direction with respect to the central semiconductor device Q12 on the substrate surface of the graphite substrate 18GH. It is also possible to arrange the semiconductor device Q13 in a so-called staggered pattern in the direction PDD of the arrangement inclined in the plus (+) direction by a predetermined angle, and in the direction PDC of the arrangement in which the semiconductor device Q13 is inclined in the minus direction by a predetermined angle from the orientation direction PD. It is possible.

Further, as shown in FIG. 89, for example, on the substrate surface of the graphite substrate 18GH of FIG. 87 (c), either one of the semiconductor devices Q11 or Q13 is arranged on the same straight line as the semiconductor device Q12 (orientation direction PD). The combination may be such that either one of the semiconductor devices Q11 or Q13 is arranged in the direction PDD or PDC of the arrangement inclined by a predetermined angle with respect to the semiconductor device Q12.

(Relationship between arrangement and thermal resistance)
Next, in the PM according to the fifteenth to eighteenth embodiments, the relationship between the amount of displacement of the arrangement of the semiconductor devices and the thermal resistance will be described.

In the PM according to the fifteenth to eighteenth embodiments, the schematic planar configuration of the simulation model used for the thermal resistance simulation is shown as shown in FIG. 88 (a), and the result of the thermal resistance simulation is shown in FIG. It is shown as shown in FIG. 88 (b), and the effect of lowering the thermal resistance (allowable range of the deviation amount) based on the simulation result is shown as shown in FIG. 88 (c).

In the simulation model, as shown in FIG. 88 (a), the semiconductor devices Q11, Q12, and Q13 are arranged in a staggered pattern (alternately with a predetermined deviation amount in the X direction) along the Y direction of the illustrated arrow. The semiconductor devices Q11, Q12, and Q13 have a size (C1 × L1) of 5 mm × 5 mm in the X direction and the Y direction.

In the semiconductor devices Q11 and Q13, the distance X1 from the near edge (near edge) of the surface electrode pattern 23 is 2 mm in the X direction, and the distance Y1 from the near edge is 2 mm in the Y direction. Has been done.

The semiconductor device Q12 has a distance Y2 of 4 mm from the adjacent semiconductor devices Q11 and Q13 in the Y direction.

In the simulation, when X1 of the semiconductor device Q13 is 2 mm, X2 = 0, and when the thermal resistance is increased by 1 mm from 0 in the X direction, when X1 of the semiconductor device Q11 is 2 mm, X3 = 0, and X3. 0 mm (illustration (a)), 1 mm (illustration (b)), 2 mm (illustration (c)), 3 mm (illustration (d)), 4 mm (illustration (e)), 5 mm (illustration (f)), It was carried out in the case of 6 mm (illustration (g)), 7 mm (illustration (h)), 8 mm (illustration (i)), and 9 mm (illustration (j)).

The simulation result of FIG. 88 (b) is standardized with the time of X2 = 9 mm and X3 = 9 mm as 1.

As is clear from the result of FIG. 88 (b), when the semiconductor devices Q11, Q12, and Q13 are arranged in a staggered manner in the Y direction, any one of the semiconductor devices Q11 and Q13 is compared with the semiconductor device Q12 arranged in the center. On the other hand, the thermal resistance increases when the line deviates from the straight line in the Y direction (YZ direction) in the X direction.

In a simulation model having such characteristics, the graphite substrate 18GH is provided with a GH (XZ) orientation along the X direction substantially orthogonal to the Y direction in which the semiconductor devices Q11, Q12, and Q13 are arranged. As shown by the shaded area YR in FIG. 88 (c), if the amount of deviation of the semiconductor devices Q11 and Q13 with respect to the central semiconductor device Q12 is 45 degrees or less, the increase in thermal resistance is suppressed to about 6%. be able to.

That is, in the case of the arrangement examples shown in FIGS. 87 (b) and 87 (c), in order to suppress the increase in thermal resistance, the graphite substrate is substantially orthogonal to the orientation direction TD corresponding to the GH (YZ) orientation of the graphite substrate 18GH. When the orientation direction (X direction) PD is set to 0, the angle of the PDD / PDC in the arrangement of the semiconductor devices Q11 / Q12 / Q13 is approximately clockwise on the plane (board surface) of the graphite substrate 18GH. It is desirable to arrange it so that it is −45 degrees or more and +45 degrees or less, preferably about 30 degrees or more and +30 degrees or less.

FIG. 89 shows another model example used for the thermal resistance simulation in the PM according to the fifteenth to eighteenth embodiments, in which the semiconductor device Q11 is displaced in the X direction with respect to the central semiconductor device Q12. This is an example in which the semiconductor device Q13 is arranged without being arranged and the semiconductor device Q13 is arranged diagonally in the X direction by a predetermined angle.

In the simulation model, the semiconductor devices Q11, Q12, and Q13 have a size (C1 × L1) of 5 mm × 5 mm in the X direction and the Y direction.

In the semiconductor device Q13, the distance X1 from the near edge of the surface electrode pattern 23 is 2 mm in the X direction, and the distance Y1 from the near edge is 2 mm in the Y direction.

The semiconductor device Q12 has a distance Y2 between the adjacent semiconductor devices Q11 and Q13 of about 4 mm in the Y direction.

The semiconductor device Q11 has a distance Y1 from the near edge of 2 mm in the Y direction.

In the case of this simulation model, the semiconductor device Q11 is arranged so that the amount of deviation in the X direction with respect to the central semiconductor device Q12 is 9 or less. That is, the distance of the semiconductor device Q11 (Q12) from the far edge (far edge) in the X direction is 11 (X3 = 9), whereas the distance of the semiconductor device Q13 from the far edge in the X direction is 20 (X2). = 18). As a result, as shown by the shaded area YR in FIG. 88 (c), the amount of deviation of the semiconductor devices Q11 and Q13 with respect to the central semiconductor device Q12 becomes 45 degrees or less, and the increase in thermal resistance is suppressed to about 6%. It becomes possible.

[17th Embodiment]
(Rough configuration)
The schematic bird's-eye view pattern configuration of PM1 according to the seventeenth embodiment is represented as shown in FIG. 90 (a), and the schematic planar pattern configuration is represented as shown in FIG. 90 (b). In addition, in FIG. 90 (a) and FIG. 90 (b), the case where it was applied to PM1 of a three-power terminal structure is exemplified.

Here, as shown in FIGS. 90 (a) and 90 (b), the PM1 according to the 17th embodiment is substantially the same as the PM1 according to the 16th embodiment except for the power terminal structure. It has a configuration.

That is, as shown in FIGS. 90 (a) and 90 (b), the PM1 according to the 17th embodiment includes the ceramic substrate 21 and the graphite substrate arranged on the upper surface (first surface) of the ceramic substrate 21. 18GH, a surface electrode pattern (second electrode pattern) 23D1, 23D4, 23DN arranged on the graphite substrate 18GH, and a back surface electrode pattern (first electrode pattern) arranged on the lower surface (second surface) of the ceramic substrate 21. It includes a graphite insulating substrate provided with (not shown), and a plurality of semiconductor devices (modules) Q1 and Q4 arranged side by side along the X direction of the illustrated arrow on the surface electrode patterns 23D1 and 23D4.

In PM1 according to the seventeenth embodiment, the GH (YZ) orientation in the orientation direction TD of the graphite substrate 18GH is a direction substantially orthogonal to the orientation direction PD along the X direction of the plurality of semiconductor devices Q1 and Q4.

In FIGS. 90 (a) and 90 (b), P is a positive power input terminal electrode, N is a negative power input terminal electrode, and O is an output terminal electrode, which is one output. It is a PM with a three-power terminal structure equipped with a terminal electrode O.

In FIGS. 90 (a) and 90 (b), GL1 is a gate signal electrode pattern to which a lead terminal (not shown) for a gate signal of SiC MOSFET Q1 is connected, and SL1 is of SiC MOSFET Q1. This is a source signal electrode pattern to which a lead terminal for a source signal (not shown) is connected. Similarly, GL4 is a gate signal electrode pattern to which a lead terminal for a gate signal of SiC MOSFET Q4 (not shown) is connected, and SL4 is connected to a lead terminal for a source signal of SiC MOSFET Q4 (not shown). It is a source signal electrode pattern to be made.

Further, BW1 in the figure is a bonding wire for a source signal for commonly connecting the source pad electrode of SiC MOSFET Q1 to the surface electrode pattern 23D4 which also functions as a source electrode, and BW4 is a source pad of SiC MOSFET Q4. A bonding wire for a source signal for commonly connecting an electrode to a surface electrode pattern 23DN that also functions as a source electrode.

Also in the PM1 according to the seventeenth embodiment, the orientation direction PD1 of the arrangement of the plurality of semiconductor devices Q1 and Q4 on the substrate surface of the graphite substrate 18GH is set to the orientation direction (Y) corresponding to the GH (YZ) orientation of the graphite substrate 18GH. Direction) By setting the orientation direction (X direction) PD substantially orthogonal to the TD, the heat diffusivity is good, the structure is simple, the cost is low, and the heat resistance can be further reduced.

[18th Embodiment]
(Rough configuration)
The schematic planar pattern configuration of PM1 according to the eighteenth embodiment is shown as shown in FIG. Note that FIG. 91 illustrates a case where, for example, an IGBT QA1 including a diode FRD QA2 and a Schottky barrier diode is applied as the semiconductor device Q.

As shown in FIG. 91, PM1 according to the eighteenth embodiment has a thermal conductivity and a thermal expansion coefficient (thermal expansion coefficient (CTE)) arranged on the upper surface (first surface) of the ceramic substrate 21. A surface electrode pattern (second electrode pattern) (not shown) in which the graphite substrate 18GH having anisotropy is provided and the IGBT QA1 and FRD QA2 are arranged side by side on the graphite substrate 18GH is the lower surface of the ceramic substrate 21 (not shown). A back surface electrode pattern (first electrode pattern) (not shown) is arranged on the second surface).

The graphite substrate 18GH has an XZ orientation, and the orientation direction PD1 substantially orthogonal to the orientation direction TD of the GH (XZ) indicated by the arrow in the illustration is substantially orthogonal to the orientation direction PD1 of the arrangement arrangement of the IGBT QA1 and the FRD QA2 arranged side by side. Y direction) PD.

The IGBT QA1 and FRD QA2 are actually bonded to the surface electrode pattern on the graphite substrate 18GH, but are not shown here in the description.

Also in the PM1 according to the eighteenth embodiment, the orientation direction PD1 of the arrangement of the IGBT QA1 and the FRD QA2 is substantially orthogonal to the orientation direction (X direction) TD of the GH (XZ) of the graphite substrate 18GH. Direction) By using PD, the heat diffusivity is good, the structure is simple, the cost is low, and the heat resistance can be further reduced.

In PM1 according to the eighteenth embodiment, in addition to the heat diffusion effect due to the graphite structure, the shape such as the orientation and the vertical and horizontal sizes of the semiconductor devices Q (QA1 and QA2) bonded on the surface electrode pattern is changed. It is possible to reduce the stress applied to the joint (silver fired layer).

That is, when a semiconductor device Q such as a square is bonded on a graphite substrate 18GH, the graphite substrate 18GH has an anisotropic coefficient of thermal expansion. Although a large stress is generated in the portion, the stress applied to the joint can be reduced by matching the shape of the semiconductor device Q with the coefficient of thermal expansion of the graphite substrate 18GH.

The reduction of stress applied to the joint portion is not limited to PM1 according to the eighteenth embodiment, and is the same for PM having a configuration according to another embodiment.

(Stress relaxation structure)
Here, the stress applied to the joint portion will be described by taking as an example the case where a graphite substrate having anisotropy in the coefficient of thermal expansion is applied in the PM according to the embodiment.

Taking FRD SC1 and IGBT SC2 as examples, a schematic planar pattern configuration (PMa) illustrating the arrangement of the semiconductor device Q with respect to the graphite substrate 18GH1 is shown as shown in FIG. 19A, and SiC MOS SC3 / SC4 is taken as an example. A schematic planar pattern configuration (PMb) illustrating the arrangement of the semiconductor device Q with respect to the graphite substrate 18GH1 is shown in FIG. 19 (b).

The semiconductor device Q is actually bonded to the surface electrode pattern on the graphite substrate 18GH1, but is not shown here in the description.

In the case of an IGBT including a diode or the like, as shown in FIG. 19A, the FRD SC1 and the IGBT SC2 are arranged side by side as the semiconductor device Q on the graphite substrate 18GH1.

In the case of the SiC MOSFET, as shown in FIG. 19B, the SiC MOS SC3 and SC4 are arranged side by side as the semiconductor device Q on the graphite substrate 18GH1.

Here, when the orientation of the coefficient of thermal expansion of the graphite substrate 18GH1 is, for example, X = 0.5 ppm / K, Y = 25 ppm / K, z = 0.5 ppm / K, FRD SC1, IGBT SC2, SiC MOS SC3. As the SC4, a rectangular device (H1> C1) having an X direction H1 and a Y direction C1 is used, and each Y direction C1 is associated with an orientation having a large coefficient of thermal expansion. This makes it possible to reduce the stress applied to the joint as well as the heat diffusion effect of the graphite substrate 18GH1.

Hereinafter, the stress reducing effect due to the application of the graphite substrate in the PM according to the fifteenth to eighteenth embodiments will be further described.

(Example 1)
The schematic plane pattern configuration of the simulation model MD for simulating the stress applied to the joint is shown in FIG. 20 (a), taking as an example the case where a graphite substrate having anisotropy in the coefficient of thermal expansion is applied. The schematic cross-sectional structure along the VI-VI line of FIG. 20 (a) is represented by FIG. 20 (b).

Here, in the simulation model MD having the configurations shown in FIGS. 20 (a) and 20 (b), the lower surface Cu foil (back surface electrode pattern 22) / Si _{3N 4 substrate} (ceramics substrate 21) / graphite plate (graphite substrate). The laminated substrate structure composed of 18GH1 / 18GH2) / upper surface Cu foil (surface electrode pattern 231-232) is referred to as graphite insulating substrate 20.

Since the graphite plate has anisotropy in thermal conductivity and coefficient of thermal expansion, when a device such as a square is die-bonded, a large stress is generated at the joint due to the difference in the coefficient of thermal expansion in the direction where the coefficient of thermal expansion is large. By matching the shape of the device with the coefficient of thermal expansion of the graphite plate, it is possible to reduce the stress applied to the joint.

In the simulation model MD, as shown in FIGS. 20 (a) and 20 (b), for example, a SiN-based ceramic substrate 21 of 10 mm (GX) × 21 mm (LY1) is used, and the semiconductor device Q is bonded. As the surface electrode pattern 232 to which the surface electrode pattern 231 and the block electrode (not shown) are joined, a Cu foil of 10 mm (GX) × 10 mm (LY) was used.

The surface electrode patterns 231 and 232 are separated by a distance of LY2 = 1 mm.

The back surface electrode pattern 22 has substantially the same dimensions (10 mm × 21 mm) as the ceramic substrate 21.

The graphite substrates 18GH1 and 18GH2 have substantially the same dimensions (10 mm × 10 mm) as the surface electrode patterns 231 and 232.

As the semiconductor device Q, a square SiC MOSFET having 5 mm (H1) × 5 mm (C1) is used (H1 = C1), and the distance from the edge of the surface electrode pattern 231 is X1 (2.5 mm) and Y1 (2.5 mm). ), The silver fired layer 27 is bonded to the substantially central portion on the surface electrode pattern 231.

The orientation of the coefficient of thermal expansion of the graphite substrates 18GH1 and 18GH2 was, for example, X = 25 ppm / K, Y = 0.1 ppm / K, and Z = 0.1 ppm / K.

As shown in FIG. 21, the thickness (mm) of each part is optimized so that the thermal resistance is the lowest. In the case of this simulation model MD, for example, the semiconductor device Q is 0.35 mm thick, the graphite substrates 18GH1 and 18GH2 are 1.5 mm thick, the ceramic substrate 21 is 0.32 mm thick, and the surface electrode patterns 231 and 232 are 0.3 mm thick. The back surface electrode pattern 22 has a thickness of 0.2 mm, and the silver fired layer 27 has a thickness of 0.05 mm, both of which are optimized.

In such a configuration, for example, the stress applied to the silver fired layer (joint portion) 27 can be obtained by calculating the Mises stress at 25 ° C., where no stress is set to 200 ° C.

In the simulation model MD having the configuration shown in FIG. 20, the orientation of the coefficient of thermal expansion of the graphite substrates 18GH1 and 18GH2 is set to, for example, X = 25ppm / K, Y = 0.5ppm / K, Z = 0.5ppm / K. FIG. 22 shows the result (overall warped shape) of the simulation of the stress applied to the silver fired layer 27 in the case of the above.

The warp of the simulation model MD was 26.322 μm at the maximum value and 0.079 μm at the minimum value.

Here, the Mises stress is one of the equivalent stresses used to indicate the stress state generated inside the object with a single value. The definition formula of Mises stress is shown below. In the definition formula, σ1 is the maximum principal stress, σ2 is the intermediate principal stress, and σ3 is the minimum principal stress. Here, each of the principal stresses σ1, σ2, and σ3 is selected from the principal stress in the X direction, the principal stress in the Y direction, and the principal stress in the Z direction acting on the silver fired layer 27.

Next, simulation models with different configurations will be described. In the simulation model MD having the configuration shown in FIG. 20, the case where the square semiconductor device Q is joined is referred to as the simulation model MD1.

FIG. 23A illustrates a case (simulation model MD2) in which vertically long semiconductor devices (H2 × C2, H2> C2) Qa are joined in the simulation model MD having the configuration shown in FIG. 20. As the semiconductor device Qa, a rectangular SiC MOSFET having 6.25 mm (H2) × 4 mm (C2) is used, and the surface is measured by the distance X2 (1.875 mm) and Y2 (3 mm) from the edge of the surface electrode pattern 231. It is joined to the substantially central portion on the electrode pattern 232.

FIG. 23 (b) illustrates a case (simulation model MD3) in which horizontally long semiconductor devices (H3 × C3, H3 <C3) Qb are joined in the simulation model MD having the configuration shown in FIG. 20. As the semiconductor device Qb, a rectangular SiC MOSFET having 4 mm (H3) × 6.25 mm (C3) is used, and the surface is measured by the distance X3 (3 mm) and Y3 (1.875 mm) from the edge of the surface electrode pattern 231. It is joined to the substantially central portion on the electrode pattern 231.

FIG. 23 (c) illustrates a case (simulation model MD4) in which vertically long semiconductor devices (H4 × C4, H4 >> C4) Qc are joined in the simulation model MD having the configuration shown in FIG. 20. As the semiconductor device Qc, a rectangular SiC MOSFET having 8.33 mm (H4) × 3 mm (C4) is used, and the distance from the edge of the surface electrode pattern 231 is X4 (0.835 mm) and Y4 (3.5 mm). , Joined approximately in the center of the surface electrode pattern 231.

FIG. 23 (d) illustrates a case (simulation model MD5) in which horizontally long semiconductor devices (H5 × C5, H5 << C5) Qd are joined in the simulation model MD having the configuration shown in FIG. 20. As the semiconductor device Qd, a rectangular SiC MOSFET having 3 mm (H5) × 8.33 mm (C5) is used, and the distance from the edge of the surface electrode pattern 231 is X5 (3.5 mm) and Y5 (0.835 mm). , Joined approximately in the center of the surface electrode pattern 231.

FIG. 24A shows a case where a graphite substrate having an anisotropy in the coefficient of thermal expansion is applied in the power module according to the fifteenth to eighteenth embodiments, and simulations are performed using the simulation models MD1 to MD5. FIG. 24 (b) is a characteristic diagram for explaining the relationship between the distance from the edge (EDG) of the silver fired layer 27 and the Mises stress (GPa), and FIG. 24 (b) shows the simulation models MD1 to MD5 and the Mises stress. It is a characteristic diagram for explaining the relationship with a ratio.

In FIGS. 24 (a) and 24 (b), the orientation of the coefficient of thermal expansion of the graphite substrate 18GH1 is, for example, X = 25 ppm / K, Y = 0.5 ppm / K, Z = 0.5 ppm / K. As an example of the case, FIG. 24A shows the Mises stress applied to the silver fired layer 27, and FIG. 24B shows the case of the simulation model MD1 as 1.

From FIGS. 24 (a) and 24 (b), assuming that the Mieses stress ratio of the simulation model MD1 is 1, the Mieses stress ratio of the simulation models MD2 and MD4 is 1.05, and the Mieses stress ratio of the simulation model MD3 is 0.83. , The Mieses stress ratio of the simulation model MD5 is 0.84.

That is, a simulation model when the orientation of the coefficient of thermal expansion of the graphite substrate 18GH1 is, for example, X = 25 ppm / K, Y = 0.5 ppm / K, Z = 0.5 ppm / K, and the stress-free state is 200 ° C. The stress (at 25 ° C.) applied to the silver fired layers 27 of MD1 to MD5 can be reduced by reducing the size of the direction (X) having a large coefficient of thermal expansion like the semiconductor devices Qb and Qd of the models MD3 and MD5. Will be.

(Example 2)
Next, the stress applied to the silver fired layer 27 will be described by taking the case where the surface electrode pattern 232 is not present as an example.

The schematic planar pattern configuration of the simulation model MD1 when there is only the surface electrode pattern 231 is shown as shown in FIG. 25 (a), and the schematic cross-sectional structure along the VII-VII line of FIG. 25 (a) is shown. , As shown in FIG. 25 (b).

The orientation of the coefficient of thermal expansion of the graphite substrate 18GH1 is, for example, X = 0.1ppm / K, Y = 25ppm / K, Z = 0.1ppm / K, and the thickness of each part (Q.18GH.21.231.27). (Mm) is optimized to have the lowest thermal resistance, as shown in FIG.

The simulation models MD2 and MD3 are also substantially the same as the MD1 in FIGS. 25 (a) and 25 (b) except that the shapes of the semiconductor devices Qa and Qb are different.

In FIG. 26 (a), simulations were performed using simulation models MD1 to MD3 in the case of applying a graphite substrate having anisotropy in the coefficient of thermal expansion in PM according to the fifteenth to eighteenth embodiments. It is a characteristic diagram for explaining the relationship between the distance from the edge (EDG) of the silver fire layer 27 and the Mises stress, and FIG. 26 (b) shows the relationship between the simulation models MD1 to MD3 and the Mises stress ratio. It is a characteristic diagram for explaining.

In FIGS. 26 (a) and 26 (b), the orientation of the coefficient of thermal expansion of the graphite substrate 18GH1 is, for example, X = 0.5 ppm / K, Y = 25 ppm / K, and Z = 0.5 ppm / K. As an example of the case, FIG. 26A shows the Mises stress applied to the silver fired layer 27, and FIG. 26B shows the case of the simulation model MD1 as 1.

From FIGS. 26 (a) and 26 (b), assuming that the von Mises stress ratio of the simulation model MD1 is 1, the von Mises stress ratio of the simulation model MD2 is 0.96 and the von Mises stress ratio of the simulation model MD3 is 1.02. ..

That is, a simulation model when the orientation of the coefficient of thermal expansion of the graphite substrate 18GH1 is, for example, X = 0.5 ppm / K, Y = 25 ppm / K, Z = 0.5 ppm / K, and the stress-free state is 200 ° C. The stress (at 25 ° C.) applied to the silver fired layers 27 of MD1 to MD3 can be reduced by reducing the size of the direction (Y) having a large coefficient of thermal expansion like the semiconductor device Qa of the model MD2.

In the simulation models MD1 to MD3 having the configurations shown in FIGS. 23 and 25, the orientation of the coefficient of thermal expansion of the graphite substrate 18GH1 is, for example, X = 0.1 ppm / K, Y = 25 ppm / K, Z = 0.1 ppm / K. 92 (a) to 92 (c) show the results (overall warped shape) when a simulation was performed on the stress applied to the silver fired layer 27 in the case of.

The maximum value of the warp of the simulation model MD1 is 22.599 μm and the minimum value is 0.128 μm, and the maximum value of the warp of the simulation model MD2 is 22.313 μm and the minimum value is 0.146 μm. The maximum value of the warp was 22.972 μm and the minimum value was 0.322 μm.

In PM1 according to the fifteenth to eighteenth embodiments, the case where the capacitor is applied to the 1 in 1 module type has been described, but the present invention is not limited to this, and for example, the 2 in 1 (two-in-one) module type. PM, 4 in 1 (four-in-one) module type PM, 6 in 1 (six-in-one) module type PM, and 7 in 1 (seven-in-one) module type PM equipped with a snubber capacitor in the 6 in 1 module. , 8 in 1 (eight-in-one) module type PM, 12 in 1 (twelve-in-one) module type PM, 14 in 1 (fourteen-in-one) module type PM, and the like.

(Specific examples of semiconductor devices)
Schematic circuit representations of the 1 in 1 module type PM50 SiC MOSFETs of the PMs according to the fifteenth to eighteenth embodiments, which are applicable as semiconductor devices, are shown as shown in FIG. 28.

FIG. 28 shows a diode DI connected in antiparallel to the SiC MOSFET Q. When a parasitic diode is used as the diode DI, it can be omitted. The main electrode of the SiC MOSFET Q is represented by a drain terminal DT and a source terminal ST. Further, it is also possible to realize (not shown) the IGBT of the 1 in 1 module 50 which is the PM according to the fifteenth to eighteenth embodiments and can be applied as a semiconductor device.

Further, the detailed circuit representation of the 1 in 1 module type PM50 SiC MOSFET which is the PM according to the fifteenth to eighteenth embodiments and can be applied as a semiconductor device is shown as shown in FIG. 29.

The PM according to the fifteenth to eighteenth embodiments includes, for example, a PM50 in which the semiconductor device is a 1 in 1 module type. That is, one SiC MOSFET Q is built in one module. As an example, 5 chips (MOSFETs × 5) can be mounted, and up to 5 SiC MOSFETs Q can be connected in parallel. It is also possible to mount a part of the five chips for diode DI.

More specifically, as shown in FIG. 29, sense MOSFETs Qs are connected in parallel with the SiC MOSFET Q. The sense MOSFET Qs are formed as fine transistors in the same chip as the SiC MOSFET Q.

In FIG. 29, SS is a source sense terminal, CS is a current sense terminal, and G is a gate terminal. Also in the fifteenth to eighteenth embodiments, the sense MOSFET Qs may be formed as fine transistors in the same chip in the SiC MOSFET Q.

(Circuit configuration)
Next, in the PM according to the fifteenth to eighteenth embodiments, a circuit configuration example of the semiconductor device will be described more specifically.

Here, it is a module applicable as a semiconductor device of PM according to the fifteenth to eighteenth embodiments, and is a PM in which two semiconductor devices are sealed in one mold resin, a so-called 2 in 1 module. The type of PM will be described.

The circuit configuration of the 2 in 1 module type PM (2 in 1 module) 130A to which the SiC MOSFETs Q1 and Q4 are applied as the semiconductor device is shown, for example, as shown in FIG.

That is, as shown in FIG. 30, the 2 in 1 module 130A includes a half-bridge built-in module in which two SiC MOSFETs Q1 and Q4 are built in as one module.

Here, the module can be regarded as one large transistor, but the built-in transistor may be one chip or a plurality of chips. That is, there are 1 in 1, 2 in 1, 4 in 1, 6 in 1 modules, etc. For example, a module containing two transistors (chips) on one module is 2 in 1, A module containing two sets of 2 in 1 is called 4 in 1, and a module containing three sets of 2 in 1 is called 6 in 1.

As shown in FIG. 30, the 2 in 1 module 130A contains two SiC MOSFETs Q1 and Q4 and diodes DI1 and DI4 connected in antiparallel to the SiC MOSFETs Q1 and Q4 as one module.

In FIG. 30, G1 is a lead terminal (so-called gate terminal) for the gate signal of the SiC MOSFET Q1, and S1 is a lead terminal (so-called source sense terminal) for the source signal of the SiC MOSFET Q1. Similarly, G4 is a lead terminal for the gate signal of the SiC MOSFET Q4, and S4 is a lead terminal for the source signal of the SiC MOSFET Q4.

Further, P is a positive power input terminal electrode, N is a negative power input terminal electrode, and O is an output terminal electrode.

Further, it is a module applicable as a semiconductor device of the power module according to the fifteenth to eighteenth embodiments, and realizes a 2 in 1 module (not shown) to which an IGBT is applied as the semiconductor devices Q1 and Q4. You can also do it.

The same applies to the semiconductor devices (Q2 and Q5) and the semiconductor devices (Q3 and Q6) applicable to the PM according to the fifteenth to eighteenth embodiments.

-Power supply-
According to the 2 in 1 module 130A according to the fifteenth to eighteenth embodiments, between the positive power input terminal electrode (first power supply) P and the negative power input terminal electrode (second power supply) N. A power supply device (power supply circuit) can be configured in which a SiC MOSFET (first switching device) Q1 and a SiC MOSFET (second switching device) Q4 are connected in series and the voltage at the connection point is output from the output terminal electrode O. ..

In particular, in the power supply device, the SiC MOSFETs Q1 and Q4 are each composed of a plurality of chips, and the distance between the chips (X2) in the arrangement direction of the plurality of chips is determined from the distance (Y1) from each chip to the end face of the graphite substrate. By shortening the ratio, it is possible to obtain a power supply device having good thermal diffusivity, structurally simple, inexpensive, and capable of lowering thermal resistance.

Although detailed description thereof is omitted here, the PMs according to other embodiments can also be similarly applied to PMs to which the IGBTs Q1 and Q4 are applied as semiconductor devices, for example. Further, a plurality of chips may be arranged side by side so as to be substantially orthogonal to the orientation direction of the graphite substrate.

(Device structure)
An example of the semiconductor devices (Q1 and Q4) applicable to the PM according to the fifteenth to eighteenth embodiments, the schematic cross-sectional structure of the SiC MOSFET 130A including the source pad electrode SP and the gate pad electrode GP is as follows. It is represented as shown in FIG.

As shown in FIG. 31, the SiC MOSFET 130A is formed on the surface of the semiconductor layer 31 composed of the n-high resistance layer, the p-body region 32 formed on the surface side of the semiconductor layer 31, and the p-body region 32. In the source region 33, the gate insulating film 34 arranged on the surface of the semiconductor layer 31 between the p body regions 32, the gate electrode 35 arranged on the gate insulating film 34, and the source region 33 and the p body region 32. It includes a connected source electrode 36, an n + drain region 37 arranged on the back surface opposite to the front surface of the semiconductor layer 31, and a drain electrode 38 connected to the n + drain region 37.

The gate pad electrode GP is connected to the gate electrode 35 arranged on the gate insulating film 34, and the source pad electrode SP is connected to the source electrode 36 connected to the source region 33 and the p body region 32. Further, as shown in FIG. 31, the gate pad electrode GP and the source pad electrode SP are arranged on the passive interlayer insulating film 39 covering the surface of the SiC MOSFET 130A.

Although not shown, a transistor structure having a fine structure may be formed in the semiconductor layer 31 below the gate pad electrode GP and the source pad electrode SP.

Further, as shown in FIG. 31, in the transistor structure in the central portion, the source pad electrode SP may be extended and arranged on the passive interlayer insulating film 39.

In FIG. 31, the SiC MOSFET 130A is composed of a planar gate type n-channel vertical SiC MOSFET, but as shown in FIG. 34 described later, it is configured by a trench gate type n-channel vertical SiC T MOSFET 130C or the like. It may have been done.

Alternatively, as the semiconductor device applicable to the PM according to the fifteenth to eighteenth embodiments, a GaN-based FET or the like can be adopted instead of the SiC MOSFET 130A.

The same applies to the semiconductor devices (Q2 / Q5, Q3 / Q6) applicable to the PM according to the fifteenth to eighteenth embodiments.

Further, the semiconductor devices Q1 to Q6 applicable to the PM according to the fifteenth to eighteenth embodiments include semiconductors having a bandgap energy of, for example, 1.1 eV to 8 eV, which is called a wide bandgap type. Can be used.

Similarly, it is an example of semiconductor devices (Q1 and Q4) applicable to PM according to the fifteenth to eighteenth embodiments, and is a schematic cross-sectional structure of an IGBT 130B including an emitter pad electrode EP and a gate pad electrode GP. Is represented as shown in FIG.

As shown in FIG. 32, the IGBT 130B has a semiconductor layer 31 composed of an n-high resistance layer, a p-body region 32 formed on the surface side of the semiconductor layer 31, and an emitter formed on the surface of the p-body region 32. Connected to the region 33E, the gate insulating film 34 arranged on the surface of the semiconductor layer 31 between the p-body regions 32, the gate electrode 35 arranged on the gate insulating film 34, and the emitter region 33E and the p-body region 32. The emitter electrode 36E is provided, a p + collector region 37P arranged on the back surface opposite to the front surface of the semiconductor layer 31, and a collector electrode 38C connected to the p + collector region 37P.

The gate pad electrode GP is connected to the gate electrode 35 arranged on the gate insulating film 34, and the emitter pad electrode EP is connected to the emitter electrode 36E connected to the emitter region 33E and the p body region 32. Further, as shown in FIG. 32, the gate pad electrode GP and the emitter pad electrode EP are arranged on the passive interlayer insulating film 39 covering the surface of the IGBT 130B.

Although not shown, an IGBT structure having a fine structure may be formed in the semiconductor layer 31 below the gate pad electrode GP and the emitter pad electrode EP.

Further, as shown in FIG. 32, even in the central IGBT structure, the emitter pad electrode EP may be extended and arranged on the passive interlayer insulating film 39.

In FIG. 32, the IGBT 130B is composed of a planar gate type n-channel vertical IGBT, but may be composed of a trench gate type n-channel vertical IGBT or the like.

The same applies to the semiconductor devices (Q2 / Q5, Q3 / Q6) applicable to the PM according to the fifteenth to eighteenth embodiments.

As the semiconductor devices Q1 to Q6, a SiC-based power device such as a SiC DI MOSFET or a SiC T MOSFET, or a GaN-based power device such as a GaN-based HEMT can be applied. In some cases, power devices such as Si-based MOSFETs and IGBTs can also be applied.

―SiC DI MOSFET―
An example of a semiconductor device applicable to PM according to the fifteenth to eighteenth embodiments, the schematic cross-sectional structure of the SiC DI MOSFET 130D is represented as shown in FIG. 33.

The SiC DI MOSFET 130D shown in FIG. 33 has a semiconductor layer 31 composed of an n-high resistance layer, a p-body region 32 formed on the surface side of the semiconductor layer 31, and n + formed on the surface of the p-body region 32. In the source region 33, the gate insulating film 34 arranged on the surface of the semiconductor layer 31 between the p body regions 32, the gate electrode 35 arranged on the gate insulating film 34, and the source region 33 and the p body region 32. It includes a connected source electrode 36, an n + drain region 37 arranged on the back surface opposite to the front surface of the semiconductor layer 31, and a drain electrode 38 connected to the n + drain region 37.

In FIG. 33, in the SiC DI MOSFET 130D, a p-body region 32 and an n + source region 33 formed on the surface of the p-body region 32 are formed by double ion implantation (DII), and the source pad electrode SP is a source. It is connected to the source electrode 36 connected to the region 33 and the p-body region 32.

The gate pad electrode GP (not shown) is connected to the gate electrode 35 arranged on the gate insulating film 34. Further, as shown in FIG. 33, the source pad electrode SP and the gate pad electrode GP are arranged on the passive interlayer insulating film 39 so as to cover the surface of the SiC DI MOSFET 130D.

As shown in FIG. 33, the SiC DI MOSFET 130D is a junction type because a depletion layer as shown by a broken line is formed in a semiconductor layer 31 composed of an n-high resistance layer sandwiched between p body regions 32. A channel resistance R _JFET is formed due to the FET (JFET) effect. Further, as shown in FIG. 33, a body diode BD is formed between the p-body region 32 and the semiconductor layer 31.

―SiC T MOSFET―
An example of a semiconductor device applicable to PM according to the fifteenth to eighteenth embodiments, a schematic cross-sectional structure of a SiC T MOSFET is represented as shown in FIG. 34.

The SiC T MOSFET 130C shown in FIG. 34 has a semiconductor layer 31N composed of n layers, a p-body region 32 formed on the surface side of the semiconductor layer 31N, and an n + source region 33 formed on the surface of the p-body region 32. The trench gate electrode 35TG formed through the p-body region 32 and formed through the gate insulating film 34 and the interlayer insulating films 39U / 39B in the trench formed up to the semiconductor layer 31N, and the source region 33 and the p-body region. It includes a source electrode 36 connected to 32, an n + drain region 37 arranged on the back surface opposite to the front surface of the semiconductor layer 31N, and a drain electrode 38 connected to the n + drain region 37.

In FIG. 34, the SiC T MOSFET 130C penetrates the p-body region 32, and the trench gate electrode 35TG is formed in the trench formed up to the semiconductor layer 31N via the gate insulating film 34 and the interlayer insulating films 39U / 39B. The source pad electrode SP is connected to the source electrode 36 connected to the source region 33 and the p body region 32.

The gate pad electrode GP (not shown) is connected to the trench gate electrode 35TG arranged on the gate insulating film 34. Further, as shown in FIG. 34, the source pad electrode SP and the gate pad electrode GP are arranged on the passive interlayer insulating film 39U so as to cover the surface of the SiC T MOSFET 130C.

In the SiC T MOSFET 130C, the channel resistance R _JFET associated with the junction FET (JFET) effect such as the SiC DI MOSFET 130D is not formed. Further, a body diode BD is formed between the p-body region 32 and the semiconductor layer 31N, as in FIG. 33.

(Application example)
It is a three-phase AC inverter 40A configured by using PM according to the fifteenth to eighteenth embodiments, a SiC MOSFET is applied as a semiconductor device, and a snubber capacitor C is connected between a power supply terminal PL and a ground terminal NL. An example of the circuit configuration is shown in FIG. 35.

Similarly, an IGBT can be applied as a semiconductor device to realize a three-phase AC inverter (not shown) in which a snubber capacitor C is connected between the power supply terminal PL and the ground terminal NL.

When the PM is connected to the power supply E and the switching operation is performed, the switching speed of the SiC MOSFET or the IGBT is high due to the inductance L of the connection line, so that a large surge voltage Ldi / dt is generated. For example, if the current change di = 300A and the time change dt = 100nsec accompanying switching, then di / dt = 3 × 10 ⁹ (A / s).

The value of the surge voltage Ldi / dt changes depending on the value of the inductance L, but the surge voltage Ldi / dt is superimposed on the power supply E. This surge voltage Ldi / dt can be absorbed by the snubber capacitor C connected between the power supply terminal PL and the ground terminal NL.

(Concrete example)
Next, with reference to FIG. 36, a three-phase AC inverter 42A configured by applying a SiC MOSFET as a semiconductor device and using PM according to the fifteenth to eighteenth embodiments will be described.

As shown in FIG. 36, the three-phase AC inverter 42A includes a power module unit 130 connected to the gate driver (GD) 180, a three-phase AC motor unit 51, a power supply or storage battery (E) 53, and a converter 55. To prepare for. The power module unit 130 is connected to the U-phase, V-phase, and W-phase inverters corresponding to the U-phase, V-phase, and W-phase of the three-phase AC motor unit 51.

Here, the GD180 is connected to the SiC MOSFETs Q1 and Q4, the SiC MOSFETs Q2 and Q5, and the SiC MOSFETs Q3 and Q6.

The power module unit 130 is connected between the positive terminal (+) P and the negative terminal (-) N of the converter 55 to which the power supply or the storage battery (E) 53 is connected, and is connected to the SiC MOSFETs Q1, Q4, and Q2 having an inverter configuration. -Provides Q5 and Q3 / Q6. Further, freewheel diodes DI1 to DI6 are connected in antiparallel between the source and drain of the SiC MOSFETs Q1 to Q6, respectively.

Further, although not shown, it is also possible to apply an IGBT as a semiconductor device and realize a three-phase AC inverter configured by using the power module according to the fifteenth to eighteenth embodiments.

As described above, according to the fifteenth to eighteenth embodiments, it is possible to realize a PM and a power supply device having good thermal diffusivity and capable of lower thermal resistance.

The semiconductor device applicable to the PM according to the fifteenth to eighteenth embodiments is not limited to the SiC-based power device, but is a power called a wide bandgap type such as a GaN-based power device or a Si-based power device. Devices can also be adopted.

Further, it can be applied not only to a resin-molded mold-type power module but also to a power module packaged by a case-type package.

[Other embodiments]
As mentioned above, some embodiments have been described, but the statements and drawings that form part of the disclosure are exemplary and should not be understood as limiting. This disclosure will reveal to those skilled in the art various alternative embodiments, examples and operational techniques.

As described above, the present embodiment includes various embodiments not described here.

The power module of this embodiment can be used for various semiconductor module manufacturing techniques such as an IGBT module, a diode module, and a MOS module (Si, SiC, GaN) using a Si substrate, a SiC substrate, or a GaN substrate. It can be applied to a wide range of application fields including power supply devices such as inverters for HEVs (Hybrid Electric Vehicles) / EVs (Electric Vehicles), industrial equipment such as robots, and inverters and converters for industrial or home appliances.

1, 1 1 ₁ , 1 ₂ 1, 1 ₃ , 2 ... PM (power module)
1A ... Electrode pattern (lower electrode)
1E ... Power device (semiconductor device)
3A, 3B, 3C, 3D, 3E, 3F ... Bonding material 5,5A, 5B1, 5C1,5B2, 5C2 ... Cu layer 6 ... Mold resin 10, 10a, 10b, 10c, 10d ... Semiconductor devices 16, 16D, 16D1, 16U ... Cu wiring pattern 18GP, 18GP (XZ), 18GH (XZ), 18GH (YZ) ... Graphite plate 18GP (XY) ... First graphite plate 18GP (XZ) 1,18GP (XZ) 2,18GP (XZ) 3,18GP (XZ) 4 ... Second graphite plate 18GH, 18GH1 / 18GH2 ... Graphite substrate 20, 20A ... Insulated substrate (graphite insulating substrate)
21, 21, 21A, 21N ... Ceramic substrate (insulating layer)
21S ... Resin sheet (insulating layer)
22 ... Backside electrode pattern (backside electrode layer of ceramic substrate (insulation layer))
22U, 22D ... Thick copper layer 22C ... Copper foil layer 22U1, 23U1 ... Drain electrode pattern 22U2, 23U2 ... Source electrode pattern 23, 231, 232, 23D, 23D1, 23D4, 23DN, 23R ... Backside electrode pattern 24 ... Graphite substrate Backside electrode layers 25, 25T ... Heat conductive layer (heat conductive sheet layer, solder layer, silver fired layer)
25D (25D1 to 25D6) ... Drain electrode pattern 25S (25S1 to 25S6) ... Source electrode pattern 26 ... Joining member 27 ... Silver fired portion (silver fired layer, joining member)
27S ... Solder layer 28 ... Coolers 29, 29A ... Block electrodes 30, 30A, 30B ... Upper wiring 30SM ... Wiring lead portion 36 ... Surface electrode layer 38 of ceramic substrate ... Drain electrodes 40A, 40B, 42A, 42B ... Three-phase AC Inverter 41 ... Radiator 45 ... Thick copper substrate 61 ... Al electrode part 63 ... Ni plating layer 130A ... Planar gate type n-channel vertical SiC MOSFET
130B ... Planagate type n-channel vertical IGBT
130C ... Trench gate type n-channel vertical SiC T MOSFET
130D ... SiC DI MOSFET
CS ... Current sense terminal CS1 ... Current sense pad electrode D, D1, D4, DT ... Drain, Drain terminal DC ... Device side junction F ... Radiator G, G1, G4, GT, GT1, GT4 ... Gate, Gate terminal GL (GL1 to GL6) ... Gate signal electrode pattern GP (GP1 to GP6) ... Gate pad electrode GS (GS1, GS2, GS3 ..., GSn) ... Graphite sheet GW (GW1 to GW6) ... Bonding wire MD, MD1 for gate signal , MD2, MD3, MD4, MD5 ... Simulation model Q, Q1 to Q6, QA, QB, Qa, Qb, Qc, Qd, Q11 to Q13 ... Transistor O ... Output terminal (output terminal electrode)
N ... Power terminal (negative power input terminal electrode (negative power terminal))
P ... Power terminal (positive power input terminal electrode (positive power terminal))
QA1 ... IGBT
QA2 ... FRD
RT ... Signal unit terminal SB ... Second land side joint SC ... Land side joint SM (SM1 to SM6) ... Lead frame SML, SML1 ... Extended lead frame S, S1 to S6, ST ... Source, source terminal SL ( SL1 to SL6) ... Source signal electrode pattern SP (SP1 to SP6) ... Source pad electrode SS, SST, SST1 to SST6 ... Source sense terminal SSP, SSP1, SSP4 ... Source sense pad electrode SSW, SSW1 to SSW4 ... Bonding for source sense Wire SPM1 ... SiC power module TD ... (relatively high thermal conductivity) Orientation direction PD ... (relatively low thermal conductivity) orientation direction PD1, PDA, PDB, PDC, PDD ... Direction of arrangement WR ... Cooling liquid

Claims (23)

Insulated board and
A power device arranged on the insulating substrate and having electrodes on the front surface side and the back surface side thereof.
Graphite having an anisotropic thermal conductivity, one end connected to the surface side of the power device and the other end connected to the insulating substrate, and a second orientation having a higher thermal conductivity in the thickness direction than in the plane direction. Equipped with wiring,
A power module characterized in that heat on the surface side of the power device is transferred to the insulating substrate via the graphite wiring. The insulating substrate includes an insulating substrate and a first electrode pattern and a second electrode pattern arranged on the first surface of the substrate.
The power device is arranged on the first electrode pattern and
The power module according to claim 1 , wherein the non-connecting portion of the graphite wiring at a position separated from the connecting portion of the power device in the same plane is connected to the second electrode pattern . The power module according to claim 1 , wherein the graphite wiring includes a plate structure in which a plurality of graphite sheets having the second orientation are laminated. The power module according to claim 1 , wherein the graphite wiring includes a first wiring pattern on a first main surface . An insulating substrate including an insulating substrate, a first electrode pattern and a second electrode pattern arranged on a first surface of the substrate, and a third electrode pattern arranged on a second surface facing the first surface. When,
A power device arranged on the first electrode pattern and having electrodes on the front surface side and the back surface side thereof,
A radiator arranged on the third electrode pattern and
The block electrode arranged on the second electrode pattern and
A graphite wiring having an anisotropic thermal conductivity, a first wiring pattern arranged on the first main surface of the graphite wiring, and a second wiring pattern arranged on the second main surface facing the first main surface. One end side is connected to the front surface side of the power device, and the other end side at a position separated from the one end side in the same plane is connected to the second electrode pattern via the block electrode. With a part,
The graphite wiring has a second orientation in which the thermal conductivity is higher in the thickness direction than in the plane direction, and has a plate structure in which a plurality of graphite sheets having the second orientation are laminated.
A power module characterized in that heat on the surface side of the power device is transferred to the insulating substrate via the graphite wiring. An insulating substrate including an insulating substrate, a first electrode pattern and a second electrode pattern arranged on a first surface of the substrate, and a third electrode pattern arranged on a second surface facing the first surface. When,
A power device arranged on the first electrode pattern and having electrodes on the front surface side and the back surface side thereof,
A radiator arranged on the third electrode pattern and
A graphite wiring having an anisotropic thermal conductivity, and a position arranged on the first main surface of the graphite wiring, one end side of which is connected to the front surface side of the power device, and a position separated from the one end side in the same plane. A wiring lead portion having a first wiring pattern having an L-shaped cross section in which the thickness of the wiring pattern is partially different so that the other end side of the wiring pattern is connected to the second electrode pattern is provided.
The graphite wiring has a second orientation in which the thermal conductivity is higher in the thickness direction than in the plane direction, and has a plate structure in which a plurality of graphite sheets having the second orientation are laminated.
A power module characterized in that heat on the surface side of the power device is transferred to the insulating substrate via the graphite wiring. Insulating board and
A graphite substrate arranged on the substrate having anisotropy in the coefficient of thermal expansion,
A power device arranged on the graphite substrate and having electrodes on the front surface side and the back surface side thereof.
Equipped with graphite wiring with anisotropic thermal conductivity connected to the surface side of the power device.
A power module characterized in that heat on the surface side of the power device is transferred to the substrate via the graphite wiring. A graphite insulating substrate comprising an insulating substrate and a graphite substrate arranged on the substrate having anisotropy in the coefficient of thermal expansion.
A power device arranged on the graphite insulating substrate and having electrodes on the front surface side and the back surface side thereof.
Equipped with graphite wiring with anisotropic thermal conductivity connected to the surface side of the power device.
A power module characterized in that heat on the surface side of the power device is transferred to the substrate via the graphite wiring. A power device arranged in series between a first power supply terminal and a second power supply terminal and arranged on the first surface of a substrate having a first surface and a second surface facing the first surface. A power module having a cooler arranged on the second surface side of the substrate and configured to connect a connection point of the power device to an output terminal.
The power device has a first surface and a second surface facing the first surface.
A graphite plate for thermally connecting the second surface side of the substrate of the cooler and the second surface side of the power device is provided.
The graphite plate has a structure in which two types of graphite plates having different thermal conductivity orientations are bonded together in a direction having high thermal conductivity.
A power module that features that. The graphite plate included in the power module according to claim 9. A substrate having a first main electrode pattern and a signal wiring pattern,
A semiconductor device having a main pad electrode on the surface and arranged on the substrate,
A lead frame connected between the main pad electrode and the first main electrode pattern,
Separated from the first joint portion between the lead frame and the main pad electrode, and the second joint portion between the lead frame and the first main electrode pattern,
A first bonding wire connected between the second junction and the signal wiring pattern, one end of which is connected to the signal wiring pattern and the other end of which is connected to the lead frame of the second junction. With the first bonding wire
Equipped with
The second junction is a power module characterized in that the temperature during operation of the semiconductor device is relatively lower than that of the first junction. 11. The power module according to claim 11, wherein the lead frame includes any of Cu, Al, a clad material, or CuMo, and is connected to a flat plate shape. The power module according to claim 11, wherein the semiconductor device is formed by connecting a plurality of devices in parallel, and the first bonding wire is commonly connected to the plurality of devices. The power module according to any one of claims 11 to 13, wherein the first bonding wire includes Al, Cu, a clad material, or an alloy having one or more of them. An insulating substrate including an insulating substrate, a first main electrode pattern, a second main electrode pattern, a signal wiring pattern, and a control signal wiring pattern arranged on the substrate.
A semiconductor device having a main pad electrode and a control pad electrode on the front surface side and a main electrode on the back surface side and arranged face-up on the second main electrode pattern.
A lead frame connected between the main pad electrode and the first main electrode pattern,
A first of the lead frame and the first main electrode pattern, which is separated from the first joint portion between the lead frame and the main pad electrode and whose temperature during operation of the semiconductor device is relatively lower than that of the first joint portion. The first bonding wire connected between the two junctions and the signal wiring pattern,
A second bonding wire connected between the control pad electrode and the control signal wiring pattern
Equipped with
The first bonding wire is a power module having one end connected to the signal wiring pattern and the other end connected to the first main electrode pattern of the second bonding portion. An insulating substrate including an insulating substrate, a first main electrode pattern, a second main electrode pattern, a signal wiring pattern, a control signal wiring pattern, and a wiring electrode pattern arranged on the substrate.
A semiconductor device having a main pad electrode and a control pad electrode on the front surface and a main electrode on the back surface and arranged face-up on the second main electrode pattern.
A lead frame connected between the main pad electrode and the first main electrode pattern, and the connection end side with the main pad electrode is extended to be connected to the wiring electrode pattern.
The lead frame and the first joint portion, which are separated from the first joint portion between the lead frame and the main pad electrode and the first joint portion, and whose temperature during operation of the semiconductor device is relatively lower than that of the first joint portion. A second junction with the main electrode pattern, and a third junction between the lead frame and the wiring electrode pattern whose temperature during operation of the semiconductor device is relatively lower than that of the first junction.
A first bonding wire having one end connected to the signal wiring pattern and the other end connected to the third bonding portion.
A second bonding wire connected between the control pad electrode and the control signal wiring pattern
Equipped with
A power module characterized in that the other end of the first bonding wire is connected to the lead frame or the wiring electrode pattern of the third bonding portion. With a conductive substrate
A main electrode pattern, a signal wiring pattern, and a control signal wiring pattern arranged on the substrate via an insulating layer,
A semiconductor device having a main pad electrode on the surface and arranged on the substrate,
A lead frame connected between the main pad electrode and the main electrode pattern,
The second junction between the lead frame and the main electrode pattern, which is separated from the first junction between the lead frame and the main pad electrode and whose temperature during operation of the semiconductor device is relatively lower than that of the first junction. With the first bonding wire connected between the unit and the signal wiring pattern
A power module characterized by being equipped with. With the board
A graphite substrate having an anisotropic thermal conductivity arranged on the first surface of the substrate and
A first electrode pattern arranged on a second surface facing the first surface of the substrate, and a first electrode pattern.
The second electrode pattern arranged on the graphite substrate and
With a plurality of semiconductor devices arranged side by side on the graphite substrate via the second electrode pattern and generating heat during operation.
Equipped with
The graphite substrate has an orientation in which the thermal conductivity is relatively high in the thickness direction rather than the plane direction.
The feature is that the alignment direction of the plurality of semiconductor devices on the substrate surface of the graphite substrate is −45 degrees or more and +45 degrees or less with respect to the orientation direction in which the thermal conductivity of the graphite substrate is relatively low. Power module to do. The power module according to claim 18, wherein the arrangement direction of the plurality of semiconductor devices is substantially orthogonal to the orientation direction in which the thermal conductivity of the graphite substrate is relatively high. Insulation layer and
A graphite substrate arranged on the insulating layer and having an anisotropic thermal conductivity,
With a semiconductor device that is placed on the graphite substrate and generates heat during operation
Equipped with
The graphite substrate is a power module characterized by having a surface electrode layer of the graphite substrate on its surface. The power module according to claim 20, wherein the graphite substrate includes a back surface electrode layer of the graphite substrate on the back surface. A power supply device in which a first switching device and a second switching device are connected in series between a first power supply and a second power supply, and the voltage at the connection point is output.
Each of the switching devices consists of a plurality of chips and is arranged side by side on a graphite substrate.
A power supply device characterized in that the spacing distance between the chips in the arrangement direction of the plurality of chips is shorter than the respective distance from each of the chips to both end faces in the longitudinal direction of the graphite substrate. A surface of an insulating substrate having an insulating substrate and an insulating substrate having a first main electrode pattern, a second main electrode pattern, a signal wiring pattern, and a control signal wiring pattern arranged on the substrate on the second main electrode pattern. A process of arranging a semiconductor device having a main pad electrode and a control pad electrode on the side and having a main electrode on the back side face-up,
A step of connecting a lead frame between the main pad electrode and the first main electrode pattern, and
A first of the lead frame and the first main electrode pattern, which is separated from the first bonding portion between the lead frame and the main pad electrode and whose temperature during operation of the semiconductor device is relatively lower than that of the first bonding portion. In the step of connecting the first bonding wire between the two bonding portions and the signal wiring pattern, one end of the first bonding wire is connected to the signal wiring pattern and the other end of the first bonding wire. In the step of connecting the wire to the lead frame of the second joint, and
A step of connecting a second bonding wire between the control pad electrode and the control signal wiring pattern.
A method for manufacturing a power module, which comprises.

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