JP2013065758A - Semiconductor device and manufacturing method of the same - Google Patents

Semiconductor device and manufacturing method of the same Download PDF

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JP2013065758A
JP2013065758A JP2011204365A JP2011204365A JP2013065758A JP 2013065758 A JP2013065758 A JP 2013065758A JP 2011204365 A JP2011204365 A JP 2011204365A JP 2011204365 A JP2011204365 A JP 2011204365A JP 2013065758 A JP2013065758 A JP 2013065758A
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electrode plate
semiconductor chip
semiconductor device
bumps
semiconductor
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Jia Yunn Ting
ジャー ユン ティン
Satoshi Hattori
聡 服部
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Toshiba Corp
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    • H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L24/39—Structure, shape, material or disposition of the strap connectors after the connecting process
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    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48471—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area being a ball bond, i.e. wedge-to-ball, reverse stitch
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    • H01L2224/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
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  • Engineering & Computer Science (AREA)
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  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
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Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which suppresses the inclination of a semiconductor chip when a solder paste is melted and improves the reliability of joining between a semiconductor chip and an electrode plate, and to provide a manufacturing method of the semiconductor device.SOLUTION: A semiconductor device according to one embodiment includes: a rear surface electrode plate having an electrode; a semiconductor chip joined to the rear surface electrode plate by solder; and a sealing material which seals the semiconductor chip with the electrode exposed. One or more first bumps are formed on a joining surface of the rear surface electrode plate and the semiconductor chip.

Description

本発明の実施形態は、表面実装型の半導体装置（ＳＭＤ：Surface Mount Device）及び該半導体装置の製造方法に関する。   Embodiments described herein relate generally to a surface-mount type semiconductor device (SMD: Surface Mount Device) and a method for manufacturing the semiconductor device.

半導体装置は、半導体チップを複数の電極を有する電極板（裏面電極板）上に接合した後、封止材により封止して製造される。この半導体チップと裏面電極板との接合には、通常、半田が使用される。半導体チップ裏面と裏面電極板との間に加熱（リフロー）・冷却により半田となる半田ペーストを塗布し、この半田ペーストを加熱後、冷却することにより、半導体チップ裏面と裏面電極板とが半田により電気的に接合される。また、近年では、半導体チップの放熱性を高めるため、半導体チップ表面と接合する電極板（表面電極板）をさらに備え、この表面電極板の半導体チップとの接合面に対向する面（表面）を露出させた状態で、封止材により封止したものがある（例えば、特許文献１参照）。   A semiconductor device is manufactured by bonding a semiconductor chip onto an electrode plate (back electrode plate) having a plurality of electrodes and then sealing with a sealing material. For joining the semiconductor chip and the back electrode plate, solder is usually used. By applying a solder paste that becomes solder by heating (reflow) / cooling between the back surface of the semiconductor chip and the back surface electrode plate, and heating and cooling this solder paste, the back surface of the semiconductor chip and the back surface electrode plate are soldered. Electrically joined. In recent years, in order to improve the heat dissipation of the semiconductor chip, an electrode plate (surface electrode plate) that is bonded to the surface of the semiconductor chip is further provided, and the surface (surface) that faces the bonding surface of the surface electrode plate to the semiconductor chip is provided. Some are sealed with a sealing material in an exposed state (see, for example, Patent Document 1).

特開２００５−５０９６１号公報JP 2005-50961 A

半田ペーストを加熱すると、半田ペーストは加熱により一旦溶融するが、この際、半導体チップが重みで傾いてしまう虞がある。半導体チップが傾いた状態で半田ペーストが冷却されると、半導体チップが傾いた状態で裏面電極板に接合されてしまう。このため、半導体チップ裏面の半田の厚みが均一とならない。さらに、半導体チップが傾いた状態で、昇温及び降温を繰り返す信頼性テスト実施した場合、半田厚みの薄い箇所から半田の脆化が進むため半導体チップと裏面電極板との接合信頼性が低下する。また、表面電極板を備える半導体装置では、表面電極板が傾くことにより、表面電極板表面が封止材から露出しない状態となる。このため、半導体チップの放熱性が低下してしまう。
本発明の実施形態は、半田ペースト溶融時の半導体チップの傾きを抑制し、半導体チップと電極板との接合の信頼性を向上できる半導体装置及び半導体装置の製造方法を提供することを目的とする。 When the solder paste is heated, the solder paste is once melted by heating. At this time, the semiconductor chip may be inclined due to the weight. When the solder paste is cooled while the semiconductor chip is inclined, the semiconductor chip is bonded to the back electrode plate while being inclined. For this reason, the thickness of the solder on the back surface of the semiconductor chip is not uniform. Furthermore, when a reliability test is repeated in which the temperature rises and falls in a state where the semiconductor chip is tilted, the solder becomes more brittle from the portion where the solder thickness is thin, so that the bonding reliability between the semiconductor chip and the back electrode plate is lowered. . Moreover, in a semiconductor device provided with a surface electrode plate, the surface electrode plate surface is not exposed from the sealing material when the surface electrode plate is inclined. For this reason, the heat dissipation of a semiconductor chip will fall.
Embodiments of the present invention have an object to provide a semiconductor device and a method for manufacturing the semiconductor device that can suppress the inclination of the semiconductor chip when the solder paste is melted and can improve the reliability of bonding between the semiconductor chip and the electrode plate. .

実施形態に係る半導体装置は、電極を有する裏面電極板と、裏面電極板に半田により接合された半導体チップと、電極が露出した状態で、半導体チップを封止する封止材と、を備え、裏面電極板と半導体チップとの接合面に、１以上の第１のバンプが形成されていることを特徴とする。   A semiconductor device according to an embodiment includes a back electrode plate having electrodes, a semiconductor chip joined to the back electrode plate by solder, and a sealing material that seals the semiconductor chip with the electrodes exposed, One or more first bumps are formed on the bonding surface between the back electrode plate and the semiconductor chip.

第１の実施形態に係る半導体装置の構成図。1 is a configuration diagram of a semiconductor device according to a first embodiment. FIG. 第１の実施形態に係る半導体装置の製造工程図。FIG. 6 is a manufacturing process diagram of the semiconductor device according to the first embodiment. 第１の実施形態に係る半導体装置の製造工程図。FIG. 6 is a manufacturing process diagram of the semiconductor device according to the first embodiment. 比較例に係る半導体装置の構成断面図。FIG. 6 is a cross-sectional view of a semiconductor device according to a comparative example. 第２の実施形態に係る半導体装置の構成断面図。FIG. 6 is a cross-sectional view of a configuration of a semiconductor device according to a second embodiment. 第３の実施形態に係る半導体装置の構成断面図。FIG. 6 is a cross-sectional view of a configuration of a semiconductor device according to a third embodiment. 第４の実施形態に係る半導体装置の構成断面図。FIG. 10 is a cross-sectional configuration diagram of a semiconductor device according to a fourth embodiment. 第５の実施形態に係る半導体装置の構成断面図。FIG. 9 is a configuration cross-sectional view of a semiconductor device according to a fifth embodiment. 第６の実施形態に係る半導体装置の構成断面図。FIG. 9 is a cross-sectional view of a configuration of a semiconductor device according to a sixth embodiment. その他の実施形態に係る半導体装置の上面図。The top view of the semiconductor device concerning other embodiments.

以下、図面を参照して、実施形態について詳細に説明する。   Hereinafter, embodiments will be described in detail with reference to the drawings.

（第１の実施形態）
図１は、第１の実施形態に係る半導体装置１の構成図である。図１（ａ）は、半導体装置１の上面図である。図１（ｂ）は、図１（ａ）の半直線Ｘ−Ｙにおける半導体装置１の断面図である。なお、図１（ａ）では、封止材１０４を透視した状態で半導体装置１を図示している。以下、図１（ａ）及び図１（ｂ）を参照して、第１の実施形態に係る半導体装置１について説明する。 (First embodiment)
FIG. 1 is a configuration diagram of a semiconductor device 1 according to the first embodiment. FIG. 1A is a top view of the semiconductor device 1. FIG. 1B is a cross-sectional view of the semiconductor device 1 taken along the half line XY in FIG. In FIG. 1A, the semiconductor device 1 is illustrated with the sealing material 104 seen through. The semiconductor device 1 according to the first embodiment will be described below with reference to FIGS. 1 (a) and 1 (b).

（半導体装置１の構成）
半導体装置１は、半導体チップ１０１と、半導体チップ１０１裏面に半田Ｐ１により接合された裏面電極板１０２と、半導体チップ１０１表面に半田Ｐ１により接合された表面電極板１０３と、半導体チップ１０１、裏面電極板１０２及び表面電極板１０３を封止する封止材１０４とを備えている。 (Configuration of Semiconductor Device 1)
The semiconductor device 1 includes a semiconductor chip 101, a back electrode plate 102 bonded to the back surface of the semiconductor chip 101 with solder P1, a front electrode plate 103 bonded to the surface of the semiconductor chip 101 with solder P1, a semiconductor chip 101, and a back electrode. And a sealing material 104 that seals the plate 102 and the surface electrode plate 103.

裏面電極板１０２は、半導体チップ１０１裏面に接合された第１電極板１０２ａと、第１電極板１０２ａから離間して配置された第２電極板１０２ｂ（ポスト部）とから構成される。第１電極板１０２ａ表面、すなわち半導体チップ１０１裏面との接合面には、略同一高さの複数のバンプＢ１が形成されている。また、第２電極板１０２ｂ表面、すなわち表面電極板１０３との接合面には、略同一高さの複数のバンプＢ３が形成されている。さらに、第１電極板１０２ａ及び第２電極板１０２ｂは、夫々複数の電極１０２ｃを有しており、この複数の電極１０２ｃが露出した状態で、封止材１０４により封止されている。   The back electrode plate 102 includes a first electrode plate 102a bonded to the back surface of the semiconductor chip 101, and a second electrode plate 102b (post portion) disposed away from the first electrode plate 102a. A plurality of bumps B1 having substantially the same height are formed on the surface of the first electrode plate 102a, that is, the joint surface with the back surface of the semiconductor chip 101. A plurality of bumps B3 having substantially the same height are formed on the surface of the second electrode plate 102b, that is, on the joint surface with the surface electrode plate 103. Furthermore, each of the first electrode plate 102a and the second electrode plate 102b has a plurality of electrodes 102c, and is sealed with a sealing material 104 with the plurality of electrodes 102c exposed.

半導体チップ１０１は、裏面電極板１０２の第１電極板１０２ａ上に半田Ｐ１により接合されている。半導体チップ１０１表面、すなわち表面電極板１０３との接合面には、略同一高さの複数のバンプＢ２が形成されている。   The semiconductor chip 101 is joined to the first electrode plate 102a of the back electrode plate 102 by solder P1. A plurality of bumps B <b> 2 having substantially the same height are formed on the surface of the semiconductor chip 101, that is, on the bonding surface with the surface electrode plate 103.

表面電極板１０３は、半導体チップ１０１表面及び裏面電極板１０２の第２電極板１０２ｂに跨った状態で、一端側が半導体チップ１０１表面に半田Ｐ１により接合され、他端側が第２電極板１０２ｂ表面に半田Ｐ１により接合されている。表面電極板１０３裏面、すなわち第２電極板１０２ｂとの接合面には、略同一高さの複数のバンプＢ３が形成されている。また、表面電極板１０３表面、すなわち、表面電極板１０３の半導体チップ１０１との接合面と対向する面は、露出した状態で封止材１０４により封止されている。   In the state where the front surface electrode plate 103 straddles the surface of the semiconductor chip 101 and the second electrode plate 102b of the back surface electrode plate 102, one end side is bonded to the surface of the semiconductor chip 101 by the solder P1, and the other end side is connected to the second electrode plate 102b surface. Joined by solder P1. A plurality of bumps B3 having substantially the same height are formed on the back surface of the front electrode plate 103, that is, on the joint surface with the second electrode plate 102b. Further, the surface electrode plate 103 surface, that is, the surface facing the bonding surface of the surface electrode plate 103 with the semiconductor chip 101 is sealed with the sealing material 104 in an exposed state.

なお、バンプＢ１〜Ｂ３は、Ａｕ（金）バンプ又はＣｕ（銅）バンプである。Ａｕ及びＣｕの融点は、それぞれ約１０６４℃及び約１０８４℃である。一方、加熱・冷却により半田Ｐ１となる半田ペーストのリフロー温度は、半田ペーストの材料にもよるが、一般的には、２２０〜２６０℃程度であり、Ａｕ及びＣｕの融点よりも十分に低いものとなっている。このため、バンプＢ１〜Ｂ３が、半田ペーストのリフロー時に溶融することはない。   The bumps B1 to B3 are Au (gold) bumps or Cu (copper) bumps. The melting points of Au and Cu are about 1064 ° C. and about 1084 ° C., respectively. On the other hand, the reflow temperature of the solder paste that becomes the solder P1 by heating / cooling is generally about 220 to 260 ° C., which is sufficiently lower than the melting points of Au and Cu, although it depends on the material of the solder paste. It has become. For this reason, the bumps B1 to B3 are not melted when the solder paste is reflowed.

（半導体装置１の製造方法）
図２、図３は、第１の実施形態に係る半導体装置１の組み立て工程を示した図である。次に、図１〜図３を参照して、第１の実施形態に係る半導体装置１の製造方法について説明する。 (Manufacturing method of the semiconductor device 1)
2 and 3 are views showing an assembly process of the semiconductor device 1 according to the first embodiment. Next, a method for manufacturing the semiconductor device 1 according to the first embodiment will be described with reference to FIGS.

（工程１：図２（ａ）参照）
第１電極板１０２ａ表面、すなわち半導体チップ１０１裏面との接合面に、略同一高さの複数のバンプＢ１を形成する。 (Step 1: see FIG. 2 (a))
A plurality of bumps B1 having substantially the same height are formed on the surface of the first electrode plate 102a, that is, the joint surface with the back surface of the semiconductor chip 101.

（工程２：図２（ｂ）参照）
第１電極板１０２ａ表面上に形成した複数のバンプＢ１上に所定量の半田ペーストＰ２を塗布する。 (Step 2: see FIG. 2 (b))
A predetermined amount of solder paste P2 is applied on the plurality of bumps B1 formed on the surface of the first electrode plate 102a.

（工程３：図２（ｃ）参照）
第１電極板１０２ａ表面に形成した複数のバンプＢ１上に半導体チップ１０１をマウントする。 (Step 3: see FIG. 2 (c))
The semiconductor chip 101 is mounted on the plurality of bumps B1 formed on the surface of the first electrode plate 102a.

（工程４：図２（ｄ）参照）
半導体チップ１０１表面、すなわち表面電極板１０３との接合面に、略同一高さの複数のバンプＢ２を形成する。また、第２電極板１０２ｂ表面、すなわち表面電極板１０３との接合面に、略同一高さの複数のバンプＢ３を形成する。 (Step 4: see FIG. 2 (d))
A plurality of bumps B <b> 2 having substantially the same height are formed on the surface of the semiconductor chip 101, that is, on the joint surface with the surface electrode plate 103. Also, a plurality of bumps B3 having substantially the same height are formed on the surface of the second electrode plate 102b, that is, the joint surface with the surface electrode plate 103.

（工程５：図３（ｅ）参照）
半導体チップ１０１表面に形成した複数のバンプＢ２及び第２電極板１０２ｂ表面に形成した複数のバンプＢ３上に所定量の半田ペーストＰ２を夫々塗布する。 (Step 5: see FIG. 3 (e))
A predetermined amount of solder paste P2 is applied onto the plurality of bumps B2 formed on the surface of the semiconductor chip 101 and the plurality of bumps B3 formed on the surface of the second electrode plate 102b.

（工程６：図３（ｆ）参照）
一端側が半導体チップ１０１表面に、他端側が第２電極板１０２ｂ表面に跨った状態となるように表面電極板１０３を所定位置にマウンドする。その後、半田ペーストＰ２の加熱（リフロー）及び冷却を行う。半田ペーストＰ２の加熱（リフロー）及び冷却を行うことで、裏面電極板１０２の第１電極板１０２ａ表面と半導体チップ１０１裏面、半導体チップ１０１表面と表面電極板１０３裏面、及び裏面電極板１０２の第２電極板１０２ｂ表面と表面電極板１０３裏面が半田Ｐ１により電気的に接合される。 (Step 6: see FIG. 3 (f))
The surface electrode plate 103 is mounted at a predetermined position so that one end side is over the surface of the semiconductor chip 101 and the other end side is over the surface of the second electrode plate 102b. Thereafter, the solder paste P2 is heated (reflowed) and cooled. By performing heating (reflow) and cooling of the solder paste P2, the surface of the first electrode plate 102a of the back electrode plate 102 and the back surface of the semiconductor chip 101, the surface of the semiconductor chip 101 and the back surface of the surface electrode plate 103, and the back surface of the back electrode plate 102 The front surface of the two-electrode plate 102b and the back surface of the front-surface electrode plate 103 are electrically joined by solder P1.

（工程７：図３（ｇ）参照）
裏面電極板１０２が有する複数の電極１０２ｃ及び表面電極板１０３表面が露出するように封止材１０４で半導体チップ１０１を封止する。 (Step 7: see FIG. 3 (g))
The semiconductor chip 101 is sealed with a sealing material 104 so that the surfaces of the plurality of electrodes 102c and the front electrode plate 103 included in the back electrode plate 102 are exposed.

（比較例）
図４は、比較例に係る半導体装置１Ａの構成断面図である。以下、図４を参照して比較例に係る半導体装置１Ａの構成について説明するが、比較例に係る半導体装置１Ａは、バンプＢ１〜Ｂ３が形成されていない点が、図１を参照して説明した半導体装置１と異なる。その他の構成は、図１を参照して説明した構成と同じ構成であるため、同一の構成には同一の符号を付して重複した説明を省略する。 (Comparative example)
FIG. 4 is a configuration cross-sectional view of a semiconductor device 1A according to a comparative example. Hereinafter, the configuration of the semiconductor device 1A according to the comparative example will be described with reference to FIG. 4, but the semiconductor device 1A according to the comparative example will be described with reference to FIG. 1 in which bumps B1 to B3 are not formed. Different from the semiconductor device 1 described above. Other configurations are the same as the configurations described with reference to FIG. 1, and thus the same configurations are denoted by the same reference numerals, and redundant description is omitted.

図４に示すように、比較例に係る半導体装置１Ａには、裏面電極板１０２の第１電極板１０２ａ表面と半導体チップ１０１裏面との間、半導体チップ１０１表面と表面電極板１０３裏面との間、及び裏面電極板１０２の第２電極板１０２ｂ表面と表面電極板１０３裏面との間に夫々バンプＢ１〜Ｂ３が形成されていない。   As shown in FIG. 4, the semiconductor device 1 </ b> A according to the comparative example includes a surface between the first electrode plate 102 a surface of the back electrode plate 102 and the back surface of the semiconductor chip 101, and between the surface of the semiconductor chip 101 and the back surface of the surface electrode plate 103. Bumps B1 to B3 are not formed between the surface of the second electrode plate 102b of the back electrode plate 102 and the back surface of the front electrode plate 103, respectively.

このため、加熱・冷却により半田Ｐ１となる半田ペーストをリフローする際に、半導体チップ１０１が自重により傾く虞がある。また、半導体チップ１０１が傾いた状態で裏面電極板１０２表面に接合された場合、半導体チップ１０１裏面の半田Ｐ１の厚みが均一とならないため、半田Ｐ１の厚みの薄い箇所から半田の脆化が進み、半導体チップ１０１と裏面電極板１０２との接合信頼性が低下してしまう。   For this reason, when reflowing the solder paste that becomes the solder P1 by heating and cooling, the semiconductor chip 101 may be inclined due to its own weight. Further, when the semiconductor chip 101 is joined to the surface of the back electrode plate 102 in an inclined state, the thickness of the solder P1 on the back surface of the semiconductor chip 101 is not uniform, so that the solder becomes more brittle from the portion where the solder P1 is thin. Then, the bonding reliability between the semiconductor chip 101 and the back electrode plate 102 is lowered.

また、半導体チップ１０１表面上にマウントされた表面電極板１０３についても傾いてしまう虞がある。表面電極板１０３が傾いた状態で、半導体チップ１０１表面及び裏面電極板１０２の第２電極板１０２ｂ表面に接合されると、表面電極板１０３表面が封止材１０４から露出しない状態で封止されてしまう。表面電極板１０３表面が封止材１０４から露出しないと、半導体チップ１０１の放熱性が低下し、その結果、半導体装置１Ａの信頼性が低下する。   Further, the surface electrode plate 103 mounted on the surface of the semiconductor chip 101 may be inclined. When the surface electrode plate 103 is inclined and bonded to the surface of the semiconductor chip 101 and the surface of the second electrode plate 102b of the back surface electrode plate 102, the surface electrode plate 103 is sealed without being exposed from the sealing material 104. End up. If the surface electrode plate 103 surface is not exposed from the sealing material 104, the heat dissipation of the semiconductor chip 101 is lowered, and as a result, the reliability of the semiconductor device 1A is lowered.

一方、第１の実施形態に係る半導体装置１は、裏面電極板１０２の第１電極板１０２ａ表面と半導体チップ１０１裏面との間にバンプＢ１が形成されている。さらに、バンプＢ１は、半田ペーストＰ２よりも融点の高いＡｕバンプ又はＣｕバンプである。このため、半田ペーストＰ２をリフローする際に、バンプＢ１は溶融することがなく、半導体チップ１０１が自重により傾くことがない。その結果、半導体チップ１０１裏面の半田Ｐ１の厚みが均一となるので、半導体チップ１０１と裏面電極板１０２との接合信頼性が向上する。   On the other hand, in the semiconductor device 1 according to the first embodiment, the bump B <b> 1 is formed between the surface of the first electrode plate 102 a of the back electrode plate 102 and the back surface of the semiconductor chip 101. Further, the bump B1 is an Au bump or a Cu bump having a higher melting point than the solder paste P2. For this reason, when the solder paste P2 is reflowed, the bump B1 is not melted and the semiconductor chip 101 is not tilted by its own weight. As a result, since the thickness of the solder P1 on the back surface of the semiconductor chip 101 becomes uniform, the bonding reliability between the semiconductor chip 101 and the back electrode plate 102 is improved.

また、第１の実施形態に係る半導体装置１は、半導体チップ１０１表面と表面電極板１０３裏面との間、及び裏面電極板１０２の第２電極板１０２ｂ表面と表面電極板１０３裏面との間に夫々バンプＢ２、Ｂ３が形成されている。さらに、バンプＢ２、Ｂ３は、半田ペーストＰ２よりも融点の高いＡｕバンプ又はＣｕバンプである。このため、半田ペーストＰ２をリフローする際に、バンプＢ２、Ｂ３は溶融することがなく、表面電極板１０３が傾くことがない。その結果、半導体チップ１０１表面と表面電極板１０３裏面との間、及び裏面電極板１０２の第２電極板１０２ｂ表面と表面電極板１０３裏面との間の半田Ｐ１の厚みが均一となるので、表面電極板１０３裏面と半導体チップ１０１表面、及び表面電極板１０３裏面と裏面電極板１０２の第２電極板１０２ｂ表面との接合信頼性が向上する。   In addition, the semiconductor device 1 according to the first embodiment is provided between the surface of the semiconductor chip 101 and the back surface of the front electrode plate 103 and between the surface of the second electrode plate 102b of the back electrode plate 102 and the back surface of the front electrode plate 103. Bumps B2 and B3 are formed, respectively. Further, the bumps B2 and B3 are Au bumps or Cu bumps having a melting point higher than that of the solder paste P2. For this reason, when the solder paste P2 is reflowed, the bumps B2 and B3 are not melted and the surface electrode plate 103 is not tilted. As a result, the thickness of the solder P1 between the surface of the semiconductor chip 101 and the back surface of the front electrode plate 103 and between the surface of the second electrode plate 102b of the back surface electrode plate 102 and the back surface of the front surface electrode plate 103 becomes uniform. The bonding reliability between the back surface of the electrode plate 103 and the surface of the semiconductor chip 101 and the back surface of the front surface electrode plate 103 and the surface of the second electrode plate 102b of the back surface electrode plate 102 is improved.

また、表面電極板１０３が傾いた状態で接合されないので、表面電極板１０３表面が封止材１０４から露出しない状態で封止されてしまうことがない。その結果、半導体チップ１０１の放熱性が低下することがなく、半導体装置１の信頼性が向上する。   Further, since the surface electrode plate 103 is not bonded in a tilted state, the surface electrode plate 103 is not sealed without being exposed from the sealing material 104. As a result, the heat dissipation of the semiconductor chip 101 is not lowered, and the reliability of the semiconductor device 1 is improved.

（第２の実施形態）
図５（ａ）は、第２の実施形態に係る半導体装置２Ａの構成断面図である。図５（ｂ）は、第２の実施形態に係る半導体装置２Ｂの構成断面図である。以下、図５（ａ）及び図５（ｂ）を参照して、第２の実施形態に係る半導体装置２Ａ、２Ｂについて説明するが、図１を参照して説明した第１の実施形態の係る半導体装置１と同一の構成には、同一の符号を付して、重複した説明を省略する。 (Second Embodiment)
FIG. 5A is a configuration cross-sectional view of a semiconductor device 2A according to the second embodiment. FIG. 5B is a configuration cross-sectional view of a semiconductor device 2B according to the second embodiment. Hereinafter, the semiconductor devices 2A and 2B according to the second embodiment will be described with reference to FIGS. 5A and 5B. However, according to the first embodiment described with reference to FIG. The same components as those of the semiconductor device 1 are denoted by the same reference numerals, and redundant description is omitted.

図５（ａ）に示す半導体装置２Ａは、半導体チップ１０１表面と表面電極板１０３裏面との間、及び裏面電極板１０２の第２電極板１０２ｂ表面と表面電極板１０３裏面との間に夫々バンプＢ２、Ｂ３が形成されていないが、裏面電極板１０２の第１電極板１０２ａ表面と半導体チップ１０１裏面との間にバンプＢ１が形成されている。このため、加熱・冷却により半田Ｐ１となる半田ペーストのリフロー時に、半導体チップ１０１が傾いてしまうことを防止できる。その結果、半導体チップ１０１裏面の半田Ｐ１の厚みが均一となるので、半導体チップ１０１と裏面電極板１０２との接合信頼性が向上する。また、半導体チップ１０１の傾きを小さくできるので、半導体チップ１０１上に接合される表面電極板１０３の傾きも小さくできる。   The semiconductor device 2A shown in FIG. 5A has bumps between the surface of the semiconductor chip 101 and the back surface of the front electrode plate 103, and between the surface of the second electrode plate 102b of the back electrode plate 102 and the back surface of the front surface electrode plate 103, respectively. B2 and B3 are not formed, but a bump B1 is formed between the surface of the first electrode plate 102a of the back electrode plate 102 and the back surface of the semiconductor chip 101. For this reason, it is possible to prevent the semiconductor chip 101 from being inclined during reflow of the solder paste that becomes the solder P1 by heating and cooling. As a result, since the thickness of the solder P1 on the back surface of the semiconductor chip 101 becomes uniform, the bonding reliability between the semiconductor chip 101 and the back electrode plate 102 is improved. Further, since the inclination of the semiconductor chip 101 can be reduced, the inclination of the surface electrode plate 103 bonded onto the semiconductor chip 101 can also be reduced.

図５（ｂ）に示す半導体装置２Ｂは、裏面電極板１０２の第１電極板１０２ａ表面と半導体チップ１０１裏面との間にバンプＢ１が形成されていないが、半導体チップ１０１表面と表面電極板１０３裏面との間、及び裏面電極板１０２の第２電極板１０２ｂ表面と表面電極板１０３裏面との間に夫々バンプＢ１、Ｂ２が形成されている。その結果、半導体チップ１０１表面と表面電極板１０３裏面との間、及び裏面電極板１０２の第２電極板１０２ｂ表面と表面電極板１０３裏面との間の半田Ｐ１の厚みが均一となるので、表面電極板１０３裏面と半導体チップ１０１表面、及び表面電極板１０３裏面と裏面電極板１０２の第２電極板１０２ｂ表面との接合信頼性が向上する。また、表面電極板１０３の傾きを抑制することができるので、表面電極板１０３表面が封止材１０４から露出しない状態で封止されてしまうことを抑制できる。その結果、半導体チップ１０１の放熱性の低下を抑制することができる。 In the semiconductor device 2 </ b> B shown in FIG. 5B, the bump B <b> 1 is not formed between the surface of the first electrode plate 102 a of the back electrode plate 102 and the back surface of the semiconductor chip 101, but the surface of the semiconductor chip 101 and the surface electrode plate 103. Bumps B1 and B2 are formed between the back surface and between the surface of the second electrode plate 102b of the back electrode plate 102 and the back surface of the front electrode plate 103, respectively. As a result, the thickness of the solder P1 between the surface of the semiconductor chip 101 and the back surface of the front electrode plate 103 and between the surface of the second electrode plate 102b of the back surface electrode plate 102 and the back surface of the front surface electrode plate 103 becomes uniform. The bonding reliability between the back surface of the electrode plate 103 and the surface of the semiconductor chip 101 and the back surface of the front surface electrode plate 103 and the surface of the second electrode plate 102b of the back surface electrode plate 102 is improved. Further, since the inclination of the surface electrode plate 103 can be suppressed, it is possible to suppress the surface electrode plate 103 from being sealed without being exposed from the sealing material 104. As a result, a reduction in heat dissipation of the semiconductor chip 101 can be suppressed.

（第３の実施形態）
図６（ａ）は、第３の実施形態に係る半導体装置３の構成断面図である。図６（ｂ）は、半導体装置３が備える表面電極板１０３Ａの拡大断面図である。以下、図６（ａ）及び図６（ｂ）を参照して、第３の実施形態に係る半導体装置３について説明するが、図１を参照して説明した第１の実施形態の係る半導体装置１と同一の構成には、同一の符号を付して、重複した説明を省略する。 (Third embodiment)
FIG. 6A is a configuration cross-sectional view of the semiconductor device 3 according to the third embodiment. FIG. 6B is an enlarged cross-sectional view of the surface electrode plate 103 </ b> A included in the semiconductor device 3. Hereinafter, the semiconductor device 3 according to the third embodiment will be described with reference to FIGS. 6A and 6B. The semiconductor device according to the first embodiment described with reference to FIG. The same components as those in FIG.

第３の実施形態に係る半導体装置３は、表面電極板１０３Ａの形状が、図１を参照して説明した第１の実施形態に係る半導体装置１の表面電極板１０３と異なる。図６（ｂ）に示すように、表面電極板１０３Ａの端部付近には、段差Ｄ１、Ｄ２が形成されている。このため、表面電極板１０３Ａ表面は、３つの領域（第１領域Ａ１〜第３領域Ａ３）に分かれている。表面電極板１０３Ａは、半導体チップ１０１表面と第１領域Ａ１において接合され、裏面電極板１０２の第２電極板１０２ｂ表面と第２領域Ａ２において接合されている。表面電極板１０３Ａでは、半導体チップ１０１表面からの高さが、第２領域Ａ２において最も高くなっている。   In the semiconductor device 3 according to the third embodiment, the shape of the surface electrode plate 103A is different from the surface electrode plate 103 of the semiconductor device 1 according to the first embodiment described with reference to FIG. As shown in FIG. 6B, steps D1 and D2 are formed in the vicinity of the end portion of the surface electrode plate 103A. For this reason, the surface electrode plate 103A surface is divided into three regions (first region A1 to third region A3). The surface electrode plate 103A is bonded to the surface of the semiconductor chip 101 in the first region A1, and is bonded to the surface of the second electrode plate 102b of the back electrode plate 102 in the second region A2. In the surface electrode plate 103A, the height from the surface of the semiconductor chip 101 is the highest in the second region A2.

ここで、第１領域Ａ１及び第２領域Ａ２は、夫々半導体チップ１０１表面及び第２電極板１０２ｂ表面との接合面積が、図１及び図５を参照して説明した第１，第２の実施形態に係る半導体装置１、２Ａ及び２Ｂに比べて小さく構成されているため、半導体チップ１０１表面に形成するバンプＢ２の数を少なくすることができる。このため、バンプＢ２を形成する時間及びコストを低減することができる。さらに、表面電極板１０３Ａ表面に段差Ｄ１、Ｄ２が形成されているので、表面電極板１０３Ａが封止材１０４から抜け落ちることを防止できる。その他の効果は、第１の実施形態に係る半導体装置１と同じである。   Here, in the first region A1 and the second region A2, the bonding areas between the surface of the semiconductor chip 101 and the surface of the second electrode plate 102b are the first and second embodiments described with reference to FIGS. Since the configuration is smaller than the semiconductor devices 1, 2 </ b> A and 2 </ b> B according to the embodiment, the number of bumps B <b> 2 formed on the surface of the semiconductor chip 101 can be reduced. For this reason, the time and cost for forming the bump B2 can be reduced. Further, since the steps D1 and D2 are formed on the surface electrode plate 103A surface, the surface electrode plate 103A can be prevented from falling off the sealing material 104. Other effects are the same as those of the semiconductor device 1 according to the first embodiment.

（第４の実施形態）
図７（ａ）は、第４の実施形態に係る半導体装置４の構成断面図である。図７（ｂ）は、第４の実施形態に係る半導体装置４が備える裏面電極板１０２Ｂの第１電極板１０２Ｂａ及び表面電極板１０３Ｂの拡大断面図である。以下、図７（ａ）及び図７（ｂ）を参照して、第４の実施形態に係る半導体装置４について説明するが、図１を参照して説明した第１の実施形態の係る半導体装置１と同一の構成には、同一の符号を付して、重複した説明を省略する。 (Fourth embodiment)
FIG. 7A is a configuration cross-sectional view of the semiconductor device 4 according to the fourth embodiment. FIG. 7B is an enlarged cross-sectional view of the first electrode plate 102Ba and the front electrode plate 103B of the back electrode plate 102B included in the semiconductor device 4 according to the fourth embodiment. Hereinafter, the semiconductor device 4 according to the fourth embodiment will be described with reference to FIGS. 7A and 7B. The semiconductor device according to the first embodiment described with reference to FIG. The same components as those in FIG.

第４の実施形態に係る半導体装置４が備える裏面電極板１０２Ｂの第１電極板１０２Ｂａ表面には、複数のバンプＢ１と各々勘合する複数のアライメント孔Ｈ１が形成されている。また、表面電極板１０３Ｂ裏面には、複数のバンプＢ２と各々勘合する複数のアライメント孔Ｈ２が形成されている。   On the surface of the first electrode plate 102Ba of the back electrode plate 102B provided in the semiconductor device 4 according to the fourth embodiment, a plurality of alignment holes H1 that respectively fit with the plurality of bumps B1 are formed. A plurality of alignment holes H2 are formed on the back surface of the front electrode plate 103B to engage with the plurality of bumps B2.

以上のように、この第４の実施形態に係る半導体装置４が備える裏面電極板１０２Ｂａ表面及び表面電極板１０３Ｂ裏面に、夫々、複数のバンプＢ１及びバンプＢ２と勘合する複数のアライメント孔Ｈ１及びアライメント孔Ｈ２を形成しているので、半導体装置４を組み立てる際の位置精度を向上することができる。その他の効果は、第１の実施形態に係る半導体装置１と同じである。なお、裏面電極板１０２Ｂのアライメント孔Ｈ１を利用して半導体チップ１０１をアライメントするためには、半導体チップ１０１裏面側にバンプＢ１を形成する必要がある点に留意する。   As described above, the plurality of alignment holes H1 and alignment that fit with the plurality of bumps B1 and the bumps B2, respectively, on the front surface of the back electrode plate 102Ba and the back surface of the front surface electrode plate 103B included in the semiconductor device 4 according to the fourth embodiment. Since the hole H2 is formed, the positional accuracy when the semiconductor device 4 is assembled can be improved. Other effects are the same as those of the semiconductor device 1 according to the first embodiment. Note that in order to align the semiconductor chip 101 using the alignment hole H1 of the back electrode plate 102B, it is necessary to form the bump B1 on the back surface side of the semiconductor chip 101.

（第５の実施形態）
図８（ａ）は、第５の実施形態に係る半導体装置５の構成断面図である。図８（ｂ）は、第５の実施形態に係る半導体装置５が備える表面電極板１０３Ｃの拡大断面図である。図８（ｃ）は、第５の実施形態の他の例に係る半導体装置５が備える表面電極板１０３Ｄの拡大断面図である。以下、図８（ａ）〜図８（ｃ）を参照して、第５の実施形態に係る半導体装置５について説明するが、図１を参照して説明した第１の実施形態の係る半導体装置１と同一の構成には、同一の符号を付して、重複した説明を省略する。 (Fifth embodiment)
FIG. 8A is a cross-sectional view of the configuration of the semiconductor device 5 according to the fifth embodiment. FIG. 8B is an enlarged cross-sectional view of the surface electrode plate 103C included in the semiconductor device 5 according to the fifth embodiment. FIG. 8C is an enlarged cross-sectional view of the surface electrode plate 103D provided in the semiconductor device 5 according to another example of the fifth embodiment. Hereinafter, the semiconductor device 5 according to the fifth embodiment will be described with reference to FIGS. 8A to 8C. However, the semiconductor device according to the first embodiment described with reference to FIG. The same components as those in FIG.

図８（ｂ）に示すように、この第５の実施形態に係る半導体装置５が備える表面電極板１０３Ｃ表面には、段差Ｄ３及び段差Ｄ４が形成されている。このため、表面電極板１０３Ｃが封止材１０４から抜け落ちることを防止できる。なお、段差Ｄ３及び段差Ｄ４の代わりに、図８（ｃ）に示すように、表面電極板１０３Ｄの側面に溝Ｄ５及び溝Ｄ６を形成した、いわゆる食付き構造としてもよい。このように構成しても、表面電極板１０３Ｄが封止材１０４から抜け落ちることを防止できる。その他の効果は、第１の実施形態に係る半導体装置１と同じである。   As shown in FIG. 8B, a step D3 and a step D4 are formed on the surface of the surface electrode plate 103C provided in the semiconductor device 5 according to the fifth embodiment. For this reason, it is possible to prevent the surface electrode plate 103 </ b> C from falling off the sealing material 104. Instead of the step D3 and the step D4, as shown in FIG. 8C, a so-called bite structure in which the groove D5 and the groove D6 are formed on the side surface of the surface electrode plate 103D may be used. Even if comprised in this way, it can prevent that surface electrode board 103D falls out from the sealing material 104. FIG. Other effects are the same as those of the semiconductor device 1 according to the first embodiment.

（第６の実施形態）
図９は、第６の実施形態に係る半導体装置６の構成断面図である。以下、図９を参照して、第６の実施形態に係る半導体装置６について説明するが、図１を参照して説明した第１の実施形態の係る半導体装置１と同一の構成には、同一の符号を付して、重複した説明を省略する。 (Sixth embodiment)
FIG. 9 is a structural cross-sectional view of a semiconductor device 6 according to the sixth embodiment. Hereinafter, the semiconductor device 6 according to the sixth embodiment will be described with reference to FIG. 9, but the same configuration as the semiconductor device 1 according to the first embodiment described with reference to FIG. The duplicated explanation is omitted.

図９に示す半導体装置６は、表面電極板１０３を備えておらず、裏面電極板１０２の第２電極板１０２ｂと、半導体チップ１０１とをボンディングワイヤＷで接続した構成となっている。なお、図９では、半導体チップ１０１側をウエッジ接合としているが、裏面電極板１０２の第２電極板１０２ｂ側をウエッジ接合としてもよい。このような構成においても、裏面電極板１０２の第１電極板１０２ａ表面と半導体チップ１０１裏面との間にバンプＢ１が形成されているため、半導体チップ１０１が自重により傾くことがない。その結果、半導体チップ１０１裏面の半田Ｐ１の厚みが均一となるので、半導体チップ１０１と裏面電極板１０２との接合信頼性が向上する。   The semiconductor device 6 shown in FIG. 9 does not include the front electrode plate 103, and has a configuration in which the second electrode plate 102 b of the back electrode plate 102 and the semiconductor chip 101 are connected by bonding wires W. In FIG. 9, the semiconductor chip 101 side is wedge bonded, but the second electrode plate 102 b side of the back electrode plate 102 may be wedge bonded. Even in such a configuration, since the bump B1 is formed between the surface of the first electrode plate 102a of the back electrode plate 102 and the back surface of the semiconductor chip 101, the semiconductor chip 101 is not inclined by its own weight. As a result, since the thickness of the solder P1 on the back surface of the semiconductor chip 101 becomes uniform, the bonding reliability between the semiconductor chip 101 and the back electrode plate 102 is improved.

（その他の実施形態）
以上のように、本発明のいくつかの実施形態について説明したが、上記実施形態は、例として提示したものであり、発明の範囲を限定することを意図するものではない。上記実施形態は、その他の様々な形態で実施されることが可能であり、発明の要旨を変更しない範囲で、種々の省略、置き換え、変更を行うことができる。これら実施形態や変形が、発明の範囲や要旨に含まれるのと同様に、特許請求の範囲に記載された発明とその均等の範囲に含まれるものである。 (Other embodiments)
As mentioned above, although several embodiment of this invention was described, the said embodiment is shown as an example and is not intending limiting the range of invention. The above embodiment can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications are included in the invention described in the claims and the equivalents thereof as well as included in the scope and gist of the invention.

例えば、図１０（ａ）に示す半導体装置１ＢのようにバンプＢ１を半導体チップ１０１の四辺に沿って形成してよく、図１０（ｂ）に示す半導体装置１ＣのようにバンプＢ１を半導体チップ１０１の四隅及び中央に形成してもよい。なお、図１０（ａ）及び図１０（ｂ）では、封止材１０４を透視した状態で半導体装置１を図示するとともに、半導体チップ１０１表面と表面電極板１０３裏面との間に形成されているバンプＢ２の図示を省略している。   For example, the bump B1 may be formed along the four sides of the semiconductor chip 101 as in the semiconductor device 1B shown in FIG. 10A, and the bump B1 is formed in the semiconductor chip 101 as in the semiconductor device 1C shown in FIG. You may form in the four corners and center. 10A and 10B, the semiconductor device 1 is illustrated in a state where the sealing material 104 is seen through, and is formed between the surface of the semiconductor chip 101 and the back surface of the front electrode plate 103. The illustration of the bump B2 is omitted.

また、上記各実施形態では、半導体チップ１０１がアノード（陽極）とカソード（陰極）を備えた２極構造であるものとして記載しているが、半導体チップ１０１が、ソース、ドレイン及びゲートを備えた３極構造チップであっても適用することができる。   In each of the above embodiments, the semiconductor chip 101 is described as having a bipolar structure including an anode (anode) and a cathode (cathode). However, the semiconductor chip 101 includes a source, a drain, and a gate. Even a three-pole structure chip can be applied.

１〜６…半導体装置、１０１…半導体チップ、１０２…裏面電極板、１０２ａ…第１電極板、１０２ｂ…第２電極板、１０２ｃ…電極、１０３，１０３Ａ〜１０３Ｄ…表面電極板、１０４…封止材、Ｂ１〜Ｂ３…バンプ、Ｄ１〜Ｄ４…段差、Ｄ５，Ｄ６…溝、Ｈ１，Ｈ２…アライメント孔、Ｐ１…半田、Ｐ２…半田ペースト、Ｗ…ボンディングワイヤ。   DESCRIPTION OF SYMBOLS 1-6 ... Semiconductor device, 101 ... Semiconductor chip, 102 ... Back electrode plate, 102a ... 1st electrode plate, 102b ... 2nd electrode plate, 102c ... Electrode, 103, 103A-103D ... Surface electrode plate, 104 ... Sealing B1, B3 ... bump, D1-D4 ... step, D5, D6 ... groove, H1, H2 ... alignment hole, P1 ... solder, P2 ... solder paste, W ... bonding wire.

Claims (11)

電極を有する裏面電極板と、
前記裏面電極板に半田により接合された半導体チップと、
前記電極が露出した状態で、前記半導体チップを封止する封止材と、
を備え、
前記裏面電極板と前記半導体チップとの接合面に、１以上の第１のバンプが形成されていることを特徴とする半導体装置。 A back electrode plate having electrodes;
A semiconductor chip joined to the back electrode plate by solder;
With the electrode exposed, a sealing material for sealing the semiconductor chip;
With
One or more 1st bumps are formed in the joint surface of the said back surface electrode plate and the said semiconductor chip, The semiconductor device characterized by the above-mentioned. 前記半導体チップは、矩形状であり、
前記裏面電極板と前記半導体チップとの接合面には、前記半導体チップの少なくとも四隅に対応する位置に前記第１のバンプが形成されていることを特徴とする請求項１に記載の半導体装置。 The semiconductor chip is rectangular,
2. The semiconductor device according to claim 1, wherein the first bump is formed at a position corresponding to at least four corners of the semiconductor chip on a bonding surface between the back electrode plate and the semiconductor chip. 前記半導体チップの略中央に対応する位置に前記第１のバンプがさらに形成されていることを特徴とする請求項２に記載の半導体装置。   The semiconductor device according to claim 2, wherein the first bump is further formed at a position corresponding to substantially the center of the semiconductor chip. 前記裏面電極板の前記半導体チップとの接合面には、前記第１のバンプの各々に対応して形成されたアライメント用の凹部が設けられていることを特徴とする請求項１乃至請求項３のいずれか１項に記載の半導体装置。   4. An alignment recess formed in correspondence with each of the first bumps is provided on a bonding surface of the back electrode plate with the semiconductor chip. The semiconductor device according to any one of the above. 前記裏面電極板は、前記半導体チップに接合された第１電極板と、前記第１電極板から離間して配置された第２電極板とから構成され、
前記半導体チップ及び前記第２電極板とに跨って、前記半導体チップ及び前記第２電極板に半田により接合された表面電極板をさらに備え、
前記表面電極板と前記半導体チップとの接合面、及び前記表面電極板と前記表面電極板の前記第２電極板との接合面には、夫々１以上の第２，第３のバンプが形成されていることを特徴とする請求項１乃至請求項４のいずれか１項に記載の半導体装置。 The back electrode plate is composed of a first electrode plate joined to the semiconductor chip and a second electrode plate disposed away from the first electrode plate,
A surface electrode plate joined to the semiconductor chip and the second electrode plate by solder across the semiconductor chip and the second electrode plate,
One or more second and third bumps are formed on the bonding surface between the surface electrode plate and the semiconductor chip and the bonding surface between the surface electrode plate and the second electrode plate of the surface electrode plate, respectively. The semiconductor device according to claim 1, wherein the semiconductor device is provided. 前記表面電極板の前記半導体チップとの接合面には、前記第２のバンプの各々に対応して形成されたアライメント用の凹部が設けられていることを特徴とする請求項５に記載の半導体装置。   6. The semiconductor according to claim 5, wherein a concave portion for alignment formed corresponding to each of the second bumps is provided on a joint surface of the surface electrode plate with the semiconductor chip. apparatus. 前記表面電極板表面の端部付近には、段差が形成されていることを特徴とする請求項５又は請求項６に記載の半導体装置。   The semiconductor device according to claim 5, wherein a step is formed in the vicinity of an end portion of the surface electrode plate surface. 前記表面電極板側面には、該側面に沿って溝が形成されていることを特徴とする請求項５又は請求項６に記載の半導体装置。   The semiconductor device according to claim 5, wherein a groove is formed along a side surface of the surface electrode plate. 前記封止体は、
前記表面電極板の前記半導体チップとの接合面と対向する面の少なくとも一部が露出した状態で、前記半導体チップを封止することを特徴とする請求項５乃至請求項８のいずれか１項に記載の半導体装置。 The sealing body is
9. The semiconductor chip according to claim 5, wherein the semiconductor chip is sealed in a state in which at least a part of a surface of the surface electrode plate facing a bonding surface with the semiconductor chip is exposed. A semiconductor device according to 1. 電極を有する裏面電極板上に半導体チップを実装し、該電極板及び半導体チップを封止材で封止した半導体装置の製造方法であって、
前記裏面電極板の前記半導体チップの実装面に１以上の第１のバンプを形成する工程と、
前記第１のバンプが形成された領域に半田ペーストを塗布する工程と、
前記第１のバンプが形成された領域を含む前記半導体チップの実装面に前記半導体チップをマウントする工程と、
前記半田ペーストを加熱及び冷却し、前記裏面電極板と前記半導体チップとを電気的に接合する工程と、
前記電極が露出した状態で、前記半導体チップを前記封止材で封止する工程と、
を備えることを特徴とする半導体装置の製造方法。 A method of manufacturing a semiconductor device comprising mounting a semiconductor chip on a back electrode plate having an electrode, and sealing the electrode plate and the semiconductor chip with a sealing material,
Forming one or more first bumps on the mounting surface of the semiconductor chip of the back electrode plate;
Applying a solder paste to a region where the first bump is formed;
Mounting the semiconductor chip on a mounting surface of the semiconductor chip including a region where the first bump is formed;
Heating and cooling the solder paste, and electrically bonding the back electrode plate and the semiconductor chip;
A step of sealing the semiconductor chip with the sealing material with the electrode exposed;
A method for manufacturing a semiconductor device, comprising: 前記裏面電極板は、前記半導体チップに接合された第１電極板と、前記第１電極板から離間して配置された第２電極板とから構成され、
前記半田ペーストを塗布する工程と、前記半田ペーストを加熱及び冷却し、前記裏面電極板と前記半導体チップとを電気的に接合する工程との間に、
前記半導体チップ表面及び前記第２電極板表面に、夫々１以上の第２，第３のバンプを形成する工程と、
前記第２，第３のバンプが形成された領域に半田ペーストを塗布する工程と、
前記第２のバンプが形成された領域及び前記第３のバンプが形成された領域にまたがるように、表面電極板をマウントする工程と、
をさらに備えることを特徴とする請求項１０に記載の半導体装置の製造方法。 The back electrode plate is composed of a first electrode plate joined to the semiconductor chip and a second electrode plate disposed away from the first electrode plate,
Between the step of applying the solder paste and the step of heating and cooling the solder paste to electrically join the back electrode plate and the semiconductor chip,
Forming one or more second and third bumps on the semiconductor chip surface and the second electrode plate surface, respectively;
Applying a solder paste to the region where the second and third bumps are formed;
Mounting a surface electrode plate so as to span the region where the second bump is formed and the region where the third bump is formed;
The method of manufacturing a semiconductor device according to claim 10, further comprising:
JP2011204365A 2011-09-20 2011-09-20 Semiconductor device and manufacturing method of the same Withdrawn JP2013065758A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2020167290A (en) * 2019-03-29 2020-10-08 株式会社デンソー Semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2020167290A (en) * 2019-03-29 2020-10-08 株式会社デンソー Semiconductor device
JP7095641B2 (en) 2019-03-29 2022-07-05 株式会社デンソー Semiconductor device

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