JP2008294390A - Module structure - Google Patents

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JP2008294390A
JP2008294390A JP2007238352A JP2007238352A JP2008294390A JP 2008294390 A JP2008294390 A JP 2008294390A JP 2007238352 A JP2007238352 A JP 2007238352A JP 2007238352 A JP2007238352 A JP 2007238352A JP 2008294390 A JP2008294390 A JP 2008294390A
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plate
solder
conductor
module
joint
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Yujiro Kaneko
裕二朗 金子
Masahide Harada
正英 原田
Hideto Yoshinari
英人 吉成
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Hitachi Ltd
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Hitachi Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L24/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L24/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H01L2224/37001—Core members of the connector
    • H01L2224/37099—Material
    • H01L2224/371—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H01L2224/37001—Core members of the connector
    • H01L2224/37099—Material
    • H01L2224/371—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/37138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/37147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/4005—Shape
    • H01L2224/4009—Loop shape
    • H01L2224/40095—Kinked
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401—Disposition
    • H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/40221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/40225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/404—Connecting portions
    • H01L2224/40475—Connecting portions connected to auxiliary connecting means on the bonding areas
    • H01L2224/40491—Connecting portions connected to auxiliary connecting means on the bonding areas being an additional member attached to the bonding area through an adhesive or solder, e.g. buffer pad
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    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/77—Apparatus for connecting with strap connectors
    • H01L2224/7725—Means for applying energy, e.g. heating means
    • H01L2224/77272—Oven
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    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/83801—Soldering or alloying
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H01L2224/848—Bonding techniques
    • H01L2224/84801—Soldering or alloying
    • H—ELECTRICITY
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a module structure that can restrain reduced reliability of soldering connection due to the problem that soldering fault is caused by soaking of melted solder along a plate-like conductor to be bonded and a solder thickness of a solder junction is made smaller than its design value in performing reflow soldering. <P>SOLUTION: For reflow solder bonding, in a plate-like conductor consisting of a plate-like junction 2A that is bonded with a solder-coated junction surface to be bonded and a plate-like inflective rising part 2B rising from the plate-like junction, the main surface of the plate-like junction 2A and that of the plate-like inflective rising part 2B make an acute angle. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

本発明は、モジュールの構成に係り、特にリフローによるはんだ付け不良の発生を抑制することのできる半導体モジュールに関する。   The present invention relates to a module configuration, and more particularly to a semiconductor module capable of suppressing the occurrence of soldering failure due to reflow.

半導体モジュールを構成する基板と該基板に実装される半導体チップとの接続には、ワイヤボンディングが採用される。しかしながら、ワイヤボンディングは、通電時の電気抵抗が高い、長期温度サイクルにより破断が発生する、ボンディング工程に時間がかかる、新たな設備投資が必要などの問題がある。   Wire bonding is adopted for connection between the substrate constituting the semiconductor module and the semiconductor chip mounted on the substrate. However, wire bonding has problems such as high electrical resistance when energized, breakage due to a long-term temperature cycle, time required for the bonding process, and the need for new equipment investment.

このため、近年では、低電気抵抗で製造時間の短縮が可能な板状導電体を用いた接続構造が用いられている。例えば、特許文献１には、半導体チップとの接続に板状の接続導体を用いて、接合部の劣化を抑制することが示されている。   For this reason, in recent years, a connection structure using a plate-like conductor with low electrical resistance and capable of shortening the manufacturing time has been used. For example, Patent Document 1 shows that a plate-like connection conductor is used for connection with a semiconductor chip to suppress deterioration of a joint portion.

このように、ワイヤボンディングに代えて、板状導電体を用いて接続することにより、温度サイクルによる接合部の劣化を抑制して、通電容量の増加を図ることが可能となる。しかしながら、はんだ接続という点において新たな問題が発生する。   As described above, instead of wire bonding, connection using a plate-like conductor can suppress deterioration of the joint portion due to a temperature cycle and increase current carrying capacity. However, a new problem arises in terms of solder connection.

図４は、従来の半導体モジュールを説明する図である。図４において、１は半導体チップ、２は板状導電体、２Ａは第１板状接合部、２Ｂは第１板状屈曲立上部、２Ｃは第２板状屈曲立上部、２Ｄは第２板状接合部、２Ｅは板状引出導体部、４は金属基板、４１は導電性パターン、４１Ａは第１導電性領域、４１Ｂは第２導電性領域、４２は樹脂絶縁層、４３は金属板（放熱板）、１０２は第２導電性領域上はんだ、１０３は第１導電性領域上はんだ、１０４は半導体チップ上はんだである。   FIG. 4 is a diagram for explaining a conventional semiconductor module. In FIG. 4, 1 is a semiconductor chip, 2 is a plate-like conductor, 2A is a first plate-like joint, 2B is a first plate-like bent upright portion, 2C is a second plate-like bent upright portion, and 2D is a second plate. 2E is a plate-like lead conductor portion, 4 is a metal substrate, 41 is a conductive pattern, 41A is a first conductive region, 41B is a second conductive region, 42 is a resin insulating layer, and 43 is a metal plate ( (Radiation plate), 102 is solder on the second conductive region, 103 is solder on the first conductive region, and 104 is solder on the semiconductor chip.

図４に示す構造の半導体モジュールにおいて、はんだ付けに際して、はんだリフローを行うと、半導体チップ上はんだ１０４が溶融し、溶融したはんだが板状導電体２に沿って矢印Ｈに示すように吸い上げられてはんだ付け不良を引き起こす。   In the semiconductor module having the structure shown in FIG. 4, when solder reflow is performed at the time of soldering, the solder 104 on the semiconductor chip is melted, and the melted solder is sucked up along the plate-like conductor 2 as indicated by an arrow H. Causes poor soldering.

このような現象に対して、特許文献２では、板状接続片の接着部を引き出し部に対しほぼ直角となるように形成することにより、はんだ付け時の表面張力によるはんだの吸い上げを抑制することが示されている。
特開２００２−４３５０８号公報 実開平５−７９９４８号公報 With respect to such a phenomenon, in Patent Document 2, the adhesive portion of the plate-like connecting piece is formed so as to be substantially perpendicular to the lead-out portion, thereby suppressing the solder suction due to the surface tension during soldering. It is shown.
JP 2002-43508 A Japanese Utility Model Publication No. 5-79948

前述のように、半導体チップと板状導電体とをリフローによるはんだ付けする際には、半導体チップ上に配置したはんだが溶融し、溶融したはんだが前記板状導電体に沿って吸い上げられてはんだ付け不良を引き起こす。
すなわち、前記吸い上げにより半導体チップ上のはんだ厚みが設計値よりも小さくなり、はんだ接続の信頼性が低下する。 As described above, when soldering the semiconductor chip and the plate-like conductor by reflow, the solder disposed on the semiconductor chip is melted, and the melted solder is sucked up along the plate-like conductor to be soldered. Causes poor attachment.
That is, due to the siphoning, the solder thickness on the semiconductor chip becomes smaller than the design value, and the reliability of solder connection is lowered.

また、半導体モジュールは複数の半導体チップを備え、該半導体チップの数に応じた板状導電体が使用される。この板状導電体のサイズは他の電子部品に比して大きい。このため、半導体モジュールの小型化が困難となる。   Further, the semiconductor module includes a plurality of semiconductor chips, and plate-like conductors corresponding to the number of the semiconductor chips are used. The size of the plate-like conductor is larger than that of other electronic components. For this reason, it is difficult to reduce the size of the semiconductor module.

本発明は、これらの問題点に鑑みてなされたもので、はんだ吸い上げに基づくはんだ付け不良の発生を抑制することのできるモジュール構成を提供するものである。   The present invention has been made in view of these problems, and provides a module configuration capable of suppressing the occurrence of poor soldering based on solder siphoning.

本発明は上記課題を解決するため、次のような手段を採用した。   In order to solve the above problems, the present invention employs the following means.

はんだ接合する板状接合部と、当該板状接合部から立ち上がる板状屈曲立上部とを少なくとも備えた板状導電体において、当該板状接合部の主面と当該板状屈曲立上部の主面とが成す角度を鋭角に形成する。   In a plate-shaped conductor having at least a plate-like joint portion to be soldered and a plate-like bent upright portion rising from the plate-like joint portion, a main surface of the plate-like joint portion and a main surface of the plate-like bent upright portion The angle formed by and is formed as an acute angle.

本発明は、以上の構成を備えるため、はんだ吸い上げに基づくはんだ付け不良の発生を抑制することができ、さらに、モジュールを小型化できる。   Since this invention is provided with the above structure, generation | occurrence | production of the soldering defect based on solder siphoning can be suppressed, and also a module can be reduced in size.

以下、最良の実施形態を添付図面を参照しながら説明する。図１および図２は本実施形態にかかる半導体モジュールを説明する図であり、図１は半導体モジュールの斜視図、図２は側面図である。これらの図において、１は半導体チップ、２は板状導電体、２Ａは、第１板状接合部、２Ｂは、第１板状屈曲立上部、２Ｃは、第２板状接合部、２Ｄは、第２板状屈曲立上部、２Ｅは板状引出導体部、３は熱拡散板、４は金属基板、５は充填樹脂、４１は導電性パターン、４１Ａは第１導電性領域、４１Ｂは第２導電性領域、４２は樹脂絶縁層、４３は金属板（放熱板）、１０１は第１導電性領域上はんだ、１０２は第２導電性領域上はんだ、１０３は熱拡散板上はんだ、１０４は半導体チップ上はんだである。なお、図１においては充填樹脂５を省略している。   Hereinafter, the best embodiment will be described with reference to the accompanying drawings. 1 and 2 are diagrams for explaining a semiconductor module according to the present embodiment. FIG. 1 is a perspective view of the semiconductor module, and FIG. 2 is a side view. In these drawings, 1 is a semiconductor chip, 2 is a plate-like conductor, 2A is a first plate-like joint, 2B is a first plate-like bent upright portion, 2C is a second plate-like joint, and 2D is , 2E is a plate-like lead conductor portion, 3E is a heat diffusion plate, 4 is a metal substrate, 5 is a filling resin, 41 is a conductive pattern, 41A is a first conductive region, and 41B is a first conductive region. 2 conductive regions, 42 is a resin insulating layer, 43 is a metal plate (heat sink), 101 is solder on the first conductive region, 102 is solder on the second conductive region, 103 is solder on the heat diffusion plate, 104 is It is solder on a semiconductor chip. In FIG. 1, the filling resin 5 is omitted.

前記半導体モジュールの組立は次のように行う。まず、金属板４３の上面に絶縁樹脂４２を形成する。金属板４３はアルミニウム、銅などの金属あるいは合金で形成し、絶縁樹脂４２は耐熱性と絶縁性の観点からセラミックスを焼結した厚膜で形成する。   The semiconductor module is assembled as follows. First, the insulating resin 42 is formed on the upper surface of the metal plate 43. The metal plate 43 is formed of a metal such as aluminum or copper or an alloy, and the insulating resin 42 is formed of a thick film obtained by sintering ceramics from the viewpoint of heat resistance and insulation.

次に、絶縁樹脂４２上に第１導電性領域４１Ａおよび第２導電性領域４１Ｂを含む導電性パターン４１を形成し金属基板４とする。ここで用いる第１導電性領域４１Ａ、第２導電性領域４１Ｂを含む導電性パターン４１は金属板４３と同様にアルミニウム、銅などの金属あるいは合金で形成する。   Next, the conductive pattern 41 including the first conductive region 41 </ b> A and the second conductive region 41 </ b> B is formed on the insulating resin 42 to form the metal substrate 4. The conductive pattern 41 including the first conductive region 41 </ b> A and the second conductive region 41 </ b> B used here is formed of a metal such as aluminum or copper or an alloy like the metal plate 43.

次に、導電性パターン４１上の熱拡散板搭載領域および板状導電体搭載領域に第１導電性領域上はんだ１０１および第２導電性領域上はんだ１０２をはんだペースト、はんだシートなどで形成する。はんだシートで供給する場合は、はんだ濡れ性を向上させるために導電性パターン４１のはんだ接続面あるいははんだシート全体にフラックスを塗布すると良い。
なお、はんだ材は環境問題の観点からＳｎ−３Ａｇ−０．５Ｃｕなどの鉛フリーはんだがよい。 Next, the first conductive region solder 101 and the second conductive region solder 102 are formed with solder paste, solder sheet, or the like in the heat diffusion plate mounting region and the plate-like conductor mounting region on the conductive pattern 41. When supplying with a solder sheet, in order to improve solder wettability, it is good to apply | coat a flux to the solder connection surface of the electroconductive pattern 41, or the whole solder sheet.
The solder material is preferably lead-free solder such as Sn-3Ag-0.5Cu from the viewpoint of environmental problems.

このように形成した第１導電性領域上はんだ１０１上に熱拡散板３を搭載する。熱拡散板３は半導体チップ１よりも大きいサイズの銅または銅合金で形成する。なお、はんだ付けがされる領域には、はんだ濡れ性を向上させるために錫、はんだ、ニッケルなどの少なくとも１層をめっきや蒸着によって形成するとよい。   The thermal diffusion plate 3 is mounted on the first conductive region upper solder 101 thus formed. The heat diffusing plate 3 is formed of copper or a copper alloy having a size larger than that of the semiconductor chip 1. In the area to be soldered, at least one layer of tin, solder, nickel or the like may be formed by plating or vapor deposition in order to improve solder wettability.

前記熱拡散板３を搭載したのちは、該熱拡散板３上に熱拡散板上はんだ１０３をはんだシート、はんだペーストなどで形成する。はんだシートで形成する場合は、はんだ濡れ性を向上させるために熱拡散板３のはんだ接続面あるいははんだシート全体にフラックスを塗布する。なお、熱拡散板上はんだ１０３は第１導電性領域上はんだ１０１や第２導電性領域上はんだ１０２に用いたはんだと同一の材料を選択する。   After mounting the heat diffusing plate 3, the solder 103 on the heat diffusing plate is formed on the heat diffusing plate 3 with a solder sheet, a solder paste or the like. When forming with a solder sheet, a flux is applied to the solder connection surface of the thermal diffusion plate 3 or the entire solder sheet in order to improve solder wettability. For the solder 103 on the heat diffusion plate, the same material as the solder used for the solder 101 on the first conductive region and the solder 102 on the second conductive region is selected.

次に、熱拡散板上はんだ１０３の上に半導体チップ１を搭載し、さらに半導体チップ上に半導体チップ上はんだ１０４をはんだシート、はんだペーストなどで形成する。
なお、はんだシートで形成する場合は、はんだ濡れ性を向上させるために半導体チップ１のはんだ接続面あるいははんだシート全体にフラックスを塗布するとよい。この半導体チップ上はんだ１０４は熱拡散板上はんだ１０３と同様に、第１導電性領域上はんだ１０１や第２導電性領域上はんだ１０２に用いたはんだと同一の材料を選択する。
なお、半導体チップ１の電極面には、はんだの濡れ性を向上させるために錫、ニッケル、金、銀などの少なくとも１層を形成するとよい。 Next, the semiconductor chip 1 is mounted on the solder 103 on the heat diffusion plate, and the semiconductor chip solder 104 is formed on the semiconductor chip by a solder sheet, a solder paste, or the like.
In addition, when forming with a solder sheet, in order to improve solder wettability, it is good to apply | coat a flux to the solder connection surface of the semiconductor chip 1, or the whole solder sheet. Similar to the solder 103 on the heat diffusion plate, the same material as the solder used for the first conductive region solder 101 and the second conductive region solder 102 is selected for the solder 104 on the semiconductor chip.
Note that at least one layer of tin, nickel, gold, silver or the like may be formed on the electrode surface of the semiconductor chip 1 in order to improve the wettability of the solder.

最後に板状導電体２を半導体チップ上はんだ１０４と第２導電性領域上はんだ１０２上に搭載する。板状導電体２は銅、銅合金などで形成する。
また、板状導電体２のはんだ付けされる領域には、はんだ濡れ性を向上させるために錫、はんだ、ニッケルなどの少なくとも１層をめっきや蒸着によって、厚さ１ないし１０μｍ形成するとよい。 Finally, the plate-like conductor 2 is mounted on the solder 104 on the semiconductor chip and the solder 102 on the second conductive region. The plate-like conductor 2 is formed of copper, copper alloy or the like.
In addition, in order to improve solder wettability, at least one layer of tin, solder, nickel, or the like may be formed in the region to be soldered of the plate-like conductor 2 by plating or vapor deposition to a thickness of 1 to 10 μm.

前記板状導電体２の形状は、半導体チップ接続側の第１板状接続部２Ａの主面と、第１板状立上部の主面とのなす角（θ１）を９０°未満とするのがよい。これにより、リフローの際に表面張力によって引き起こされる半導体チップ上はんだ１０４の板状屈曲立上部２Ｂへの吸い上がりを抑制することができる。
ここで主面とは、板状体が備える面の内、他の面より相対的に広い面を意味する。 The shape of the plate-like conductor 2 is such that the angle (θ1) formed between the main surface of the first plate-like connection portion 2A on the semiconductor chip connection side and the main surface of the first plate-like upright portion is less than 90 °. Is good. As a result, it is possible to suppress sucking of the solder 104 on the semiconductor chip 104 to the plate-like bent upright portion 2B caused by surface tension during reflow.
Here, the main surface means a surface relatively wider than other surfaces among the surfaces provided in the plate-like body.

この点を図５に基づいて説明する。
図５は、半導体チップ上はんだ104の前記板状導電体２への吸い上がりについて、板状接合部の主面と板状屈曲立上部の主面とがなす角よる影響を示す図である。
ここでは、図２に示した前記第１板状接合部２Ａの主面と第１板状屈曲立上部の主面とのなす角（θ１）を、鋭角、直角、および鈍角と変化させた3種類のサンプルを用いて行った。 すなわち、
従来の半導体モジュールのように第１板状接合部２Ａの主面と第１板状屈曲立上部の主面とのなす角（θ１）が直角、および鈍角の場合、半導体チップ上はんだ１０４のはんだ厚さは設計値よりも小さくなった。これは、半導体チップ上はんだ１０４がリフロー時に溶融した際、図4に示すように板状導電体２の第１板状屈曲立上部２Ｂに沿って過剰に吸い上げられたためである。 This point will be described with reference to FIG.
FIG. 5 is a diagram showing the influence of the angle formed by the main surface of the plate-like joint portion and the main surface of the plate-like bent upright portion on the sucking of the solder 104 on the semiconductor chip to the plate-like conductor 2.
Here, the angle (θ1) formed between the main surface of the first plate-like joint 2A shown in FIG. 2 and the main surface of the first plate-shaped bent upright portion is changed to an acute angle, a right angle, and an obtuse angle 3 This was done using different types of samples. That is,
When the angle (θ1) formed between the main surface of the first plate-like joint portion 2A and the main surface of the first plate-like bent upright portion is a right angle and an obtuse angle as in the conventional semiconductor module, the solder of the solder 104 on the semiconductor chip The thickness was smaller than the design value. This is because when the solder 104 on the semiconductor chip is melted at the time of reflow, it is excessively sucked up along the first plate-like bent upright portion 2B of the plate-like conductor 2 as shown in FIG.

このように、当該成す角（θ１）が直角、および鈍角の場合は、半導体チップ上はんだ１０４の厚さが低減し、このことに起因してはんだ接続の信頼性等、特性劣化が生じる。
一方、本願発明による半導体モジュールのように板状導電体２の第１板状接合部２Ａの主面と第１板状屈曲立上部２Ｂの主面とのなす角（θ１）が鋭角の場合、半導体チップ上はんだ１０４のはんだ厚さは、設計値とほぼ同等になった。これは、半導体チップ上はんだ１０４がリフロー時に溶融した際に、板状導電体２の第１立上部２Ｂに沿って吸い上げられるのを防止できたためである。
以上のように、板状導電体２の板状接合部の主面と板状屈曲立上部の主面とのなす角が鋭角の場合、当該板状導電体２を半導体モジュールに用いることで、半導体モジュールに搭載された半導体チップ上はんだ１０４のはんだ付け不良の発生を抑制できるものである。 As described above, when the formed angle (θ1) is a right angle and an obtuse angle, the thickness of the solder 104 on the semiconductor chip is reduced, and this causes deterioration of characteristics such as reliability of solder connection.
On the other hand, when the angle (θ1) formed by the main surface of the first plate-like joint portion 2A of the plate-like conductor 2 and the main surface of the first plate-like bent upright portion 2B is an acute angle as in the semiconductor module according to the present invention, The solder thickness of the solder 104 on the semiconductor chip is almost equal to the design value. This is because when the solder 104 on the semiconductor chip is melted at the time of reflow, it is prevented from being sucked up along the first raised portions 2B of the plate-like conductor 2.
As described above, when the angle formed by the main surface of the plate-like joint portion of the plate-like conductor 2 and the main surface of the plate-like bent upright portion is an acute angle, by using the plate-like conductor 2 for a semiconductor module, The occurrence of poor soldering of the solder 104 on the semiconductor chip mounted on the semiconductor module can be suppressed.

図３は、板状導電体２の板状屈曲立上部２Ｂの近傍の詳細を説明する図である。
板状導電体２を半導体チップ上はんだ１０４上に搭載する際は、図３に示すように、半導体チップ上はんだ１０４の塗布範囲を第１板状接合部２Ａの端部から、板状屈曲端部２Ｆに至らない範囲とし、第２板状接合部２Ｄのはんだ塗布範囲も同様とする。
これにより、半導体チップ上はんだの吸い上がりを抑制する効果がより向上する。
このように、はんだの吸い上がりを抑制することにより、はんだの層厚の減少幅を抑制して半導体チップに印加される熱歪みを抑制することができる。
板状導電体２の板状引出導体部２Ｅの主面は、マウンタにより板状導電体２を安定的に供給するため第１板状接合部の主面および第２板状接合部の主面と平行（水平）であるのがよい。
これにより、板状導電体２の重心位置である板状引出導体部２Ｅを保持具により吸着保持することができる。 FIG. 3 is a diagram for explaining the details of the vicinity of the plate-like bent upright portion 2B of the plate-like conductor 2.
When the plate-like conductor 2 is mounted on the semiconductor-chip solder 104, as shown in FIG. 3, the application range of the semiconductor-chip solder 104 is changed from the end of the first plate-like joint 2A to the plate-like bent end. The range does not reach part 2F, and the solder application range of second plate-like joint 2D is the same.
Thereby, the effect which suppresses the siphoning of the solder on a semiconductor chip improves more.
In this way, by suppressing solder wicking, it is possible to suppress a decrease in the solder layer thickness and suppress thermal strain applied to the semiconductor chip.
The main surface of the plate-like lead conductor portion 2E of the plate-like conductor 2 is the main surface of the first plate-like joint portion and the main surface of the second plate-like joint portion in order to stably supply the plate-like conductor 2 by the mounter. And parallel (horizontal).
Thereby, the plate-like lead conductor portion 2E that is the position of the center of gravity of the plate-like conductor 2 can be sucked and held by the holder.

また、半導体チップに接続する第１板状接合部と板状引出導体部を挟んで反対側の第２板状接合部２Ｄの主面と第２板状屈曲立上部の主面とのなす角（θ２）も９０°未満とするのがよい。
このように、板状導電体２の両側の板状接合部の主面とその対応する板状屈曲立上部の主面とのなす角（θ１およびθ２）をそれぞれ９０°未満とすることで、両側のはんだ接続面積および板状引出導体部の長さはそのままに両側の接続領域間隔を狭めることができる。
これにより、板状導電体の実装面積が低減され、半導体モジュールを小型化することができる。 In addition, an angle formed between the main surface of the second plate-shaped joint portion 2D on the opposite side across the first plate-shaped joint portion connected to the semiconductor chip and the plate-shaped lead conductor portion and the main surface of the second plate-shaped bent upright portion (Θ2) is also preferably less than 90 °.
Thus, the angles (θ1 and θ2) formed by the main surfaces of the plate-like joints on both sides of the plate-like conductor 2 and the corresponding main surfaces of the plate-like bent upright portions are each less than 90 °, The distance between the connection areas on both sides can be narrowed while the solder connection areas on both sides and the length of the plate-like lead conductor portion remain unchanged.
Thereby, the mounting area of the plate-like conductor is reduced, and the semiconductor module can be miniaturized.

この点を図２に基づいて詳細に説明する。
特許文献１に示されるような、第１、２板状接合部に対して第１，２板状屈曲立上部が直角に立ち上がった場合、図２におけるαは、α＝第１板状接合部２Ａの長さ＋板状引出導体部２Ｅの長さ＋第２板状接合部２Ｄの長さとなるが、上記実施例によれば、α＝第１板状接合部２Ａの長さ＋板状引出導体部２Ｅの長さ＋第２板状接合部２Ｄの長−β−γとなる。
すなわち、β＋γだけ小型化できることとなる。 This point will be described in detail with reference to FIG.
When the first and second plate-like bent uprights rise at a right angle with respect to the first and second plate-like joints as shown in Patent Document 1, α in FIG. 2 is α = first plate-like joint. The length of 2A + the length of the plate-like lead conductor portion 2E + the length of the second plate-like joint portion 2D. According to the above embodiment, α = the length of the first plate-like joint portion 2A + the plate shape. The length of the lead conductor portion 2E + the length of the second plate-like joint portion 2D−β−γ.
That is, the size can be reduced by β + γ.

このようにして、金属基板上に板状導電体２まで搭載した半導体モジュールを不活性雰囲気の炉中でリフローする。これにより、第１導電性領域上はんだ１０１、第２導電性領域上はんだ１０２、熱拡散板上はんだ１０３および半導体チップ上はんだ１０４が溶融して一括接続されて半導体モジュールが完成する。   In this manner, the semiconductor module mounted up to the plate-like conductor 2 on the metal substrate is reflowed in a furnace in an inert atmosphere. As a result, the first conductive region solder 101, the second conductive region solder 102, the heat diffusion plate solder 103, and the semiconductor chip solder 104 are melted and collectively connected to complete the semiconductor module.

他の実施変形例として、
前記実施例では、チップ側と第２導電性領域に各々接続する板状導体の板状接合部の主面と、板状屈曲立上部の主面の成す角を共に鋭角に形成したが、どちらか一方にのみ形成しても良い。
さらに、当該板状導電体は、チップと第２導電性領域とのの接続に限らず、各種導体間の接続に適用できることは明らかである。 As other implementation variations,
In the above embodiment, the angle formed by the main surface of the plate-like joint portion of the plate-like conductor connected to the chip side and the second conductive region and the main surface of the plate-like bent upright portion are both formed as acute angles. You may form only in either.
Further, it is obvious that the plate-like conductor can be applied not only to the connection between the chip and the second conductive region but also to the connection between various conductors.

なお、Ｓｎ−３Ａｇ−０．５Ｃｕはんだを用いる場合、接続温度は２４０℃〜２６０℃
程度がよい。最後に充填樹脂５により構造体の一部あるいは全体を封止する。充填樹脂５
はゲル、モールドレジンのいずれでもよい。 In addition, when using Sn-3Ag-0.5Cu solder, connection temperature is 240 degreeC-260 degreeC
The degree is good. Finally, a part or the whole of the structure is sealed with the filling resin 5. Filling resin 5
May be either a gel or a mold resin.

以上説明したように、本実施形態によれば、階層接続を有する構造体を一括して接続することができる。また、充填樹脂５によりはんだ接続部を覆うことによってはんだ接続の信頼性を向上させることができる。   As described above, according to the present embodiment, structures having hierarchical connections can be connected together. Moreover, the reliability of solder connection can be improved by covering the solder connection portion with the filling resin 5.

また、板状接続部から立ち上がる、板状屈曲引出導体部の立ち上がり角度（θ１、θ２）を９０°未満としている。これにより、はんだの板状導電体への吸い上りを抑制することができ、はんだ接続の信頼性を高めることができる。
また、板状導電体の実装面積を低減することができ、半導体モジュールをより小型化することができる。 Further, the rising angle (θ1, θ2) of the plate-like bent lead conductor portion rising from the plate-like connecting portion is less than 90 °. Thereby, the suction of the solder to the plate-like conductor can be suppressed, and the reliability of the solder connection can be improved.
Moreover, the mounting area of the plate-like conductor can be reduced, and the semiconductor module can be further downsized.

本実施形態にかかる半導体モジュールの斜視図。The perspective view of the semiconductor module concerning this embodiment. 半導体モジュールの側面図。The side view of a semiconductor module. 板状導電体の立上がり部の近傍の詳細を説明する図。The figure explaining the detail of the vicinity of the rising part of a plate-shaped conductor. 従来の半導体モジュールを説明する図。The figure explaining the conventional semiconductor module. 板状接合部の主面と板状屈曲立上部の主面とのなす角（θ１）と半導体チップ上はんだ厚さとの関係を示す図である。It is a figure which shows the relationship between the angle | corner ((theta) 1) which the main surface of a plate-shaped junction part and the main surface of a plate-shaped bending upright part, and the solder thickness on a semiconductor chip.

符号の説明Explanation of symbols

１ 半導体チップ
２ 板状導電体
２Ａ 第１板状接合部
２Ｂ 第１板状屈曲立上部
２Ｃ 第２板状接合部
２Ｄ 第２板状屈曲立上部
２Ｅ 板状引出導体部
２Ｆ 端部
３ 熱拡散板
４ 金属基板
５ 充填樹脂
４１ 導電性パターン
４１Ａ 第１導電性領域
４１Ｂ 第２導電性領域
４２ 絶縁樹脂層
４３ 金属板
１０１ 第１導電性領域上はんだ
１０２ 第２導電性領域上はんだ
１０３ 熱拡散板上はんだ
１０４ 半導体チップ上はんだ DESCRIPTION OF SYMBOLS 1 Semiconductor chip 2 Plate-like conductor 2A 1st plate-like junction part 2B 1st plate-like bending upright part 2C 2nd plate-like joining part 2D 2nd plate-like bending upright part 2E Plate-like lead conductor part 2F End part 3 Thermal diffusion Plate 4 Metal substrate 5 Filling resin 41 Conductive pattern 41A First conductive region 41B Second conductive region 42 Insulating resin layer 43 Metal plate
101 Solder on the first conductive area 102 Solder on the second conductive area 103 Solder on the heat diffusion plate 104 Solder on the semiconductor chip

Claims (9)

はんだ接合面となる板状接合部と、当該板状接合部から屈曲して立ち上がる板状屈曲立上部とを備えた板状導電体と、当該板状導電体とリフローによるはんだ接続される被接続導体から構成されるモジュールにおいて、当該板状導体の形状が、板状接合部の主面と板状屈曲立上部の主面とで成す角度が鋭角であるモジュール。     A plate-like conductor having a plate-like joint portion to be a solder joint surface, and a plate-like bent upright portion that bends and rises from the plate-like joint portion, and a connection to be connected to the plate conductor by soldering by reflow The module comprised from a conductor, The angle which the angle which the shape of the said plate-shaped conductor forms with the main surface of a plate-shaped junction part and the main surface of a plate-shaped bending upright is an acute angle. 請求項１における板状導電体が、
第１被接続導体と接続する、第１板状接合部と、
当該第１板状接合部から立ち上がる第１板状屈曲部と、
第２被接続導体と接続する、第２板状接合部と、
当該第２板状接合部から立ち上がる第２板状屈曲部と、
当該第１板状屈曲立上部と第２板状屈曲立上部とを接続する板状引出導体部から構成された板状導電体であるモジュール。 The plate-like conductor according to claim 1,
A first plate-like joint connected to the first connected conductor;
A first plate-like bent portion rising from the first plate-like joint portion;
A second plate-like joint connected to the second connected conductor;
A second plate-like bent portion rising from the second plate-like joint,
The module which is a plate-shaped conductor comprised from the plate-shaped lead conductor part which connects the said 1st plate-shaped bending upright part and the 2nd plate-like bending upright part. 請求項２における板状引出導体部は、その主面が前記第１板状接合部の主面および第２板状接合部の主面と平行であるモジュール。   The plate-like lead conductor portion according to claim 2, wherein the main surface is parallel to the main surface of the first plate-like joint portion and the main surface of the second plate-like joint portion. 請求項１乃至３における板状導電体は、銅または銅合金からなり、前記板状接合部には、はんだぬれ性を改善するためのめっき層が形成されたモジュール。   4. The module according to claim 1, wherein the plate-like conductor is made of copper or a copper alloy, and a plating layer for improving solder wettability is formed at the plate-like joint portion. 請求項４におけるメッキ層は、厚さ１ないし１０μｍのＳｎ−Ａｇめっき層，Ｎｉめっき層、またはＳｎめっき層であるモジュール。   5. The module according to claim 4, wherein the plating layer is a Sn—Ag plating layer, a Ni plating layer, or a Sn plating layer having a thickness of 1 to 10 μm. 請求項１乃至５における被接続導体が、
金属板上に絶縁層を介して形成された第１導電性領域にその一方端を接続して配置された半導体チップと、
前記金属板上に絶縁層を介して形成された第２導電性領域と、
である半導体モジュール。 The connected conductor according to any one of claims 1 to 5,
A semiconductor chip disposed on a metal plate with one end connected to a first conductive region formed via an insulating layer;
A second conductive region formed on the metal plate via an insulating layer;
Is a semiconductor module. 請求項６における半導体チップは、第１導電性領域と、その上面に配置される半導体チップとの間に熱拡散板が配設されたモジュール。   The semiconductor chip according to claim 6 is a module in which a heat diffusion plate is disposed between a first conductive region and a semiconductor chip disposed on an upper surface thereof. 請求項１乃至７におけるモジュールは、
モジュールの全体または一部が樹脂によって被覆されているモジュール。 The modules according to claims 1 to 7 are:
A module in which all or part of the module is covered with resin. 請求項１乃至８における、リフローによるハンダ接合のハンダ塗布面が、前記板状接合部端部から、前記板状屈曲立上部に至らない範囲であるモジュール。   9. The module according to claim 1, wherein a solder application surface of solder joint by reflow does not reach the plate-like bent upright portion from the end of the plate-like joint portion.
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WO2014068936A1 (en) * 2012-11-05 2014-05-08 日本精工株式会社 Semiconductor module
CN103930981A (en) * 2012-11-05 2014-07-16 日本精工株式会社 Semiconductor module
CN103930981B (en) * 2012-11-05 2016-07-13 日本精工株式会社 Semiconductor module
US9609775B2 (en) 2012-11-05 2017-03-28 Nsk Ltd. Semiconductor module
JP6364556B1 (en) * 2017-02-20 2018-07-25 新電元工業株式会社 Electronic equipment
US10600712B2 (en) 2017-02-20 2020-03-24 Shindengen Electric Manufacturing Co., Ltd. Electronic device
WO2020208677A1 (en) * 2019-04-08 2020-10-15 新電元工業株式会社 Semiconductor device
JPWO2020208677A1 (en) * 2019-04-08 2021-05-06 新電元工業株式会社 Semiconductor device
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CN113056813B (en) * 2019-04-08 2024-03-12 新电元工业株式会社 Semiconductor device with a semiconductor device having a plurality of semiconductor chips
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