JP7006686B2 - Semiconductor devices and methods for manufacturing semiconductor devices - Google Patents

Semiconductor devices and methods for manufacturing semiconductor devices Download PDF

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JP7006686B2
JP7006686B2 JP2019513270A JP2019513270A JP7006686B2 JP 7006686 B2 JP7006686 B2 JP 7006686B2 JP 2019513270 A JP2019513270 A JP 2019513270A JP 2019513270 A JP2019513270 A JP 2019513270A JP 7006686 B2 JP7006686 B2 JP 7006686B2
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solder
copper
semiconductor device
laminated substrate
solder material
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JPWO2018193760A1 (en
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隆 齊藤
克己 谷口
英司 望月
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Fuji Electric Co Ltd
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    • BPERFORMING OPERATIONS; TRANSPORTING
    • B23MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23KSOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K1/00Soldering, e.g. brazing, or unsoldering
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B23MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23KSOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K35/00Rods, electrodes, materials, or media, for use in soldering, welding, or cutting
    • B23K35/22Rods, electrodes, materials, or media, for use in soldering, welding, or cutting characterised by the composition or nature of the material
    • B23K35/24Selection of soldering or welding materials proper
    • B23K35/26Selection of soldering or welding materials proper with the principal constituent melting at less than 400 degrees C
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/52Mounting semiconductor bodies in containers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/34Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • CCHEMISTRY; METALLURGY
    • C22METALLURGY; FERROUS OR NON-FERROUS ALLOYS; TREATMENT OF ALLOYS OR NON-FERROUS METALS
    • C22CALLOYS
    • C22C12/00Alloys based on antimony or bismuth
    • CCHEMISTRY; METALLURGY
    • C22METALLURGY; FERROUS OR NON-FERROUS ALLOYS; TREATMENT OF ALLOYS OR NON-FERROUS METALS
    • C22CALLOYS
    • C22C13/00Alloys based on tin
    • CCHEMISTRY; METALLURGY
    • C22METALLURGY; FERROUS OR NON-FERROUS ALLOYS; TREATMENT OF ALLOYS OR NON-FERROUS METALS
    • C22CALLOYS
    • C22C13/00Alloys based on tin
    • C22C13/02Alloys based on tin with antimony or bismuth as the next major constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/33Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Mechanical Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
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Description

この発明は、半導体装置および半導体装置の製造方法に関する。 The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.

パワー半導体モジュールは、1つまたは複数のパワー半導体チップを内蔵して変換接続の一部または全体を構成し、かつ、パワー半導体チップと積層基板または金属基板との間が電気的に絶縁された構造を持つパワー半導体デバイスである。パワー半導体モジュールは、産業用途としてエレベータなどのモータ駆動制御インバータなどに使われている。さらに近年では、車載用モータ駆動制御インバータに広く用いられるようになっている。車載用インバータでは、燃費向上のため小型・軽量化や、エンジンルーム内の駆動用モータ近傍に配置されることから、高温動作での長期信頼性が求められる。 A power semiconductor module has a structure in which one or more power semiconductor chips are incorporated to form a part or the whole of a conversion connection, and the power semiconductor chip is electrically insulated from a laminated substrate or a metal substrate. It is a power semiconductor device with. Power semiconductor modules are used in motor drive control inverters such as elevators for industrial purposes. Furthermore, in recent years, it has come to be widely used in in-vehicle motor drive control inverters. In-vehicle inverters are required to be compact and lightweight in order to improve fuel efficiency, and to be placed near the drive motor in the engine room, so that long-term reliability in high-temperature operation is required.

従来のパワー半導体モジュールの構造を、一般的なIGBT(Insulated Gate Bipolar Transistor)パワー半導体モジュール構造を例にとって説明する。 The structure of a conventional power semiconductor module will be described by taking a general IGBT (Insulated Gate Bipolar Transistor) power semiconductor module structure as an example.

図9は、従来構造のパワー半導体モジュールの構成を示す断面図である。図9に示すように、パワー半導体モジュールは、パワー半導体チップ1と、絶縁基板2と、電極パターン3と、絶縁基板2の裏面に配置される導電性板9、はんだ材14と、放熱板5と、冷却体7と、金属ワイヤ10と、外部端子11と、端子ケース12と、封止材料13と、を備える。 FIG. 9 is a cross-sectional view showing the configuration of a power semiconductor module having a conventional structure. As shown in FIG. 9, the power semiconductor module includes a power semiconductor chip 1, an insulating substrate 2, an electrode pattern 3, a conductive plate 9, a solder material 14, and a heat radiating plate 5 arranged on the back surface of the insulating substrate 2. A cooling body 7, a metal wire 10, an external terminal 11, a terminal case 12, and a sealing material 13.

パワー半導体チップ1は、IGBTあるいはダイオードチップ等の半導体素子である。絶縁基板2の両面には、電極パターン3と導電性板9が設けられている。電極パターン3上には、接合材であるはんだ材14にてパワー半導体チップ1が接合される。裏面の導電性板9上には、はんだ材14にて放熱板5が接合される。放熱板5は、放熱グリス6を介して放熱フィンが設けられた冷却体7に接合される。なお、絶縁基板2の少なくとも片面に電極パターン3が設けられた基板を積層基板という。また、パワー半導体チップ1の上面には、電気接続用の配線として金属ワイヤ10が電極パターン3との間を接続している。電極パターン3の上面には、外部接続用の金属外部端子11が設けられている。また、パワー半導体チップ1の絶縁保護のため、端子ケース12内には低弾性率のシリコンゲル等の封止材料13が充填され、蓋(不図示)にてパッケージされている。 The power semiconductor chip 1 is a semiconductor element such as an IGBT or a diode chip. An electrode pattern 3 and a conductive plate 9 are provided on both sides of the insulating substrate 2. The power semiconductor chip 1 is bonded onto the electrode pattern 3 with a solder material 14 which is a bonding material. A heat radiating plate 5 is bonded to the conductive plate 9 on the back surface with a solder material 14. The heat radiating plate 5 is joined to the cooling body 7 provided with the heat radiating fins via the heat radiating grease 6. A substrate provided with an electrode pattern 3 on at least one surface of the insulating substrate 2 is referred to as a laminated substrate. Further, on the upper surface of the power semiconductor chip 1, a metal wire 10 is connected to the electrode pattern 3 as wiring for electrical connection. A metal external terminal 11 for external connection is provided on the upper surface of the electrode pattern 3. Further, in order to protect the insulation of the power semiconductor chip 1, the terminal case 12 is filled with a sealing material 13 such as silicon gel having a low elastic modulus, and is packaged with a lid (not shown).

ここで、車載用パワー半導体モジュールは、産業用パワー半導体モジュールに比べ、設置空間の制約から小型、軽量化が求められる。また、モータを駆動するための出力パワー密度が高くなるため、運転時における半導体チップ温度が高くなるとともに、高温動作時の長期信頼性の要求も高まってきている。このため、高温動作・長期信頼性を有したパワー半導体モジュール構造が要求されてきている。 Here, the in-vehicle power semiconductor module is required to be smaller and lighter than the industrial power semiconductor module due to the limitation of the installation space. Further, since the output power density for driving the motor becomes high, the temperature of the semiconductor chip during operation becomes high, and the demand for long-term reliability during high temperature operation is also increasing. Therefore, there is a demand for a power semiconductor module structure having high temperature operation and long-term reliability.

上記構成のパワー半導体モジュールは、放熱フィンが設けられた冷却体7が取り付けられ、通電に伴うパワー半導体チップ1の発生熱を放熱フィンに伝熱させて系外に放熱するようにしている。冷却体7の表面と放熱板5の表面との間が密着していないと両者間の接触熱抵抗が増して放熱性が低下する。 In the power semiconductor module having the above configuration, a cooling body 7 provided with heat dissipation fins is attached, and the heat generated by the power semiconductor chip 1 accompanying energization is transferred to the heat dissipation fins to dissipate heat to the outside of the system. If the surface of the cooling body 7 and the surface of the heat radiating plate 5 are not in close contact with each other, the contact thermal resistance between the two increases and the heat radiating property deteriorates.

そこで、従来の半導体装置では、高い放熱性能を確保するために放熱板5および冷却体7の表面平坦度、表面粗さができるだけ小さくなるように仕上げ、さらに冷却体7の表面に放熱グリス6等のサーマルコンパウンドを塗布するなどして放熱板5と冷却体7間の接触熱抵抗を低く抑えるようにしている。 Therefore, in the conventional semiconductor device, in order to ensure high heat dissipation performance, the surface flatness and surface roughness of the heat sink 5 and the cooling body 7 are finished so as to be as small as possible, and further, the heat radiation grease 6 or the like is formed on the surface of the cooling body 7. The thermal resistance between the heat radiating plate 5 and the cooling body 7 is kept low by applying the thermal compound of.

また、パワー半導体チップ1と電極パターン3との間、および、導電性板9と放熱板5との間を、はんだ材14を用いて接合している。例えば、パワー半導体チップ1の下の接合には、Pb(鉛)フリーはんだを、フラックス含有したペーストはんだ、または、板はんだで接合している。 Further, the power semiconductor chip 1 and the electrode pattern 3 and the conductive plate 9 and the heat radiating plate 5 are joined by using a solder material 14. For example, Pb (lead) -free solder is bonded under the power semiconductor chip 1 with flux-containing paste solder or plate solder.

半導体モジュールに用いるPbフリーはんだとして、半導体チップのダイボンドなどの温度階層接続に用いられる、Cu(銅)からなる金属網が2枚のはんだ箔によって挟まれて圧着された構成からなる複合はんだがある(例えば、特許文献1参照。)。 As Pb-free solder used for semiconductor modules, there is a composite solder having a structure in which a metal mesh made of Cu (copper), which is used for temperature layer connection such as die bonding of semiconductor chips, is sandwiched between two solder foils and crimped. (See, for example, Patent Document 1.).

特開2004-174522号公報Japanese Unexamined Patent Publication No. 2004-174522

ここで、パワー半導体チップ1の下の接合に用いられるはんだ材14の熱伝導率は40~60W/m・Kである。この値は、銅の熱伝導率390W/m・Kと比較すると低い値である。このため、通電に伴うパワー半導体チップ1の発生熱を電極パターン3に十分伝熱できず、発生熱が放熱フィンに到達できないため、パワー半導体チップ1を十分に冷却することができないという課題がある。また、はんだ材14の熱伝導率が低いため、はんだ材14自身の温度が上昇し、はんだ材14中にクラックが発生して熱抵抗が上昇し、放熱性能がさらに低下するという課題がある。 Here, the thermal conductivity of the solder material 14 used for bonding under the power semiconductor chip 1 is 40 to 60 W / m · K. This value is lower than the thermal conductivity of copper of 390 W / m · K. Therefore, there is a problem that the heat generated by the power semiconductor chip 1 due to energization cannot be sufficiently transferred to the electrode pattern 3 and the generated heat cannot reach the heat radiation fins, so that the power semiconductor chip 1 cannot be sufficiently cooled. .. Further, since the thermal conductivity of the solder material 14 is low, there is a problem that the temperature of the solder material 14 itself rises, cracks occur in the solder material 14, the thermal resistance rises, and the heat dissipation performance further deteriorates.

この発明は、上述した従来技術による問題点を解消するため、パワー半導体チップの発生熱を効率よく放熱でき、はんだにクラックが発生して熱抵抗が上昇することを抑制できる半導体装置および半導体装置の製造方法を提供することを目的とする。 INDUSTRIAL APPLICABILITY The present invention solves the above-mentioned problems caused by the prior art, and thus can efficiently dissipate the heat generated by the power semiconductor chip, and suppress the generation of cracks in the solder and the increase in thermal resistance of the semiconductor device and the semiconductor device. The purpose is to provide a manufacturing method.

上述した課題を解決し、本発明の目的を達成するため、この発明にかかる半導体装置は、次の特徴を有する。半導体装置は、半導体素子を積層基板に搭載した組立構造を有する。前記半導体素子と前記積層基板上の電極パターンとを接合する接合層は、金属繊維を含み、前記金属繊維間がはんだで充填されているはんだ材が使用される。前記はんだは、Sn-Bi系はんだに、Ni、Coを入れたSn-(40~70)Bi-(0.1~1)Ni、Coのはんだである。
In order to solve the above-mentioned problems and achieve the object of the present invention, the semiconductor device according to the present invention has the following features. The semiconductor device has an assembly structure in which a semiconductor element is mounted on a laminated substrate. The bonding layer that joins the semiconductor element and the electrode pattern on the laminated substrate contains metal fibers, and a solder material in which the metal fibers are filled with solder is used . The solder is a Sn- (40 to 70) Bi- (0.1 to 1) Ni, Co solder obtained by adding Ni and Co to a Sn—Bi type solder .

また、この発明にかかる半導体装置は、上述した発明において、前記半導体素子と、前記半導体素子と前記積層基板上の電極パターンとの電気接続用の配線とを接合する接合層は、前記はんだ材が使用されることを特徴とする。 Further, in the semiconductor device according to the present invention, in the above-described invention, the solder material is used as the bonding layer for bonding the semiconductor element and the wiring for electrical connection between the semiconductor element and the electrode pattern on the laminated substrate. It is characterized by being used.

また、この発明にかかる半導体装置は、上述した発明において、前記組立構造は、前記積層基板を搭載した放熱板をさらに有し、前記積層基板と前記放熱板とを接合する接合層は、前記はんだ材が使用されることを特徴とする。 Further, in the semiconductor device according to the present invention, in the above-described invention, the assembled structure further has a heat radiating plate on which the laminated substrate is mounted, and the bonding layer for joining the laminated substrate and the heat radiating plate is the solder. It is characterized in that the material is used.

また、この発明にかかる半導体装置は、上述した発明において、前記接合層では、前記はんだ材に含まれる前記金属繊維は中央部に配置され、前記接合層の端部から、前記電極パターンの表面と平行な方向に所定の距離の間、前記金属繊維が配置されないことを特徴とする。
Further, in the above-described invention, in the semiconductor device according to the present invention, in the bonding layer, the metal fiber contained in the solder material is arranged in the central portion, and from the end portion of the bonding layer to the surface of the electrode pattern. It is characterized in that the metal fibers are not arranged for a predetermined distance in a parallel direction .

また、この発明にかかる半導体装置は、上述した発明において、前記所定の距離は、0.1mm以上1mm以下であることを特徴とする。 Further, the semiconductor device according to the present invention is characterized in that, in the above-described invention, the predetermined distance is 0.1 mm or more and 1 mm or less.

また、この発明にかかる半導体装置は、上述した発明において、前記接合層では、前記はんだ材に含まれる前記金属繊維は、前記半導体素子、前記積層基板および前記放熱板側に配置され、前記金属繊維間に、所定の厚さのはんだが配置されることを特徴とする。 Further, in the above-described invention, in the semiconductor device according to the present invention, in the bonding layer, the metal fibers contained in the solder material are arranged on the semiconductor element, the laminated substrate and the heat radiation plate side, and the metal fibers are arranged. It is characterized in that solder of a predetermined thickness is arranged between them.

また、この発明にかかる半導体装置は、上述した発明において、前記所定の厚さは、5μm以上20μm以下であることを特徴とする。 Further, the semiconductor device according to the present invention is characterized in that, in the above-mentioned invention, the predetermined thickness is 5 μm or more and 20 μm or less.

また、この発明にかかる半導体装置は、上述した発明において、前記所定の厚さは、前記はんだ材の厚さの5%から20%であることを特徴とする。 Further, the semiconductor device according to the present invention is characterized in that, in the above-described invention, the predetermined thickness is 5% to 20% of the thickness of the solder material.

また、この発明にかかる半導体装置は、上述した発明において、前記はんだは銅を含まないことを特徴とする。 Further, the semiconductor device according to the present invention is characterized in that, in the above-mentioned invention, the solder does not contain copper.

また、この発明にかかる半導体装置は、上述した発明において、前記金属繊維は、Coめっきがされていることを特徴とする。 Further, the semiconductor device according to the present invention is characterized in that, in the above-mentioned invention, the metal fiber is Co-plated.

上述した課題を解決し、本発明の目的を達成するため、この発明にかかる半導体装置の製造方法は、次の特徴を有する。まず、金属繊維を含み、前記金属繊維間がはんだで充填されているはんだ材を用いて、積層基板上の電極パターンと半導体素子とを接合して、前記積層基板に前記半導体素子を搭載する工程を行う。前記積層基板を積層組立体に組み立てる工程を行う。次に、前記半導体素子と、前記積層基板上の電極パターンとを、電気的に接続する工程を行う。次に、前記積層組立体に、樹脂ケースを組み合わせる工程を行う。前記はんだは、Sn-Bi系はんだに、Ni、Coを入れたSn-(40~70)Bi-(0.1~1)Ni、Coのはんだである。 In order to solve the above-mentioned problems and achieve the object of the present invention, the method for manufacturing a semiconductor device according to the present invention has the following features. First, a step of joining an electrode pattern on a laminated substrate and a semiconductor element using a solder material containing metal fibers and having the metal fibers filled with solder, and mounting the semiconductor element on the laminated substrate. I do. A step of assembling the laminated substrate into a laminated assembly is performed. Next, a step of electrically connecting the semiconductor element and the electrode pattern on the laminated substrate is performed. Next, a step of combining the resin case with the laminated assembly is performed. The solder is a Sn- (40 to 70) Bi- (0.1 to 1) Ni, Co solder obtained by adding Ni and Co to a Sn—Bi type solder .

また、この発明にかかる半導体装置の製造方法は、上述した発明において、前記電気的に接続する工程では、前記はんだ材を用いて、前記半導体素子と、前記積層基板上の電極パターンとを、電気的に接続することを特徴とする。 Further, in the method for manufacturing a semiconductor device according to the present invention, in the above-described invention, in the step of electrically connecting, the semiconductor element and the electrode pattern on the laminated substrate are electrically connected by using the solder material. It is characterized by connecting in a targeted manner.

また、この発明にかかる半導体装置の製造方法は、上述した発明において、前記組み立てる工程では、前記積層基板を、前記はんだ材を用いて、前記積層組立体の放熱板に接合することを特徴とする。 Further, the method for manufacturing a semiconductor device according to the present invention is characterized in that, in the above-described invention, the laminated substrate is joined to the heat sink of the laminated assembly by using the solder material in the assembling step. ..

上述した発明によれば、パワー半導体素子と電極パターンとを接合する接合部は、銅繊維を含み、銅繊維間がはんだで充填されている銅繊維含有はんだ材である。これにより、熱伝導率が、フラックスを含有したペーストはんだや板はんだより向上するため、パワー半導体チップの発生熱を効率よく放熱できる。また、はんだの中に銅繊維が含まれているため、はんだ中にクラックが発生しても、クラックが迂回して進展するため、はんだの寿命が向上する。さらに、はんだの中に銅繊維が含まれているため、フィレットが発生することを防止でき、はんだが脇にはみ出ることが少なくなる。また、銅繊維が互いに接点を有し熱パスを形成しているため、はんだにクラックが発生しても熱抵抗の上昇を抑制できる。また、銅繊維部材に、はんだをしみこませて板はんだとすることで、従来と同様の取り扱いができ、従来よりもはんだ厚さを均一に制御することが可能になる。 According to the above-mentioned invention, the joint portion for joining the power semiconductor element and the electrode pattern is a copper fiber-containing solder material containing copper fibers and the copper fibers are filled with solder. As a result, the thermal conductivity is improved as compared with the paste solder and the plate solder containing flux, so that the heat generated by the power semiconductor chip can be efficiently dissipated. Further, since copper fibers are contained in the solder, even if cracks occur in the solder, the cracks bypass and propagate, so that the life of the solder is improved. Further, since the copper fiber is contained in the solder, it is possible to prevent the fillet from being generated, and the solder is less likely to protrude to the side. Further, since the copper fibers have contacts with each other and form a thermal path, it is possible to suppress an increase in thermal resistance even if cracks occur in the solder. Further, by impregnating the copper fiber member with solder to form a plate solder, the same handling as in the conventional case can be achieved, and the solder thickness can be controlled more uniformly than in the conventional case.

本発明にかかる半導体装置および半導体装置の製造方法によれば、パワー半導体チップの発生熱を効率よく放熱でき、はんだにクラックが発生して熱抵抗が上昇することを抑制できるという効果を奏する。 According to the semiconductor device and the method for manufacturing the semiconductor device according to the present invention, it is possible to efficiently dissipate the heat generated by the power semiconductor chip, and to suppress the generation of cracks in the solder and the increase in thermal resistance.

図1は、実施の形態にかかるパワー半導体モジュールの構成を示す断面図である。FIG. 1 is a cross-sectional view showing the configuration of a power semiconductor module according to an embodiment. 図2は、パワー半導体チップと電極パターンを接合するはんだ材の詳細を示す断面図である(その1)。FIG. 2 is a cross-sectional view showing details of a solder material for joining a power semiconductor chip and an electrode pattern (No. 1). 図3は、パワー半導体チップと電極パターンを接合するはんだ材の詳細を示す断面図である(その2)。FIG. 3 is a cross-sectional view showing details of a solder material for joining a power semiconductor chip and an electrode pattern (No. 2). 図4は、実施の形態にかかるはんだのパワーサイクル試験の結果を示す表である。FIG. 4 is a table showing the results of the power cycle test of the solder according to the embodiment. 図5は、はんだ厚と等価熱伝導率との関係を示すグラフである。FIG. 5 is a graph showing the relationship between the solder thickness and the equivalent thermal conductivity. 図6は、銅占有率と等価熱伝導率との関係を示すグラフである。FIG. 6 is a graph showing the relationship between the copper occupancy and the equivalent thermal conductivity. 図7は、銅繊維含有はんだ材の実施例を示す断面図である。FIG. 7 is a cross-sectional view showing an example of a copper fiber-containing solder material. 図8は、銅繊維含有はんだ材の実施例の接合部の断面図である。FIG. 8 is a cross-sectional view of the joint portion of the example of the copper fiber-containing solder material. 図9は、従来構造のパワー半導体モジュールの構成を示す断面図である。FIG. 9 is a cross-sectional view showing the configuration of a power semiconductor module having a conventional structure.

以下に添付図面を参照して、この発明にかかる半導体装置および半導体装置の製造方法の好適な実施の形態を詳細に説明する。図1は、実施の形態にかかるパワー半導体モジュールの構成を示す断面図である。 Hereinafter, preferred embodiments of the semiconductor device and the method for manufacturing the semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings. FIG. 1 is a cross-sectional view showing the configuration of a power semiconductor module according to an embodiment.

(実施の形態)
図1に示すように、パワー半導体モジュールは、パワー半導体チップ1と、絶縁基板2と、電極パターン3と、接合部4と、放熱板5と、リードフレーム配線8と、絶縁基板2の裏面に配置される導電性板9、を備える。ここでは、従来構造のパワー半導体モジュールと同様のため、冷却体7、外部端子11、端子ケース12、封止材料13等の記載は省略する。図1では、リードフレーム配線8を用いて、パワー半導体チップ1と電極パターン3とを接続しているが、従来構造と同様に金属ワイヤ10を用いて接続してもよい。
(Embodiment)
As shown in FIG. 1, the power semiconductor module is provided on the power semiconductor chip 1, the insulating substrate 2, the electrode pattern 3, the joint portion 4, the heat sink 5, the lead frame wiring 8, and the back surface of the insulating substrate 2. A conductive plate 9 to be arranged is provided. Here, since it is the same as the power semiconductor module having the conventional structure, the description of the cooling body 7, the external terminal 11, the terminal case 12, the sealing material 13, and the like is omitted. In FIG. 1, the power semiconductor chip 1 and the electrode pattern 3 are connected by using the lead frame wiring 8, but the metal wire 10 may be used to connect the power semiconductor chip 1 and the electrode pattern 3 as in the conventional structure.

パワー半導体チップ1は、IGBTあるいはダイオードチップ等の半導体素子である。絶縁性を確保するセラミック基板等の絶縁基板2のおもて面(パワー半導体チップ1側)および裏面(放熱板5側)には、銅(Cu)等の導電性の板などからなる電極パターン3等が設けられている。なお、絶縁基板2の少なくとも片面に電極パターン3が設けられた基板を積層基板とする。電極パターン3上には、接合部4にてパワー半導体チップ1が接合される。裏面の導電性板9上には、接合部4にて放熱板5が接合される。放熱板5は、放熱フィンが設けられた冷却体(不図示)に接合される。なお、積層基板のおもて面の銅などの導電性板を電極パターンといい、裏面の銅等の導電性板を導電性板という。また、パワー半導体チップ1の上面(接合部4と接する面と反対側の面)には、電気接続用の配線としてリードフレーム配線8の一端が接合部4にて接合される。リードフレーム配線8の他端は、電極パターン3と接合される。また、上述の箇所以外においても、従来の半導体モジュールにおいてはんだ材が用いられる箇所において、本発明の接合部は用いられる。 The power semiconductor chip 1 is a semiconductor element such as an IGBT or a diode chip. An electrode pattern made of a conductive plate such as copper (Cu) on the front surface (power semiconductor chip 1 side) and back surface (heat sink 5 side) of an insulating substrate 2 such as a ceramic substrate that ensures insulation. 3 etc. are provided. A substrate provided with an electrode pattern 3 on at least one surface of the insulating substrate 2 is used as a laminated substrate. The power semiconductor chip 1 is bonded to the electrode pattern 3 at the bonding portion 4. A heat sink 5 is joined to the conductive plate 9 on the back surface at the joint portion 4. The heat radiating plate 5 is joined to a cooling body (not shown) provided with radiating fins. The conductive plate such as copper on the front surface of the laminated substrate is called an electrode pattern, and the conductive plate such as copper on the back surface is called a conductive plate. Further, one end of the lead frame wiring 8 is joined at the joint portion 4 as wiring for electrical connection to the upper surface of the power semiconductor chip 1 (the surface opposite to the surface in contact with the joint portion 4). The other end of the lead frame wiring 8 is joined to the electrode pattern 3. In addition to the above-mentioned locations, the joint portion of the present invention is used in locations where solder materials are used in conventional semiconductor modules.

接合部4は、金属繊維部材を含んだ金属繊維含有はんだ材により形成される。金属繊維含有はんだ材は、繊維状の金属(以下、金属繊維と称する)を含み、その金属繊維が互いに接点を有し熱パスを形成し、さらに、金属繊維間がはんだで充填されている。金属としては、熱伝導率の高い金属、例えば銅であることが好ましい。以下、繊維状の銅を銅繊維と称し、接合部4を銅繊維含有はんだ材4と称する。以降は銅繊維について説明する。なお、ここで、繊維状とは、細長い形状、つまり直径に対して長さがきわめて大きいものをいう。実施の形態では、1本の銅繊維の直径が20μm以下であることが好ましい。また、銅繊維の長さは50μm以上が好ましく、1mm以上がより好ましい。前記長さであると、銅繊維間の接触がより多くなり、3次元的な構造になり易いからである。また、長さは銅繊維部材の長さ程度である10mm以下であることが好ましい。 The joint portion 4 is formed of a metal fiber-containing solder material including a metal fiber member. The metal fiber-containing solder material contains a fibrous metal (hereinafter referred to as metal fiber), and the metal fibers have contacts with each other to form a heat path, and the metal fibers are filled with solder. The metal is preferably a metal having high thermal conductivity, for example, copper. Hereinafter, the fibrous copper is referred to as a copper fiber, and the joint portion 4 is referred to as a copper fiber-containing solder material 4. Hereinafter, copper fibers will be described. Here, the fibrous form means an elongated shape, that is, a shape having an extremely large length with respect to the diameter. In the embodiment, the diameter of one copper fiber is preferably 20 μm or less. The length of the copper fiber is preferably 50 μm or more, more preferably 1 mm or more. This is because the length makes more contact between the copper fibers and tends to form a three-dimensional structure. Further, the length is preferably 10 mm or less, which is about the length of the copper fiber member.

また、接点とは、銅繊維含有はんだ材4の銅繊維が、他の銅繊維と接触している点のことである。銅繊維部材は、複数の銅繊維により形成される。銅繊維部材は、織物のように銅繊維が織られた布状でもよく、網状またはメッシュ状に形成されても良い。これらの、布状または網状の銅繊維が複数枚積層されてもよい。また、複数の繊維がランダムに集積され積層されてシート状に形成されていてもよい。さらに、積層されたシート状を加圧し、銅繊維同士を圧着してもよい。また、これらはシート状に成形されていることが好ましい。シート状の銅繊維部材の厚さは、50μmから200μmが好ましい。50μmより厚くすると所定の接合強度を得られるためである。また、200μm以上にすると熱抵抗自体が増加するとともに、ボイドが発生し、熱伝導率が低下し、熱抵抗を増加させてしまう。なお、銅繊維間は、はんだで充填するのではなく、銀(Ag)またはCuの焼結材で充填してもよい。 Further, the contact point is a point where the copper fiber of the copper fiber-containing solder material 4 is in contact with another copper fiber. The copper fiber member is formed of a plurality of copper fibers. The copper fiber member may be in the form of a cloth in which copper fibers are woven like a woven fabric, or may be formed in the form of a mesh or a mesh. A plurality of these cloth-like or net-like copper fibers may be laminated. Further, a plurality of fibers may be randomly accumulated and laminated to form a sheet. Further, the laminated sheet shape may be pressed and the copper fibers may be pressure-bonded to each other. Further, it is preferable that these are formed into a sheet shape. The thickness of the sheet-shaped copper fiber member is preferably 50 μm to 200 μm. This is because a predetermined bonding strength can be obtained when the thickness is thicker than 50 μm. Further, when the thickness is 200 μm or more, the thermal resistance itself increases, voids are generated, the thermal conductivity decreases, and the thermal resistance increases. The copper fibers may be filled with a sintered material of silver (Ag) or Cu instead of filling with solder.

このように、実施の形態の銅繊維含有はんだ材4は、互いに接点を有し熱パスを形成した銅繊維を含み、球状の銅を含んだはんだ材とは異なる。なお、熱パスとは、パワー半導体チップ等の発生熱を伝熱するための経路である。球状の銅を含んだはんだ材は、銅繊維に比べて熱パスが少なく、熱抵抗は大きく、接合強度もはんだ自体と変わらない。なお、単に板状あるいは箔状の銅などの金属をはんだ中に配置しても、銅繊維部材含有はんだのような接合強度や熱伝導率は得られない。銅板等をはんだ中に配置しても、所定の接合強度を得るためには、はんだ層自体の厚さは変わらないからである。つまり、熱抵抗は変わらない。3次元的な銅繊維間にはんだが含浸することにより、熱抵抗は低下し、さらに接合強度も向上することができる。 As described above, the copper fiber-containing solder material 4 of the embodiment contains copper fibers having contacts with each other and forming a heat path, and is different from the solder material containing spherical copper. The heat path is a path for transferring heat generated by a power semiconductor chip or the like. Solder materials containing spherical copper have fewer heat paths than copper fibers, have higher thermal resistance, and have the same bonding strength as the solder itself. Even if a plate-shaped or foil-shaped metal such as copper is simply placed in the solder, the bonding strength and thermal conductivity unlike those of the copper fiber member-containing solder cannot be obtained. This is because even if a copper plate or the like is placed in the solder, the thickness of the solder layer itself does not change in order to obtain a predetermined bonding strength. That is, the thermal resistance does not change. By impregnating the solder between the three-dimensional copper fibers, the thermal resistance can be lowered and the bonding strength can be further improved.

銅繊維含有はんだ材4は、銅繊維を織り込み、焼結させて繊維間が互いに接点を有するよう折り重ねられている銅繊維部材を形成し、銅繊維部材に、はんだをしみこませて形成したはんだ材でもよい。予め、はんだをしみこませることで、板はんだとして取り扱うことができる。具体的には、予め、銅繊維部材にはんだを含浸させた銅繊維含有はんだを形成し、それを被接合材間に配置し、加熱し接合することができる。また、半導体モジュールを組み立てる際に、はんだと銅繊維部材を被接合材の間に配置して、加熱し接合してもよい。ここで、銅繊維は2層以上折り重ねられていることが好ましい。2層以上折り重ねられているとは、厚み方向(パワー半導体チップ1から放熱板5への方向)に互いに接点を有する銅繊維が2本以上存在することである。図1の例では、銅繊維は3層に折り重ねられている。ここで、銅が繊維状で折り重なっているために、メッシュ状に加工したものより、銅占有率が高く、例えば、銅繊維含有はんだ材4では、はんだと銅繊維部材の総量に対して、銅繊維部材の銅占有率は22~30重量%である。銅繊維部材の銅占有率は高い方が熱伝導性が優れるが、はんだの含浸量が少ないと接合性が悪くなる。従って、様々な形態の銅繊維部材の銅占有率は5~50重量%が好ましく、更に好ましくは、20~30重量%である。 The copper fiber-containing solder material 4 is a solder formed by weaving copper fibers and sintering them to form a copper fiber member that is folded so that the fibers have contacts with each other, and the copper fiber member is impregnated with solder. It may be made of wood. By soaking the solder in advance, it can be handled as plate solder. Specifically, it is possible to form a copper fiber-containing solder in which a copper fiber member is impregnated with solder in advance, arrange the solder fiber-containing solder between the materials to be joined, and heat and join the solder. Further, when assembling the semiconductor module, the solder and the copper fiber member may be arranged between the materials to be joined and heated to be joined. Here, it is preferable that two or more layers of copper fibers are folded. Folding two or more layers means that there are two or more copper fibers having contacts with each other in the thickness direction (direction from the power semiconductor chip 1 to the heat sink 5). In the example of FIG. 1, the copper fiber is folded into three layers. Here, since the copper is fibrous and folded, the copper occupancy rate is higher than that of the one processed into a mesh shape. For example, in the copper fiber-containing solder material 4, copper is used with respect to the total amount of solder and copper fiber members. The copper occupancy of the fiber member is 22 to 30% by weight. The higher the copper occupancy of the copper fiber member, the better the thermal conductivity, but the smaller the amount of solder impregnated, the worse the bondability. Therefore, the copper occupancy of various forms of copper fiber members is preferably 5 to 50% by weight, more preferably 20 to 30% by weight.

このように、銅繊維部材がはんだ中に配置されることにより、銅繊維含有はんだ材4の熱伝導率は向上し、発生熱を効率よく放熱することができる。また、はんだの中に銅繊維が含まれているため、はんだ中にクラックが発生しても、クラックが迂回して進展するため、接合強度は向上する。また、銅繊維自体に強度があるため、接合強度は高い。ひいては、はんだの寿命が向上する。また、上記のシート状の銅繊維部材を用いることにより、銅繊維含有はんだ材4の厚さを均一にすることができる。従来のはんだ材のみの接合の場合、パワー半導体チップ1をはんだ材上に配置する際に位置ずれをおこしたり、加熱接合時にはんだ材が流れてしまったりし、はんだ材1014の厚さを均一にすることが難しかった。しかし、銅繊維部材を導入することで、上記の不具合が解消され、銅繊維含有はんだ材4の厚さを均一にすることができる。 By arranging the copper fiber member in the solder in this way, the thermal conductivity of the copper fiber-containing solder material 4 is improved, and the generated heat can be efficiently dissipated. Further, since copper fibers are contained in the solder, even if cracks occur in the solder, the cracks bypass and propagate, so that the bonding strength is improved. Moreover, since the copper fiber itself has strength, the bonding strength is high. As a result, the life of the solder is improved. Further, by using the above-mentioned sheet-shaped copper fiber member, the thickness of the copper fiber-containing solder material 4 can be made uniform. In the case of conventional soldering only, the power semiconductor chip 1 may be misaligned when placed on the soldering material, or the soldering material may flow during heat bonding, making the thickness of the soldering material 1014 uniform. It was difficult to do. However, by introducing the copper fiber member, the above-mentioned problems can be solved and the thickness of the copper fiber-containing solder material 4 can be made uniform.

また、銅繊維含有はんだ材4は、パワー半導体チップ1の発生熱を効率よく拡散するために、パワー半導体チップ1の下、つまり、パワー半導体チップ1と電極パターン3との接合層に使用することが好ましい。また、銅繊維含有はんだ材4は、導電性板9と放熱板5との接合層、パワー半導体チップ1とリードフレーム配線8との接合層に使用してもよい。 Further, the copper fiber-containing solder material 4 is used under the power semiconductor chip 1, that is, in the bonding layer between the power semiconductor chip 1 and the electrode pattern 3 in order to efficiently diffuse the heat generated by the power semiconductor chip 1. Is preferable. Further, the copper fiber-containing solder material 4 may be used as a bonding layer between the conductive plate 9 and the heat radiating plate 5, and as a bonding layer between the power semiconductor chip 1 and the lead frame wiring 8.

パワー半導体モジュールの製造方法では、まず、銅繊維含有はんだ材4を用いて、パワー半導体チップ1を積層基板に接合することで、積層基板にパワー半導体チップ1を実装する。ここで、銅繊維含有はんだ材4は、パワー半導体モジュールの製造より前に、銅繊維部材に、はんだをしみこませて作成しておいてもよい。また、パワー半導体チップ1を積層基板に接合する際、銅繊維部材とはんだを重ねて、例えば、銅繊維部材をはんだで挟むようにして、銅繊維含有はんだ材4を作成するようにしてもよい。 In the method for manufacturing a power semiconductor module, first, the power semiconductor chip 1 is mounted on the laminated substrate by joining the power semiconductor chip 1 to the laminated substrate by using the copper fiber-containing solder material 4. Here, the copper fiber-containing solder material 4 may be produced by impregnating the copper fiber member with solder before manufacturing the power semiconductor module. Further, when the power semiconductor chip 1 is bonded to the laminated substrate, the copper fiber member and the solder may be overlapped with each other, for example, the copper fiber member may be sandwiched between the solders to prepare the copper fiber-containing solder material 4.

次に、パワー半導体チップ1と、絶縁基板2上に設けられた電極パターン3とを、リードフレーム配線8で電気的に接続する。次に、銅繊維含有はんだ材4を用いて、これらを放熱板5に接合して、パワー半導体チップ1、積層基板および放熱板5からなる積層組立体を組み立てる。この積層組立体に樹脂ケースをシリコンなどの接着剤で接着する。なお、金属ワイヤで、パワー半導体チップ1と、絶縁基板2上に設けられた電極パターン3と、を電気的に接続してもよい。 Next, the power semiconductor chip 1 and the electrode pattern 3 provided on the insulating substrate 2 are electrically connected by the lead frame wiring 8. Next, using the copper fiber-containing solder material 4, these are joined to the heat sink 5, and a laminated assembly including the power semiconductor chip 1, the laminated substrate, and the heat sink 5 is assembled. The resin case is adhered to this laminated assembly with an adhesive such as silicon. The power semiconductor chip 1 and the electrode pattern 3 provided on the insulating substrate 2 may be electrically connected by a metal wire.

次に、金属ワイヤで電極パターン3と金属外部端子11との間を接続し、樹脂ケース内にエポキシなどの硬質樹脂等の封止材料を充填する。これにより、図1に示す実施の形態にかかるパワー半導体モジュールが完成する。なお、封止材料がエポキシ樹脂等の封止材料でない場合、封止材料が外に漏れないようにするため、蓋を取り付けるようにする。 Next, the electrode pattern 3 and the metal external terminal 11 are connected with a metal wire, and the resin case is filled with a sealing material such as a hard resin such as epoxy. As a result, the power semiconductor module according to the embodiment shown in FIG. 1 is completed. If the sealing material is not a sealing material such as epoxy resin, a lid is attached to prevent the sealing material from leaking to the outside.

次に、銅繊維含有はんだ材4について説明する。パワー半導体チップの裏面のほぼ全面に銅繊維含有はんだ材4が配置される。図2、図3は、パワー半導体チップと電極パターンを接合するはんだ材の詳細を示す断面図である。図2に示すように、銅繊維含有はんだ材4の内部に銅繊維部材20を中央部に配置される。また、銅繊維を含まないはんだ23をパワー半導体チップ1や電極パターン3側に配置してもよい。この場合のそれぞれのはんだ23の厚さは、25μmから100μmが好ましい。この範囲にすることで、接合強度とボイドの低減を両立できるからである。これは、パワー半導体チップ1の発生熱が、銅繊維部材20が配置された中央部から放熱されるためである。ここで、銅繊維部材20を銅繊維含有はんだ材4の端部から所定の距離dだけ離すことで、ボイドを低減し、接合性も向上させることができる。銅繊維部材20は銅繊維が複雑に折れ曲がり、互いに交差した構造で、空乏が存在する。加熱接合する際に、はんだは、銅繊維部材20中に含浸するが、前記空乏近傍でボイドになりやすい。しかし、所定の距離dだけ離すことで、ボイドが排出されやすく、結果としてボイドが低減されると推定される。距離dは、パワー半導体チップ1のサイズに関係なく、0.1mm以上1mm以下であることが好ましい。より好ましくは。0.2mm以上である。これは、0.1mmより短いと、ボイドが生じ、電極パターン3との接合性が悪化し、制御も困難になるためである。 Next, the copper fiber-containing solder material 4 will be described. The copper fiber-containing solder material 4 is arranged on almost the entire back surface of the power semiconductor chip. 2 and 3 are cross-sectional views showing details of a solder material for joining a power semiconductor chip and an electrode pattern. As shown in FIG. 2, the copper fiber member 20 is arranged in the central portion inside the copper fiber-containing solder material 4. Further, the solder 23 containing no copper fiber may be arranged on the power semiconductor chip 1 or the electrode pattern 3 side. In this case, the thickness of each solder 23 is preferably 25 μm to 100 μm. This is because the bonding strength and the reduction of voids can be achieved at the same time by setting the range within this range. This is because the heat generated by the power semiconductor chip 1 is dissipated from the central portion where the copper fiber member 20 is arranged. Here, by separating the copper fiber member 20 from the end portion of the copper fiber-containing solder material 4 by a predetermined distance d, voids can be reduced and bondability can be improved. The copper fiber member 20 has a structure in which copper fibers are complicatedly bent and intersect with each other, and there is a deficiency. At the time of heat bonding, the solder is impregnated into the copper fiber member 20, but tends to become a void in the vicinity of the void. However, it is presumed that the voids are easily discharged by separating them by a predetermined distance d, and as a result, the voids are reduced. The distance d is preferably 0.1 mm or more and 1 mm or less regardless of the size of the power semiconductor chip 1. More preferably. It is 0.2 mm or more. This is because if it is shorter than 0.1 mm, voids are generated, the bondability with the electrode pattern 3 is deteriorated, and control becomes difficult.

また、図3に示すように、銅繊維含有はんだ材4の内部に銅繊維部材20ではんだ23を挟んで配置してもよい。この場合、銅繊維部材の層の間に所定の厚さtのはんだ23の層がある。この形態では、パワー半導体チップ1や電極パターン3側に銅繊維部材20が配置されるため熱伝導性が向上する。例えば、図3の形態は、はんだ23がパワー半導体チップ1や電極パターン3側に存在する図2の形態よりも熱伝導性が向上する。また、この構造とすることで、銅繊維部材20近傍でボイドが生じにくくなる。中央部の厚さtは、5μm以上20μm以下であることが好ましい。20μm以上だと熱抵抗が増し、5μm以下だとボイドが生じやすいためである。また、厚さtは、銅繊維含有はんだ材4の厚さに対する比率が、5%から20%であることが好ましい。 Further, as shown in FIG. 3, the solder 23 may be sandwiched between the copper fiber members 20 inside the copper fiber-containing solder material 4. In this case, there is a layer of solder 23 having a predetermined thickness t between the layers of the copper fiber member. In this embodiment, the copper fiber member 20 is arranged on the power semiconductor chip 1 and the electrode pattern 3 side, so that the thermal conductivity is improved. For example, in the form of FIG. 3, the thermal conductivity is improved as compared with the form of FIG. 2 in which the solder 23 is present on the power semiconductor chip 1 or the electrode pattern 3 side. Further, with this structure, voids are less likely to occur in the vicinity of the copper fiber member 20. The thickness t of the central portion is preferably 5 μm or more and 20 μm or less. This is because if it is 20 μm or more, the thermal resistance increases, and if it is 5 μm or less, voids are likely to occur. The thickness t is preferably 5% to 20% in proportion to the thickness of the copper fiber-containing solder material 4.

また、銅繊維含有はんだ材のはんだにおいて、特定の組成のはんだを用いることで、接合強度および熱物性の効果を生じさせることができる。例えば、銅繊維含有はんだ材4のはんだでは、銅繊維により伝熱するため、銅繊維の銅および銅合金の拡散を抑制するCuフリーのはんだが好ましい。例えば、銅繊維の銅がスズ(Sn)と合金化して拡散すると伝熱する部分が減少し、熱伝導率が下がるため、銅および銅合金の拡散を抑制できるニッケル(Ni)、コバルト(Co)をはんだに入れることが好ましい。なお、Cuフリーとは、不純物程度以外にCuを含まないということである。 Further, in the solder of the copper fiber-containing solder material, by using the solder having a specific composition, the effects of bonding strength and thermal characteristics can be produced. For example, in the solder of the copper fiber-containing solder material 4, heat is transferred by the copper fibers, so a Cu-free solder that suppresses the diffusion of copper and the copper alloy of the copper fibers is preferable. For example, when copper in a copper fiber alloys with tin (Sn) and diffuses, the heat transfer portion decreases and the thermal conductivity decreases, so that diffusion of copper and copper alloy can be suppressed. Nickel (Ni) and cobalt (Co) Is preferably put in the solder. Note that Cu-free means that Cu is not contained except for impurities.

具体的なはんだの組成として、Sn-Sb(アンチモン)系のはんだにNi、Coを入れたSn-(5~10)Sb-(0.1~1)Ni、Coのはんだ(実施例1)を用いることが好ましい。ここでの単位は、重量%(wt%)である。例えば、実施例1では、Sbは、はんだ中に5~10重量%含まれる。また、Ni、Coは、同様の効果を有するため、Niのみを入れてもよいし、Coのみを入れてもよい。さらに、Ni、Coは、はんだ中に0.2~0.5重量%含まれるのがより好ましい。 As a specific solder composition, Sn- (5 to 10) Sb- (0.1 to 1) Ni and Co solders in which Ni and Co are added to Sn—Sb (antimony) solder (Example 1). It is preferable to use. The unit here is weight% (wt%). For example, in Example 1, Sb is contained in the solder in an amount of 5 to 10% by weight. Further, since Ni and Co have the same effect, only Ni may be added or only Co may be added. Further, it is more preferable that Ni and Co are contained in the solder in an amount of 0.2 to 0.5% by weight.

また、Sn-Bi(ビスマス)系のはんだにNi、Coを入れたSn-(40~70)Bi-(0.1~1)Ni、Coのはんだ(実施例2)を用いることも好ましい。この組成のはんだは、脆いため通常ではパワー半導体チップ1の接合に用いることはできないが、実施の形態のように銅繊維部材と一緒に用いることで十分な強度を持ち、パワー半導体チップ1の接合に用いることができる。また、Ni、Coに関しては、Sn-Sb系のはんだと同様である。 It is also preferable to use Sn- (40 to 70) Bi- (0.1 to 1) Ni and Co solders (Example 2) in which Ni and Co are added to the Sn—Bi (bismuth) type solder. Since the solder having this composition is brittle, it cannot normally be used for joining the power semiconductor chip 1, but it has sufficient strength when used together with a copper fiber member as in the embodiment, and joins the power semiconductor chip 1. Can be used for. Further, Ni and Co are the same as those of Sn—Sb type solder.

また、Sn-Ag(銀)系のはんだにNi、Coを入れたSn-(1~6)Ag-(0.1~1)Ni、Coのはんだ(実施例3)を用いることも好ましい。また、Ni、Coに関しては、Sn-Sb系のはんだと同様である。 It is also preferable to use Sn- (1 to 6) Ag- (0.1 to 1) Ni and Co solders (Example 3) in which Ni and Co are added to Sn-Ag (silver) -based solder. Further, Ni and Co are the same as those of Sn—Sb type solder.

また、上記でははんだにNi、Coを入れることにより、銅繊維の銅および銅合金の拡散を抑制していたが、銅繊維にNiめっきまたはCoめっきをすることにより、同様の効果を得ることができる。 Further, in the above, the diffusion of copper and the copper alloy of the copper fiber was suppressed by adding Ni and Co to the solder, but the same effect can be obtained by plating the copper fiber with Ni or Co. can.

図4は、実施の形態にかかるはんだのパワーサイクル試験の結果を示す表である。上記の実施例1から実施例3のはんだに加え、比較例として、Sn-Sb-Cu-Ni系のはんだも試験した。また、実施例1の場合は、Ni、Coが、はんだ中に0.4重量%含まれる場合も試験した。パワーサイクル試験は、電源のオン/オフを繰り返して、熱抵抗が初期より20%以上上昇した回数を測定した。 FIG. 4 is a table showing the results of the power cycle test of the solder according to the embodiment. In addition to the solders of Examples 1 to 3 above, Sn—Sb—Cu—Ni-based solders were also tested as comparative examples. Further, in the case of Example 1, it was also tested that Ni and Co were contained in the solder in an amount of 0.4% by weight. In the power cycle test, the power was repeatedly turned on and off, and the number of times the thermal resistance increased by 20% or more from the initial stage was measured.

図4に示すように、実施例1から実施例3の場合、電源のオン/オフを10万回以上繰り返しても、熱抵抗が初期より20%以上上昇しなかった。特に、Ni、Coが、はんだ中に0.4重量%含まれる場合は、20万回以上繰り返しても、熱抵抗が初期より20%以上上昇しなかった。これに対して、比較例の場合、5万回以下の繰り返しで熱抵抗が初期より20%以上上昇した。これにより、実施例1から実施例3のはんだを用いることで、接合強度および熱物性の効果を生じさせることがわかった。 As shown in FIG. 4, in the case of Examples 1 to 3, the thermal resistance did not increase by 20% or more from the initial stage even when the power was turned on / off 100,000 times or more. In particular, when Ni and Co were contained in the solder in an amount of 0.4% by weight, the thermal resistance did not increase by 20% or more from the initial stage even after repeating 200,000 times or more. On the other hand, in the case of the comparative example, the thermal resistance increased by 20% or more from the initial stage after repeating 50,000 times or less. From this, it was found that the use of the solders of Examples 1 to 3 produces the effects of bonding strength and thermal characteristics.

次に、本発明の効果を実際の例により確かめた。まず、銅繊維部材20に、はんだを上下から挟んで形成する際のはんだの厚さを決定する。図5は、はんだ厚と等価熱伝導率との関係を示すグラフである。横軸は、上下のはんだの厚さの合計であり、単位はμmであり、縦軸は等価熱伝導率であり、単位は、W/m・Kである。ここで、等価熱伝導率とは、複数の材質で構成される部品を、1つのブロックとみなして与える熱伝導率のことである。なお、銅繊維含有はんだ材4の端部から銅繊維部材の端までの距離dは0.5mmとした。 Next, the effect of the present invention was confirmed by an actual example. First, the thickness of the solder to be formed by sandwiching the solder from above and below on the copper fiber member 20 is determined. FIG. 5 is a graph showing the relationship between the solder thickness and the equivalent thermal conductivity. The horizontal axis is the total thickness of the upper and lower solders, the unit is μm, the vertical axis is the equivalent thermal conductivity, and the unit is W / m · K. Here, the equivalent thermal conductivity is a thermal conductivity given by regarding a component made of a plurality of materials as one block. The distance d from the end of the copper fiber-containing solder material 4 to the end of the copper fiber member was set to 0.5 mm.

図5は、はんだの熱伝導率を40W/m・K、銅の熱伝導率を390W/m・Kとして、銅繊維部材の銅占有率を22%、銅繊維部材の厚さを100μmにした場合の計算結果である。図5に示すように、等価熱伝導率yと上下のはんだの厚さの合計xとの関係は、
y=113.04x-0.151
で表される。例えば、上側のはんだの厚さ、銅繊維部材の厚さ、下側のはんだの厚さをそれぞれ、10μm、100μm、10μmとした場合、等価熱伝導率は約80W/m・Kとなり、はんだ単体の40W/m・Kの約2倍となる。また、それぞれ20μm、100μm、20μmとした場合、等価熱伝導率は約72W/m・Kとなる。
In FIG. 5, the thermal conductivity of solder is 40 W / m · K, the thermal conductivity of copper is 390 W / m · K, the copper occupancy of the copper fiber member is 22%, and the thickness of the copper fiber member is 100 μm. It is the calculation result of the case. As shown in FIG. 5, the relationship between the equivalent thermal conductivity y and the total thickness x of the upper and lower solders is
y = 113.04x -0.151
It is represented by. For example, when the thickness of the upper solder, the thickness of the copper fiber member, and the thickness of the lower solder are 10 μm, 100 μm, and 10 μm, respectively, the equivalent thermal conductivity is about 80 W / m · K, and the solder alone. It is about twice as much as 40 W / mK. Further, when it is set to 20 μm, 100 μm, and 20 μm, respectively, the equivalent thermal conductivity is about 72 W / m · K.

図6は、銅占有率と等価熱伝導率との関係を示すグラフである。横軸は、銅占有率であり、単位は重量%であり、縦軸は等価熱伝導率であり、単位は、W/m・Kである。ここで、銅占有率とは、銅繊維部材に含まれる銅の重量%であり、残りは、はんだの重量である。図6において、●の直線は、上側のはんだの厚さ、銅繊維部材の厚さ、下側のはんだの厚さをそれぞれ、10μm、100μm、10μmとした場合の銅占有率xと等価熱伝導率yとの関係であり、この場合、
y=3.25x+6.6667
で表される。また、○の直線は、それぞれ、50μm、100μm、50μmとした場合の銅占有率xと等価熱伝導率yとの関係であり、この場合、
y=1.95x+20
で表される。図6より、●の直線の場合で、銅占有率を22重量%にすると等価熱伝導率は約80W/m・Kとなることがわかる。
FIG. 6 is a graph showing the relationship between the copper occupancy and the equivalent thermal conductivity. The horizontal axis is the copper occupancy rate, the unit is weight%, the vertical axis is the equivalent thermal conductivity, and the unit is W / m · K. Here, the copper occupancy rate is the weight% of the copper contained in the copper fiber member, and the rest is the weight of the solder. In FIG. 6, the straight line of ● is equivalent to the copper occupancy rate x when the thickness of the upper solder, the thickness of the copper fiber member, and the thickness of the lower solder are 10 μm, 100 μm, and 10 μm, respectively. It is the relationship with the rate y, in this case
y = 3.25x + 6.6667
It is represented by. Further, the straight line of ◯ is the relationship between the copper occupancy rate x and the equivalent thermal conductivity y when the values are 50 μm, 100 μm, and 50 μm, respectively. In this case,
y = 1.95x + 20
It is represented by. From FIG. 6, it can be seen that in the case of the straight line of ●, when the copper occupancy is 22% by weight, the equivalent thermal conductivity is about 80 W / m · K.

以上の結果に基づいて、厚さ100μmの銅繊維部材20に、それぞれ厚さ10μmのSn-Sb系のはんだを上下から挟んで形成した結果を示す。図7は、銅繊維含有はんだ材4の実施例を示す断面図である。図7に示すように、銅繊維含有はんだ材4は、銅繊維間が互いに接点を有するよう折り重ねられている銅繊維部22と、銅繊維部材20の間にはんだがしみこんだはんだ浸漬部21とからなる。 Based on the above results, the results obtained by sandwiching a Sn—Sb-based solder having a thickness of 10 μm from above and below on a copper fiber member 20 having a thickness of 100 μm are shown. FIG. 7 is a cross-sectional view showing an embodiment of the copper fiber-containing solder material 4. As shown in FIG. 7, in the copper fiber-containing solder material 4, the copper fiber portion 22 is folded so that the copper fibers have contacts with each other, and the solder dipping portion 21 in which the solder has penetrated between the copper fiber members 20. It consists of.

図8は、銅繊維含有はんだ材の実施例の接合部の断面図である。図8において、右図は左図の中央を拡大したものである。図8に示すように、銅繊維部材20は互いに接点を持ち、銅繊維部材20間がはんだ23で充填されていることがわかる。このように作成した銅繊維含有はんだ材の熱伝導率は、計算上で72.2W/m・Kである。レーザーフラッシュ法により実測した結果、Sn-Sb系のはんだのみでは、熱伝導率が約40W/m・Kであるところ、銅繊維含有はんだ材では、熱伝導率が75.8W/m・Kまで向上したことを確認した。ここで、レーザーフラッシュ法とは、断熱真空中に置かれた平板状試料の表面を均一にパルス加熱し、表面から裏面への1次元の熱拡散現象を観測することにより、熱拡散率を求める方法である。 FIG. 8 is a cross-sectional view of the joint portion of the example of the copper fiber-containing solder material. In FIG. 8, the right figure is an enlarged view of the center of the left figure. As shown in FIG. 8, it can be seen that the copper fiber members 20 have contacts with each other and the copper fiber members 20 are filled with solder 23. The thermal conductivity of the copper fiber-containing solder material thus produced is calculated to be 72.2 W / m · K. As a result of actual measurement by the laser flash method, the thermal conductivity is about 40 W / m · K only with the Sn—Sb type solder, but the thermal conductivity is up to 75.8 W / m · K with the copper fiber-containing solder material. I confirmed that it was improved. Here, in the laser flash method, the thermal diffusivity is obtained by uniformly pulse-heating the surface of a flat plate sample placed in an adiabatic vacuum and observing a one-dimensional thermal diffusivity phenomenon from the front surface to the back surface. The method.

以上、説明したように、実施の形態にかかる半導体装置によれば、パワー半導体素子と電極パターンとを接合する接合部は、銅繊維を含み、銅繊維間がはんだで充填されている銅繊維含有はんだ材である。これにより、熱伝導率が、フラックスを含有したペーストはんだや板はんだより向上するため、パワー半導体チップの発生熱を効率よく放熱できる。また、はんだの中に銅繊維が含まれているため、はんだ中にクラックが発生しても、クラックが迂回して進展するため、はんだの寿命が向上する。さらに、はんだの中に銅繊維が含まれているため、フィレットが発生することを防止でき、はんだが脇にはみ出ることが少なくなる。また、銅繊維が互いに接点を有し熱パスを形成しているため、はんだにクラックが発生しても熱抵抗の上昇を抑制できる。また、銅繊維部材に、はんだをしみこませて板はんだとすることで、従来と同様の取り扱いができ、従来よりもはんだ厚さを均一に制御することが可能になる。 As described above, according to the semiconductor device according to the embodiment, the joint portion for joining the power semiconductor element and the electrode pattern contains copper fibers, and the copper fibers are filled with solder. It is a solder material. As a result, the thermal conductivity is improved as compared with the paste solder and the plate solder containing flux, so that the heat generated by the power semiconductor chip can be efficiently dissipated. Further, since copper fibers are contained in the solder, even if cracks occur in the solder, the cracks bypass and propagate, so that the life of the solder is improved. Further, since the copper fiber is contained in the solder, it is possible to prevent the fillet from being generated, and the solder is less likely to protrude to the side. Further, since the copper fibers have contacts with each other and form a thermal path, it is possible to suppress an increase in thermal resistance even if cracks occur in the solder. Further, by impregnating the copper fiber member with solder to form a plate solder, the same handling as in the conventional case can be achieved, and the solder thickness can be controlled more uniformly than in the conventional case.

また、銅繊維含有はんだ材は、内部の銅繊維を中央部に配置し、内部の銅繊維がパワー半導体素子および電極パターンから離れて配置され、銅繊維含有はんだ材の端部には、銅繊維が配置されない。これにより、パワー半導体チップの発生熱を、銅繊維が配置された中央部から放熱し、ボイドを低減し、接合性も向上させることができる。 Further, in the copper fiber-containing solder material, the internal copper fiber is arranged in the central portion, the internal copper fiber is arranged away from the power semiconductor element and the electrode pattern, and the copper fiber is arranged at the end of the copper fiber-containing solder material. Is not placed. As a result, the heat generated by the power semiconductor chip can be dissipated from the central portion where the copper fibers are arranged, voids can be reduced, and bondability can be improved.

また、銅繊維含有はんだ材は、銅繊維ではんだを挟んで接合し、パワー半導体チップや電極パターン側に銅繊維が配置される。これにより、熱伝導性がさらに向上する。銅繊維部材ではんだを挟んだ構造にした場合、はんだで銅繊維部材を挟んだ上記の結果に比べて、熱伝導率は約5%向上した。なお、銅繊維部材およびはんだを同じ厚さとした。また、銅繊維近傍でボイドが生じにくくなる。 Further, the copper fiber-containing solder material is joined by sandwiching the solder with copper fibers, and the copper fibers are arranged on the power semiconductor chip or the electrode pattern side. This further improves thermal conductivity. In the case of the structure in which the solder is sandwiched between the copper fiber members, the thermal conductivity is improved by about 5% as compared with the above result in which the copper fiber member is sandwiched between the solders. The copper fiber member and the solder had the same thickness. In addition, voids are less likely to occur in the vicinity of the copper fiber.

また、銅繊維含有はんだ材に含まれるはんだの組成は、Sn-(5~10)Sb-(0.1~1)Ni、Co、Sn-(40~70)Sb-(0.1~1)Ni、Co、または、Sn-(1~6)Sb-(0.1~1)Ni、Coである。Ni、Coにより銅繊維の銅および銅合金の拡散を抑制することができ、熱伝導率が下がることを抑制できる。さらに、これらのはんだを用いることで、接合強度および熱物性の効果を生じさせることができる。 The composition of the solder contained in the copper fiber-containing solder material is Sn- (5 to 10) Sb- (0.1 to 1) Ni, Co, Sn- (40 to 70) Sb- (0.1 to 1). ) Ni, Co, or Sn- (1 to 6) Sb- (0.1 to 1) Ni, Co. With Ni and Co, the diffusion of copper and copper alloys of copper fibers can be suppressed, and the decrease in thermal conductivity can be suppressed. Further, by using these solders, the effects of bonding strength and thermal characteristics can be produced.

また、銅繊維にNiめっきまたはCoめっきをしてもよい。Ni、Coにより銅繊維の銅および銅合金の拡散を抑制することができ、熱伝導率が下がることを抑制できる。 Further, the copper fiber may be Ni-plated or Co-plated. With Ni and Co, the diffusion of copper and copper alloys of copper fibers can be suppressed, and the decrease in thermal conductivity can be suppressed.

以上のように、本発明にかかる半導体装置および半導体装置の製造方法は、インバータなどの電力変換装置や種々の産業用機械などの電源装置や自動車のイグナイタなどに使用されるパワー半導体装置に有用である。 As described above, the semiconductor device and the method for manufacturing the semiconductor device according to the present invention are useful for power conversion devices such as inverters, power supply devices for various industrial machines, and power semiconductor devices used for igniters of automobiles. be.

1 パワー半導体チップ
2 絶縁基板
3 電極パターン
4 接合部(銅繊維含有はんだ材)
5 放熱板
6 放熱グリス
7 冷却体
8 リードフレーム配線
9 導電性板
10 金属ワイヤ
11 外部端子
12 端子ケース
13 封止材料
14 はんだ材
20 銅繊維部材
21 はんだ浸漬部
22 銅繊維部
23 はんだ
1 Power semiconductor chip 2 Insulated substrate 3 Electrode pattern 4 Joint (copper fiber-containing solder material)
5 Heat sink 6 Thermal paste 7 Cooler 8 Lead frame wiring 9 Conductive plate 10 Metal wire 11 External terminal 12 Terminal case 13 Encapsulation material 14 Solder material 20 Copper fiber member 21 Solder immersion part 22 Copper fiber part 23 Solder

Claims (13)

半導体素子を積層基板に搭載した組立構造を有する半導体装置において、
前記半導体素子と前記積層基板上の電極パターンとを接合する接合層は、金属繊維を含み、前記金属繊維間がはんだで充填されているはんだ材が使用され、
前記はんだは、Sn-Bi系はんだに、Ni、Coを入れたSn-(40~70)Bi-(0.1~1)Ni、Coのはんだであることを特徴とする半導体装置。
In a semiconductor device having an assembly structure in which a semiconductor element is mounted on a laminated substrate,
The bonding layer that joins the semiconductor element and the electrode pattern on the laminated substrate contains metal fibers, and a solder material in which the metal fibers are filled with solder is used.
The solder is a semiconductor device characterized by being a Sn- (40 to 70) Bi- (0.1 to 1) Ni, Co solder obtained by adding Ni and Co to a Sn—Bi type solder .
前記半導体素子と、前記半導体素子と前記積層基板上の電極パターンとの電気接続用の配線とを接合する接合層は、前記はんだ材が使用されることを特徴とする請求項1に記載の半導体装置。The semiconductor according to claim 1, wherein the solder material is used as the bonding layer for joining the semiconductor element and the wiring for electrical connection between the semiconductor element and the electrode pattern on the laminated substrate. Device. 前記組立構造は、前記積層基板を搭載した放熱板をさらに有し、The assembled structure further comprises a heat sink on which the laminated substrate is mounted.
前記積層基板と前記放熱板とを接合する接合層は、前記はんだ材が使用されることを特徴とする請求項1または2に記載の半導体装置。The semiconductor device according to claim 1 or 2, wherein the solder material is used as the bonding layer for joining the laminated substrate and the heat sink.
前記接合層では、前記はんだ材に含まれる前記金属繊維は中央部に配置され、
前記接合層の端部から、前記電極パターンの表面と平行な方向に所定の距離の間、前記金属繊維が配置されないことを特徴とする請求項1~3のいずれか一つに記載の半導体装置
In the bonding layer, the metal fibers contained in the solder material are arranged in the central portion.
The semiconductor device according to any one of claims 1 to 3, wherein the metal fiber is not arranged from the end of the bonding layer in a direction parallel to the surface of the electrode pattern for a predetermined distance. ..
前記所定の距離は、0.1mm以上1mm以下であることを特徴とする請求項4に記載の半導体装置。The semiconductor device according to claim 4, wherein the predetermined distance is 0.1 mm or more and 1 mm or less. 前記接合層では、前記はんだ材に含まれる前記金属繊維は、前記半導体素子、前記積層基板および前記放熱板側に配置され、前記金属繊維間に、所定の厚さのはんだが配置されることを特徴とする請求項1~3のいずれか一つに記載の半導体装置。In the bonding layer, the metal fibers contained in the solder material are arranged on the semiconductor element, the laminated substrate, and the heat radiating plate side, and solder having a predetermined thickness is arranged between the metal fibers. The semiconductor device according to any one of claims 1 to 3, wherein the semiconductor device is characterized. 前記所定の厚さは、5μm以上20μm以下であることを特徴とする請求項6に記載の半導体装置。The semiconductor device according to claim 6, wherein the predetermined thickness is 5 μm or more and 20 μm or less. 前記所定の厚さは、前記はんだ材の厚さの5%から20%であることを特徴とする請求項6に記載の半導体装置。The semiconductor device according to claim 6, wherein the predetermined thickness is 5% to 20% of the thickness of the solder material. 前記はんだは銅を含まないことを特徴とする請求項1~8のいずれか一つに記載の半導体装置。The semiconductor device according to any one of claims 1 to 8, wherein the solder does not contain copper. 前記金属繊維は、Coめっきがされていることを特徴とする請求項1~8のいずれか一つに記載の半導体装置。The semiconductor device according to any one of claims 1 to 8, wherein the metal fiber is Co-plated. 金属繊維を含み、前記金属繊維間がはんだで充填されているはんだ材を用いて、積層基板上の電極パターンと半導体素子とを接合して、前記積層基板に前記半導体素子を搭載する工程と、A step of joining an electrode pattern on a laminated substrate and a semiconductor element using a solder material containing metal fibers and having the metal fibers filled with solder, and mounting the semiconductor element on the laminated substrate.
前記積層基板を積層組立体に組み立てる工程と、The process of assembling the laminated substrate into a laminated assembly and
前記半導体素子と、前記積層基板上の電極パターンとを、電気的に接続する工程と、A step of electrically connecting the semiconductor element and the electrode pattern on the laminated substrate,
前記積層組立体に、樹脂ケースを組み合わせる工程と、The process of combining the resin case with the laminated assembly and
を含み、Including
前記はんだは、Sn-Bi系はんだに、Ni、Coを入れたSn-(40~70)Bi-(0.1~1)Ni、Coのはんだであることを特徴とする半導体装置の製造方法。The method for manufacturing a semiconductor device, wherein the solder is a Sn- (40 to 70) Bi- (0.1 to 1) Ni, Co solder obtained by adding Ni and Co to a Sn—Bi-based solder. ..
前記電気的に接続する工程では、前記はんだ材を用いて、前記半導体素子と、前記積層基板上の電極パターンとを、電気的に接続することを特徴とする請求項11に記載の半導体装置の製造方法。The semiconductor device according to claim 11, wherein in the step of electrically connecting, the semiconductor element and the electrode pattern on the laminated substrate are electrically connected by using the solder material. Production method. 前記組み立てる工程では、前記積層基板を、前記はんだ材を用いて、前記積層組立体の放熱板に接合することを特徴とする請求項11または12に記載の半導体装置の製造方法。The method for manufacturing a semiconductor device according to claim 11 or 12, wherein in the assembling step, the laminated substrate is joined to a heat sink of the laminated assembly by using the solder material.
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