JP2006066716A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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JP2006066716A
JP2006066716A JP2004248843A JP2004248843A JP2006066716A JP 2006066716 A JP2006066716 A JP 2006066716A JP 2004248843 A JP2004248843 A JP 2004248843A JP 2004248843 A JP2004248843 A JP 2004248843A JP 2006066716 A JP2006066716 A JP 2006066716A
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solder
bonding
semiconductor chip
film
insulating substrate
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JP2004248843A
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Yoshinari Ikeda
良成 池田
Mitsuo Yamashita
満男 山下
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Fuji Electric Co Ltd
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Fuji Electric Holdings Ltd
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  • Engineering & Computer Science (AREA)
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Abstract

<P>PROBLEM TO BE SOLVED: To improve a fatigue life and reliability of a solder bonding portion by suppressing low the elution of Ni filmed on the surface of a base metal to a solder and the growth of a metal compound generated on a bonding interface with regard to the solder bonding portion between members comprising a module type semiconductor device. <P>SOLUTION: In the module type semiconductor device, a power semiconductor chip 3 is mounted on a conductor pattern 2a of an insulating substrate 2 packaged on a copper base plate 1, and a lead frame 4 is connected to the upper surface electrode of the semiconductor chip. In such a module type semiconductor device soldering respective members and bonding their faces, an Ni film 9 is formed by filming Ni as surface treatment on a solder bonding surface of each of bonding members including the semiconductor chip 3. Further, a Cu film 10 is formed on the surface of the Ni film for thickness (of ≤1 μm) to be perfectly dissolved in solder bonding steps, and the members are then solder-bonded by Sn-rich soldering. Thus, a ternary metal compound of Cu-Ni-Sn is generated on the bonding interface of the solder, this metal compound becomes a barrier to suppress the elution of Ni and the growth of the metal compound with electrification and heating during actual use, thereby improving reliability of the solder bonding portion. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

本発明は、パワー半導体モジュールなど、発熱量の大きなパワー半導体素子を搭載した半導体装置に関し、詳しくはパワー半導体素子を含む構成部材の半田接合構造に係わる。   The present invention relates to a semiconductor device including a power semiconductor element having a large calorific value, such as a power semiconductor module, and more particularly to a solder joint structure of components including the power semiconductor element.

近年になり、パワー半導体装置の定格拡大，高密度実装化に伴い、半導体素子の発生熱を効率よく放熱することが重要課題となっている。このような要求からパッケージ内で絶縁基板に半田マウントしたパワー半導体素子の配線構造について、在来のワイヤボンディングに代えてリードフレーム（導体板）を半導体チップの上面電極に半田接合し、該リードフレームを伝熱経路として半導体チップの発生熱を上面側の主面からも放熱させるようにした構成のものが採用されるようになっている（例えば、特許文献１参照）。
次に、金属ベース板上に絶縁基板を介してパワー半導体チップを搭載したモジュール形の半導体装置について、半導体チップに接続する配線リードに前記のリードフレームを採用した半導体装置の組立構造を図２に示す。図において、１はヒートシンクとなる放熱用銅ベース板、２は絶縁基板（例えば、セラミックス基板２ａの表，裏両面に銅箔を直接接合して導体パターン２ｂ，２ｃを形成したＤＣＢ（Direct Copper Bonding）基板）、３は絶縁基板２の上にマウントしたパワー半導体チップ（例えばＩＧＢＴ）、４は半導体チップ２の上面電極（ＩＧＢＴのエミッタ電極パッド）と絶縁基板２の導体パターンとの間にまたがって接合した内部配線用のリードフレーム（銅製の導体板）、５は外囲樹脂ケース、６は外部導出端子、７は外部導出端子６と絶縁基板２の上面側導体パターン２ｂ（導体パターン２ａは、図示してないが半導体チップ３との接合，接続に合わせた回路パターンに区分されている）との間に配線したボンディングワイヤであり、銅ベース板１／絶縁基板２，絶縁基板２／半導体チップ３，半導体チップ３／リードフレーム４，リードフレーム４／絶縁基板２の間が半田８（リフロー半田付け法）で接合されている。なお、半導体チップ２を湿気，塵などから保護するために、外囲樹脂ケース５の内部にはシリコーンゲルなどを充填して封止している。また、ここで使用する半田材について、最近は鉛フリー化の問題からからＳｎリッチな半田材が多く使用されるようになっている。 In recent years, it has become an important issue to efficiently dissipate heat generated by semiconductor elements as the rating of power semiconductor devices is increased and the mounting density is increased. In view of these requirements, a lead frame (conductor plate) is solder-bonded to the upper surface electrode of a semiconductor chip in place of the conventional wire bonding for the wiring structure of the power semiconductor element solder-mounted on the insulating substrate in the package. As a heat transfer path, a configuration is adopted in which the heat generated by the semiconductor chip is also dissipated from the main surface on the upper surface side (see, for example, Patent Document 1).
Next, FIG. 2 shows an assembly structure of a semiconductor device in which a power semiconductor chip is mounted on a metal base plate via an insulating substrate and the lead frame is used as a wiring lead connected to the semiconductor chip. Show. In the figure, 1 is a heat radiating copper base plate serving as a heat sink, 2 is an insulating substrate (for example, DCB (Direct Copper Bonding) in which conductor patterns 2b and 2c are formed by directly bonding copper foil to the front and back surfaces of the ceramic substrate 2a. ) Substrate) 3 is a power semiconductor chip (for example, IGBT) mounted on the insulating substrate 2, and 4 is between the upper surface electrode (IGBT emitter electrode pad) of the semiconductor chip 2 and the conductor pattern of the insulating substrate 2. Bonded lead frame for internal wiring (copper conductor plate), 5 is an outer resin case, 6 is an external lead-out terminal, 7 is an external lead-out terminal 6 and the upper surface side conductor pattern 2b of the insulating substrate 2 (the conductor pattern 2a is Although not shown, it is a bonding wire that is wired between the copper base plate 1 and the semiconductor chip 3. Insulating substrate 2, an insulating substrate 2 / semiconductor chip 3, the semiconductor chip 3 / lead frame 4, between the lead frame 4 / insulating substrate 2 are joined by solder 8 (reflow soldering method). In order to protect the semiconductor chip 2 from moisture, dust and the like, the outer resin case 5 is filled with silicone gel or the like and sealed. Further, as for the solder material used here, recently, a Sn-rich solder material is often used due to the problem of lead-free.

一方、上記構成の半導体装置については、温度サイクルなどの外的ストレスを受けて半田接合部に疲労破壊，クラックが発生すると致命的なダメージを受けることから、このようなクラック発生を防止して半田接合部の信頼性を確保するための様々な対応策が研究されている。
すなわち、前記した各接合部材の間を半田接合すると、接合部材の母材金属（Ｃｕ）と半田との濡れにより母材金属の半田への溶出によって接合界面に脆性の高い金属間化合物（Ｃｕ−Ｓｎ）が生成し、かつこの金属間化合物が半導体チップの通電に伴う発熱により層状，コブ状に成長し、これが基で温度サイクルなどによる熱的ストレスで半田接合部にクラックが発生することが知られている。
そこで、半田接合部のクラック発生防止策として、半田への溶出速度，および半田材成分のＳｎとの金属間化合物の成長速度が遅いＮｉを母材金属（銅）の表面に成膜することにより、半田接合部の疲労寿命が向上することが報告されており、現在その実用化が進められている。
特開２００１−３３２６６４号公報 On the other hand, since the semiconductor device having the above-described structure is subject to fatal damage when fatigue breakage or cracks occur in the solder joints due to external stress such as temperature cycles, the occurrence of such cracks is prevented and soldering is performed. Various countermeasures for ensuring the reliability of the joint have been studied.
That is, when the above-mentioned joining members are solder-bonded, an intermetallic compound (Cu--) having a high brittleness at the joint interface due to elution of the base metal to the solder due to wetting of the base metal (Cu) and the solder of the joining member. It is known that Sn) is generated, and this intermetallic compound grows in layers and bumps due to heat generated by energization of the semiconductor chip, which causes cracks in the solder joints due to thermal stress due to temperature cycles. It has been.
Therefore, as a measure for preventing the occurrence of cracks in the solder joints, by depositing Ni on the surface of the base metal (copper), the elution rate into the solder and the slow growth rate of the intermetallic compound with Sn as the solder material component are formed. It has been reported that the fatigue life of solder joints is improved, and its practical application is currently underway.
JP 2001-332664 A

ところで、先記のように接合部材の表面処理として母材金属の表面にＮｉを成膜するクラック防止対策をそのまま発熱量の大きなパワー半導体装置に適用すると次記のような問題点がある。
すなわち、Ｓｎリッチな半田材で前記接合部材の間を半田付すると、母材金属の半田への溶出により半田接合界面には金属間化合物として母材金属がＣｕであればＣｕ−Ｓｎが、また母材金属にＮｉを成膜した場合にはＮｉ−Ｓｎ合金が生成する。この場合にＮｉ−Ｓｎ合金の成長速度は、１５０℃以下の温度範囲ではＣｕ−Ｓｎ合金に比べて低いが、１５０℃を超えた高温領域ではＮｉ−Ｓｎ合金の成長速度が増してＣｕ−Ｓｎ合金の成長速度よりもむしろ大きくなる傾向を示す（例えば、大塚寛治著、「界面工学」、培風館、ｐ１１４参照）。 By the way, as described above, when the crack prevention measure for forming a Ni film on the surface of the base metal is applied to the power semiconductor device having a large calorific value as the surface treatment of the joining member, there is the following problem.
That is, when the joining members are soldered with a Sn-rich solder material, Cu—Sn is obtained when the base metal is Cu as an intermetallic compound at the solder joint interface due to elution of the base metal into the solder. When Ni is deposited on the base metal, a Ni—Sn alloy is formed. In this case, the growth rate of the Ni—Sn alloy is lower than that of the Cu—Sn alloy in the temperature range of 150 ° C. or less, but the growth rate of the Ni—Sn alloy increases in the high temperature region exceeding 150 ° C. It shows a tendency to increase rather than the growth rate of the alloy (see, for example, Koji Otsuka, “Interface Engineering”, Baifukan, p114).

このために、半導体チップの発熱温度が保証温度である接合温度（Ｔｊ）＝１５０℃（シリコンの場合）を超えるようなパワー半導体チップに対しては、前記のように母材金属の表面にＮｉを成膜しただけでは、半田接合後の通電に伴う半導体チップの高温発熱によるＮｉの半田への溶出が継続して半田の接合界面に生じた金属間化合物の成長が進み、その結果として半田接合部の疲労寿命向上の成果が十分に発揮できない。
本発明は上記の点に鑑みなされたものであり、その目的は先記したモジュール形の半導体装置を対象に、接合部材の母材金属表面に成膜したＮｉの半田への溶出，および接合界面に生成した金属間化合物の成長を低く抑えて半田接合部の信頼性向上が図れるように改良した半導体装置を提供することにある。 Therefore, for a power semiconductor chip in which the heat generation temperature of the semiconductor chip exceeds the guaranteed temperature of the junction temperature (Tj) = 150 ° C. (in the case of silicon), the surface of the base metal is Ni as described above. As a result, the elution of Ni into the solder due to the high-temperature heat generation of the semiconductor chip accompanying the energization after solder bonding continues, and the growth of intermetallic compounds generated at the solder bonding interface proceeds. As a result, solder bonding The results of improving the fatigue life of the part cannot be fully demonstrated.
The present invention has been made in view of the above points, and its purpose is to elute the Ni deposited on the base metal surface of the bonding member into the solder and the bonding interface for the module-type semiconductor device described above. Another object of the present invention is to provide an improved semiconductor device that can suppress the growth of the intermetallic compound formed at a low level and improve the reliability of solder joints.

上記目的を達成するために、本発明によれば、金属ベース板上に絶縁基板を介して半導体チップを搭載してその相互間を半田接合し、さらに半導体チップの上面電極に接続する配線リードに導体板を採用して半田接合したモジュール形の半導体装置を対象に、その半田付け部には次記のような処理を施して半田接合するものとする。
（１）絶縁基板の導体パターンと該絶縁基板にマウントした半導体チップとの間,および半導体チップの上面電極と配線リードとの間の半田接合部について、半導体チップおよび半導体チップに半田付けする接合相手部材の半田接合面に表面処理としてＮｉを成膜した上で、さらに該Ｎｉ層の表面に半田接合工程で完全に溶解し得る厚さのＣｕを成膜して半田接合する（請求項１）。
（２）金属ベース板と該ベース板上に搭載した絶縁基板の下面の導体パターンとの間，および絶縁基板の上面の導体パターンと絶縁基板にマウントした半導体チップとの間の半田接合部について、絶縁基板の各導体パターンおよび該基板の各導体パターンに半田付けする接合相手部材の半田接合面に表面処理としてＮｉを成膜した上で、さらに該Ｎｉ層の表面に半田接合工程で完全に溶解し得る厚さのＣｕを成膜して半田接合する（請求項２）。 In order to achieve the above object, according to the present invention, a semiconductor chip is mounted on a metal base plate through an insulating substrate, soldered between the two, and further connected to the upper surface electrode of the semiconductor chip. For a module-type semiconductor device that employs a conductor plate and is soldered, the soldering part is subjected to the following processing and soldered.
(1) Bonding solders to be soldered to the semiconductor chip and the semiconductor chip between the solder pattern between the conductor pattern of the insulating substrate and the semiconductor chip mounted on the insulating substrate and between the upper surface electrode of the semiconductor chip and the wiring lead After Ni is formed as a surface treatment on the solder joint surface of the member, Cu having a thickness that can be completely dissolved in the solder joint process is further formed on the surface of the Ni layer and solder joined (Claim 1). .
(2) About the solder joint between the metal base plate and the conductor pattern on the lower surface of the insulating substrate mounted on the base plate, and between the conductor pattern on the upper surface of the insulating substrate and the semiconductor chip mounted on the insulating substrate, After Ni is deposited as a surface treatment on each solder pattern of the insulating substrate and each solder pattern of the mating member to be soldered to each conductor pattern of the substrate, it is further completely dissolved on the surface of the Ni layer in the solder bonding process. A Cu film having a thickness that can be obtained is formed and solder-bonded (Claim 2).

ここで、Ｎｉ層の表面に成膜したＣｕ層は、その膜厚を１μｍ以下としてＮｉ層より薄く設定し（請求項３）、また半田材にはＳｎリッチな半田を用いる（請求項４）ものとする。   Here, the Cu layer formed on the surface of the Ni layer is set to be 1 μm or thinner and thinner than the Ni layer (Claim 3), and Sn-rich solder is used as the solder material (Claim 4). Shall.

上記のように、パワー半導体チップを含めてモジュール形半導体装置を構成する各接合部材の半田接合面に表面処理としてＮｉを成膜した上で、さらに該Ｎｉ層の表面には半田との濡れ性がよく、かつ半田接合工程で完全に溶解し得る厚さのＣｕを成膜した上で半田付けを行うことにより、前記Ｃｕ膜が完全に溶解し、半田の接合界面には溶解したＣｕ，Ｎｉ層から溶出したＮｉ，および半田のＳｎとでＣｕ−Ｎｉ−Ｓｎの３元系金属間化合物が形成される。このＣｕ−Ｎｉ−Ｓｎの３元系金属間化合物は先記したＣｕ−Ｓｎの２元系金属間化合物に比べて成長速度が遅く、かつ母材金属の表面に成膜した下地のＮｉ層に対してバリアとして働き、半田へのＮｉの溶出，拡散を抑止する。したがって、半田接合後は温度負荷のかかる実使用時でも接合界面に生成した金属間化合物の成長を効果的に抑えることができ、これにより半田接合部の疲労寿命が大幅に改善される。   As described above, after Ni is deposited as a surface treatment on the solder joint surface of each joint member including the power semiconductor chip constituting the module type semiconductor device, the surface of the Ni layer is further wettable with solder. The Cu film is completely dissolved by forming a Cu film having a thickness that can be completely dissolved in the solder bonding step, and the Cu film is completely dissolved. A Cu—Ni—Sn ternary intermetallic compound is formed by Ni eluted from the layer and Sn of the solder. This Cu—Ni—Sn ternary intermetallic compound has a slower growth rate than the Cu—Sn binary intermetallic compound described above, and the underlying Ni layer is formed on the surface of the base metal. It acts as a barrier against the dissolution and diffusion of Ni into the solder. Accordingly, after solder bonding, the growth of intermetallic compounds generated at the bonding interface can be effectively suppressed even during actual use where a temperature load is applied, and the fatigue life of the solder joint is thereby greatly improved.

以下、本発明の実施の形態を図１（ａ），（ｂ）に示す実施例に基づいて説明する。なお、実施例の図中で図２に対応する同一部材には同じ符号を付してその詳細な説明は省略する。
すなわち、図示実施例は図２に示した半導体装置と基本的に同じ構造であるが、金属ベース板としての銅ベース板１，絶縁基板２，パワー半導体チップ３，およびリードフレーム４の各部材に対して、その半田接合面（銅ベース板１の上面，絶縁基板２の導体パターン２ａおよび２ｂ，パワー半導体チップ３の主面電極（エミッタ，コレクタの電極パッド），およびリードフレーム４の接合端面）には、図１（ａ）で示すように、あらかじめ厚さ５μｍ程度にＮｉ膜９を成膜した上で、さらにＮｉ膜の上に厚さ１μｍ以下の薄いＣｕ膜１０を成膜しておく。なお、Ｎｉ膜９，Ｃｕ膜１０の成膜には蒸着，スパッタ，メッキなどの方法が用いられる。 Embodiments of the present invention will be described below based on the examples shown in FIGS. 1 (a) and 1 (b). In the drawings of the embodiment, the same members corresponding to those in FIG. 2 are denoted by the same reference numerals, and detailed description thereof is omitted.
That is, the illustrated embodiment has basically the same structure as that of the semiconductor device shown in FIG. 2, but each member of the copper base plate 1, the insulating substrate 2, the power semiconductor chip 3, and the lead frame 4 as a metal base plate. On the other hand, the solder joint surface (the upper surface of the copper base plate 1, the conductor patterns 2a and 2b of the insulating substrate 2, the main surface electrodes (emitter and collector electrode pads) of the power semiconductor chip 3, and the joint end surface of the lead frame 4) As shown in FIG. 1A, a Ni film 9 having a thickness of about 5 μm is formed in advance, and a thin Cu film 10 having a thickness of 1 μm or less is further formed on the Ni film. . Note that deposition, sputtering, plating, or the like is used to form the Ni film 9 and the Cu film 10.

そして、半導体装置の組立工程では銅ベース板１の上面，絶縁基板２の上面側導体パターン２ａ，および半導体チップ３の上面側電極（エミッタ電極パッド）に対し、前記Ｃｕ膜１０の上に半田材（例えばＳｎ−３．５ＡｇのＳｎリッチなクリーム半田）８ａを塗布し、銅ベース板１の上に絶縁基板２，半導体チップ３，リードフレーム４を定位置に重ね合わせた上で、この仮組立体をリフロー炉に搬入して半田接合（リフロー半田接合工程の条件は、例えば温度：２５０℃，時間：２分）する。なお、図１（ａ）では説明の便宜上、銅ベース板１，絶縁基板２，パワー半導体チップ３，リードフレーム４の半田付けを同じ工程で一括して行うようにしているが、銅ベース板１／絶縁基板２，絶縁基板２／パワー半導体チップ３，パワー半導体チップ３，リードフレーム４間の半田付けを別工程に分けて行う場合でも同様である。   In the assembly process of the semiconductor device, a solder material is applied on the Cu film 10 to the upper surface of the copper base plate 1, the upper surface side conductor pattern 2 a of the insulating substrate 2, and the upper surface side electrode (emitter electrode pad) of the semiconductor chip 3. (For example, Sn-3.5Ag Sn-rich cream solder) 8a is applied, and the insulating substrate 2, the semiconductor chip 3, and the lead frame 4 are superposed on the copper base plate 1 in a fixed position. The solid is carried into a reflow furnace and soldered (reflow soldering process conditions are, for example, temperature: 250 ° C., time: 2 minutes). In FIG. 1A, for convenience of explanation, the copper base plate 1, the insulating substrate 2, the power semiconductor chip 3, and the lead frame 4 are soldered together in the same process. The same applies to the case where the soldering between the insulating substrate 2, the insulating substrate 2, the power semiconductor chip 3, the power semiconductor chip 3, and the lead frame 4 is performed in separate steps.

上記のリフロー半田接合工程では、膜厚１μｍ以下に設定したＣｕ膜１０は全て溶解し、さらにその下地のＮｉ膜も表面一部が溶出して半田の接合界面には、図１（ｂ）で表すようにＣｕ−Ｎｉ−Ｓｎの３元系合金になる金属間化合物１１が層状に形成される（Ｃｕ膜１０の膜厚が厚いと、半田接合工程中に完全に溶解しないで下地のＮｉ膜９を覆ったままとなるため、Ｃｕ−Ｎｉ−Ｓｎの３元系合金が形成されない）。なお、この場合にＣｕの供給源となるＣｕ膜１０の膜厚が１μｍ以下と極薄いためにＣｕ−Ｓｎ合金の生成は極僅かであり、かつ接合部材の母材金属（銅）はその表面がＮｉ膜９で覆われてＣｕの供給源とはならないことから経時的な成長も見られない。
しかも、前記したＣｕ−Ｎｉ−Ｓｎの３元系金属間化合物１１は、Ｃｕ−Ｓｎの２元系金属間化合物に比べて成長速度が遅く、かつ下地のＮｉ膜９に対してバリアとして有効に働く。これにより、半田接合後は通電によるパワー半導体チップ３の高温発熱が加わっても半田の接合界面に生成した金属間化合物の成長が効果的に抑制される。その結果として、半導体装置の実使用時の温度サイクルにより半田接合部に熱的ストレスが加わっても脆い金属間化合物に起因するクラックの発生を抑えて半田接合部の疲労寿命が大幅に改善されて高い信頼性が確保できる。 In the above reflow soldering process, the Cu film 10 set to a film thickness of 1 μm or less is completely dissolved, and a part of the surface of the underlying Ni film is eluted, and the solder bonding interface is shown in FIG. As shown, an intermetallic compound 11 that becomes a Cu—Ni—Sn ternary alloy is formed in a layered form (if the Cu film 10 is thick, the underlying Ni film does not completely dissolve during the solder bonding process) 9 remains covered, and a Cu—Ni—Sn ternary alloy is not formed). In this case, since the film thickness of the Cu film 10 serving as a Cu supply source is as extremely thin as 1 μm or less, the formation of the Cu—Sn alloy is very small, and the base metal (copper) of the joining member is the surface thereof. Since it is covered with the Ni film 9 and does not serve as a Cu supply source, no growth over time is observed.
Moreover, the Cu—Ni—Sn ternary intermetallic compound 11 described above has a slower growth rate than the Cu—Sn binary intermetallic compound, and is effective as a barrier against the underlying Ni film 9. work. Thereby, even if high temperature heat generation of the power semiconductor chip 3 due to energization is applied after solder bonding, the growth of the intermetallic compound generated at the solder bonding interface is effectively suppressed. As a result, even if thermal stress is applied to the solder joint due to the temperature cycle during actual use of the semiconductor device, the fatigue life of the solder joint is greatly improved by suppressing the occurrence of cracks due to brittle intermetallic compounds. High reliability can be secured.

なお、前記の半田８にはＳｎリッチな半田材，鉛フリーの半田材を使用するのがよく、具体的にはＳｎ−Ｃｕ系，Ｓｎ−Ａｇ系，Ｓｎ−Ｚｎ系，Ｓｎ−Ｂｉ系などの２元系、あるいは、Ｓｎ−Ａｇ−Ｃｕ系，Ｓｎ−Ａｇ−Ｉｎ系などの３元系半田を用いることができる。
また図示実施例では、絶縁基板２／半導体チップ３／配線リード４間の半田接合部のほか、銅ベース板１／絶縁基板２間の半田接合部についても母材金属の表面にＮｉ膜９，Ｃｕ膜１０の成膜処理を施した上で半田接合しており、このように接合面積が大きい母材金属間の半田接合に対しても有効である。なお、状況によっては母材金属に対するＮｉ膜９，Ｃｕ膜１０の成膜処理を絶縁基板２の導体パターン２ａ，半導体チップ３の主面電極，およびリードフレーム４に対してのみ施し、銅ベース板１，絶縁基板２の表面処理を省略して実施してもよい。 In addition, it is preferable to use a Sn-rich solder material or a lead-free solder material for the solder 8, specifically, Sn—Cu, Sn—Ag, Sn—Zn, Sn—Bi, or the like. Binary solder such as Sn-Ag-Cu or Sn-Ag-In can be used.
In the illustrated embodiment, in addition to the solder joint between the insulating substrate 2 / semiconductor chip 3 / wiring leads 4, the Ni film 9 on the surface of the base metal is also applied to the solder joint between the copper base plate 1 / insulating substrate 2. Solder bonding is performed after the Cu film 10 is formed, and this is also effective for solder bonding between base metals having a large bonding area. In some cases, the Ni film 9 and the Cu film 10 are formed on the base metal only on the conductor pattern 2a of the insulating substrate 2, the main surface electrode of the semiconductor chip 3, and the lead frame 4, and the copper base plate. 1, surface treatment of the insulating substrate 2 may be omitted.

本発明の実施例による半導体装置の構成図で、（ａ）は半田接合工程実施の前の状態を表す分解図、（ｂ）は半田接合後の状態を表す図BRIEF DESCRIPTION OF THE DRAWINGS It is a block diagram of the semiconductor device by the Example of this invention, (a) is an exploded view showing the state before implementation of a solder joint process, (b) is a figure showing the state after solder joining 本発明の実施対象となるパワー半導体装置全体の組立構成図Assembly diagram of the entire power semiconductor device to be implemented by the present invention

符号の説明Explanation of symbols

１ 放熱用銅ベース板
２ 絶縁基板
２ａ，２ｂ 導体パターン
３ パワー半導体チップ
４ リードフレーム（配線リード）
８ 半田
９ Ｎｉ膜
１０ Ｃｕ膜
１１ Ｃｕ−Ｎｉ−Ｓｎの３元系金属間化合物 DESCRIPTION OF SYMBOLS 1 Heat dissipation copper base board 2 Insulation board 2a, 2b Conductor pattern 3 Power semiconductor chip 4 Lead frame (wiring lead)
8 Solder 9 Ni film 10 Cu film 11 Cu—Ni—Sn ternary intermetallic compound

Claims (4)

絶縁基板の導体パターンと絶縁基板にマウントした半導体チップとの間,および半導体チップの上面電極と配線リードとの間を半田付けして面接合した半導体装置において、
少なくとも半導体チップおよび半導体チップに半田付けする接合相手部材の半田接合面に表面処理としてＮｉを成膜した上で、さらに該Ｎｉ層の表面に半田接合工程で完全に溶解し得る厚さのＣｕを成膜して半田接合したことを特徴とする半導体装置。 In a semiconductor device in which surface bonding is performed by soldering between a conductor pattern of an insulating substrate and a semiconductor chip mounted on the insulating substrate, and between an upper surface electrode of the semiconductor chip and a wiring lead,
After forming a Ni film as a surface treatment on at least a semiconductor chip and a solder bonding surface of a bonding partner member to be soldered to the semiconductor chip, Cu having a thickness that can be completely dissolved in the solder bonding process on the surface of the Ni layer A semiconductor device formed by film formation and solder bonding. 金属ベース板と該ベース板上に搭載した絶縁基板の下面の導体パターンとの間，および絶縁基板の上面の導体パターンと絶縁基板にマウントした半導体チップとの間を半田付けして面接合した半導体装置において、
少なくとも絶縁基板の各導体パターン，および該基板の各導体パターンに半田付けする接合相手部材の半田接合面に表面処理としてＮｉを成膜した上で、さらに該Ｎｉ層の表面に半田接合工程で完全に溶解し得る厚さのＣｕを成膜して半田接合したことを特徴とする半導体装置。 A semiconductor in which surface bonding is performed by soldering between a metal base plate and a conductor pattern on the lower surface of the insulating substrate mounted on the base plate, and between a conductor pattern on the upper surface of the insulating substrate and a semiconductor chip mounted on the insulating substrate. In the device
After forming Ni as a surface treatment on at least each conductor pattern of the insulating substrate and the solder bonding surface of the bonding partner member to be soldered to each conductor pattern of the substrate, the surface of the Ni layer is further completely soldered A semiconductor device characterized in that Cu having a thickness that can be dissolved in a film is formed and soldered. 請求項１または２に記載の半導体装置において、Ｎｉ層の表面に成膜したＣｕ層の膜厚が１μｍ以下で、かつＮｉ層より薄く設定したことを特徴とする半導体装置。 3. The semiconductor device according to claim 1, wherein the Cu layer formed on the surface of the Ni layer is set to have a thickness of 1 [mu] m or less and thinner than the Ni layer. 請求項１ないし３に記載の半導体装置において、半田材がＳｎリッチな半田であることを特徴とする半導体装置。 4. The semiconductor device according to claim 1, wherein the solder material is Sn-rich solder.
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