JP4814196B2 - Circuit board - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a highly reliable circuit board etc., on which a defect in contact with a semiconductor chip is suppressed even when lead-free solder having a higher fusion point than before is used. <P>SOLUTION: The circuit board 10 is provided with a recessed portion extending from an edge of an electrode 13A disposed in a peripheral area on an outer peripheral side among electrodes arrayed in a matrix. Consequently, even if force is applied from the electrode to the solder in a direction shown by an arrow D12, a raised wall portion relieves stress and cracking is hardly caused. <P>COPYRIGHT: (C)2009,JPO&amp;INPIT

Description

  The present invention relates to a circuit board on which a semiconductor chip is mounted, a semiconductor device including the circuit board and the semiconductor chip, and a method for manufacturing the semiconductor device.

  Along with miniaturization and high performance of electronic devices such as portable electronic devices, semiconductor chips to be mounted are required to be miniaturized and mounted with high density. In order to meet these requirements, surface mount type semiconductor chips called area array types such as BGA (Ball Grid Array) and CSP (Chip Size Package) are widely used. Here, the semiconductor chip includes a form in which a semiconductor substrate is sealed in a package.

  Electrodes are arranged at a constant pitch on the bottom surface of such a surface mount type semiconductor chip, and solder bumps for connection to a circuit board are provided on the electrodes. After the semiconductor chip is placed on the circuit board so that the solder bumps are aligned with the electrode on the circuit board side, the semiconductor device is obtained by soldering the electrode of the circuit board and the electrode of the semiconductor chip by reflow soldering. Complete.

  A semiconductor chip connected to a circuit board using solder bumps is superior in signal high-speed transmission characteristics because it has a shorter electrical wiring length than when connected via a lead wire. Further, since the solder bumps can be arranged over the entire bottom surface of the semiconductor chip, it is suitable for a multi-pin structure.

  FIG. 1 is a partial cross-sectional view illustrating a mounting structure in a conventional semiconductor device. Part (A) in FIG. 1 shows a state before mounting, and part (B) shows a state after mounting. In the cross-sectional view, all parts are shown as cross-sections, but hatching is omitted for easy understanding of the drawing.

  As shown in Part (A) of FIG. 1, solder bumps 22 are provided on the electrodes arranged on the bottom surface of the semiconductor chip 20. As a material for the solder bump, for example, Sn-Pb solder or Sn-Ag-Cu solder is used. In general BGA type semiconductor chips, the diameter of solder bumps is 600 to 700 μm, and the pitch between solder bumps is about 1 to 1.5 mm. The circuit board 90 is provided with electrodes 93 at positions corresponding to the electrodes of the semiconductor chip 20. A semiconductor device as shown in Part (B) of FIG. 1 is completed by placing the semiconductor chip 20 on the circuit board 90 and undergoing a reflow process. The semiconductor chip and the circuit board are heated and expanded in the reflow process. However, since the circuit board generally has a higher coefficient of thermal expansion than the semiconductor chip, a positional shift occurs between the electrodes.

  FIG. 2 is an enlarged cross-sectional view showing a part of the mounting structure shown in FIG. FIG. 2 shows one solder and its vicinity in the mounting structure shown in FIG.

  The electrode 21 of the semiconductor chip 20 and the electrode 93 of the circuit board 90 shown in FIG. 2 are joined by solder 22A formed by melting and solidifying the solder bumps 22. In this figure, the positional deviation between the electrode 21 of the semiconductor chip 20 and the electrode 93 of the circuit board 90 is emphasized. The circuit board 90 has a higher coefficient of thermal expansion than the semiconductor chip 20 and expands larger than the semiconductor chip 20 in reflow soldering. That is, the peripheral portion of the circuit board 90 moves relative to the semiconductor chip 20 in the direction indicated by the arrow D1 from the central portion toward the peripheral portion.

  The solder solidifies in the cooling process after heating, but the circuit board 90 still expands at the solidification point of the solder 22A. Therefore, the solder 22A is solidified in the state shown in FIG. When the temperature further decreases after the solder 22A solidifies, the circuit board 90 tends to contract, and at normal temperature, the electrode 93 continues to apply a force in the direction indicated by the arrow D2 to the solder 22A. For this reason, a stress is always generated at the boundary between the electrode 93 and the solder 22A, and there is a possibility that the connection portion will be cracked due to the passage of time or an impact such as dropping, and the connection reliability is lowered.

In order to suppress damage to the connection portion, for example, in Patent Document 1 and Patent Document 2, in a semiconductor chip in which a plurality of connection terminals protrude from a resin package at a predetermined interval, the protrusion of the connection terminal disposed outside is disclosed. The amount is shown larger than the protruding amount of the other connection terminals. Patent Document 3 discloses a circuit board having electrodes whose ends are inclined in order to avoid concentration of an electric field.
Japanese Patent Laid-Open No. 10-25646 JP 2004-179606 A Japanese Patent No. 3491414

  However, the semiconductor chip in which the protruding amount of the connection terminals is changed and the circuit board in which the ends of the electrodes are inclined as shown in Patent Documents 1 and 2 cannot sufficiently suppress a decrease in reliability at the connection portion.

  In recent years, the influence of lead on the environment has been taken into consideration and its use has been regulated. Therefore, as a lead-free solder material that does not contain lead, a solder material mainly composed of Sn, for example, Sn-Ag- The use of solder materials made of Cu or the like has been promoted. Such a solder material has a melting point of 217 ° C., which is about 40 ° C. higher than the melting point of conventional Sn—Pb eutectic solder, 183 ° C., and when used for mounting a semiconductor chip on a circuit board, There are the following problems.

  (1) The temperature difference between the melting point and room temperature is about 200 ° C., which is 40 ° C. higher than that of the conventional Sn—Pb eutectic solder. Therefore, deformation due to a difference in thermal expansion between the circuit board and the package increases. In particular, the influence of deformation is large at the peripheral portion of the semiconductor chip, and connection failure is likely to occur in a large semiconductor chip having a side length exceeding 330 mm.

  (2) While the mechanical properties of the solder itself, such as the elastic modulus (Young's modulus) and tensile strength, are larger than those of the conventional Sn-Pb eutectic solder, the elongation characteristics that affect the fatigue life characteristics are Sn-Pb. Reduced compared to eutectic solder. For this reason, the stress applied to the solder joint is increased, and connection failure tends to occur.

  (3) At the time of bonding, a CuSn alloy as a reaction layer is formed at the bonding interface between the solder and the electrode. FIG. 3 is an enlarged cross-sectional view schematically showing only the electrode portion of FIG. An alloy 94 is formed in a film shape at the joint interface between the electrode 93 and the solder shown in FIG. 3 during the reflow solder joint. This CuSn alloy is formed into a thin film because the melting point of the solder is high. For this reason, it is thought that it becomes weak with respect to dynamic distortions, such as a drop impact.

  In view of the above circumstances, an object of the present invention is to provide a highly reliable circuit board, a semiconductor device, and a method for manufacturing the semiconductor device in which occurrence of poor contact with a semiconductor chip is suppressed.

The circuit board of the present invention that achieves the above object includes an electrode having a recess extending from the edge. In the circuit board of the present invention, the electrode has a recess extending from the edge. Therefore, the generation and progression of cracks between the electrode and the solder can be suppressed. Therefore, the occurrence of contact failure between the circuit board and the semiconductor chip can be suppressed.

  Here, in the circuit board of the present invention, it is preferable that the concave portion is provided toward the periphery of the circuit board.

  The portion of the circuit board on which the semiconductor chip is mounted shrinks toward the center of the mounting portion relative to the semiconductor chip after thermal expansion due to reflow soldering. Providing the concave portion toward the peripheral edge of the circuit board further suppresses the generation and progression of cracks between the electrode and the solder.

  In the circuit board of the present invention, it is preferable that the electrode is disposed in a peripheral region of the circuit board.

  The stress generated between the electrode and the solder is larger as the electrode is arranged in the peripheral region of the circuit board. By arranging the electrodes having recesses in the peripheral region, the generation and progression of cracks that are likely to occur particularly in the electrodes in the peripheral region can be suppressed.

  In the circuit board of the present invention, at least one part of the electrode is preferably composed of an alloy layer with the electrode material.

  An alloy containing the electrode material is formed by reflow soldering at the joint interface between the electrode and solder. By forming an alloy layer of the same material as this alloy on the solder weld surface in advance, the alloy material part of the joint interface Can be thickened. As a result, it is possible to avoid stress concentration on the alloy portion and to further suppress the occurrence and progression of cracks.

  Further, in the circuit board of the present invention, a plurality of the electrodes are arranged, and the depth of the concave portion of the electrode arranged on the peripheral side is larger than the depth of the concave portion of the electrode arranged on the inner side of the circuit board. It is preferable that this is larger.

In the circuit board of the present invention, the electrode includes a first electrode region located on a bottom surface of the recess,
A second electrode region located higher than the bottom surface;
A step formed between the first electrode region and the second electrode region,
The step is preferably continuous from one edge of the electrode to the other edge.

The first semiconductor device of the semiconductor device of the present invention that achieves the above object includes a semiconductor chip,
A circuit board comprising: a first electrode; and a second electrode having a large recess on the surface as compared with the surface of the first electrode;
It has a junction part which joins said 1st electrode and said 2nd electrode, and said semiconductor chip, It is characterized by the above-mentioned.

Of the semiconductor devices of the present invention that achieve the above object, the second semiconductor device is:
A semiconductor chip;
A circuit board comprising a second electrode having a recess extending from the edge;
It is preferable to have a bonding portion that bonds the semiconductor chip and the second electrode.

  Here, in the second semiconductor device of the semiconductor device according to the present invention, it is preferable that the second electrode is disposed in a peripheral region of the circuit board.

A method for manufacturing a semiconductor device of the present invention that achieves the above object is a method for manufacturing a semiconductor device including a semiconductor chip and a circuit board,
Provide an electrode having a recess extending from the edge on the circuit board,
The semiconductor chip and the electrode are bonded by a bonding portion.

  As described above, according to the present invention, a highly reliable circuit board, semiconductor device, and semiconductor device manufacturing method in which the occurrence of poor contact with a semiconductor chip is suppressed are realized.

  FIG. 4 is a plan view showing the appearance of the first embodiment of the circuit board of the present invention. 5 is an enlarged plan view showing an enlarged corner portion of the circuit board shown in FIG. 4, and FIG. 6 is a cross-sectional view taken along line AA of the circuit board shown in FIG.

  A circuit board 10 shown in FIGS. 4 to 6 is made of a substrate body 11, a solder resist 12 made of an insulating resin, and copper (Cu) for electrically coupling to a semiconductor chip as shown in FIG. It has the electrode 13 which becomes. The solder resist 12 and the electrode 13 are formed on the surface of the substrate body 11. Although wiring made of a metal such as copper is also provided inside the substrate body 11 following each electrode 13, illustration thereof is omitted.

  A BGA type semiconductor chip 20 is surface-mounted by soldering on the chip mounting area 15 of the circuit board 10. As shown in FIG. 4, the electrodes 13 of the circuit board 10 are arranged in a matrix corresponding to the electrodes 21 of the semiconductor chip 20 in the chip mounting region 15. In the present embodiment, the upper surface of each electrode 13 is exposed in a circular shape, and this exposed portion is a welding surface F on which solder is welded. Of the electrodes 13 arranged in a matrix, a stepped portion H and a concave portion L are formed on the welding surface F of the electrode 13A arranged in the peripheral region on the outer peripheral side, and the stepped portion H is higher than the concave portion L. . On the other hand, the electrode 13B surrounded by the electrode 13A and arranged on the inner side has the solder welding surface F formed flat and has no recess. Compared to the welding surface F, which is the electrode surface of the electrode 13B, the electrode 13A having a recess is referred to as an anchor electrode 13A. The anchor electrode 13A corresponds to an example of the electrode referred to in the circuit board of the present invention and the second electrode referred to in the semiconductor device of the present invention, and the electrode 13B excluding the anchor electrode 13A among the arranged electrodes 13 is the present invention. This corresponds to an example of the first electrode in the semiconductor device.

The stepped portion H and the recessed portion L of each anchor electrode 13A are provided at a position in contact with an edge portion E corresponding to a circumferential portion exposed in a circular shape. More specifically, as shown in FIG. 5, the step H of each anchor electrode 13A extends from the edge E of the anchor electrode 13A and is closer to the center 15c (see FIG. 4) in the mounting region. Is provided. The recess L extends from the edge E of the anchor electrode 13 </ b> A and is provided toward the periphery in the mounting region of the circuit board 10. Of the welding surface F of the anchor electrode 13A, the portion located at the bottom surface of the recess L is referred to as a first electrode region, and the portion higher than the bottom surface of the recess L, that is, the stepped portion H is defined as the second electrode region. Called.
Since the first electrode region and the second electrode region are integral with the recess L and the stepped portion H, the description will be continued with the same reference numerals L and H. A standing wall S is formed between the first electrode region L and the second electrode region H. As better shown in FIG. 5, the standing wall S continuously extends from a part of the edge E of the solder welding surface to another part. The standing wall S corresponds to an example of a step according to the present invention. FIG. 7 is a partial cross-sectional view showing a mounting structure of a semiconductor device including the circuit board shown in FIGS. Part (A) in FIG. 7 shows a state before mounting, and part (B) shows a state after mounting. Since the semiconductor chip 20 shown in FIG. 7 has the same structure as that described with reference to FIG. 1, the same reference numerals are given and detailed description thereof is omitted.

  The semiconductor device 100 according to an embodiment of the present invention is completed by placing the semiconductor chip 20 on the circuit board 10 and soldering in a reflow process as shown in part (B) of FIG. Solder 22A joins electrode 13B and anchor electrode 13A to semiconductor chip 20. The solder 22A corresponds to an example of the joint portion referred to in the present invention.

  The circuit board 10 has a higher coefficient of thermal expansion than the semiconductor chip 20 and is solder-connected in a state where the circuit board 10 is larger than the semiconductor chip 20 in reflow soldering. For this reason, when the temperature of the circuit board decreases after the solder 22A is solidified, the circuit board tends to contract, and a force in the direction indicated by the arrow D12 is applied from the electrode to the solder.

  FIG. 8 is an enlarged cross-sectional view showing a portion of the anchor electrode 13A_5 in the mounting structure shown in FIG.

As described above, when the circuit board 10 contracts, a force in the direction indicated by the arrow D2 is applied to the solder 22A from the anchor electrode 13A_5. However, according to the circuit board 10 of the present embodiment, the anchor electrode 13A_5 is applied. It is difficult for cracks to enter between the solder 22A and the solder 22A. This is because the area where the solder 22A is fused is expanded by the amount of the standing wall S provided between the step H and the recess L, the stress is dispersed, and the fused surface is It is thought that it is complicated and the coupling is dense. Further, since the standing wall S receives the force in the direction indicated by the arrow D2 at an angle close to the vertical, a tensile force works instead of a shearing force. For this reason, it is thought that a crack is hard to enter and the crack to enter does not advance easily. In addition, the stress caused by the difference in the coefficient of thermal expansion described above is larger in the electrode disposed in the peripheral region, but according to the circuit board 10 of the present embodiment, the electrode disposed in the peripheral region is used as the anchor electrode. The stress is efficiently reduced. Here, the description has been given of the form in which the anchor electrodes 13A are arranged in one row outside the electrodes 13 arranged in a matrix. However, in the circuit board of the present invention, the anchor electrodes are The arrangement is not limited to one column, and a plurality of columns may be arranged.

  Subsequently, a simulation model is created for the mounting structure of the semiconductor device, and the results of obtaining the stress by simulation will be described.

  FIG. 9 is a diagram illustrating a simulation model of the mounting structure of the semiconductor device. FIG. 10 is a diagram showing the arrangement of anchor electrodes on the circuit board used in the simulation.

  The simulation model of the semiconductor device shown in FIG. 9 represents a mounting structure in which a semiconductor chip is soldered to a circuit board as a three-dimensional model. In the simulation, after the solder reflow process, when the circuit board is contracted more than the semiconductor chip on the assumption that the temperature has further decreased from the state where the solder is solidified, each of the electrodes arranged on the circuit board is further subdivided. The distribution of stress at each point was obtained. Since the mounting structure to be simulated, that is, the circuit board and the semiconductor chip are symmetrical in the front-rear direction and the left-right direction along the circuit board, the simulation is performed on a quarter region of the mounting structure. It was.

  Five types of models 210, 220, 230, 240, and 250 having different anchor electrode distributions were created as circuit board simulation models. In the first model (Model-1) 210, the anchor electrodes 213A are arranged in one row in the peripheral region, and in the second model (Model-2) 220, the anchor electrodes 223A are arranged in two rows in the peripheral region. In the third model (Model-3) 230, the anchor electrodes 233A are arranged in three rows in the peripheral region, and in the fourth model (Model-4) 240, the anchor electrodes 243A are arranged in four rows in the peripheral region. In the fifth model (Model-5) 250, the anchor electrodes 253A are arranged in five rows in the peripheral region. All electrodes including the anchor electrode have a diameter of 0.7 mm and are arranged at a pitch of 2 mm. In addition, as a reference model, a reference model 260 (Reference) 260 provided with no anchor electrode as shown in FIG. 11 was also created.

  In FIGS. 10 and 11, the value of the maximum stress among the stresses obtained as simulation results for each model is also shown. As a result of this simulation, it was confirmed that the maximum stress was generated particularly in the recess L of the anchor electrode. The maximum stress is 226 MPa in the case of the reference model 260 not provided with the anchor electrode, whereas the model 210 to 250 maximum stress provided with the anchor electrodes 213A to 253A has one row of anchor electrodes. It was confirmed that it decreased to 223 MPa, 218 MPa, 210 MPa, 206 MPa, and 200 MPa, respectively, in accordance with the increase from 5 to 5 rows. Thus, it was confirmed that the stress was relieved by the anchor electrode in which the concave portion was formed.

  Next, a method for manufacturing a semiconductor device will be described. In the semiconductor device 100 shown in part (B) of FIG. 7, first, the anchor electrode 13A and the other electrode 13B are formed on the circuit board 10, and then the semiconductor chip 20 and the electrodes 13A and 13B are joined by the solder 22A. Manufactured by. A manufacturing method for forming anchor electrodes on a circuit board will be described.

  FIG. 12 is a partial cross-sectional view illustrating a circuit board manufacturing process. FIG. 12 shows the process of forming electrodes on the circuit board in order from part (A) to part (F). FIG. 13 is a partial plan view for explaining the manufacturing process of the circuit board. The parts (B), (D), (E), and (F) in FIG. 13 correspond to (B), (D), (E), and (F) in FIG. 12, respectively. Here, a circuit board in which anchor electrodes are arranged in three rows on the outside as shown as the third model in FIG. 10 will be described. FIG. 13 shows a corner portion of a circuit board in which anchor electrodes are arranged in three rows.

  In order to manufacture a circuit board, first, a substrate body 311 having a wiring pattern 312 made of copper (Cu) partly serving as an electrode is formed on the surface, and a solder resist coating shown in Part (A) of FIG. In the process, a solder resist 313 is coated on the surface of the substrate body 311. Next, in the pattern etching step shown in Part (B) of FIGS. 12 and 13, a hole 313 a is formed in the shape of the electrode by etching the solder resist 313. Next, a resist 314 is further coated on the solder resist 313 layer of the substrate body 311 in a resist coating process shown in Part (C) of FIG. Next, in the etching step shown in Part (D) of FIGS. 12 and 13, a hole 314a having a shape corresponding to the step portion of the anchor electrode is formed in the resist 314 by etching. A copper wiring pattern 312 is exposed at the bottom of the hole 314a. Next, electrolytic copper plating is performed in the plating step shown in Part (E) of FIGS. As a result, the copper plating layer 315 is deposited on the bottom of the hole 314a in the wiring pattern 312. The copper plating layer 315 is made of the same copper material as the wiring pattern 312 and is integrated with the wiring pattern 312.

  Next, when the resist 314 is removed in the resist removal step shown in Part (F) of FIGS. 12 and 13, the circuit board 310 in which the anchor electrode 316 is provided on the substrate body 311 is completed. The anchor electrode 316 has a recess L extending from the edge.

  The electrodes other than the anchor electrode 316 are not shown in the figure, but are not formed in the etching step shown in Part (D) of FIG. For the electrodes other than the anchor electrode 316, an anchor electrode is formed by forming a hole over the entire electrode in the etching process shown in Part (D) of FIG. 13 and copper plating in the plating process of Part (E). It is also possible to form the same height as the stepped portion H in 316.

  Thus, the circuit board provided with the anchor electrode shown in the model of FIG. 10 and FIG. 4 can be manufactured.

  Subsequently, a second embodiment of the present invention will be described. In the following description of the second embodiment, differences from the embodiments described so far will be described.

  FIG. 14 is a partial cross-sectional view showing a second embodiment of the circuit board of the present invention.

  The circuit board 40 shown in FIG. 14 is different from the circuit board of the first embodiment shown in FIG. 6 in that a part of the anchor electrode 43A is made of an alloy layer 47. The alloy layer 47 is formed on the solder welding surface F of the anchor electrode 43A. In the present embodiment, the alloy layer 47 is also formed on the solder welding surface F of the electrode 43B other than the anchor electrode 43A. The alloy layer 47 is formed of the same material as the alloy formed at the interface by Sn-Ag-Cu solder welding to the anchor electrode 43A. More specifically, the alloy layer 47 is formed of a CuSn alloy composed of copper Cu, which is a material of the anchor electrode 43A, and tin Sn, which is a part of Sn—Ag—Cu solder.

  FIG. 15 is a partial cross-sectional view showing a state in which a semiconductor device is completed by mounting a semiconductor chip on the circuit board shown in FIG.

  In the semiconductor device 400 shown in FIG. 15, the CuSn alloy layer 47 is formed in advance on the anchor electrode 43A. For this reason, it becomes possible to form a CuSn alloy layer thicker than the film-like CuSn alloy formed at the time of reflow soldering shown in FIG.

  In the semiconductor device 400, the joint portion of the anchor electrode 43A with the solder is made of three kinds of metals made of Cu / CuSn alloy / Sn—Ag—Cu. There is a relationship of Cu> CuSn> Sn—Ag—Cu between the elastic moduli which are mechanical properties of these three kinds of metals. The elastic modulus of Cu is about twice that of CuSn, the elastic modulus of CuSn is about twice that of Sn—Ag—Cu, and the elastic modulus of Cu is about four times that of Sn—Ag—Cu.

  In the semiconductor device 400, stress caused by contraction after expansion and impact force due to dropping or the like are concentrated on a thin part among parts having different mechanical properties.

  As described with reference to FIG. 3, when Sn—Ag—Cu solder is fused to an electrode made of copper in solder bonding, a CuSn alloy layer is not formed on the electrode in advance, but between the electrode and the solder. A CuSn alloy is formed. However, since the melting point of Sn—Ag—Cu solder is high, the CuSn alloy becomes thin. On the other hand, in the semiconductor device 400 shown in FIG. 15, the CuSn alloy layer 47 is formed in advance on the anchor electrode 43A, and the CuSn alloy layer between the Cu of the electrode and the Sn—Ag—Cu solder can be thickened. it can. As a result, the stress due to shrinkage after expansion in the CuSn alloy layer and the impact force due to dropping or the like are reduced. Therefore, the generation and progress of cracks can be suppressed.

  FIG. 16 is a partial cross-sectional view illustrating a process for forming a CuSn alloy layer in advance on the anchor electrode of the circuit board shown in FIG. FIG. 16 shows a process of forming a CuSn alloy layer in advance on the anchor electrode in order from part (A) to part (C).

  In order to form the CuSn alloy layer on the anchor electrode, first, the anchor electrode 43A is formed on the substrate body 41 as shown in Part (A) of FIG. 16, and then the anchor electrode as shown in Part (B). An Sn or CuSn paste 47P is applied to the top of 43A. The process of applying the paste 47P includes resist forming, screen printing, and resist stripping processes (not shown). Next, as shown in Part (C), a Cu6Sn5 alloy layer is formed by performing a heat treatment. Note that Sn can be deposited by a process different from the paste application shown in Part (B) of FIG.

  FIG. 17 is a partial cross-sectional view illustrating a process of forming a CuSn alloy layer in advance on the anchor electrode by a process different from that in FIG.

  In the method of FIG. 17, after forming the anchor electrode 43A on the substrate body 41 as shown in Part (A), the Sn layer 47Q is formed on the top of the anchor electrode 43A by electrolytic plating as shown in Part (B). Form. The electroplating process includes plating seed layer formation, resist coating / pattern formation, plating, resist stripping, and plating seed layer stripping (not shown). Finally, the Cu6Sn5 alloy layer is formed by performing heat treatment as shown in Part (C).

  Here, a circuit board having the structure described in the second embodiment was created, and a connection reliability test of a semiconductor device having a semiconductor chip mounted on the circuit board was performed.

  First, an anchor electrode was formed on a circuit board by the manufacturing method described with reference to FIG. More specifically, a solder resist having a film thickness of about 30 to 50 μm is formed on the copper foil formed on the substrate body 41 (see Part (A) of FIG. 12), and a portion to be an anchor electrode is formed by pattern etching. It was removed (see part (B) of FIG. 12). A step portion made of copper was formed by electrolytic plating on a part of the portion to be the anchor electrode (see Part (E) of FIG. 12). An Sn layer having a film thickness of about 5 to 7 μm is formed on the formed anchor electrode (see FIG. 17), the resist is removed (see Part (F) in FIG. 12), and then 15 ° C. in a nitrogen atmosphere at 220 ° C. A heat treatment of ~ 20 hours was applied. In this way, a circuit board having a step portion and an alloy layer formed on the anchor electrode was produced.

  Next, after the RM type flux is applied to the circuit board thus prepared, the semiconductor chip provided with Sn-3.0Ag-0.5Cu solder balls (freezing point 217 ° C.) is positioned so that the solder balls are aligned with the electrodes. They were put together and solder reflow bonding was performed in a nitrogen atmosphere of a conveyor furnace. The solder reflow conditions were 217 ° C. or higher and 250 ° C. or lower, which is the solidification point of the solder, for 2 minutes. In this way, a sample of a semiconductor device having a semiconductor chip mounted on a circuit board was prepared. Separately from this sample, a semiconductor chip was mounted on a circuit board on which an electrode on which no step portion or alloy layer was formed was arranged, and a semiconductor device of a reference example was produced.

  Two types of reliability tests were performed on the prepared semiconductor device of the sample and the semiconductor device of the reference example. The first test is a temperature cycle test, in which a temperature cycle consisting of −55 ° C. (30 minutes) and 125 ° C. (30 minutes) is repeated 500 times, and then the electric current between the circuit board electrode and the semiconductor chip electrode is measured. Measure whether the resistance has increased. The second test is a drop impact test, and it is measured whether or not the electrical resistance has increased after repeating impact application by free fall from a height of 10 cm 200 times.

  As a result of the first test, the resistance of 7 of the 20 semiconductor devices in the reference example increased. On the other hand, of the 20 semiconductor devices, the number of the semiconductor device samples according to the examples of the present invention increased in resistance. Further, as a result of the second test, the resistance of the semiconductor device of the reference example increased for 15 of the 20 devices. On the other hand, of the 20 semiconductor devices, the number of the semiconductor device samples according to the examples of the present invention increased in resistance.

  Thus, it was confirmed that the semiconductor device provided with the circuit board of the example can suppress a decrease in reliability.

  Subsequently, a third embodiment of the present invention will be described. In the following description of the third embodiment, differences from the embodiments described so far will be described.

  FIG. 18 is a partial cross-sectional view showing a circuit board according to a third embodiment of the present invention. FIG. 18 shows the vicinity of one anchor electrode in the circuit board.

  In the circuit board 50 shown in FIG. 18, the stepped portion H of the anchor electrode 53A is different from the other embodiments in that the stepped portion H is formed higher than the recessed portion L by laminating the CuSn alloy layer. That is, in the circuit board 50, the portion where the CuSn alloy layer is not laminated becomes the recess L due to the lamination of the CuSn alloy layer. In the manufacture of the circuit board 50, an electrode made of Cu is formed on the board body 51, and a CuSn alloy layer is laminated on a part of the top part of these electrodes which are to be the anchor electrode 53A. The step portion H is higher than the partial recess portion L of the CuSn alloy layer, and the concave portion L is lower than the step portion H of the CuSn alloy layer. In the manufacture of the circuit board 50, the formation of the thick CuSn alloy layer can also be used as the formation of the stepped portion H, so that the manufacture of the circuit board is simplified.

  Subsequently, a fourth embodiment of the present invention will be described. In the following description of the fourth embodiment, differences from the above-described embodiments will be described.

  FIG. 19 is a partial cross-sectional view showing a circuit board according to a fourth embodiment of the present invention. FIG. 19 shows the vicinity of one anchor electrode of the circuit board together with the solder. The solder is schematically shown.

  A circuit board 60 shown in FIG. 19 is formed such that the first electrode region L and the second electrode region H overlap each other in plan view. More specifically, the standing wall S formed at the boundary between the stepped portion H and the remaining recessed portion L on the solder welding surface F of the anchor electrode 63A protrudes from the stepped portion H into an overhang shape, and has a shape erected at an acute angle. Have.

  Subsequently, a fifth embodiment of the present invention will be described. In describing the fifth embodiment below, differences from the above-described embodiments will be described.

  FIG. 20 is a partial cross-sectional view showing a circuit board according to a fifth embodiment of the present invention. FIG. 20 shows a portion near one anchor electrode in the circuit board together with solder. The solder is schematically shown.

  The circuit board 70 shown in FIG. 20 has a plurality of recesses L and L ′ formed in the anchor electrode 73A. More specifically, a recess L ′ is further formed in the recess L. By further forming the recesses in the recesses, the stress dispersion effect is enhanced.

  The anchor electrode 73A shown in FIG. 20 can be formed by forming a portion that becomes the recess L by the manufacturing method described above, and forming the stepped portion H by repeating the same method as the recess L for a narrower range. it can.

  Subsequently, a sixth embodiment of the present invention will be described. In describing the sixth embodiment below, differences from the above-described embodiments will be described.

  FIG. 21 is a partial sectional view showing a circuit board according to the sixth embodiment of the present invention. FIG. 21 shows a cross section of a circuit board including four anchor electrodes 83A_1, 83A_2, 83A_3, 83A_4 and an electrode 83B other than the anchor electrode.

  In the circuit board 80 shown in FIG. 21, the depths of the recesses L1, L2, L3, and L4 formed in the anchor electrodes 83A_1, 83A_2, 83A_3, and 83A_4 are different from each other, and these depths are anchor electrodes arranged on the peripheral side. It is so big. For this reason, it is formed at the boundary between the step portions H1, H2, H3, H4 formed on the anchor electrodes 83A_1, 83A_2, 83A_3, 83A_4, respectively, and the recesses L1, L2, L3, L4 adjacent to the step portions, respectively. The heights of the standing walls S1, S2, S3, and S4 are different from each other, and the height of the standing wall is higher as the anchor electrode is disposed in the peripheral region. The circuit board 80 shown in FIG. 21 can be manufactured by performing copper plating in a state in which some of the plurality of electrodes are masked with a resist, and repeating a cycle of copper plating while changing the masking electrode. .

  Here, the example in which the height of the concave portion is reduced as the anchor electrode arranged in the peripheral region has been described, but the present invention is not limited to this, and for example, the height of the concave portion is constant. The anchor electrode arranged in the peripheral region may be formed so that the stepped portion becomes higher.

  Moreover, in embodiment mentioned above, although the example of copper was demonstrated as a material of the electrode of this invention, this invention is not limited to this, For example, metals other than copper, such as aluminum, may be sufficient.

  In the above-described embodiment, the example of the solder material containing Sn is described as the solder bump material. However, the present invention is not limited to this. For example, instead of Sn as the solder bump material, It may contain Bi, In, Zn, Ag, Sb, Cu, or may contain Bi, In, Zn, Ag, Sb, Cu in addition to Sn.

  In the above-described embodiment, the example of the circuit board on which both the electrode other than the anchor electrode and the anchor electrode are formed has been described, but the present invention is not limited to this. In the present invention, at least a part of the electrode may be an anchor electrode. For example, all the electrodes may be anchor electrodes.

  Hereinafter, various embodiments of the present invention will be additionally described.

(Appendix 1)
A circuit board comprising an electrode having a recess extending from an edge.

(Appendix 2)
The circuit board according to appendix 1, wherein the concave portion is provided toward a peripheral edge of the circuit board.

(Appendix 3)
The circuit board according to appendix 1 or 2, wherein the electrode is disposed in a peripheral region of the circuit board.

(Appendix 4)
At least one part of the said electrode consists of an alloy layer with the said electrode material, The circuit board of any one of Additional remark 1 to 3 characterized by the above-mentioned.

(Appendix 5)
The circuit board according to appendix 4, wherein the recess is formed by the alloy layer.

(Appendix 6)
The circuit board according to any one of appendices 1 to 5, wherein a plurality of the recesses are formed.

(Appendix 7)
The circuit board according to any one of appendices 1 to 6, wherein a plurality of the electrodes having different depths of the recesses are arranged on the circuit board.

(Appendix 8)
The circuit board according to appendix 7, wherein the depth of the concave portion of the electrode arranged on the peripheral side is larger than the depth of the concave portion of the electrode arranged on the inner side of the circuit board. .

(Appendix 9)
The electrode includes a first electrode region located on a bottom surface of the recess;
A second electrode region located higher than the bottom surface;
A step formed between the first electrode region and the second electrode region,
The circuit board according to any one of appendices 1 to 8, wherein the step is continuous from one edge of the electrode to the other edge.

(Appendix 10)
The circuit board according to appendix 9, wherein the first electrode region and the second electrode region overlap each other in plan view.

(Appendix 11)
A semiconductor chip;
A circuit board comprising: a first electrode; and a second electrode having a large recess on the surface as compared to the surface of the first electrode;
A semiconductor device comprising: a joining portion that joins the first electrode, the second electrode, and the semiconductor chip.

(Appendix 12)
The second electrode is disposed in a peripheral region of the circuit board;
The semiconductor device according to appendix 11, wherein the first electrode is disposed on the inner side of the peripheral region.

(Appendix 13)
A semiconductor chip;
A circuit board comprising a second electrode having a recess extending from the edge;
A semiconductor device comprising: a joining portion that joins the semiconductor chip and the second electrode.

(Appendix 14)
14. The semiconductor device according to appendix 13, wherein the second electrode is disposed in a peripheral region of the circuit board.

(Appendix 15)
15. The semiconductor device according to any one of appendices 11 to 14, wherein the recess is provided toward a peripheral edge of the circuit board.

(Appendix 16)
16. The semiconductor device according to any one of appendices 11 to 15, wherein at least a part of the second electrode is made of an alloy layer with the electrode material.

(Appendix 17)
The semiconductor device according to appendix 16, wherein the recess is formed by the alloy layer.

(Appendix 18)
18. The semiconductor device according to any one of appendices 11 to 17, wherein a plurality of the recesses are formed.

(Appendix 19)
19. The semiconductor device according to any one of appendices 11 to 18, wherein a plurality of the second electrodes having different depths of the recesses are arranged on the circuit board.

(Appendix 20)
A method of manufacturing a semiconductor device including a semiconductor chip and a circuit board,
Providing an electrode having a recess extending from an edge on the circuit board;
A manufacturing method, wherein the semiconductor chip and the electrode are bonded together by a bonding portion.

It is a partial cross section figure explaining the mounting structure in the semiconductor device of a prior art. It is an expanded sectional view which shows a part of mounting structure shown in FIG. FIG. 2 is an enlarged cross-sectional view schematically showing only an electrode portion in FIG. 1. It is a top view which shows the external appearance of 1st Embodiment of the circuit board of this invention. It is an enlarged plan view which expands and shows the corner | angular part of the circuit board shown in FIG. FIG. 5 is a cross-sectional view of the circuit board shown in FIG. 4 taken along the line AA. FIG. 5 is a partial cross-sectional view illustrating a mounting structure in a semiconductor device including the circuit board illustrated in FIG. 4. It is an expanded sectional view which shows the part of anchor electrode 13A_5 among the mounting structures shown in FIG. It is a figure which shows the simulation model of the mounting structure of a semiconductor device. It is a figure which shows the model of the circuit board used for simulation. It is a figure which shows the arrangement | sequence of a reference model. It is a fragmentary sectional view explaining the manufacturing process of a circuit board. It is a partial top view explaining the manufacturing process of a circuit board. It is a partial cross section figure which shows 2nd Embodiment of the circuit board of this invention. FIG. 15 is a partial cross-sectional view showing a state where a semiconductor chip is mounted on the circuit board shown in FIG. 14 and a semiconductor device is completed. FIG. 15 is a partial cross-sectional view illustrating a process for forming a CuSn alloy layer in advance on the anchor electrode of the circuit board shown in FIG. 14. FIG. 17 is a partial cross-sectional view illustrating a process for forming a CuSn alloy layer in advance on the anchor electrode by a process different from that in FIG. 16. It is a fragmentary sectional view showing a circuit board of a 3rd embodiment of the present invention. It is a fragmentary sectional view showing a circuit board of a 4th embodiment of the present invention. It is a fragmentary sectional view showing a circuit board of a 5th embodiment of the present invention. It is a fragmentary sectional view showing a circuit board of a 6th embodiment of the present invention.

Explanation of symbols

20 Semiconductor chip 22A Solder (joint part)
10, 40, 50, 70, 80, 90, 310 Circuit board 13A, 43A, 53A, 63A, 73A, 316 Anchor electrode (electrode, second electrode)
13B electrode (first electrode)
15 Chip mounting area 47 CuSn alloy layer (alloy layer)
100, 400 Semiconductor device F Solder welding surface H, H1, H2, H3, H4 Stepped portion L, L1, L2, L3, L4 Recessed portion S, S1, S2, S3, S4 Standing wall (step)

Claims (3)

A circuit board having a plurality of electrodes electrically coupled to a semiconductor chip having a recess extending from an edge,
The electrode is provided with an alloy layer containing the electrode material ,
The electrode is disposed on a peripheral side of the circuit board in a region where the semiconductor chip is mounted,
The electrode includes a first electrode region located on a bottom surface of the recess;
A second electrode region located higher than the bottom surface;
A step formed between the first electrode region and the second electrode region,
The step is continuous from one edge of the electrode to the other edge in a straight line shape or a polygonal line shape in plan view,
The first electrode region is disposed on the peripheral side of the circuit board in the region where the semiconductor chip is mounted, and is provided on the electrode toward the peripheral side of the circuit board as viewed from the inside of the circuit board.
The circuit board characterized in that the step of the electrode disposed on the peripheral side of the circuit board is larger than the step of the electrode disposed on the inner side of the circuit board. The circuit board according to claim 1, wherein the alloy layer is formed of a CuSn alloy layer. 3. The circuit board according to claim 1, wherein the first electrode region and the second electrode region are formed to overlap each other in a plan view.

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