JP3246010B2 - Electrode structure of flip-chip mounting substrate - Google Patents
Electrode structure of flip-chip mounting substrateInfo
- Publication number
- JP3246010B2 JP3246010B2 JP32234992A JP32234992A JP3246010B2 JP 3246010 B2 JP3246010 B2 JP 3246010B2 JP 32234992 A JP32234992 A JP 32234992A JP 32234992 A JP32234992 A JP 32234992A JP 3246010 B2 JP3246010 B2 JP 3246010B2
- Authority
- JP
- Japan
- Prior art keywords
- land
- substrate
- flip
- chip mounting
- mounting substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16237—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area disposed in a recess of the surface of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16238—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area protruding from the surface of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8119—Arrangement of the bump connectors prior to mounting
- H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8119—Arrangement of the bump connectors prior to mounting
- H01L2224/81192—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8119—Arrangement of the bump connectors prior to mounting
- H01L2224/81193—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/81385—Shape, e.g. interlocking features
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
- H01L2224/8238—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/82385—Shape, e.g. interlocking features
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3457—Solder materials or compositions; Methods of application thereof
Description
【０００１】[0001]
【産業上の利用分野】本発明は、フリップチップ実装用
基板の電極構造に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electrode structure of a flip-chip mounting substrate.
【０００２】[0002]
【従来の技術】一般に、フリップチップ実装において
は、半導体チップ上にバンプを形成し、これをフェイス
ダウンで配線基板導体と接続する。配線基板上、つまり
フリップチップ実装用の基板上には半導体チップのバン
プに対応して電極パッドが設けられており、これらを突
き合わせた状態で熱圧着あるいは加熱溶着により基板上
に半導体チップを実装していた。2. Description of the Related Art In general, in flip-chip mounting, bumps are formed on a semiconductor chip and are connected face-down to a wiring board conductor. Electrode pads are provided on the wiring board, that is, on the flip-chip mounting board, corresponding to the bumps of the semiconductor chip, and the semiconductor chip is mounted on the board by thermocompression bonding or heat welding with these butted against each other. I was
【０００３】図６は従来例を説明するための図であり、
図において、１はフリップチップ実装用基板（以下、単
に基板と称す）、２は基板１上に設けられた電極パッ
ド、３は半導体チップ、４は半導体チップ３上に形成さ
れたバンプである。基板１に設けられた電極パッド２
は、基板１の回路パターン上に設けられたランド５と、
このランド５上にメッキ処理等で被着されたハンダ層６
から成る。FIG. 6 is a diagram for explaining a conventional example.
In the drawing, reference numeral 1 denotes a flip-chip mounting substrate (hereinafter, simply referred to as a substrate), 2 denotes an electrode pad provided on the substrate 1, 3 denotes a semiconductor chip, and 4 denotes a bump formed on the semiconductor chip 3. Electrode pad 2 provided on substrate 1
Is a land 5 provided on the circuit pattern of the substrate 1,
A solder layer 6 applied on the land 5 by plating or the like.
Consists of
【０００４】基板１上にフェースダウンで半導体チップ
３を実装する場合は、まず図示のように電極パッド２に
バンプ４を位置合わせして載せ、この状態から熱圧着等
の手段により両者を接合して基板１と半導体チップ３を
電気的に接続する。When the semiconductor chip 3 is mounted face down on the substrate 1, the bumps 4 are first positioned on the electrode pads 2 as shown in the figure, and the two are joined together by means such as thermocompression bonding. To electrically connect the substrate 1 and the semiconductor chip 3.
【０００５】[0005]
【発明が解決しようとする課題】しかしながら従来にお
いては、基板１のランド５にハンダ層６を被着させた
際、ハンダ層６の中央部分が盛り上がった状態となるた
め、この上からバンプ６を載せると両者間で位置ずれを
起こしやすく、正確な位置決めが難しいといった問題が
あった。また、上記位置ずれが起こると電極パッド２と
バンプ４の接合部が小さくなるため、接合強度が規定以
上に得られず不良となったり、ハンダ付けの信頼性が著
しく損なわれるなどの問題もあった。However, in the prior art, when the solder layer 6 is adhered to the land 5 of the substrate 1, the central portion of the solder layer 6 is in a raised state. When they are mounted, there is a problem that positional deviation easily occurs between the two, and accurate positioning is difficult. In addition, when the above-mentioned displacement occurs, the bonding portion between the electrode pad 2 and the bump 4 becomes small, so that there is a problem that the bonding strength cannot be obtained more than a specified value, resulting in a failure, and the reliability of soldering is significantly impaired. Was.
【０００６】本発明は、上記問題を解決するためになさ
れたもので、基板上の電極パッドに対して半導体チップ
上のバンプを正確且つ容易に位置決めすることができる
フリップチップ実装用基板の電極構造を提供することを
目的とする。SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an electrode structure of a flip-chip mounting substrate capable of accurately and easily positioning a bump on a semiconductor chip with respect to an electrode pad on the substrate. The purpose is to provide.
【０００７】[0007]
【課題を解決するための手段】本発明は、上記目的を達
成するためになされたもので、フリップチップ実装用基
板上に設けられたランドと、このランド上に被着された
ハンダ層とからなる電極パッドの構造において、ランド
の上面に、平面視略十字形に形成された所定深さの凹部
を有するフリップチップ実装用基板の電極構造である。SUMMARY OF THE INVENTION The present invention has been made to achieve the above-mentioned object, and comprises a land provided on a flip-chip mounting substrate and a solder layer adhered on the land. This is an electrode structure of a flip-chip mounting substrate having a concave portion of a predetermined depth formed in a substantially cross shape in a plan view on an upper surface of a land in an electrode pad structure.
【０００８】[0008]
【作用】本発明のフリップチップ実装用基板の電極構造
においては、ランドの上面に、平面視略十字形に形成さ
れた所定深さの凹部を有する構成とすることで、このラ
ンド上に被着されるハンダ層もランドの表面形状に沿っ
て形成される。これにより、半導体チップを実装する際
には、バンプと電極パッドの位置ずれが抑制され、両者
間の位置決めが正確且つ容易に行えるようになる。According to the electrode structure of the flip-chip mounting substrate of the present invention, a substantially cross-shaped planar view is formed on the top surface of the land.
With the configuration having the concave portion having the predetermined depth, the solder layer adhered on the land is also formed along the surface shape of the land. As a result , when mounting a semiconductor chip
In this case, the displacement between the bump and the electrode pad is suppressed, and the positioning between the two can be performed accurately and easily.
【０００９】[0009]
【実施例】以下、本発明の実施例について図面を参照し
ながら詳細に説明する。図１は本発明に係わるフリップ
チップ実装用基板の電極構造の一実施例を説明するため
の図であり、図において、１は基板（フリップチップ実
装用基板）、２は基板１上に設けられた電極パッド、３
は半導体チップ、４は半導体チップ３上に形成されたバ
ンプである。基板１に設けられた電極パッド２は、基板
１の回路パターン上に設けられたランド５と、このラン
ド５上にメッキ処理等で被着されたハンダ層６から成
る。Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a view for explaining an embodiment of an electrode structure of a flip-chip mounting substrate according to the present invention. In the drawing, 1 is a substrate (flip-chip mounting substrate), and 2 is provided on a substrate 1. Electrode pad, 3
Denotes a semiconductor chip, and 4 denotes a bump formed on the semiconductor chip 3. The electrode pad 2 provided on the substrate 1 includes a land 5 provided on a circuit pattern of the substrate 1 and a solder layer 6 applied on the land 5 by plating or the like.
【００１０】本実施例の電極構造においては、基板１上
に設けられたランド５の上面に所定深さの凹部７が設け
られている。ランド５の上面に凹部７を設ける手段とし
ては、例えば基板１上に設けられたランド５に対して、
先端に丸みをつけた突起物をプレス金型等を用いて圧接
し、これによりランド７の上面に例えば図２（ａ）に示
すような凹部７を形成する方法や、基板１上に設けられ
たランド５上にフォトレジストをパターニングし、これ
にエッチング処理を施して例えば図２（ｂ）に示すよう
な凹部７を形成する方法がある。In the electrode structure of this embodiment, a concave portion 7 having a predetermined depth is provided on the upper surface of a land 5 provided on the substrate 1. As means for providing the concave portion 7 on the upper surface of the land 5, for example, for the land 5 provided on the substrate 1,
A protrusion having a rounded tip is pressed into contact with a press die or the like, thereby forming a recess 7 on the upper surface of the land 7 as shown in FIG. There is a method of forming a concave portion 7 as shown in FIG.
【００１１】また、上記以外の手段としては、図３に示
すような方法も考えられる。すなわち、図３（ａ）に示
すように、まず基板１上にベースとなる銅製のランド５
ａを設ける。次いで、図３（ｂ）に示すように、ランド
５ａ上にレジスト８をパターニングする。続いて、図３
（ｃ）に示すように、無電解メッキにより銅製のランド
５ｂを積層する。次に、図３（ｄ）に示すように、先程
パターニングしたレジスト８を除去する。これによりラ
ンド５の上面に凹部７が設けられる。As a means other than the above, a method as shown in FIG. 3 can be considered. That is, as shown in FIG. 3A, first, a copper land 5 serving as a base is formed on a substrate 1.
a is provided. Next, as shown in FIG. 3B, a resist 8 is patterned on the land 5a. Subsequently, FIG.
As shown in (c), copper lands 5b are laminated by electroless plating. Next, as shown in FIG. 3D, the resist 8 patterned previously is removed. Thereby, the concave portion 7 is provided on the upper surface of the land 5.
【００１２】ここで、ランド５の実施態様としては、例
えば図４（ａ）に示すようにランド５上面を部分的に凹
ませて凹部７を形成したものから、図４（ｂ）に示すよ
うに凹部７を長溝状に形成したもの、さらには図４
（ｃ）に示すように凹部７を平面視略十字形に形成した
ものなど、種々の態様が考えられる。Here, as an embodiment of the land 5, for example, as shown in FIG. 4A, the upper surface of the land 5 is partially recessed to form the concave portion 7, and then as shown in FIG. In which a concave portion 7 is formed in a long groove shape, and FIG.
Various modes are conceivable, such as the one in which the concave portion 7 is formed in a substantially cross shape in a plan view as shown in FIG.
【００１３】こうした種々の手段でランド５の上面に所
定深さの凹部７を設けることにより、その後のハンダプ
リコートやハンダメッキ処理等においては、ランド５に
対してハンダ層６が、その中央部分で盛り上がることな
くランド５の表面形状に沿って被着される。すなわち、
図１、図３（ｅ）に示すように、ランド５上に凹部７が
設けられている場合は、これに被着されるハンダ層６の
上面にも上記凹部７の深さに対応した凹みが形成され
る。By providing the concave portion 7 having a predetermined depth on the upper surface of the land 5 by such various means, in the subsequent solder precoating, solder plating, or the like, the solder layer 6 is applied to the land 5 at the central portion thereof. It is applied along the surface shape of the land 5 without rising. That is,
As shown in FIGS. 1 and 3E, when the recess 7 is provided on the land 5, the upper surface of the solder layer 6 attached to the land 5 also has a recess corresponding to the depth of the recess 7. Is formed.
【００１４】このような電極構造をなす基板１に対して
半導体チップ３を実装する場合は、図１、図３（ｆ）に
示すように、半導体チップ３上のバンプ４が基板１上の
電極部分に形成された凹みに嵌まり込み、これにより基
板１上の電極パッド２に対して半導体チップ３上のバン
プ４が正確に位置決めされる。When the semiconductor chip 3 is mounted on the substrate 1 having such an electrode structure, as shown in FIG. 1 and FIG. The bumps 4 on the semiconductor chip 3 are accurately positioned with respect to the electrode pads 2 on the substrate 1 by fitting into the recesses formed in the portions.
【００１５】ここで、ランド５上面からの凹部７の深さ
としては、ランド５上にハンダ層６を被着させた際にハ
ンダ層６の中央部分が少なくとも盛り上がらない程度、
つまりハンダ層６の中央部分が平坦になるか幾分凹むよ
うに、ランド５の大きさやハンダ層６の厚みなどを調整
して適宜設定するのがよい。ちなみに、位置合わせの容
易性や正確性を考慮すると、後者の方、すなわちハンダ
層６に凹みが形成されている方が、凹みにバンプ４が嵌
り込む為より正確に位置決めがなされて好適である。Here, the depth of the concave portion 7 from the upper surface of the land 5 is such that the central portion of the solder layer 6 does not rise at least when the solder layer 6 is deposited on the land 5.
That is, the size of the land 5 and the thickness of the solder layer 6 are preferably adjusted and set appropriately so that the central portion of the solder layer 6 becomes flat or slightly concave. By the way, in consideration of the ease and accuracy of the alignment, the latter, that is, the one in which the solder layer 6 has a recess, is more preferable because the bump 4 is fitted into the recess, so that the positioning is more accurately performed. .
【００１６】続いて、本発明の電極構造に係わる他の実
施例について図５を参照しながら説明する。なお、本例
では上記実施例と同様の部材に対して同じ符号を付して
説明する。図において、１は基板（フリップチップ実装
用基板）、２は電極パッド、３は半導体チップ、４はバ
ンプである。本例においては、半導体チップ１の個々の
バンプ４に対応して基板１上に設けられたランド５が複
数に分割されており、この分割されたランド５間に所定
深さの凹部７が設けられている。さらに、分割された各
ランド５上にはそれぞれハンダ層６が被着され、これに
より各々のバンプ４に対応する電極パッド２が構成され
ている。Next, another embodiment according to the electrode structure of the present invention will be described with reference to FIG. In this embodiment, the same members as those in the above embodiment are denoted by the same reference numerals and described. In the figure, 1 is a substrate (flip chip mounting substrate), 2 is an electrode pad, 3 is a semiconductor chip, and 4 is a bump. In this example, the lands 5 provided on the substrate 1 corresponding to the individual bumps 4 of the semiconductor chip 1 are divided into a plurality of portions, and a concave portion 7 having a predetermined depth is provided between the divided lands 5. Have been. Further, a solder layer 6 is applied on each of the divided lands 5, whereby the electrode pads 2 corresponding to the respective bumps 4 are formed.
【００１７】このような電極構造をなす基板１に対して
半導体チップ３を実装する場合も、上述した実施例と同
様に、半導体チップ３上のバンプ４が基板１上の電極部
分に形成された凹部７に嵌まり込み、これにより基板１
上の電極パッド２に対して半導体チップ３上のバンプ４
が正確に位置決めされる。When the semiconductor chip 3 is mounted on the substrate 1 having such an electrode structure, the bumps 4 on the semiconductor chip 3 are formed on the electrode portions on the substrate 1 as in the above-described embodiment. The substrate 1 fits into the recess 7,
Bump 4 on semiconductor chip 3 with respect to upper electrode pad 2
Are accurately positioned.
【００１８】[0018]
【発明の効果】以上、説明したように本発明によれば、
基板上に設けられた電極パッドに対して半導体チップ上
のバンプを正確且つ容易に位置決めすることが可能とな
る。これにより、電極パッドとバンプの接合強度は常に
規定以上に得られるようになり、電極パッドとバンプの
位置ずれに伴う接合不良の発生が低減されるとともに、
フリップチップ実装におけるハンダ付けの信頼性向上が
図られる。As described above, according to the present invention,
The bumps on the semiconductor chip can be accurately and easily positioned with respect to the electrode pads provided on the substrate. As a result, the bonding strength between the electrode pad and the bump can always be obtained higher than the specified value, and the occurrence of bonding failure due to the displacement of the electrode pad and the bump is reduced.
The reliability of soldering in flip chip mounting is improved.
【図面の簡単な説明】[Brief description of the drawings]
【図１】本発明に係わるフリップチップ実装用基板の電
極構造の一実施例を説明するための図である。FIG. 1 is a diagram for explaining an embodiment of an electrode structure of a flip-chip mounting substrate according to the present invention.
【図２】実施例におけるランドの形成方法を説明するた
めの図である。FIG. 2 is a view for explaining a method of forming a land in an embodiment.
【図３】実施例におけるランドの他の形成方法を説明す
るための図である。FIG. 3 is a view for explaining another method of forming a land in the embodiment.
【図４】実施例におけるランドの実施態様を説明する図
である。FIG. 4 is a view for explaining an embodiment of a land in the embodiment.
【図５】本発明に係わるフリップチップ実装用基板の電
極構造の他の実施例を説明するための図である。FIG. 5 is a view for explaining another embodiment of the electrode structure of the flip-chip mounting substrate according to the present invention.
【図６】従来例を説明するための図である。FIG. 6 is a diagram for explaining a conventional example.
１ 基板（フリップチップ実装用基板） ２ 電極パッド ３ 半導体チップ ４ バンプ ５ ランド ６ ハンダ層 ７ 凹部 Reference Signs List 1 substrate (flip chip mounting substrate) 2 electrode pad 3 semiconductor chip 4 bump 5 land 6 solder layer 7 recess
───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 平５−21523（ＪＰ，Ａ) 特開 昭49−83860（ＪＰ，Ａ) 特開 昭63−56922（ＪＰ，Ａ) 特開 平３−218036（ＪＰ，Ａ) 特開 平５−235061（ＪＰ，Ａ) 実開 昭58−168136（ＪＰ，Ｕ) (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 21/60 311 ──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-5-21523 (JP, A) JP-A-49-83860 (JP, A) JP-A-63-56922 (JP, A) 218036 (JP, A) JP-A-5-250661 (JP, A) JP-A-58-168136 (JP, U) (58) Fields investigated (Int. Cl. 7 , DB name) H01L 21/60 311
Claims (1)
たランドと、前記ランド上に被着されたハンダ層とから
なる電極パッドの構造において、 前記ランドの上面に、平面視略十字形に形成された所定
深さの凹部を有することを特徴とするフリップチップ実
装用基板の電極構造。1. A structure of an electrode pad comprising a land provided on a flip-chip mounting substrate and a solder layer adhered on the land, wherein the electrode pad is formed on the upper surface of the land in a substantially cross shape in plan view. An electrode structure for a flip-chip mounting substrate, characterized in that the electrode structure has a recessed portion having a predetermined depth.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP32234992A JP3246010B2 (en) | 1992-11-06 | 1992-11-06 | Electrode structure of flip-chip mounting substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP32234992A JP3246010B2 (en) | 1992-11-06 | 1992-11-06 | Electrode structure of flip-chip mounting substrate |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH06151506A JPH06151506A (en) | 1994-05-31 |
| JP3246010B2 true JP3246010B2 (en) | 2002-01-15 |
Family
ID=18142654
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP32234992A Expired - Fee Related JP3246010B2 (en) | 1992-11-06 | 1992-11-06 | Electrode structure of flip-chip mounting substrate |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3246010B2 (en) |
Families Citing this family (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3209977B2 (en) * | 1999-04-02 | 2001-09-17 | 沖電気工業株式会社 | Semiconductor module |
| KR20020058205A (en) * | 2000-12-29 | 2002-07-12 | 마이클 디. 오브라이언 | Circuit board and semiconductor package using it |
| JP4520052B2 (en) * | 2001-01-17 | 2010-08-04 | パナソニック株式会社 | Semiconductor device and manufacturing method thereof |
| KR100429134B1 (en) * | 2001-06-28 | 2004-04-28 | 동부전자 주식회사 | Ball leveling apparatus for attaching ball of a ball grid array package |
| JP4573657B2 (en) * | 2005-01-27 | 2010-11-04 | パナソニック株式会社 | Semiconductor device and manufacturing method thereof |
| JP2006310477A (en) * | 2005-04-27 | 2006-11-09 | Akita Denshi Systems:Kk | Semiconductor device and manufacturing method therefor |
| JP4697600B2 (en) * | 2006-06-01 | 2011-06-08 | Ｔｄｋ株式会社 | Manufacturing method of composite wiring board |
| JP5187714B2 (en) * | 2006-07-11 | 2013-04-24 | 独立行政法人産業技術総合研究所 | Semiconductor chip electrode connection structure |
| JP4814196B2 (en) * | 2007-10-15 | 2011-11-16 | 富士通株式会社 | Circuit board |
| JP4986072B2 (en) * | 2008-03-26 | 2012-07-25 | 日立化成工業株式会社 | Manufacturing method of chip mounting substrate |
| JP5585155B2 (en) * | 2010-03-26 | 2014-09-10 | 富士通株式会社 | Manufacturing method of circuit board for mounting semiconductor element |
-
1992
- 1992-11-06 JP JP32234992A patent/JP3246010B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH06151506A (en) | 1994-05-31 |
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