JP2685900B2 - Film carrier - Google Patents
Film carrierInfo
- Publication number
- JP2685900B2 JP2685900B2 JP14578789A JP14578789A JP2685900B2 JP 2685900 B2 JP2685900 B2 JP 2685900B2 JP 14578789 A JP14578789 A JP 14578789A JP 14578789 A JP14578789 A JP 14578789A JP 2685900 B2 JP2685900 B2 JP 2685900B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- circuit pattern
- carrier
- semiconductor element
- carrier film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Landscapes
- Wire Bonding (AREA)
Description
【発明の詳細な説明】 (産業上の利用分野) 本発明はエリアTABと通称されるTAB用等に用いられる
フィルムキャリアに関する。DETAILED DESCRIPTION OF THE INVENTION (Industrial field of application) The present invention relates to a film carrier used for TAB, which is commonly referred to as area TAB.
(従来の技術) エリアTAB(AREA-TAB)は第4図および第5図に示す
ように、ポリイミド等の耐熱性を有するキャリアフィル
ム12の片面側に外部接続用の回路パターン14が形成さ
れ、キャリアフィルム12の他面側に、スルーホールめっ
き層16を介して上記回路パターン14に導通する内部回路
パターン18が形成されて、該内部回路パターン18上にバ
ンプ26を介して半導体素子20が接続されるようになって
いる このようにエリアTABでは、外部接続用の回路パ
ターン14に重ねて内部回路パターン18を形成しうるた
め、複雑な回路パターンの設計が自由に行え、特に半導
体素子20の接続用電極の位置に合わせて内部回路パター
ン18を設計することが可能となり、半導体素子20の回路
配置がTAB側の接続ピン位置に制約されることなく行な
えるので、半導体素子20の回路配置の自由度が増し、一
層の高集積化が可能となる利点を有している。(Prior Art) As shown in FIGS. 4 and 5, the area TAB (AREA-TAB) has a circuit pattern 14 for external connection formed on one side of a heat-resistant carrier film 12 such as polyimide. On the other surface side of the carrier film 12, an internal circuit pattern 18 which is electrically connected to the circuit pattern 14 via a through hole plating layer 16 is formed, and a semiconductor element 20 is connected to the internal circuit pattern 18 via a bump 26. In this way, in the area TAB, the internal circuit pattern 18 can be formed so as to be overlapped with the circuit pattern 14 for external connection, so that it is possible to freely design a complicated circuit pattern, especially for the semiconductor element 20. The internal circuit pattern 18 can be designed according to the position of the connection electrode, and the circuit layout of the semiconductor element 20 can be performed without being restricted by the connection pin position on the TAB side. This has the advantage that the degree of freedom of arrangement is increased and higher integration is possible.
(発明が解決しようとする課題) しかしながら従来のエリアATBには次のような問題点
がある。(Problems to be Solved by the Invention) However, the conventional area ATB has the following problems.
すなわち、半導体素子20を接合するバンプ26は通常数
十μm程度の厚さしかなく、半導体素子20はキャリアフ
ィルム12上にほとんど接した状態で搭載されるので、半
導体素子20と内部回路パターン18先端部の接合状態、例
えば金−シリコン共晶合金によるバンプ26のメニスカス
形状等を外部から確認しにくく、信頼性に劣る問題点が
あった。That is, the bumps 26 for joining the semiconductor elements 20 usually have a thickness of only about several tens of μm, and the semiconductor elements 20 are mounted on the carrier film 12 almost in contact with each other. There is a problem that it is difficult to confirm the bonding state of the parts, for example, the meniscus shape of the bump 26 made of a gold-silicon eutectic alloy from the outside and the reliability is poor.
そこで本発明では、半導体素子と内部回路パターンの
接合状態を外部から容易に確認でき、信頼性に優れるTA
B用等に用いられるフィルムキャリアを提供することを
目的としている。Therefore, according to the present invention, it is possible to easily confirm the bonding state between the semiconductor element and the internal circuit pattern from the outside, and to improve the reliability of the TA.
It is intended to provide a film carrier used for B or the like.
(課題を解決するための手段) 上記目的による本発明に係るフィルムキャリアでは、
キャリアフィルムの両面に互いに導通する回路パターン
が形成され、該キャリアフィルムの片面側の回路パター
ン上にバンプを介して半導体素子が搭載されるフィルム
キャリアにおいて、前記半導体素子が接合される部位の
近傍となるキャリアフィルムに透孔を設けたことを特徴
としている。(Means for Solving the Problems) In the film carrier according to the present invention according to the above object,
In a film carrier in which circuit patterns are formed on both sides of the carrier film so as to be electrically connected to each other, and a semiconductor element is mounted via bumps on the circuit pattern on one side of the carrier film, in the vicinity of a portion to which the semiconductor element is bonded. Is characterized in that through holes are provided in the carrier film.
(作用) 本発明に係るフィルムキャリアでは半導体素子の接合
部近傍のキャリアフィルム上に透孔を設けたので、半導
体素子がほとんどキャリアフィルムに接した状態で搭載
されても、上記透孔から半導体素子の接合状態の良否を
目視により確認でき、信頼性の高いフィルムキャリアが
提供される。(Operation) In the film carrier according to the present invention, since the through holes are provided on the carrier film in the vicinity of the bonding portion of the semiconductor element, even if the semiconductor element is mounted in a state of being almost in contact with the carrier film, the semiconductor element is not exposed through the through holes. The quality of the joined state of can be visually confirmed, and a highly reliable film carrier can be provided.
(実施例) 以下では本発明の好適な実施例を添付図面に基づいて
詳細に説明する。Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
第1図はTBA用フィルムキャリア10の部分平面図、第
2図は部分断面図である。FIG. 1 is a partial plan view of the TBA film carrier 10, and FIG. 2 is a partial sectional view.
ポリイミド等の耐熱性を有するキャリアフィルム12の
片面側に外部接続用の回路パターン14が形成され、キャ
リアフィルム12の他面側に、スルーホールめっき皮膜16
を介して上記回路パターン14に導通する内部回路パター
ン18が形成されている点は従来と同じである。A circuit pattern 14 for external connection is formed on one side of a heat-resistant carrier film 12 such as polyimide, and a through-hole plating film 16 is formed on the other side of the carrier film 12.
The point that an internal circuit pattern 18 that is electrically connected to the circuit pattern 14 via the through hole is formed is the same as the conventional one.
本実施例で特徴とする点は、半導体素子20が接合され
る部位の内部回路パターン18の先端部近傍となるキャリ
アフィルム12上に透孔22が形成されている点にある。A feature of this embodiment is that the through holes 22 are formed on the carrier film 12 in the vicinity of the tip of the internal circuit pattern 18 at the portion where the semiconductor element 20 is bonded.
上記のTAB用フィルムキャリア10を形成するには、ま
ずキャリアフィルム12に上記の透孔22およびその他の必
要な透孔などを打ち抜き、しかる後に該キャリアフィル
ム上に接着剤により銅箔を接着して所要のエッチング加
工を施して回路パターン14、内部回路パターン18を形成
するか、あるいはキャリアフィルム12上に蒸着もしくは
スパッタリングにより銅層を形成し、この銅層をエッチ
ング加工して回路パターン14、内部回路パターン18に形
成してのち、上記透孔22等をキャリアフィルム12をエッ
チング加工することによって形成するとよい。In order to form the TAB film carrier 10, first, the through hole 22 and other necessary through holes in the carrier film 12 are punched out, and then a copper foil is bonded onto the carrier film with an adhesive. The circuit pattern 14 and the internal circuit pattern 18 are formed by performing a required etching process, or a copper layer is formed on the carrier film 12 by vapor deposition or sputtering, and the copper layer is processed by etching to form the circuit pattern 14 and the internal circuit. After forming the pattern 18, the through holes 22 and the like may be formed by etching the carrier film 12.
なおスルーホールめっき皮膜16は通常のごとく無電解
めっき等によって形成する。The through-hole plating film 16 is usually formed by electroless plating or the like.
上記のように構成されているので、半導体素子20を半
導体素子20に形成されているバンプ26によって内部回路
パターン18先端部上に接合して搭載することができる。Since the semiconductor element 20 is configured as described above, the semiconductor element 20 can be mounted on the tip portion of the internal circuit pattern 18 by being bonded thereto by the bump 26 formed on the semiconductor element 20.
なおバンプ26は、内部回路パターン18先端部側にあら
かじめ形成しておいてもよい。The bump 26 may be formed in advance on the tip side of the internal circuit pattern 18.
この半導体素子20と内部回路パターン18先端部の接合
部近傍のキャリアフィルム12上に前記の如く透孔22が形
成されているので、半導体素子接合後、半導体素子20を
接合した側とは反対側から透孔22により当該接合部位の
接合状態の良否、例えば金−シリコン共晶合金によるバ
ンプ26のメニスカス形状などを確認することができる。Since the through hole 22 is formed on the carrier film 12 in the vicinity of the joint between the tip of the semiconductor element 20 and the internal circuit pattern 18, the side opposite to the side where the semiconductor element 20 is joined after the semiconductor element is joined. From the through hole 22, it is possible to confirm the quality of the bonding state of the bonding portion, for example, the meniscus shape of the bump 26 made of a gold-silicon eutectic alloy.
第3図は他の実施例を示す。 FIG. 3 shows another embodiment.
本実施例では、外部接続用の回路パターン14から一旦
スルーホールめっき皮膜16を介してキャリアフィルム12
の他面側に回路パターンを上げてのち、ビア28を介して
回路パターン14側に回路を降ろしている。このビア28内
にはんだ合金30を盛り込んで回路パターン14側にバンプ
26を形成している。In this embodiment, the carrier film 12 is once passed through the through-hole plating film 16 from the circuit pattern 14 for external connection.
After raising the circuit pattern to the other surface side, the circuit is lowered to the circuit pattern 14 side via the via 28. Solder alloy 30 is put in this via 28 and bumps are placed on the circuit pattern 14 side.
Forming 26.
したがって本実施例では回路パターン14側に半導体素
子20を搭載しうるようになっている。Therefore, in this embodiment, the semiconductor element 20 can be mounted on the circuit pattern 14 side.
本実施例でも半導体素子20との接合部近傍のキャリア
フィルム12上に透孔22を形成しておけばよい。Also in this embodiment, the through holes 22 may be formed on the carrier film 12 in the vicinity of the junction with the semiconductor element 20.
以上、本発明につき好適な実施例を挙げて種々説明し
たが、本発明はこの実施例に限定されるものではなく、
発明の精神を逸脱しない範囲内で多くの改変を施し得る
のはもちろんのことである。As described above, the present invention has been described in various ways with reference to preferred embodiments. However, the present invention is not limited to these embodiments.
Of course, many modifications can be made without departing from the spirit of the invention.
(発明の効果) 以上のように本発明に係るフィルムキャリアによれ
ば、半導体素子の接合部近傍のキャリアフィルム上に透
孔を設けたので、半導体素子がほとんどキャリアフィル
ムに接した状態でキャリアフィルム上に搭載されても、
上記透孔から半導体素子の接合状態の良否を目視により
確認でき、信頼性の高いフィルムキャリアが提供でき
る。(Effect of the invention) As described above, according to the film carrier of the present invention, since the through holes are provided on the carrier film in the vicinity of the bonding portion of the semiconductor element, the carrier film is almost in contact with the carrier film. Even when mounted on top,
The quality of the bonded state of the semiconductor element can be visually confirmed through the through hole, and a highly reliable film carrier can be provided.
第1図は本発明に係るフィルムキャリアの一例を示す部
分平面図、第2図はその部分断面図、第3図は他の実施
例を示す部分断面図を示す。 第4図は従来のTAB用フィルムキャリアの平面図、第5
図はその部分断面図を示す。 10……TAB用フィルムキャリア、12……キャリアフィル
ム、14……回路パターン、18……内部回路パターン、20
……半導体素子、22……透孔、26……バンプ。FIG. 1 is a partial plan view showing an example of a film carrier according to the present invention, FIG. 2 is a partial sectional view thereof, and FIG. 3 is a partial sectional view showing another embodiment. FIG. 4 is a plan view of a conventional TAB film carrier, and FIG.
The figure shows a partial sectional view thereof. 10 …… TAB film carrier, 12 …… Carrier film, 14 …… Circuit pattern, 18 …… Internal circuit pattern, 20
...... Semiconductor element, 22 …… Through hole, 26 …… Bump.
Claims (1)
回路パターンが形成され、該キャリアフィルムの片面側
の回路パターン上にバンプを介して半導体素子が搭載さ
れるフィルムキャリアにおいて、 前記半導体素子が接合される部位の近傍となるキャリア
フィルムに透孔を設けたことを特徴とするフィルムキャ
リア。1. A film carrier in which circuit patterns are formed on both sides of a carrier film so as to be electrically connected to each other, and a semiconductor element is mounted on the circuit pattern on one side of the carrier film via bumps. A film carrier characterized in that a through hole is provided in a carrier film in the vicinity of a portion to be filled.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14578789A JP2685900B2 (en) | 1989-06-08 | 1989-06-08 | Film carrier |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14578789A JP2685900B2 (en) | 1989-06-08 | 1989-06-08 | Film carrier |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH0311645A JPH0311645A (en) | 1991-01-18 |
JP2685900B2 true JP2685900B2 (en) | 1997-12-03 |
Family
ID=15393153
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP14578789A Expired - Fee Related JP2685900B2 (en) | 1989-06-08 | 1989-06-08 | Film carrier |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2685900B2 (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5613033A (en) * | 1995-01-18 | 1997-03-18 | Dell Usa, Lp | Laminated module for stacking integrated circuits |
-
1989
- 1989-06-08 JP JP14578789A patent/JP2685900B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JPH0311645A (en) | 1991-01-18 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
LAPS | Cancellation because of no payment of annual fees |