JPH0677285A - Mounting of ic element - Google Patents

Mounting of ic element

Info

Publication number
JPH0677285A
JPH0677285A JP22983892A JP22983892A JPH0677285A JP H0677285 A JPH0677285 A JP H0677285A JP 22983892 A JP22983892 A JP 22983892A JP 22983892 A JP22983892 A JP 22983892A JP H0677285 A JPH0677285 A JP H0677285A
Authority
JP
Japan
Prior art keywords
circuit board
mounting
electrode
connection
electrode terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP22983892A
Other languages
Japanese (ja)
Inventor
Hideo Aoki
秀夫 青木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP22983892A priority Critical patent/JPH0677285A/en
Publication of JPH0677285A publication Critical patent/JPH0677285A/en
Withdrawn legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/09Use of materials for the conductive, e.g. metallic pattern
    • H05K1/092Dispersed materials, e.g. conductive pastes or inks
    • H05K1/095Dispersed materials, e.g. conductive pastes or inks for polymer thick films, i.e. having a permanent organic polymeric binder
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/303Surface mounted components, e.g. affixing before soldering, aligning means, spacing means
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/321Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by conductive adhesives

Landscapes

  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To provide a method of mounting an IC element for eliminating complicatedness in manufacturing procedures and rise of cost and additionally being functionally suitable for constitution of a mounting circuit device. CONSTITUTION:In a method of mounting an IC element 9 having an electrode terminal 9 for connection at the main surface thereof to the surface of a circuit board 6 having a wiring circuit 6b formed by a conductive paste, an insulating film 7 of a thermosetting resin group providing a through-cutting hole 7a in the thickness direction at the region corresponding to the electrode terminal 9 for connection of the IC element 9 and an electrode pad 6a at the surface of the circuit board 6 is arranged after alignment between the IC element 9 and the surface of the circuit board 6. This stacked layer body is subjected to thermal and pressurized processings for integration with the IC element 9 and the circuit board 6 and completion of electrical connection between the electrode terminal 9a for connection and electrode pad 6a.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明はIC素子の実装方法に係
り、特に導電性ペーストから成る配線回路を有する回路
基板面にIC素子を実装する方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for mounting an IC element, and more particularly to a method for mounting an IC element on the surface of a circuit board having a wiring circuit made of a conductive paste.

【0002】[0002]

【従来の技術】回路装置ないし回路部品の小形化を目的
として、たとえば厚膜回路基板のような回路基板面に、
モールドされたIC素子などを実装する手段が知られて
いる。図3(a) 〜(c) は、従来のICチップを実装する
方式例で、IC素子を厚膜回路基板などの面に実装する
実施態様を模式的に示したもので、先ず、図3(a) に断
面的に示すごとく、電極端子1a面上に半田,金,他の合
金類から成るバンプ2と総称される突起電極を形成した
構成のIC素子1を、図3(b) に断面的に示すごとく、
たとえば厚膜回路基板3面の電極パッド3a面に、前記バ
ンプ2を介して実装・接続する方式が広く実用に供され
ている。また、この方式において、図3(c) に断面的に
示すごとく、バンプ2と電極パッド3a面との間に、異方
導電性層4を介在させる構成も試みられている。その
他、モールドIC素子の場合は、モールドIC素子の電
極端子を、たとえば厚膜回路基板面の対応する電極パッ
ド面とワイヤボンディングにより電気的に接続するか、
あるいはモールドIC素子から導出したリード端子を、
たとえば厚膜回路基板面の対応する電極パッド面に位置
合わせし、半田付けにより電気的に接続する手段が採ら
れている。
2. Description of the Related Art For the purpose of downsizing a circuit device or a circuit component, for example, on a circuit board surface such as a thick film circuit board,
Means for mounting a molded IC element or the like are known. FIGS. 3 (a) to 3 (c) are examples of a conventional method of mounting an IC chip, and schematically show an embodiment in which an IC element is mounted on a surface of a thick film circuit board or the like. As shown in a sectional view in FIG. 3 (a), an IC element 1 having a structure in which bump electrodes made of solder, gold, and other alloys are collectively formed on the surface of the electrode terminal 1a is shown in FIG. 3 (b). As shown in cross section,
For example, a method of mounting and connecting to the surface of the thick film circuit board 3 on the surface of the electrode pad 3a through the bump 2 is widely used. Further, in this method, as shown in a sectional view in FIG. 3 (c), a structure in which an anisotropic conductive layer 4 is interposed between the bump 2 and the surface of the electrode pad 3a has been attempted. In addition, in the case of the molded IC element, the electrode terminal of the molded IC element is electrically connected to the corresponding electrode pad surface of the thick film circuit board surface by wire bonding, or
Alternatively, the lead terminal derived from the molded IC element
For example, a means for aligning with the corresponding electrode pad surface of the thick film circuit board surface and electrically connecting by soldering is adopted.

【0003】[0003]

【発明が解決しようとする課題】しかしながら、上記し
たバンプ2を介して実装・接続する方式においては、次
のような問題がある。すなわち、前記突起電極を成すバ
ンプ2を介して回路基板面に直接実装・接続方式は、た
とえばワイヤボンディングにより、あるいは半田付けに
よって電気的に接続する方式に比べて、薄型化を容易に
図り得るし、また回路基板の耐熱性や柔軟性などに伴う
制約も大幅に解消し得る半面、コストアップや信頼性の
点でなお問題がある。
However, the above-mentioned method of mounting and connecting via the bump 2 has the following problems. That is, the direct mounting / connecting method on the surface of the circuit board via the bumps 2 forming the protruding electrodes can easily be made thinner than the method of electrically connecting by, for example, wire bonding or soldering. Moreover, the restrictions associated with the heat resistance and flexibility of the circuit board can be largely eliminated, but there are still problems in terms of cost increase and reliability.

【0004】先ず第1に、IC素子1の電極端子1a面上
の突起電極(バンプ)2は、一般的に低融点金属のメッ
キにより形成され、かつこのメッキによるバンプ2形成
は、IC素子の製造に準ずる製造工程(製造条件)を必
要とするため、大幅なコストアップを回避し得ないのが
実情である。第2に、回路基板3面の電極パッド3a面に
対する実装・接続の工程において、突起電極(バンプ)
2が溶融して半田機能を呈する際、隣接する電極パッド
3a間、あるいは近傍の回路パターン間の、電気的な接続
(電気的な短絡)を起こし易く、接続・実装の信頼性に
問題がある。すなわち、前記突起電極2の溶融加熱によ
る半田付けにおいて、電極パッド3a間の短絡などが発生
したり、この短絡発生を考慮した半田付けを行うと半田
付け不良が生じたりする恐れがある。したがって、前記
電極パッド3a間などに、たとえばソルダーレジスト層
(パターン)を配置し、半田の溶融による短絡防止を図
ることも試みられている。そして、このソルダーレジス
ト層(パターン)の配置・形成は、新たな工程の付加と
なるばかりでなく、その工程が煩雑で量産性も損なわれ
るため、コストアップを招来するという問題がある。
First, the protruding electrodes (bumps) 2 on the surface of the electrode terminals 1a of the IC element 1 are generally formed by plating a low melting point metal, and the bumps 2 are formed by this plating. Since a manufacturing process (manufacturing condition) similar to the manufacturing is required, it is a fact that a large increase in cost cannot be avoided. Secondly, in the process of mounting / connecting the surface of the circuit board 3 to the surface of the electrode pad 3a, bump electrodes are provided.
When 2 melts and exhibits a soldering function, adjacent electrode pads
Electrical connection (electrical short circuit) easily occurs between 3a or between adjacent circuit patterns, and there is a problem in connection / mounting reliability. That is, when soldering the projecting electrodes 2 by melting and heating, a short circuit or the like between the electrode pads 3a may occur, or if soldering in consideration of this short circuit may cause soldering failure. Therefore, for example, a solder resist layer (pattern) is arranged between the electrode pads 3a to prevent short circuit due to melting of solder. The placement and formation of this solder resist layer (pattern) not only involves the addition of new steps, but also the steps are complicated and the mass productivity is impaired, which causes a problem of increasing costs.

【0005】本発明は上記事情に対処してなされたもの
で、製造操作の繁雑性やコストアップを解消しながら、
機能的にも信頼性の高い実装回路装置の構成に適するI
C素子の実装方法の提供を目的とする。
The present invention has been made in view of the above circumstances, and eliminates the complexity of manufacturing operations and the increase in cost.
I suitable for the construction of a mounting circuit device that is functionally highly reliable
It is intended to provide a method for mounting a C element.

【0006】[0006]

【課題を解決するための手段】本発明に係るIC素子の
実装方法は、接続用電極端子を主面に有するIC素子
を、導電性ペーストから成る配線回路を有する回路基板
面に実装する方法において、前記IC素子の接続用電極
端子および回路基板面の電極パッドに対応した領域を厚
さ方向に貫通・切除した熱可塑性樹脂系の絶縁性フィル
ムを、IC素子と回路基板面との間にに位置合わせ配置
し、この積層体に加熱・加圧処理を施して、IC素子お
よび回路基板を一体化するとともに、接続用電極端子と
電極パッドとを電気的に接続することを特徴とする。
A method of mounting an IC element according to the present invention is a method of mounting an IC element having a connecting electrode terminal on a main surface on a circuit board surface having a wiring circuit made of a conductive paste. A thermoplastic resin-based insulating film is formed between the IC element and the surface of the circuit board by penetrating and cutting the regions corresponding to the connecting electrode terminals of the IC element and the electrode pads on the surface of the circuit board in the thickness direction. It is characterized in that they are aligned and arranged, and the laminated body is subjected to a heating / pressurizing treatment to integrate the IC element and the circuit board and electrically connect the connecting electrode terminals and the electrode pads.

【0007】本発明において、熱可塑性樹脂系の絶縁性
フィルムは、回路基板の基材樹脂のガラス転移点温度よ
りも高いガラス転移点温度を有することが望ましく、ま
た、加熱・加圧処理により一体化するとき、接着剤層を
介在させておてもよく、さらに実装・接続後その実装・
接続部を含む領域を熱硬化性樹脂で被覆封止してもよ
い。
In the present invention, the thermoplastic resin-based insulating film preferably has a glass transition temperature higher than the glass transition temperature of the base resin of the circuit board, and is integrated by heat / pressure treatment. The adhesive layer may be interposed between the mounting and connection, and after mounting and connecting
The area including the connecting portion may be covered and sealed with a thermosetting resin.

【0008】[0008]

【作用】本発明に係るIC素子の実装方法においては、
互いに接続する電極端子および電極パッドに対応した領
域が厚さ方向に貫通・切除した熱可塑性樹脂系の絶縁性
フィルムを、IC素子面と回路基板面に介在させ、互い
に対応する電極端子面−電極パッド面を対接させた構成
を採って加熱・加圧によりIC素子および回路基板を一
体化する。つまり、各接続部を成す電極端子−電極パッ
ドは、それぞれ絶縁性フィルムの溶融・収縮作用によっ
て相互に対接する面同士が密に接触する一方、その絶縁
性フィルムが成す堰(壁)によって、離隔・個別化され
た状態(独立的に接続)を呈すしながら、IC素子およ
び回路基板も絶縁性フィルムの融着収縮作用で一体化
し、信頼性の高い接続・実装構造が達成される。
In the method of mounting an IC element according to the present invention,
A region corresponding to the electrode terminal and the electrode pad to be connected to each other is penetrated and cut in the thickness direction, and an insulating film made of a thermoplastic resin is interposed between the IC element surface and the circuit board surface, and the corresponding electrode terminal surface-electrode By adopting a structure in which the pad surfaces are in contact with each other, the IC element and the circuit board are integrated by heating and pressing. In other words, the electrode terminals-electrode pads that form each connection part are closely contacted with each other due to the melting and shrinking action of the insulating film, while they are separated by the weir (wall) formed by the insulating film. -The IC element and the circuit board are integrated by the fusion shrinkage action of the insulating film while exhibiting an individualized state (independent connection), and a highly reliable connection / mounting structure is achieved.

【0009】[0009]

【実施例】以下、図1(a) 〜(b) および図2(a) 〜(b)
を参照して本発明の実施例を説明する。
EXAMPLES Hereinafter, FIGS. 1 (a)-(b) and FIGS. 2 (a)-(b)
An embodiment of the present invention will be described with reference to FIG.

【0010】先ず、実装用の回路基板として、たとえば
ポリカーボネート樹脂,ポリエーテルイミド樹脂,ポリ
エチレンテレフタレート樹脂などの熱可塑性樹脂を基材
とす絶縁性基板面上に、たとえばAg,Cr,Auなどの導電
性粉末を含む導電性組成物(導電性ペースト)から成る
所要の電極パッドおよび配線回路が形成された配線回路
基板を用意した。なお、この配線回路基板の電極パッド
は、後述するところの実装用IC素子の接続用電極端子
に対応した数、位置に形成してある。一方、前記配線回
路基板の電極パッドに対応する領域(部分)を選択的に
切除(貫通)孔を設けた熱可塑性樹脂フィルム、たとえ
ば厚さ50μm 程度のポリエーテルイミド樹脂フィルムや
ポリイミド樹脂フィルム、および実装用のIC素子、た
とえばモールドIC素子を用意した。ここで、前記IC
素子面の接続用電極端子面には、突起電極(バンプ)が
形成されておらず、また、熱可塑性樹脂フィルムの厚さ
は、前記配線回路基板の電極パッド面とIC素子面の接
続用電極端子面とが十分に対接し得るように選択・設定
される。
First, as a circuit board for mounting, for example, a conductive material such as Ag, Cr, Au is formed on the surface of an insulating substrate having a thermoplastic resin such as polycarbonate resin, polyetherimide resin, polyethylene terephthalate resin as a base material. A wiring circuit board having a required electrode pad and a wiring circuit made of a conductive composition (conductive paste) containing a conductive powder was prepared. The electrode pads of the printed circuit board are formed in the numbers and positions corresponding to the connecting electrode terminals of the mounting IC element, which will be described later. On the other hand, a thermoplastic resin film in which a region (portion) corresponding to the electrode pad of the printed circuit board is selectively cut (through) holes, for example, a polyetherimide resin film or a polyimide resin film having a thickness of about 50 μm, and An IC element for mounting, for example, a molded IC element was prepared. Where the IC
No bump electrodes are formed on the connection electrode terminal surface of the element surface, and the thickness of the thermoplastic resin film is the same as the connection electrode between the electrode pad surface of the printed circuit board and the IC element surface. It is selected and set so that it can sufficiently contact the terminal surface.

【0011】次いで、前記用意した配線回路基板、熱可
塑性樹脂フィルム、およびモールドIC素子を、図1
(a) に断面的に示すごとく、位置決めして積層・配置す
る。すなわち、加熱機構を備えた載置台5面上に、所要
の電極パッド6aおよび配線回路6bが形成された配線回路
基板6を配置する。このとき、配線回路基板6は、電極
パッド6a形成面を上面とする。この後、前記配置した配
線回路基板6面に、前記熱可塑性樹脂フィルム7を位置
決め配置する。すなわち、前記配線回路基板6の電極パ
ッド6aに対応する領域(部分)を選択的に切除(貫通)
孔7aを形成した熱可塑性樹脂フィルム7を、電極パッド
6aに対応する切除(貫通)孔7aがそれぞれ嵌合する状態
に位置決め配置する。このようにして、配線回路基板6
面に熱可塑性樹脂フィルム7を位置決め配置してから、
たとえば加熱機構付きのピックアップヘッド8を有する
マウンターにより、前記モールドIC素子9を熱可塑性
樹脂フィルム7面上に移載し、配線回路基板6の電極パ
ッド6a面に、熱可塑性樹脂フィルム7切除孔7aを介し
て、対応するモールドIC素子9の接続用電極端子9aを
それぞれ位置決め・対接させる。
Next, the wiring circuit board, the thermoplastic resin film, and the molded IC element prepared as described above are attached to FIG.
As shown in cross section in (a), position and stack and arrange. That is, the printed circuit board 6 on which the required electrode pads 6a and the wiring circuits 6b are formed is arranged on the surface of the mounting table 5 provided with the heating mechanism. At this time, the printed circuit board 6 has the electrode pad 6a forming surface as the upper surface. Then, the thermoplastic resin film 7 is positioned and arranged on the surface of the arranged printed circuit board 6. That is, a region (portion) corresponding to the electrode pad 6a of the printed circuit board 6 is selectively cut (penetrated).
The thermoplastic resin film 7 having the holes 7a is formed on the electrode pad.
The cutting (through) holes 7a corresponding to 6a are positioned and arranged so as to fit with each other. In this way, the printed circuit board 6
After positioning the thermoplastic resin film 7 on the surface,
For example, the molded IC element 9 is transferred onto the surface of the thermoplastic resin film 7 by a mounter having a pickup head 8 with a heating mechanism, and the thermoplastic resin film 7 cut hole 7a is formed on the surface of the electrode pad 6a of the printed circuit board 6. The corresponding connecting electrode terminals 9a of the molded IC element 9 are respectively positioned and brought into contact with each other via.

【0012】次に、図1(b) に断面的に示すごとく、前
記載置台5の加熱機構およびマウンターを成すピックア
ップヘッド8の加熱機構を動作させる一方、前記マウン
ターでモールドIC素子9を配線回路基板6面に圧着す
る。この加熱・加圧(圧着)によって容易に一体化する
とともに、熱可塑性樹脂フィルム7の溶着および収縮の
作用が効果的になされ、配線回路基板6の電極パッド6a
面に、モールドIC素子9の接続用電極端子9a面が密に
対接して、信頼性の高い電気的な接続も達成される。こ
こで、加熱・加圧条件は、配線回路基板6の基材樹脂や
熱可塑性樹脂フィルム7の種類などによって異なるが、
たとえばポリエチレンテレフタレート樹脂の場合は、加
熱温度 350℃程度でよい。
Next, as shown in a sectional view in FIG. 1 (b), the heating mechanism of the mounting table 5 and the heating mechanism of the pick-up head 8 forming the mounter are operated, while the mold IC element 9 is wired by the mounter. It is pressure-bonded to the surface of the substrate 6. The heating / pressurization (pressure bonding) facilitates the integration, and the effects of welding and shrinking the thermoplastic resin film 7 are effectively exerted, so that the electrode pad 6a of the printed circuit board 6 can be obtained.
The surface is closely contacted with the surface of the connecting electrode terminal 9a of the molded IC element 9, and a highly reliable electrical connection is also achieved. Here, although the heating / pressurizing conditions vary depending on the type of the base resin of the printed circuit board 6 and the thermoplastic resin film 7,
For example, in the case of polyethylene terephthalate resin, the heating temperature may be about 350 ° C.

【0013】なお、上記実施例において、図2(a) に断
面的に示すごとく、配線回路基板6とモールドIC素子
9との間に介在させた絶縁性フイルム7の両主面にそれ
ぞれ熱硬化性接着剤層10を配置した構成としてもよい
し、さらに、図2(b) に断面的に示すごとく、前記接続
・実装後、接続・実装したモールドIC素子9の周辺部
などを熱硬化性樹脂11で被覆・封止することも可能であ
る。さらに、本発明は配線回路基板6の構成、実装・接
続するIC素子の構成も前記例示のものに限定されるも
のでない。
In the above embodiment, as shown in a sectional view in FIG. 2 (a), both main surfaces of the insulating film 7 interposed between the printed circuit board 6 and the molded IC element 9 are thermoset. The adhesive layer 10 may be arranged, and as shown in the sectional view of FIG. 2 (b), after the connection / mounting, the peripheral part of the molded IC element 9 connected / mounted is thermosettable. It is also possible to cover and seal with resin 11. Further, in the present invention, the configuration of the printed circuit board 6 and the configuration of the IC element to be mounted / connected are not limited to those exemplified above.

【0014】[0014]

【発明の効果】以上説明したように、本発明に係るIC
素子の実装方法によれば、実装・接続するIC素子の接
続用電極端子面への突起電極の形成が不要となるため、
製造工程の簡略化やコスト低減を図り得るばかりでな
く、電極パッド間の短絡発生の恐れも解消され、信頼性
の高い実装・接続が可能となる。そして、配線回路基板
とIC素子との間の絶縁性フイルム面に熱硬化性接着剤
層を介在させたり(図2(a) 参照)、あるいは接続・実
装したIC素子の周辺部などを熱硬化性樹脂で被覆・封
止した場合(図2(b) 参照)は、前記樹脂の硬化収縮性
も加算される形となるので、IC素子の配線回路基板に
対する電気的な接続性をさらに向上し得る。
As described above, the IC according to the present invention
According to the element mounting method, it is not necessary to form the protruding electrode on the connection electrode terminal surface of the IC element to be mounted / connected.
Not only can the manufacturing process be simplified and costs can be reduced, but also the possibility of short-circuiting between the electrode pads can be eliminated, and highly reliable mounting and connection can be achieved. Then, a thermosetting adhesive layer may be interposed on the insulating film surface between the printed circuit board and the IC element (see FIG. 2 (a)), or the peripheral portion of the connected / mounted IC element may be thermoset. When the resin is coated and sealed (see Fig. 2 (b)), the curing shrinkage of the resin is also added, so the electrical connectivity of the IC element to the printed circuit board is further improved. obtain.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明に係るIC素子の実装方法の実施態様例
を模式的に示したもので、(a)は配線回路基板上に絶縁
フィルムおよびIC素子を位置決め配置する状態を示す
断面図、(b) は配線回路基板上に絶縁フィルムおよびI
C素子を位置決め配置した後加圧・加熱する状態を示す
断面図。
FIG. 1 schematically shows an embodiment of an IC element mounting method according to the present invention, in which (a) is a cross-sectional view showing a state in which an insulating film and an IC element are positioned and arranged on a printed circuit board; (b) is an insulating film and I on the printed circuit board.
Sectional drawing which shows the state which pressurizes and heats after C element is positioned and arranged.

【図2】本発明に係るIC素子の実装方法において他の
実施態様例で接続・実装した構成を示したもので、(a)
は絶縁性フイルム面に熱硬化性接着剤層を介在差せた場
合の断面図、(b) は接続・実装したIC素子の周辺部な
どを熱硬化性樹脂で被覆・封止した場合の断面図。
FIG. 2 shows a configuration in which the method for mounting an IC element according to the present invention is connected and mounted in another embodiment example.
Is a cross-sectional view when a thermosetting adhesive layer is inserted between the insulating film surface, and (b) is a cross-sectional view when the peripheral parts of the connected / mounted IC elements are covered / sealed with a thermosetting resin. .

【図3】従来のIC素子の実装方法の実施態様を模式的
に示したもので、(a) はIC素子の構成を示す断面図、
(b) は実装・接続した状態を示す断面図、(c) は他の実
施態様で実装・接続した状態を示す断面図。
FIG. 3 schematically shows an embodiment of a conventional method for mounting an IC element, (a) is a cross-sectional view showing the configuration of the IC element,
(b) is a sectional view showing a mounted / connected state, and (c) is a sectional view showing a mounted / connected state in another embodiment.

【符号の説明】[Explanation of symbols]

1,9…IC素子 1a,9a…IC素子の接続用電極端
子 2…バンプ 3,6…回路基板 3a,6a…回路基板の電極パッド
4…異方導電性層 5…載置台 6b…回路基板の配線回路 7…絶縁性
フィルム(熱可塑性樹脂)7a…絶縁性フィルムの貫通孔
8…ピックアップヘッド 10…熱硬化性接着剤層
11…熱硬化性樹脂による被覆・封止層
1, 9 ... IC element 1a, 9a ... Electrode terminal for connection of IC element 2 ... Bump 3, 6 ... Circuit board 3a, 6a ... Electrode pad of circuit board
4 ... Anisotropic conductive layer 5 ... Mounting table 6b ... Wiring circuit of circuit board 7 ... Insulating film (thermoplastic resin) 7a ... Through hole of insulating film 8 ... Pickup head 10 ... Thermosetting adhesive layer
11 ... Coating / sealing layer made of thermosetting resin

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 接続用電極端子を主面に有するIC素子
を、導電性ペーストから成る配線回路を有する回路基板
面に実装する方法において、 前記IC素子の接続用電極端子および回路基板面の電極
パッドに対応した領域を厚さ方向に貫通・切除した熱可
塑性樹脂系の絶縁性フィルムを、IC素子と回路基板面
との間にに位置合わせ配置し、この積層体に加熱・加圧
処理を施して、IC素子および回路基板を一体化すると
ともに、接続用電極端子と電極パッドとを電気的に接続
することを特徴とするIC素子の実装方法。
1. A method of mounting an IC element having a connecting electrode terminal on a main surface on a circuit board surface having a wiring circuit made of a conductive paste, wherein the connecting electrode terminal of the IC element and an electrode on the circuit board surface are provided. A thermoplastic resin-based insulating film, which penetrates and cuts the area corresponding to the pad in the thickness direction, is aligned and arranged between the IC element and the circuit board surface, and the laminated body is subjected to heat / pressure treatment. A mounting method of an IC element, characterized by performing the integration of the IC element and the circuit board and electrically connecting the connection electrode terminal and the electrode pad.
JP22983892A 1992-08-28 1992-08-28 Mounting of ic element Withdrawn JPH0677285A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP22983892A JPH0677285A (en) 1992-08-28 1992-08-28 Mounting of ic element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP22983892A JPH0677285A (en) 1992-08-28 1992-08-28 Mounting of ic element

Publications (1)

Publication Number Publication Date
JPH0677285A true JPH0677285A (en) 1994-03-18

Family

ID=16898476

Family Applications (1)

Application Number Title Priority Date Filing Date
JP22983892A Withdrawn JPH0677285A (en) 1992-08-28 1992-08-28 Mounting of ic element

Country Status (1)

Country Link
JP (1) JPH0677285A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005285943A (en) * 2004-03-29 2005-10-13 Nec Electronics Corp Multichip package, and wiring material between chips
JP2006156438A (en) * 2004-11-25 2006-06-15 Matsushita Electric Works Ltd Manufacturing method of electronic component loading device and electronic component loading device
JP2009272645A (en) * 2009-08-07 2009-11-19 Denso Corp Mounting method for ic chip

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005285943A (en) * 2004-03-29 2005-10-13 Nec Electronics Corp Multichip package, and wiring material between chips
JP4593951B2 (en) * 2004-03-29 2010-12-08 ルネサスエレクトロニクス株式会社 Multi-chip package manufacturing method
JP2006156438A (en) * 2004-11-25 2006-06-15 Matsushita Electric Works Ltd Manufacturing method of electronic component loading device and electronic component loading device
JP2009272645A (en) * 2009-08-07 2009-11-19 Denso Corp Mounting method for ic chip

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