JPH11135567A - Anisotropic conductive film and manufacture of semiconductor device - Google Patents

Anisotropic conductive film and manufacture of semiconductor device

Info

Publication number
JPH11135567A
JPH11135567A JP29832697A JP29832697A JPH11135567A JP H11135567 A JPH11135567 A JP H11135567A JP 29832697 A JP29832697 A JP 29832697A JP 29832697 A JP29832697 A JP 29832697A JP H11135567 A JPH11135567 A JP H11135567A
Authority
JP
Japan
Prior art keywords
adhesive layer
conductive film
anisotropic conductive
flexible substrate
conductive particles
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP29832697A
Other languages
Japanese (ja)
Inventor
Akiko Torii
明子 鳥居
Minoru Takizawa
稔 滝澤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP29832697A priority Critical patent/JPH11135567A/en
Publication of JPH11135567A publication Critical patent/JPH11135567A/en
Withdrawn legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/321Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by conductive adhesives

Landscapes

  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Wire Bonding (AREA)

Abstract

PROBLEM TO BE SOLVED: To obtain stable electrical connection by positively joining the elec trode of semiconductor parts to an electrode being formed on a substrate. SOLUTION: A double structure of a first adhesive layer 51 including a conductive particle 53 and a second adhesive layer 52 without including the conductive particle 53 is provided, insulation in upper and lower directions can be maintained while a semiconductor device is merely placed, and electrical connection in upper and lower directions can be obtained by pressing using a projecting part.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】この発明は、半導体部品、特
にベアICチップを基板(プリント基板)に実装するこ
とにより得られる半導体装置の製造法及びこの製造方法
において用いられる異方性導電膜に関するものである。
[0001] 1. Field of the Invention [0002] The present invention relates to a method for manufacturing a semiconductor device obtained by mounting a semiconductor component, particularly a bare IC chip on a substrate (printed circuit board), and to an anisotropic conductive film used in the method. It is.

【0002】[0002]

【従来の技術】近年、半導体装置を構成する場合には、
実装面積をより小さく、かつ、薄く、という要求が多
く、これに応えるものとして、ベアICチップをパッケ
ージングせずに直接に基板に実装するフリップチップ実
装法が知られている。この実装方法を図11を用いて説
明する。
2. Description of the Related Art In recent years, when a semiconductor device is constructed,
There are many demands for a smaller and thinner mounting area, and a flip-chip mounting method in which a bare IC chip is directly mounted on a substrate without packaging is known as a method for meeting this demand. This mounting method will be described with reference to FIG.

【0003】半導体部品であるベアICチップ30が実
装される基板10の部品実装面11には導電材料によっ
て複数の配線パターン12が形成されており、各配線パ
ターン12の先端の表面には金メッキが施されて電極1
3が形成されている。また、各配線パターン12におい
ては、電極13の部分を除いてソルダーレジスト14で
覆われ絶縁されている。
[0003] A plurality of wiring patterns 12 are formed of a conductive material on a component mounting surface 11 of a substrate 10 on which a bare IC chip 30 as a semiconductor component is mounted. Applied electrode 1
3 are formed. Each wiring pattern 12 is covered with a solder resist 14 except for a part of the electrode 13 and is insulated.

【0004】ベアICチップ30においては、所定の面
31にAl(アルミニューム)等の導電材料で形成された
複数の電極32が基板10の電極13に対応させて配置
され、各電極32の表面には各々バンプ33が形成され
ている。バンプ33はAu(金)又はSn-Pb (スズ−鉛)
合金等の金属材料で構成されている。
In the bare IC chip 30, a plurality of electrodes 32 made of a conductive material such as Al (aluminum) are arranged on a predetermined surface 31 so as to correspond to the electrodes 13 of the substrate 10. Are formed with bumps 33 respectively. The bump 33 is made of Au (gold) or Sn-Pb (tin-lead)
It is made of a metal material such as an alloy.

【0005】ベアICチップ30の実装のために用いら
れる異方性導電膜20は絶縁性樹脂21に導電粒子22
が混在されたもので、この異方性導電膜20は使用前に
は一方の面が保護用テープで覆われている。
[0005] Anisotropic conductive film 20 used for mounting bare IC chip 30 is made of insulating resin 21 and conductive particles 22.
Before use, the anisotropic conductive film 20 is covered on one side with a protective tape.

【0006】ベアICチップ30の実装に際しては、異
方性導電膜20が露出した一方の面を基板10に向けて
基板10の部品実装面11に異方性導電膜20を載置
し、異方性導電膜20を保護用テープ側から加圧、加熱
して仮接着を行う。この場合に、異方性導電膜20は基
板10の配線パターン12や電極13を覆うようにして
ベアICチップ30の実装箇所に接着される。このと
き、基板10に対する異方性導電膜20の位置ずれ等を
考慮し、異方性導電膜20の面積はベアICチップ30
の所定の面31の面積の2倍程度とされる。
When mounting the bare IC chip 30, the anisotropic conductive film 20 is placed on the component mounting surface 11 of the substrate 10 with one of the exposed surfaces of the anisotropic conductive film 20 facing the substrate 10. The isotropic conductive film 20 is pressurized and heated from the protective tape side to perform temporary bonding. In this case, the anisotropic conductive film 20 is bonded to the mounting location of the bare IC chip 30 so as to cover the wiring pattern 12 and the electrode 13 of the substrate 10. At this time, the area of the anisotropic conductive film 20 is determined in consideration of the displacement of the anisotropic conductive film 20 with respect to the substrate 10 or the like.
Is approximately twice as large as the area of the predetermined surface 31.

【0007】次に、基板10に接着された異方性導電膜
20の保護用テープを剥がし、ベアICチップ30の所
定の面31が異方性導電膜20の他方の面に向くように
設定して異方性導電膜20上にベアICチップ30を載
置し、異方性導電膜20を加圧、加熱してベアICチッ
プ30の本接着を行う。かくして、基板10の部品実装
面11とベアICチップ30の所定の面31側とが異方
性導電膜20の絶縁性樹脂21を介して接合される。ま
た、異方性導電膜20の導電粒子22はバンプ33によ
り基板10の電極13に押圧されるので、基板10とベ
アICチップ30とは電気的に接続される。
Next, the protective tape of the anisotropic conductive film 20 adhered to the substrate 10 is peeled off, and the predetermined surface 31 of the bare IC chip 30 is set so as to face the other surface of the anisotropic conductive film 20. Then, the bare IC chip 30 is placed on the anisotropic conductive film 20, and the anisotropic conductive film 20 is pressurized and heated to perform the actual bonding of the bare IC chip 30. Thus, the component mounting surface 11 of the substrate 10 and the predetermined surface 31 side of the bare IC chip 30 are joined via the insulating resin 21 of the anisotropic conductive film 20. Further, since the conductive particles 22 of the anisotropic conductive film 20 are pressed by the bumps 33 against the electrodes 13 of the substrate 10, the substrate 10 and the bare IC chip 30 are electrically connected.

【0008】[0008]

【発明が解決しようとする課題】この従来の実装方法で
は、基板10はガラスエポキシ系の硬質基板であり、基
板10が反っている場合に基板10の部品実装面11に
異方性導電膜20を仮接着した後、異方性導電膜20上
にベアICチップ30を載置し、本接着すると、基板1
0に形成されている電極13とベアICチップ30の電
極32に対応させて形成されているバンプ33との間に
間隙が生じ、電気的接続が得られないという問題があっ
た。
In this conventional mounting method, the substrate 10 is a hard substrate made of glass epoxy, and when the substrate 10 is warped, the anisotropic conductive film 20 is formed on the component mounting surface 11 of the substrate 10. After the temporary bonding, the bare IC chip 30 is placed on the anisotropic conductive film 20 and the main bonding is performed.
There is a problem that a gap is generated between the electrode 13 formed at 0 and the bump 33 formed corresponding to the electrode 32 of the bare IC chip 30, and electrical connection cannot be obtained.

【0009】また、異方性導電膜20は絶縁性樹脂21
に一様に導電粒子22を混在させた1層構造であり、フ
リップチップ実装における基板10の各電極13の間隔
が約200μm程度の狭いものであるため、導電粒子2
2が各電極13の間隔に散在し、回路絶縁の維持が困難
になるという問題があった。
The anisotropic conductive film 20 is made of an insulating resin 21.
Since the conductive particles 22 are uniformly mixed in a one-layer structure, and the distance between the electrodes 13 of the substrate 10 in the flip-chip mounting is as narrow as about 200 μm, the conductive particles 2
2 are scattered at intervals between the electrodes 13, and there is a problem that it is difficult to maintain circuit insulation.

【0010】更にまた、異方性導電膜20は絶縁性樹脂
に一様に導電粒子22を混在させた1層構造であるた
め、ベアICチップ30の各バンプ33とこれに対応す
る基板10の各電極13との間に十分な数の導電粒子2
2を介在させるには、異方性導電膜20の厚さを厚くす
る必要がある。このような理由で異方性導電膜20の厚
みを厚くすると、異方性導電膜20上にベアICチップ
30を載置し、ボンディングツール40にて本接着する
ときに、加熱により溶融した異方性導電膜20の絶縁性
樹脂21の余剰部分がボンディングツール40に付着、
汚染する。そこで、ボンディングツール40に付着した
絶縁性樹脂21を除去する必要があり、作業を中断せね
ばならないという不都合があった。また、異方性導電膜
20の厚さを厚くした場合、不透明な導電粒子22が多
くなり透明性が低下する。この結果、基板10の部品実
装面11に異方性導電膜20を仮接着した後にベアIC
チップ30を本接着する工程において、基板10の電極
13を異方性導電膜20の上から位置合わせのために透
過認識することが困難になり、接合の位置精度が低下
し、品質低下を招くという問題があった。
Furthermore, since the anisotropic conductive film 20 has a one-layer structure in which conductive particles 22 are uniformly mixed in an insulating resin, each bump 33 of the bare IC chip 30 and the corresponding substrate 10 A sufficient number of conductive particles 2 between each electrode 13
In order to interpose 2, the thickness of the anisotropic conductive film 20 needs to be increased. When the thickness of the anisotropic conductive film 20 is increased for such a reason, when the bare IC chip 30 is placed on the anisotropic conductive film 20 and the actual bonding is performed by the bonding tool 40, the difference caused by the heating is eliminated. The surplus portion of the insulating resin 21 of the isotropic conductive film 20 adheres to the bonding tool 40,
To contaminate. Therefore, it is necessary to remove the insulating resin 21 attached to the bonding tool 40, and there is a disadvantage that the operation must be interrupted. In addition, when the thickness of the anisotropic conductive film 20 is increased, the number of opaque conductive particles 22 increases, and the transparency decreases. As a result, after the anisotropic conductive film 20 is temporarily bonded to the component mounting surface 11 of the
In the step of fully bonding the chip 30, it is difficult to recognize the electrode 13 of the substrate 10 from the top of the anisotropic conductive film 20 for alignment, thereby lowering the positional accuracy of the bonding and deteriorating the quality. There was a problem.

【0011】本発明は上記の従来技術における問題点を
解決せんとしてなされたもので、その目的は、半導体部
品の電極と基板に形成されている電極とを確実に接合で
き、安定的な電気的接続を得ることのできる半導体装置
の製造方法を提供することである。また、他の目的は、
電極間の不要な接続をなくし、更に、作業性の向上を図
ることができる半導体装置の製造方法及びそれに用いる
異方性導電膜を提供することである。
SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems in the prior art, and an object of the present invention is to make it possible to reliably join an electrode of a semiconductor component to an electrode formed on a substrate, and to realize a stable electrical connection. An object of the present invention is to provide a method for manufacturing a semiconductor device capable of obtaining a connection. Also, for other purposes,
An object of the present invention is to provide a method for manufacturing a semiconductor device and an anisotropic conductive film used therefor, which can eliminate unnecessary connection between electrodes and can further improve workability.

【0012】[0012]

【課題を解決するための手段】本発明の異方性導電膜
は、導電粒子を含む接着剤層と、導電粒子を含まない接
着剤層との多層構造を有する。この多層構造により、単
に載置した状態では、上下方向の絶縁が保たれ、突出し
た部分で押圧することにより、上下方向の電気的接続を
得ることができる。
Means for Solving the Problems The anisotropic conductive film of the present invention has a multilayer structure of an adhesive layer containing conductive particles and an adhesive layer containing no conductive particles. With this multi-layer structure, in the state of being simply placed, the insulation in the vertical direction is maintained, and the electrical connection in the vertical direction can be obtained by pressing the protruding portion.

【0013】本発明の請求項2に記載の異方性導電膜
は、導電粒子を含む第1の接着剤層と、導電粒子を含ま
ない第2の接着剤層との2層構造を有し、本発明の請求
項3に記載の異方性導電膜は、導電粒子を含む第1の接
着剤層と、導電粒子を含まない第2の接着剤層と、導電
粒子を含まない第3の接着剤層と、の3層構造を有し、
前記第1の接着剤層が前記第2の接着剤層と前記第3の
接着剤層との間に挟まれていることを特徴とする。これ
により、全体の厚みを変えることなく、導電粒子が含ま
れる第1の接着剤層の厚みを適切に変更し、単に載置し
た状態では、上下方向の絶縁が保たれ、突出した部分で
押圧することにより、上下方向の電気的接続を得る構造
とすることができる。
The anisotropic conductive film according to the present invention has a two-layer structure of a first adhesive layer containing conductive particles and a second adhesive layer containing no conductive particles. The anisotropic conductive film according to claim 3 of the present invention includes a first adhesive layer containing conductive particles, a second adhesive layer containing no conductive particles, and a third adhesive layer containing no conductive particles. Having a three-layer structure of an adhesive layer and
The first adhesive layer is sandwiched between the second adhesive layer and the third adhesive layer. Thereby, the thickness of the first adhesive layer including the conductive particles is appropriately changed without changing the overall thickness, and when the first adhesive layer is simply placed, the insulation in the vertical direction is maintained, and the pressure is applied to the protruding portion. By doing so, a structure for obtaining electrical connection in the vertical direction can be obtained.

【0014】本発明の請求項4に記載の半導体装置の製
造方法は、半導体部品の電極に対して接続する電極を有
する可撓性基板を用い、実装される前記半導体部品に対
応して異方性導電膜を前記可撓性基板の前記電極を覆う
ように載置して熱圧着し、熱圧着された前記異方性導電
膜に対して前記半導体の電極面を向けて載置し熱圧着す
ることにより、前記半導体部品の電極と前記可撓性基板
の電極との電気的な接続を得て半導体装置を製造するこ
とを特徴とする。これにより、基板に反りがあっても加
圧時に撓んで、可撓性基板の電極に対して半導体部品が
接合されることになり、確実な電気的接続を得ることが
できる。
According to a fourth aspect of the present invention, there is provided a method of manufacturing a semiconductor device, wherein a flexible substrate having an electrode connected to an electrode of a semiconductor component is used. A conductive conductive film is placed so as to cover the electrode of the flexible substrate and thermocompression-bonded, and the thermocompression bonding is performed with the electrode surface of the semiconductor facing the thermocompression-bonded anisotropic conductive film. Thus, the semiconductor device is manufactured by obtaining electrical connection between the electrode of the semiconductor component and the electrode of the flexible substrate. Thus, even if the substrate is warped, it is bent at the time of pressurization, and the semiconductor component is joined to the electrode of the flexible substrate, so that reliable electrical connection can be obtained.

【0015】本発明の請求項5に記載の半導体装置の製
造方法は、半導体部品の電極に対してバンプ形成を行う
工程を有し、前記半導体部品の電極と可撓性基板の電極
との電気的な接続は、前記バンプを介して得ることを特
徴とする。これにより、バンプ形成がなされた半導体部
品を得て前記半導体部品の電極と可撓性基板の電極との
電気的な接続を行うことができる。
According to a fifth aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising the step of forming a bump on an electrode of a semiconductor component, wherein an electrical connection between the electrode of the semiconductor component and the electrode of a flexible substrate is provided. A characteristic connection is obtained through the bump. Thereby, the semiconductor component on which the bumps are formed can be obtained, and the electrodes of the semiconductor component can be electrically connected to the electrodes of the flexible substrate.

【0016】本発明の請求項6に記載の半導体製造方法
は、導電粒子を含む接着剤層と、導電粒子を含まない接
着剤層との多層構造を有する異方性導電膜を用いること
を特徴とする。これにより、多層構造の異方性導電膜に
対し単に載置した状態では、上下方向の絶縁が保たれ、
突出した部分で押圧することにより、上下方向の電気的
接続を得ることができ、必要な接続状態を実現する。
A semiconductor manufacturing method according to a sixth aspect of the present invention uses an anisotropic conductive film having a multilayer structure of an adhesive layer containing conductive particles and an adhesive layer not containing conductive particles. And With this, when simply placed on the anisotropic conductive film having a multilayer structure, vertical insulation is maintained,
By pressing the protruding portion, electrical connection in the vertical direction can be obtained, and a necessary connection state is realized.

【0017】本発明の請求項7に記載の半導体装置の製
造方法にて用いる異方性導電膜は、は、導電粒子を含ま
ない接着剤層と、導電粒子を含む接着剤層との2層構造
または3層構造であることを特徴とする。これにより、
全体の厚みを変えることなく、2層または3層の構造と
し、導電粒子が含まれる第1の接着剤層の厚みを適切に
変更し、単に載置した状態では、上下方向の絶縁が保た
れ、突出した部分で押圧することにより、上下方向の電
気的接続を得る構造とすることができる。
The anisotropic conductive film used in the method of manufacturing a semiconductor device according to claim 7 of the present invention has two layers: an adhesive layer containing no conductive particles and an adhesive layer containing conductive particles. It has a structure or a three-layer structure. This allows
Without changing the overall thickness, a two-layer or three-layer structure is used, and the thickness of the first adhesive layer containing the conductive particles is appropriately changed. By pressing the protruding portion, a structure for obtaining an electrical connection in the vertical direction can be obtained.

【0018】本発明の請求項8に記載の半導体装置の製
造方法は、半導体部品の実装工程の前に、可撓性基板に
対し半導体パッケージとチップ部品との少なくとも一方
が実装される工程が実行されていることを特徴とする。
これにより、先に半導体パッケージやチップ部品が実装
されており、基板に実装された半導体部品がその後のの
実装により剥がれることがなくなる。
According to the method of manufacturing a semiconductor device of the present invention, at least one of a semiconductor package and a chip component is mounted on the flexible substrate before the semiconductor component mounting process. It is characterized by having been done.
As a result, the semiconductor package or chip component is mounted first, and the semiconductor component mounted on the substrate does not peel off during subsequent mounting.

【0019】本発明の請求項9に記載の半導体装置の製
造方法は、半導体部品の実装工程の前に、可撓性基板に
印刷抵抗体が形成される工程が実行されていることを特
徴とする。これにより、マルチチップモジュールを形成
する際に、抵抗チップ部品を新たに可撓性基板に実装す
る必要がなく、基板に実装された半導体部品がその後の
実装により剥がれることがなくなる。
A method of manufacturing a semiconductor device according to a ninth aspect of the present invention is characterized in that a step of forming a printed resistor on a flexible substrate is performed before the step of mounting a semiconductor component. I do. Thus, when forming the multi-chip module, it is not necessary to newly mount the resistive chip component on the flexible substrate, and the semiconductor component mounted on the substrate does not peel off by subsequent mounting.

【0020】本発明の請求項10に記載の半導体装置の
製造方法は、可撓性基板の裏面に離脱自在に硬質基板が
固定されていることを特徴とする。これにより、異方性
導電膜を介在させた状態で半導体部品を可撓性基板に加
熱下で圧着する際に、可撓性基板を搬送し、圧着用の自
動機のヒーターステージ等に固定することが容易であ
り、且つ、固定位置を正確に決めることができることに
なる。
A method of manufacturing a semiconductor device according to a tenth aspect of the present invention is characterized in that a hard substrate is detachably fixed to a back surface of a flexible substrate. With this, when the semiconductor component is press-bonded to the flexible substrate under heating with the anisotropic conductive film interposed, the flexible substrate is transported and fixed to a heater stage of an automatic press-bonding machine. This is easy, and the fixing position can be accurately determined.

【0021】本発明の請求項11に記載の半導体装置の
製造方法では、半導体部品がベアICチップであること
を特徴とする。これにより、ベアICチップを基板に適
切に実装できる。
According to a semiconductor device manufacturing method of the present invention, the semiconductor component is a bare IC chip. Thereby, the bare IC chip can be appropriately mounted on the substrate.

【0022】[0022]

【発明の実施の形態】以下、添付図面を参照して本発明
の実施の形態に係る半導体装置の製造方法及びそれに用
いられる異方性導電膜を説明する。各図において同一構
成要素には、同一の符号を付して重複する説明を省略す
る。本発明の異方性導電膜は図1または図2に示すよう
に、導電粒子を含む接着剤層と、導電粒子を含まない接
着剤層と、の多層構造を有する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A method for manufacturing a semiconductor device according to an embodiment of the present invention and an anisotropic conductive film used therefor will be described below with reference to the accompanying drawings. In the drawings, the same components are denoted by the same reference numerals, and redundant description will be omitted. The anisotropic conductive film of the present invention has a multilayer structure of an adhesive layer containing conductive particles and an adhesive layer not containing conductive particles, as shown in FIG. 1 or FIG.

【0023】図1に、本発明の第1の実施の形態に係る
異方性導電膜50を示す。この異方性導電膜50は、絶
縁性樹脂54内に導電粒子53を含む第1の接着剤層5
1と、導電粒子53を含まない絶縁性樹脂からなる第2
の接着剤層52との2層構造を有する。第1の接着剤層
51の第2の接着剤層52と接しない側の面には剥離可
能な保護用テープ55が貼着されている。第1の接着剤
層51の厚みと第2の接着剤層52の厚みとを加えた厚
みが、従来の異方性導電膜20の厚み(例えば、40〜
50ミクロン)に匹敵し、第1の接着剤層51の厚みと
第2の接着剤層52の厚みの比は、1:1程度である。
絶縁性樹脂54内に含まれる導電粒子53の密度は、従
来の異方性導電膜20の密度に等しい。
FIG. 1 shows an anisotropic conductive film 50 according to a first embodiment of the present invention. This anisotropic conductive film 50 is made of a first adhesive layer 5 containing conductive particles 53 in an insulating resin 54.
1 and a second resin made of an insulating resin not containing the conductive particles 53.
Has a two-layer structure with the adhesive layer 52 of FIG. A releasable protective tape 55 is adhered to a surface of the first adhesive layer 51 that is not in contact with the second adhesive layer 52. The thickness obtained by adding the thickness of the first adhesive layer 51 and the thickness of the second adhesive layer 52 is equal to the thickness of the conventional anisotropic conductive film 20 (for example, 40 to 40).
50 microns), and the ratio of the thickness of the first adhesive layer 51 to the thickness of the second adhesive layer 52 is about 1: 1.
The density of the conductive particles 53 contained in the insulating resin 54 is equal to the density of the conventional anisotropic conductive film 20.

【0024】図2に、本発明の第2の実施の形態に係る
異方性導電膜50Aを示す。この異方性導電膜50A
は、絶縁性樹脂54内に導電粒子53を含む第1の接着
剤層56と、導電粒子53を含まない絶縁性樹脂からな
る第2の接着剤層57と、同じく導電粒子53を含まな
い絶縁性樹脂からなる第3の接着剤層58との3層構造
を有する。そして、上記第1の接着剤層56が前記第2
の接着剤層57と前記第3の接着剤層58との間に挟ま
れている。第2の接着剤層57の第1の接着剤層56と
接しない側の面には剥離可能な保護用テープ55が貼着
されている。第1の接着剤層56の厚みと第2の接着剤
層57の厚みと第3の接着剤層58の厚みとを加えた厚
みが、従来の異方性導電膜20の厚み(例えば、40〜
50ミクロン)に匹敵し、第1の接着剤層56の厚みと
第2の接着剤層57の厚みと第3の接着剤層58の厚み
の比は、1:1:1程度である。絶縁性樹脂54内に含
まれる導電粒子53の密度は、従来の異方性導電膜20
の絶縁性樹脂21内に含まれる導電粒子22の密度に等
しい。
FIG. 2 shows an anisotropic conductive film 50A according to a second embodiment of the present invention. This anisotropic conductive film 50A
Are a first adhesive layer 56 containing conductive particles 53 in an insulating resin 54, a second adhesive layer 57 made of an insulating resin not containing the conductive particles 53, and an insulating layer containing no conductive particles 53. It has a three-layer structure with a third adhesive layer 58 made of a conductive resin. Then, the first adhesive layer 56 is
Between the third adhesive layer 58 and the third adhesive layer 58. A releasable protective tape 55 is adhered to a surface of the second adhesive layer 57 that is not in contact with the first adhesive layer 56. The thickness obtained by adding the thickness of the first adhesive layer 56, the thickness of the second adhesive layer 57, and the thickness of the third adhesive layer 58 is equal to the thickness of the conventional anisotropic conductive film 20 (for example, 40 ~
50 μm), and the ratio of the thickness of the first adhesive layer 56, the thickness of the second adhesive layer 57, and the thickness of the third adhesive layer 58 is about 1: 1: 1. The density of the conductive particles 53 contained in the insulating resin 54 is the same as that of the conventional anisotropic conductive film 20.
Is equal to the density of the conductive particles 22 contained in the insulating resin 21.

【0025】本発明の実施の形態に係る半導体装置の製
造工程フローは図3に示すようであり、製造工程が図4
〜図7に示されている。これを説明すると、図4等に示
されるような可撓性基板40が用意される(S1)。こ
の可撓性基板40はポリイミド等にて形成され、半導体
部品であるベアICチップ60が実装される部品実装面
41には複数の配線パターン42が導電材料にて形成さ
れている。また、各配線パターン42の先端には金メッ
キが施されて電極43が形成され、且つ、各配線パター
ン42は、電極43の部分を除いてカバーレイ44で覆
われ絶縁されている。
The manufacturing process flow of the semiconductor device according to the embodiment of the present invention is as shown in FIG.
7 to FIG. To explain this, a flexible substrate 40 as shown in FIG. 4 and the like is prepared (S1). The flexible substrate 40 is formed of polyimide or the like, and a plurality of wiring patterns 42 are formed of a conductive material on a component mounting surface 41 on which a bare IC chip 60 as a semiconductor component is mounted. Also, gold plating is applied to the tip of each wiring pattern 42 to form an electrode 43, and each wiring pattern 42 is covered with a coverlay 44 and insulated except for the electrode 43.

【0026】ベアICチップ60の実装のために用いら
れる異方性導電膜50は、面積の広いシート形状をして
おり、ベアICチップ60の所定の面61の面積よりも
若干大きく切り出される(S2)。異方性導電膜50の
導電粒子53を含まない第2の接着剤層52(図5に示
す3層構造の異方性導電膜50Aを用いた場合には、第
3の接着剤層58)の一方の面を可撓性基板40に接着
する(S3)。具体的には、ボンディングツール70の
バキューム機構により、図4に示されるように異方性導
電膜50を保護シート55側から吸着して、可撓性基板
40の部品実装面41上に載置する。一方、可撓性基板
40はヒーターステージ71上にセットされ加熱さる。
そして、ボンディングツール70を可撓性基板40上の
所定位置に位置付け、このボンディングツール70を下
降させ、異方性導電膜50を保護用テープ55側から加
圧、加熱する。次に、異方性導電膜50の保護シート5
5が剥がされる。斯して、図5に示すような異方性導電
膜50が接着された状態の可撓性基板40が得られる。
The anisotropic conductive film 50 used for mounting the bare IC chip 60 has a sheet shape with a large area, and is cut out slightly larger than the area of the predetermined surface 61 of the bare IC chip 60 ( S2). Second adhesive layer 52 not including conductive particles 53 of anisotropic conductive film 50 (third adhesive layer 58 when using anisotropic conductive film 50A having a three-layer structure shown in FIG. 5) Is bonded to the flexible substrate 40 (S3). More specifically, the anisotropic conductive film 50 is sucked from the protective sheet 55 side by the vacuum mechanism of the bonding tool 70 and placed on the component mounting surface 41 of the flexible substrate 40 as shown in FIG. I do. On the other hand, the flexible substrate 40 is set on the heater stage 71 and heated.
Then, the bonding tool 70 is positioned at a predetermined position on the flexible substrate 40, the bonding tool 70 is lowered, and the anisotropic conductive film 50 is pressed and heated from the protective tape 55 side. Next, the protective sheet 5 of the anisotropic conductive film 50
5 is peeled off. Thus, the flexible substrate 40 with the anisotropic conductive film 50 adhered thereto as shown in FIG. 5 is obtained.

【0027】一方、図6等に示されるようなベアICチ
ップ60を用意する(S4)。このベアICチップ60
は、所定の面61にAl(アルミニューム)等の導電材料
で形成された複数の電極62が可撓性基板40の電極4
3に対応させて配置されている。次に、ベアICチップ
60の各電極62の表面にめっき等によって各々バンプ
63を形成する(S5)。バンプ63はAu(金)又はSn
-Pb (スズ−鉛)合金等の金属材料で形成されている。
On the other hand, a bare IC chip 60 as shown in FIG. 6 and the like is prepared (S4). This bare IC chip 60
A plurality of electrodes 62 formed of a conductive material such as Al (aluminum) on a predetermined surface 61
3 are arranged. Next, bumps 63 are formed on the surfaces of the electrodes 62 of the bare IC chip 60 by plating or the like (S5). The bump 63 is made of Au (gold) or Sn
-Pb (Tin-Lead) alloy and other metal materials.

【0028】次の工程(S6)においては、可撓性基板
40に接着された異方性導電膜50の導電粒子53を含
む第1の接着剤層51に、バンプ63が形成されたベア
ICチップ60を接着する。この工程(S6)において
は、図6に示すように、可撓性基板40はヒータステー
ジ71上にセットされ加熱される。そして、ベアICチ
ップ60をボンディングツール70に保持させ、このベ
アICチップ60を可撓性基板40上の異方性導電膜5
0上に位置付け、このボンディングツール70を下降さ
せ、可撓性基板40に接着されている異方性導電膜50
の導電粒子53を含む第1の接着剤層51にベアICチ
ップ60を押しつけて異方性導電膜50を加圧、加熱す
る。
In the next step (S6), a bare IC having bumps 63 formed on a first adhesive layer 51 including conductive particles 53 of an anisotropic conductive film 50 bonded to a flexible substrate 40 is formed. The chip 60 is bonded. In this step (S6), as shown in FIG. 6, the flexible substrate 40 is set on the heater stage 71 and heated. Then, the bare IC chip 60 is held by the bonding tool 70, and the bare IC chip 60 is attached to the anisotropic conductive film 5 on the flexible substrate 40.
0, the bonding tool 70 is lowered, and the anisotropic conductive film 50 adhered to the flexible substrate 40 is
The bare IC chip 60 is pressed against the first adhesive layer 51 containing the conductive particles 53, and the anisotropic conductive film 50 is pressed and heated.

【0029】上記により、図7に示すように、可撓性基
板40の部品実装面41側とベアICチップ60の所定
の面61側とは異方性導電膜50の絶縁性樹脂54を介
して接合される。また、異方性導電膜50の導電粒子5
3はバンプ63により可撓性基板40の電極43に押圧
されるので、可撓性基板40上の電極43とベアICチ
ップ60の電極62とは電気的に接続される。これと共
に、可撓性基板40が可撓性である故に加圧によって撓
むことにより、可撓性基板40の電極43とベアICチ
ップ60のバンプ63との間の間隙が消滅され、可撓性
基板40とベアICチップ60との電気的接続は適切に
確保される。
As described above, as shown in FIG. 7, the component mounting surface 41 of the flexible substrate 40 and the predetermined surface 61 of the bare IC chip 60 are interposed via the insulating resin 54 of the anisotropic conductive film 50. Joined. The conductive particles 5 of the anisotropic conductive film 50
3 is pressed against the electrode 43 of the flexible substrate 40 by the bump 63, so that the electrode 43 on the flexible substrate 40 and the electrode 62 of the bare IC chip 60 are electrically connected. At the same time, since the flexible substrate 40 is flexible and bends due to pressure, the gap between the electrode 43 of the flexible substrate 40 and the bump 63 of the bare IC chip 60 disappears, Electrical connection between the conductive substrate 40 and the bare IC chip 60 is appropriately secured.

【0030】上記により、可撓性基板40が反りを帯び
ている場合にも、加圧によりベアICチップ60に追従
すべく撓むことにより可撓性基板40の電極43とベア
ICチップ60のバンプ63との間の間隙が消滅され
る。また、2層構造の異方性導電膜50を用いているた
め、可撓性基板40の部品実装面41に形成されている
各電極43の間は、導電粒子53を含まない第2の接着
剤層52によって覆われるため、回路絶縁の維持が容易
に実現できる。また、2層構造の異方性導電膜50を用
いているが、第1の接着剤層51の導電粒子53が突起
物であるベアICチップ60のバンプ63に押されて可
撓性基板40の電極43側に運ばれ、バンプ63と電極
43間に必要十分な導電粒子53を介在させることが可
能で、特に異方性導電膜50を厚くする必要がない。つ
まり、面41から面61に到る距離(厚み)を第1の接
着剤層51と第2の接着剤層52により実現している。
このため、異方性導電膜50によるボンディングツール
70の汚染を防止できる上に、導電粒子53が含まれる
第1の接着剤層51が薄く、導電粒子53が含まれない
第2の接着剤層52(第3の接着剤層58も)はほぼ透
明であり、全体として透明度が高くなるので、可撓性基
板40上の電極43を目視認識することも容易であり、
位置合わせの精度を向上させ、品質の良い半導体装置を
製造することができる。
As described above, even when the flexible substrate 40 is warped, the electrode 43 of the flexible substrate 40 and the bare IC chip 60 are bent by bending to follow the bare IC chip 60 by pressing. The gap between the bump 63 is eliminated. In addition, since the two-layer anisotropic conductive film 50 is used, the second adhesives not including the conductive particles 53 are provided between the electrodes 43 formed on the component mounting surface 41 of the flexible substrate 40. Since it is covered by the agent layer 52, maintenance of circuit insulation can be easily realized. Further, although the anisotropic conductive film 50 having a two-layer structure is used, the conductive particles 53 of the first adhesive layer 51 are pressed by the bumps 63 of the bare IC chip 60 which are protrusions, and the flexible substrate 40 is formed. And the conductive particles 53 required and sufficient can be interposed between the bump 63 and the electrode 43, and it is not particularly necessary to increase the thickness of the anisotropic conductive film 50. That is, the distance (thickness) from the surface 41 to the surface 61 is realized by the first adhesive layer 51 and the second adhesive layer 52.
Therefore, contamination of the bonding tool 70 by the anisotropic conductive film 50 can be prevented, and the first adhesive layer 51 including the conductive particles 53 is thin and the second adhesive layer including no conductive particles 53 is included. 52 (also the third adhesive layer 58) is substantially transparent and has high transparency as a whole, so that it is easy to visually recognize the electrode 43 on the flexible substrate 40,
The alignment accuracy can be improved, and a high-quality semiconductor device can be manufactured.

【0031】なお、図2に示した3層構造の異方性導電
膜50Aを用いた場合にも、上記と同様に、各電極43
相互の絶縁を図ることができ、バンプ63と電極43間
に必要十分な導電粒子53を介在させることが可能で、
特に異方性導電膜50Aを厚くする必要がない。このた
め、異方性導電膜50Aによるボンディングツール70
の汚染を防止できる上に、導電粒子53が含まれる第1
の接着剤層56が薄く、全体として透明度が高くなるの
で、可撓性基板40上の電極43を目視認識することも
容易であり、位置合わせの精度を向上させ、品質の良い
半導体装置を製造することができる。
In the case where the anisotropic conductive film 50A having a three-layer structure shown in FIG.
Mutual insulation can be achieved, and necessary and sufficient conductive particles 53 can be interposed between the bump 63 and the electrode 43.
In particular, it is not necessary to increase the thickness of the anisotropic conductive film 50A. Therefore, the bonding tool 70 using the anisotropic conductive film 50A is used.
And the first particles containing the conductive particles 53 can be prevented.
Since the adhesive layer 56 is thin and the overall transparency is high, it is also easy to visually recognize the electrode 43 on the flexible substrate 40, improve the alignment accuracy, and manufacture a high-quality semiconductor device. can do.

【0032】図8には、変形例に係る可撓性基板40A
及びそれの使用例が示されている。この可撓性基板40
Aは、図8(a)に示すように、ベアICチップ60が
実装される前に、半導体パッケージ81とチップ部品8
2と(勿論、これらの少なくとも一方でも良い)が実装
される工程が実行されていることを特徴とする。ここ
に、半導体パッケージ81とチップ部品82とは、例え
ば、リフロー半田付けの工程により半田付けがなされ
る。この後に、ベアICチップ60が図3乃至図7を用
いて説明した如くにして実装される。そして、更に、図
8(b)に示すように、筐体80内の基板83と基板8
4との間に折り曲げて実装する。基板83とは、例え
ば、可撓性基板40Aの電極49Aにより接続され、基
板84とは可撓性基板40Aの電極49Bにより接続が
なされる。
FIG. 8 shows a flexible substrate 40A according to a modification.
And examples of its use. This flexible substrate 40
8A, before the bare IC chip 60 is mounted, as shown in FIG.
2 (and, of course, at least one of them) may be implemented. Here, the semiconductor package 81 and the chip component 82 are soldered by, for example, a reflow soldering process. Thereafter, the bare IC chip 60 is mounted as described with reference to FIGS. Then, as shown in FIG. 8B, the board 83 and the board 8
4 and mounted. The substrate 83 is connected, for example, by an electrode 49A of the flexible substrate 40A, and the substrate 84 is connected by an electrode 49B of the flexible substrate 40A.

【0033】上記により、半導体パッケージ81とチッ
プ部品82が、ベアICチップ60の実装を行う前に実
装されているので、ベアICチップ60を実装した後に
半田付け等による熱で剥離したりダメージを受ける心配
がない。また、図8(b)のような三次元実装構造のマ
ルチチップモジュールも容易に構成できる。
As described above, since the semiconductor package 81 and the chip component 82 are mounted before the mounting of the bare IC chip 60, the semiconductor package 81 and the chip component 82 are peeled off or damaged by heat after soldering or the like after mounting the bare IC chip 60. I do not have to worry. Also, a multi-chip module having a three-dimensional mounting structure as shown in FIG. 8B can be easily configured.

【0034】図9には、変形例に係る可撓性基板40B
が示されている。ベアICチップ60の実装工程の前
に、可撓性基板40Bに印刷抵抗体48が形成される工
程が実行されていることを特徴とする。この印刷抵抗体
48は次のようにして形成される。印刷抵抗体48を転
写するためのシート90上には、印刷抵抗体膜91が設
けられている。一方、可撓性基板40Bには、印刷抵抗
体48の電極47A、47Bが形成されている。そこ
で、シート90の印刷抵抗体膜91が電極47A、47
Bを端部とするように位置合わせして重ね、ローラー9
2により加圧・加熱して転写を行う。この後に、ベアI
Cチップ60が図3乃至図7を用いて説明した如くにし
て実装される。これにより、マルチチップモジュールを
形成する際に、印刷抵抗体48を新たに可撓性基板40
Bに実装する必要がなく、抵抗を半田等により実装する
こともないから、可撓性基板40Bに実装された半導体
部品であるベアICチップ60が抵抗の実装(半田付
け)時の熱により剥がれることがなくなる。
FIG. 9 shows a flexible substrate 40B according to a modification.
It is shown. Before the step of mounting the bare IC chip 60, a step of forming the printed resistor 48 on the flexible substrate 40B is performed. This print resistor 48 is formed as follows. A print resistor film 91 is provided on a sheet 90 for transferring the print resistor 48. On the other hand, the electrodes 47A and 47B of the printed resistor 48 are formed on the flexible substrate 40B. Therefore, the printed resistor film 91 of the sheet 90 is connected to the electrodes 47A and 47A.
B is positioned at the end so that the roller 9
The transfer is performed by applying pressure and heating in step 2. After this, Bear I
The C chip 60 is mounted as described with reference to FIGS. Thereby, when forming the multi-chip module, the printed resistor 48 is newly added to the flexible substrate 40.
Since it is not necessary to mount the resistor on the flexible substrate 40B, the bare IC chip 60, which is a semiconductor component mounted on the flexible substrate 40B, is peeled off by the heat when the resistor is mounted (soldered). Disappears.

【0035】図10には、変形例に係る可撓性基板40
Cが示されている。この可撓性基板の40C裏面には離
脱自在にガラスエポキシ系の材料にて構成される硬質基
板95が固定されている。具体的には、可撓性基板の4
0Cと硬質基板95とは、端縁部から所定の幅の位置に
穴97が一周して穿設されている。そして、穴97より
も外の周縁においては、可撓性基板の40Cと硬質基板
95とが接着剤により接着されており、穴97が描く四
角形の内側では可撓性基板の40Cと硬質基板95とが
非接着の状態にある。
FIG. 10 shows a flexible substrate 40 according to a modification.
C is shown. A rigid substrate 95 made of a glass epoxy material is fixed to the back surface of the flexible substrate 40C so as to be detachable. Specifically, 4 of the flexible substrate
A hole 97 is formed in the 0C and the hard substrate 95 at a position having a predetermined width from the edge portion. At the outer periphery of the hole 97, the flexible substrate 40C and the rigid substrate 95 are adhered by an adhesive, and inside the rectangle defined by the hole 97, the flexible substrate 40C and the rigid substrate 95 are bonded. Are in a non-adhered state.

【0036】この可撓性基板40Cを用いて、図3乃至
図7を用いて説明した如くにして、異方性導電膜50を
介在させた状態でベアICチップ60を可撓性基板40
Cの部品実装面に加熱下で圧着する際には、可撓性基板
40Cを硬質基板95が付加された図10の状態で搬送
し、圧着用の自動機のヒーターステージ71上に固定す
ることが容易であり、且つ、固定位置を正確に決めるこ
とができる。そして、ベアICチップ60の実装が終了
した段階で、穴97が描く四角形の破線部で接断して可
撓性基板の40Cを硬質基板95から切り離す。この可
撓性基板40Cは、例えば、図8(b)に示されるよう
に、三次元実装に用いられる。なお、本発明の可撓性基
板は、図8から図10の組み合わせにより構成される。
つまり、必要に応じて部品が実装され、また、裏面に硬
質基板が取り外し可能に設けられる。
Using the flexible substrate 40C, as described with reference to FIGS. 3 to 7, the bare IC chip 60 is attached to the flexible substrate 40 with the anisotropic conductive film 50 interposed therebetween.
When pressure-bonding to the component mounting surface of C under heating, the flexible substrate 40C is transported in the state of FIG. 10 to which the hard substrate 95 is added, and is fixed on the heater stage 71 of an automatic crimping machine. And the fixing position can be accurately determined. Then, at the stage where the mounting of the bare IC chip 60 is completed, the flexible substrate 40 </ b> C is cut off from the hard substrate 95 by cutting and connecting at a rectangular broken line portion drawn by the hole 97. This flexible substrate 40C is used for three-dimensional mounting, for example, as shown in FIG. Note that the flexible substrate of the present invention is configured by a combination of FIGS.
That is, components are mounted as needed, and a hard substrate is detachably provided on the back surface.

【0037】[0037]

【発明の効果】以上説明したように本発明の異方性導電
膜によれば、導電粒子を含む接着剤層と、導電粒子を含
まない接着剤層との多層構造となっているので、単に載
置した状態では、上下方向の絶縁が保たれ、突出した部
分で押圧することにより、上下方向の電気的接続を得る
ことができる。
As described above, the anisotropic conductive film of the present invention has a multilayer structure of an adhesive layer containing conductive particles and an adhesive layer not containing conductive particles. In the mounted state, the insulation in the vertical direction is maintained, and the electrical connection in the vertical direction can be obtained by pressing the protruding portion.

【0038】以上説明したように本発明の半導体装置の
製造方法によれば、可撓性基板を用いているので、基板
に反りがあっても加圧時に撓んで、可撓性基板の電極に
対して半導体部品が接合されることになり、確実な電気
的接続を得ることができる。
As described above, according to the method of manufacturing a semiconductor device of the present invention, since a flexible substrate is used, even if the substrate is warped, the substrate is bent at the time of pressurization, and the electrode of the flexible substrate is bent. On the other hand, the semiconductor components are joined, so that reliable electrical connection can be obtained.

【0039】以上説明したように本発明の半導体装置の
製造方法によれば、導電粒子を含む接着剤層と、導電粒
子を含まない接着剤層との多層構造の異方性導電膜を用
いるので、単に載置した状態では、上下方向の絶縁が保
たれ、突出した部分で押圧することにより、上下方向の
電気的接続を得ることができる。
As described above, according to the method of manufacturing a semiconductor device of the present invention, the anisotropic conductive film having a multilayer structure of the adhesive layer containing conductive particles and the adhesive layer not containing conductive particles is used. In the state of being simply placed, the insulation in the up-down direction is maintained, and the electrical connection in the up-down direction can be obtained by pressing the protruding portion.

【0040】以上説明したように本発明の半導体装置の
製造方法によれば、半導体部品の電極に対してバンプ形
成を行う工程を有し、前記半導体部品の電極と可撓性基
板の電極との電気的な接続は、前記バンプを介して得る
ので、バンプ形成がなされた半導体部品を得て前記半導
体部品の電極と可撓性基板の電極との電気的な接続を行
うことができる。
As described above, according to the method of manufacturing a semiconductor device of the present invention, a step of forming a bump on an electrode of a semiconductor component is provided. Since the electrical connection is obtained via the bumps, it is possible to obtain the semiconductor component on which the bump is formed, and to electrically connect the electrodes of the semiconductor component and the electrodes of the flexible substrate.

【0041】以上説明したように本発明の半導体装置の
製造方法によれば、半導体部品の実装工程の前に、可撓
性基板に対し半導体パッケージとチップ部品との少なく
とも一方が実装される工程が実行されるので、、先に半
導体パッケージやチップ部品が実装されており、基板に
実装された半導体部品がその後の実装により剥がれるこ
とがなくなる。
As described above, according to the method of manufacturing a semiconductor device of the present invention, before the semiconductor component mounting step, the step of mounting at least one of the semiconductor package and the chip component on the flexible substrate is performed. Since the process is executed, the semiconductor package and the chip component are mounted first, and the semiconductor component mounted on the substrate does not peel off by the subsequent mounting.

【0042】以上説明したように本発明の半導体装置の
製造方法によれば、半導体部品の実装工程の前に、可撓
性基板に印刷抵抗体が形成される工程が実行されるの
で、マルチチップモジュールを形成する際に、抵抗部品
を新たに可撓性基板に実装する必要がなく、基板に実装
された半導体部品がその後の実装により剥がれることが
なくなる。
As described above, according to the method of manufacturing a semiconductor device of the present invention, the step of forming a printed resistor on a flexible substrate is performed before the step of mounting a semiconductor component. When forming the module, it is not necessary to newly mount the resistance component on the flexible substrate, and the semiconductor component mounted on the substrate does not peel off by subsequent mounting.

【0043】以上説明したように本発明の半導体装置の
製造方法によれば、可撓性基板の裏面に離脱自在に硬質
基板が固定されているものを用いるので、異方性導電膜
を介在させた状態で半導体部品を可撓性基板に加熱下で
圧着する際に、可撓性基板を搬送し、圧着用の自動機の
ヒーターステージ等に固定することが容易であり、且
つ、固定位置を正確に決めることができることになる。
As described above, according to the method for manufacturing a semiconductor device of the present invention, a flexible substrate is used in which a hard substrate is fixed to the back surface so as to be detachable. When the semiconductor component is press-bonded to the flexible substrate in a heated state in a heated state, it is easy to transport the flexible substrate and fix it to a heater stage or the like of an automatic crimping machine, and set the fixing position. It can be determined accurately.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の実施の形態に係る2層構造の異方性導
電膜の断面図。
FIG. 1 is a cross-sectional view of a two-layer anisotropic conductive film according to an embodiment of the present invention.

【図2】本発明の実施の形態に係る3層構造の異方性導
電膜の断面図。
FIG. 2 is a cross-sectional view of a three-layered anisotropic conductive film according to an embodiment of the present invention.

【図3】本発明の実施の形態に係る半導体装置の製造方
法の工程フローを示す図。
FIG. 3 is a view showing a process flow of a method for manufacturing a semiconductor device according to an embodiment of the present invention;

【図4】本発明の実施の形態に係る半導体装置の製造方
法における異方性導電膜の接着工程を示す図。
FIG. 4 is a view showing a step of bonding an anisotropic conductive film in a method for manufacturing a semiconductor device according to an embodiment of the present invention.

【図5】本発明の実施の形態に係る半導体装置の製造方
法における異方性導電膜が接着された状態を示す図。
FIG. 5 is a diagram showing a state in which an anisotropic conductive film is bonded in the method for manufacturing a semiconductor device according to the embodiment of the present invention.

【図6】本発明の実施の形態に係る半導体装置の製造方
法におけるベアICチップの接着初期の工程を示す図。
FIG. 6 is a diagram showing an initial step of bonding bare IC chips in a method of manufacturing a semiconductor device according to an embodiment of the present invention.

【図7】本発明の実施の形態に係る半導体装置の製造方
法におけるベアICチップの接着最終の工程を示す図。
FIG. 7 is a view showing a final step of bonding bare IC chips in the method of manufacturing a semiconductor device according to the embodiment of the present invention;

【図8】第1の変形例に係る可撓性基板及びその使用例
を示す図。
FIG. 8 is a view showing a flexible substrate according to a first modification and an example of its use.

【図9】第2の変形例に係る可撓性基板を示す図。FIG. 9 is a view showing a flexible substrate according to a second modification.

【図10】第3の変形例に係る可撓性基板を示す図。FIG. 10 is a view showing a flexible substrate according to a third modification.

【図11】従来例に係る半導体装置の製造方法における
ベアICチップの接着の工程を示す図。
FIG. 11 is a view showing a step of bonding bare IC chips in a method of manufacturing a semiconductor device according to a conventional example.

【符号の説明】[Explanation of symbols]

40、40A〜40C 可撓性基板 43 電極 50、50A 異方性導電膜 51、56
第1の接着剤層 52、57 第2の接着剤層 58 第3
の接着剤層 60 ベアICチップ 62 電極 63 バンプ
40, 40A to 40C Flexible substrate 43 Electrode 50, 50A Anisotropic conductive film 51, 56
First adhesive layer 52, 57 Second adhesive layer 58 Third
Adhesive layer 60 bare IC chip 62 electrode 63 bump

Claims (11)

【特許請求の範囲】[Claims] 【請求項1】 導電粒子を含む接着剤層と、 導電粒子を含まない接着剤層との多層構造を有する異方
性導電膜。
1. An anisotropic conductive film having a multilayer structure of an adhesive layer containing conductive particles and an adhesive layer not containing conductive particles.
【請求項2】 導電粒子を含む第1の接着剤層と、 導電粒子を含まない第2の接着剤層との2層構造を有す
る異方性導電膜。
2. An anisotropic conductive film having a two-layer structure of a first adhesive layer containing conductive particles and a second adhesive layer containing no conductive particles.
【請求項3】 導電粒子を含む第1の接着剤層と、 導電粒子を含まない第2の接着剤層と、 導電粒子を含まない第3の接着剤層との3層構造を有
し、 前記第1の接着剤層が前記第2の接着剤層と前記第3の
接着剤層との間に挟まれていることを特徴とする異方性
導電膜。
3. It has a three-layer structure of a first adhesive layer containing conductive particles, a second adhesive layer not containing conductive particles, and a third adhesive layer not containing conductive particles. An anisotropic conductive film, wherein the first adhesive layer is sandwiched between the second adhesive layer and the third adhesive layer.
【請求項4】 半導体部品の電極に対して接続する電極
を有する可撓性基板を用い、 実装される前記半導体部品に対応して異方性導電膜を前
記可撓性基板の前記電極を覆うように載置して熱圧着
し、 熱圧着された前記異方性導電膜に対して前記半導体の電
極面を向けて載置し熱圧着することにより、 前記半導体部品の電極と前記可撓性基板の電極との電気
的な接続を得て半導体装置を製造することを特徴とする
半導体装置の製造方法。
4. A flexible substrate having an electrode connected to an electrode of a semiconductor component, and an anisotropic conductive film covering the electrode of the flexible substrate corresponding to the semiconductor component to be mounted. And the thermocompression bonding is performed, and the thermocompression bonding is performed by mounting the thermoelectrically pressurized anisotropic conductive film with the electrode surface of the semiconductor facing the anisotropic conductive film. A method for manufacturing a semiconductor device, comprising: manufacturing a semiconductor device by obtaining electrical connection with an electrode of a substrate.
【請求項5】 半導体部品の電極に対してバンプ形成を
行う工程を有し、 前記半導体部品の電極と可撓性基板の電極との電気的な
接続は、前記バンプを介して得ることを特徴とする請求
項4に記載の半導体装置の製造方法。
5. The method according to claim 1, further comprising the step of forming a bump on the electrode of the semiconductor component, wherein the electrical connection between the electrode of the semiconductor component and the electrode of the flexible substrate is obtained via the bump. The method for manufacturing a semiconductor device according to claim 4.
【請求項6】 導電粒子を含む接着剤層と、導電粒子を
含まない接着剤層との多層構造を有する異方性導電膜を
用いることを特徴とする請求項4または請求項5に記載
の半導体装置の製造方法。
6. The anisotropic conductive film having a multilayer structure of an adhesive layer containing conductive particles and an adhesive layer not containing conductive particles is used according to claim 4 or 5. A method for manufacturing a semiconductor device.
【請求項7】 異方性導電膜は、導電粒子を含む接着剤
層と、導電粒子を含まない接着剤層との2層構造、また
は、3層構造であることを特徴とする請求項6に記載の
半導体装置の製造方法。
7. The anisotropic conductive film has a two-layer structure or a three-layer structure of an adhesive layer containing conductive particles and an adhesive layer not containing conductive particles. 13. The method for manufacturing a semiconductor device according to item 5.
【請求項8】 半導体部品の実装工程の前に、可撓性基
板にに対し半導体パッケージとチップ部品との少なくと
も一方が実装される工程が実行されていることを特徴と
する請求項4乃至7のいずれか1項に記載の半導体装置
の製造方法。
8. The method according to claim 4, wherein a step of mounting at least one of a semiconductor package and a chip component on the flexible substrate is performed before the semiconductor component mounting step. 13. The method for manufacturing a semiconductor device according to claim 1.
【請求項9】 半導体部品の実装工程の前に、可撓性基
板に印刷抵抗体が形成される工程が実行されていること
を特徴とする請求項4乃至8のいずれか1項に記載の半
導体装置の製造方法。
9. The method according to claim 4, wherein a step of forming a printed resistor on the flexible substrate is performed before the step of mounting the semiconductor component. A method for manufacturing a semiconductor device.
【請求項10】 可撓性基板の裏面に離脱自在に硬質基
板が固定されていることを特徴とする請求項4乃至9の
いずれか1項に記載の半導体装置の製造方法。
10. The method of manufacturing a semiconductor device according to claim 4, wherein a hard substrate is detachably fixed to a back surface of the flexible substrate.
【請求項11】 半導体部品は、ベアICチップである
ことを特徴とする請求項4乃至10のいずれか1項に記
載の半導体装置の製造方法。
11. The method for manufacturing a semiconductor device according to claim 4, wherein the semiconductor component is a bare IC chip.
JP29832697A 1997-10-30 1997-10-30 Anisotropic conductive film and manufacture of semiconductor device Withdrawn JPH11135567A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP29832697A JPH11135567A (en) 1997-10-30 1997-10-30 Anisotropic conductive film and manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP29832697A JPH11135567A (en) 1997-10-30 1997-10-30 Anisotropic conductive film and manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH11135567A true JPH11135567A (en) 1999-05-21

Family

ID=17858219

Family Applications (1)

Application Number Title Priority Date Filing Date
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Country Status (1)

Country Link
JP (1) JPH11135567A (en)

Cited By (7)

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Publication number Priority date Publication date Assignee Title
JPH11195860A (en) * 1997-12-27 1999-07-21 Canon Inc Bonding member, multichip module with the bonding member and bonding method using the bonding member
WO2000033375A1 (en) * 1998-12-02 2000-06-08 Seiko Epson Corporation Anisotropic conductor film, semiconductor chip, and method of packaging
JP2002280716A (en) * 2001-03-19 2002-09-27 Pioneer Electronic Corp Electronic part mounting method and bonded body
JP2007281054A (en) * 2006-04-04 2007-10-25 Nec Corp Electronic component mounting structure, and its manufacturing method
JP2011211245A (en) * 2011-07-27 2011-10-20 Sony Chemical & Information Device Corp Method of manufacturing connection structure, connection structure, and connection method
JP2014043574A (en) * 2012-08-03 2014-03-13 Dexerials Corp Anisotropic conductive film and method for producing the same
WO2023162666A1 (en) * 2022-02-28 2023-08-31 デクセリアルズ株式会社 Connection structure manufacturing method, film structure, and film structure manufacturing method

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11195860A (en) * 1997-12-27 1999-07-21 Canon Inc Bonding member, multichip module with the bonding member and bonding method using the bonding member
WO2000033375A1 (en) * 1998-12-02 2000-06-08 Seiko Epson Corporation Anisotropic conductor film, semiconductor chip, and method of packaging
US6426566B1 (en) 1998-12-02 2002-07-30 Seiko Epson Corporation Anisotropic conductor film, semiconductor chip, and method of packaging
JP2002280716A (en) * 2001-03-19 2002-09-27 Pioneer Electronic Corp Electronic part mounting method and bonded body
JP2007281054A (en) * 2006-04-04 2007-10-25 Nec Corp Electronic component mounting structure, and its manufacturing method
JP4735378B2 (en) * 2006-04-04 2011-07-27 日本電気株式会社 Electronic component mounting structure and manufacturing method thereof
JP2011211245A (en) * 2011-07-27 2011-10-20 Sony Chemical & Information Device Corp Method of manufacturing connection structure, connection structure, and connection method
JP2014043574A (en) * 2012-08-03 2014-03-13 Dexerials Corp Anisotropic conductive film and method for producing the same
WO2023162666A1 (en) * 2022-02-28 2023-08-31 デクセリアルズ株式会社 Connection structure manufacturing method, film structure, and film structure manufacturing method

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