JPH11195860A - Bonding member, multichip module with the bonding member and bonding method using the bonding member - Google Patents

Bonding member, multichip module with the bonding member and bonding method using the bonding member

Info

Publication number
JPH11195860A
JPH11195860A JP9369101A JP36910197A JPH11195860A JP H11195860 A JPH11195860 A JP H11195860A JP 9369101 A JP9369101 A JP 9369101A JP 36910197 A JP36910197 A JP 36910197A JP H11195860 A JPH11195860 A JP H11195860A
Authority
JP
Japan
Prior art keywords
substrate
electrodes
electric
adhesive layer
electric element
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9369101A
Other languages
Japanese (ja)
Inventor
Hiroshi Takabayashi
広 高林
Masanori Takahashi
雅則 高橋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Canon Inc
Original Assignee
Canon Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Canon Inc filed Critical Canon Inc
Priority to JP9369101A priority Critical patent/JPH11195860A/en
Priority to US09/221,142 priority patent/US6172878B1/en
Publication of JPH11195860A publication Critical patent/JPH11195860A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/831Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
    • H01L2224/83101Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus as prepeg comprising a layer connector, e.g. provided in an insulating plate member
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06Polymers
    • H01L2924/078Adhesive characteristics other than chemical
    • H01L2924/0781Adhesive characteristics other than chemical being an ohmic electrical conductor
    • H01L2924/07811Extrinsic, i.e. with electrical conductive fillers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191Disposition
    • H01L2924/19101Disposition of discrete passive components
    • H01L2924/19105Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

Landscapes

  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Abstract

PROBLEM TO BE SOLVED: To perform a temporary bonding operation by a simple apparatus and to suppress a rise in the production cost of a multichip module. SOLUTION: When electric elements 2, 3, 4, 5 are bonded to a board 1, an ACF 10 as shown in the figure is used. The ACF 10 is constituted in such a way that a bonding layer 11 which is adhesive at room temperature and an anisotropic conductive layer 12 which is formed by dispersing and mixing conductive particles 12b into and with a resin 12a are laminated. When the electric elements 2, 3, 4, 5 are pressed to the board 1 so as to sandwich the ACF 10, both are bonded temporarily by the adhesive property of the bonding layer 11. Consequently, it is not required to perform a heating operation and a pressurizing operation when both are bonded temporarily as different from an ACF 10 in conventional cases. Both are bonded temporarily by a simple and low-cost apparatus which is provided with only a pressurizing function and which is not provided with a heating function, and a rise in the production cost of a multichip module can be suppressed.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、2つの電気部品に
おける対向する電極相互の導電性を確保した状態でこれ
ら2つの電気部品を接着する接着部材、該接着部材を備
えたマルチチップモジュール、及び該接着部材による接
着方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an adhesive member for adhering two electric components while ensuring the mutual conductivity of the opposing electrodes of the two electric components, a multi-chip module provided with the adhesive member, and The present invention relates to a bonding method using the bonding member.

【0002】[0002]

【従来の技術】従来より、2つの電気部品を接着するた
めの接着部材であって、これら2つの電気部品における
対向する電極相互の導電性を確保できるようにしたもの
としては、半田や、異方性導電接着剤(以下、“AC
F”とする)が利用されている。
2. Description of the Related Art Conventionally, as an adhesive member for adhering two electric components, which can ensure the conductivity between opposing electrodes of the two electric components, there are solder, a different material, and the like. Anisotropic conductive adhesive (hereinafter referred to as “AC
F ") is used.

【0003】図1は、2つの電気部品(基板及び電気素
子)を半田によって接着した従来構造の一例を示したも
のである。図中の符号1は、ガラスエポキシやセラミッ
ク等からなる基板であり、この基板1には、複数の電気
素子(例えば、IC2、抵抗やコンデンサー等の受動素
子3、及びコネクター等の機構部品4,5)が半田6に
よって接着されている。なお、基板1の表面並びに各電
気素子2,3,4,5には、それらが接着された状態で
互いに対向するように電極1a,1b,1c,1d及び
電極2a,3a,4a,5aがそれぞれ形成されてい
る。
FIG. 1 shows an example of a conventional structure in which two electric components (a substrate and an electric element) are bonded by soldering. Reference numeral 1 in the figure denotes a substrate made of glass epoxy, ceramic, or the like. The substrate 1 includes a plurality of electric elements (for example, ICs 2, passive elements 3 such as resistors and capacitors, and mechanical parts 4 such as connectors). 5) is bonded by solder 6. The electrodes 1a, 1b, 1c, 1d and the electrodes 2a, 3a, 4a, 5a are provided on the surface of the substrate 1 and the electric elements 2, 3, 4, 5 so that they face each other in a bonded state. Each is formed.

【0004】ところで、このような電気素子2,3,
4,5を基板1に半田付けするに際しては、電気素子
2,3,4,5と基板1との仮付けを行うため、種々の
方法が取られていた。
By the way, such electric elements 2, 3,
When soldering the substrates 4 and 5 to the substrate 1, various methods have been adopted in order to temporarily attach the electric elements 2, 3, 4, and 5 to the substrate 1.

【0005】その一つとしては、図2に示すように、基
板1の表面に接着剤7を予め塗布しておき、部品搭載装
置(以下、“マウンター”とする)によって電気素子
2,3,4,5を基板1の所定位置に搭載する方法があ
る。この方法によれば、基板1に搭載された電気素子
2,3,4,5は、接着剤7によって基板1に接着さ
れ、仮付けがなされる。
As one of them, as shown in FIG. 2, an adhesive 7 is applied to the surface of the substrate 1 in advance, and the electric elements 2, 3 are mounted by a component mounting apparatus (hereinafter referred to as "mounter"). There is a method of mounting the substrates 4 and 5 at predetermined positions on the substrate 1. According to this method, the electric elements 2, 3, 4, and 5 mounted on the substrate 1 are adhered to the substrate 1 by the adhesive 7 and are temporarily attached.

【0006】また、別の方法としては、図3に示すよう
に、半田6にクリーム状の半田ペーストを用い、上述し
たのと同様にマウンターによって電気素子2,3,4,
5を基板1の所定位置に搭載する方法がある。この方法
によれば、基板1に搭載された電気素子2,3,4,5
は、半田6の粘着性によって仮付けがなされる。
As another method, as shown in FIG. 3, a creamy solder paste is used for the solder 6, and the electric elements 2, 3, 4, and 4 are mounted by a mounter in the same manner as described above.
5 is mounted at a predetermined position on the substrate 1. According to this method, the electric elements 2, 3, 4, 5 mounted on the substrate 1
Is temporarily attached by the adhesiveness of the solder 6.

【0007】一方、ACFとしては、樹脂に導電粒子を
分散・混入させたものであって、前記2つの電気部品に
おける対向する電極相互の導電性を確保すると共に他の
電極(隣接される電極)との絶縁性を確保するようにし
たものが種々の分野で利用されており、このACFを用
いたマルチチップモジュール(MCM)は特公昭59−
2179号公報や特公昭61−27902号公報に開示
されている。
On the other hand, the ACF is a resin in which conductive particles are dispersed and mixed in a resin. The ACF secures the conductivity between the electrodes facing each other in the two electric components, and the other electrodes (adjacent electrodes). A multi-chip module (MCM) using the ACF has been used in various fields.
No. 2179 and Japanese Patent Publication No. 61-27902.

【0008】また、液晶ディスプレイのドライバーIC
の実装に際してACFを用いたCOG方式を採用する方
向が検討されている。
Also, a driver IC for a liquid crystal display
When mounting the device, a direction to adopt a COG method using an ACF is being studied.

【0009】[0009]

【発明が解決しようとする課題】しかしながら、接着部
材として半田を用いた場合には、 半田にはPbが含有されていることから、環境に対
する悪影響を除去するために残滓や廃棄物に適正な処理
を行う必要があり、該処理に多くの費用がかかって製品
コストが上昇してしまうという問題があった。 また、接着箇所の表面を活性化させるためにフラッ
クスを用いる必要があると共に、半田の微粒子(半田ボ
ール)が発生するおそれがあるが、これらのフラックス
並びに半田ボールの除去のために洗浄工程が必要とな
り、製造工程が複雑となって製造コストが上昇してしま
うという問題があった。 さらに、接着箇所を湿気や塵埃から保護するために
エポキシやシリコン等の樹脂で被覆する必要があるが、
上記と同様に製造工程が複雑となって製造コストが上
昇してしまうという問題があった。 電極のピッチが0.3mm以下のものでは、隣接配置
される半田どうしが接着してしまい、隣接される電極相
互間の絶縁性が確保できないという問題があった。 その他、種々の理由で半田付け工程において不良品
が発生し易く、製造歩留りが低下するという問題があっ
た。
However, when solder is used as an adhesive member, since the solder contains Pb, proper treatment of residues and wastes is required to remove adverse effects on the environment. It is necessary to carry out the process, and there is a problem that the cost is increased and the product cost is increased. In addition, it is necessary to use a flux to activate the surface of the bonding portion, and there is a possibility that fine particles of solder (solder balls) may be generated. However, a cleaning step is required to remove the flux and the solder balls. Therefore, there is a problem that the manufacturing process becomes complicated and the manufacturing cost increases. In addition, it is necessary to cover the bonding point with a resin such as epoxy or silicone to protect it from moisture and dust.
As described above, there is a problem that the manufacturing process becomes complicated and the manufacturing cost increases. When the pitch of the electrodes is 0.3 mm or less, there is a problem that the solders arranged adjacently adhere to each other, so that the insulation property between the adjacent electrodes cannot be secured. In addition, there is a problem that a defective product is easily generated in the soldering process for various reasons, and the production yield is reduced.

【0010】一方、上述したACFを用いる場合には、
従来のACF自体は室温では粘着性を有していなかった
ため、電気素子2,3,4,5の基板1への搭載(仮付
け)は、マウンターで電気素子2,3,4,5を基板1
の所定位置に保持した状態で加圧と加熱とを行ってAC
Fの粘着性を高めるようにしていた。このため、 加圧と加熱とを行え、しかも接着部に加えなければ
ならない加圧力(一般に1〜5kgf/cm2 程度)や温度
(一般に80±10℃程度)の下においても精度を高く
維持できるような特殊で高価なマウンターが必要とな
り、製造コストが上昇してしまうという問題があった。 基板1に接着するACFが複数個であって、それら
の仮付けを加熱によって行う場合には、ACFの位置決
め・加熱は1つずつ個別に行う必要がある。かかる場
合、1回の加熱には1〜5秒程度の時間を要するため、
仮付けのための時間がかなり長くなって生産性が悪くな
るという問題があった。
On the other hand, when the above-mentioned ACF is used,
Since the conventional ACF itself did not have adhesiveness at room temperature, the electric elements 2, 3, 4, and 5 were mounted on the substrate 1 (temporarily attached) by mounting the electric elements 2, 3, 4, and 5 on the substrate. 1
Pressurizing and heating while holding the
F was designed to increase the adhesiveness. For this reason, pressurization and heating can be performed, and high accuracy can be maintained even under the pressure (generally about 1 to 5 kgf / cm 2 ) and temperature (generally about 80 ± 10 ° C.) which must be applied to the bonded portion. Such a special and expensive mounter is required, and there is a problem that the manufacturing cost is increased. When there are a plurality of ACFs to be bonded to the substrate 1 and the temporary attachment is performed by heating, it is necessary to individually position and heat the ACFs one by one. In such a case, since one heating takes about 1 to 5 seconds,
There is a problem that the time for tacking is considerably long and productivity is deteriorated.

【0011】そこで、本発明は、製品コストの上昇を抑
えることができる接着部材を提供することを目的とする
ものである。
Accordingly, an object of the present invention is to provide an adhesive member that can suppress an increase in product cost.

【0012】また、本発明は、電極のピッチが狭い電気
素子であっても接着が可能な接着部材を提供することを
目的とするものである。
Another object of the present invention is to provide an adhesive member capable of adhering even an electric element having a narrow electrode pitch.

【0013】さらに、本発明は、製造歩留りの低減を防
止する接着部材を提供することを目的とするものであ
る。
Another object of the present invention is to provide an adhesive member that prevents a reduction in production yield.

【0014】またさらに、本発明は、電気素子の接着性
及び異方導電性の両方を確保できる接着部材を提供する
ことを目的とするものである。
Still another object of the present invention is to provide an adhesive member which can secure both the adhesiveness and anisotropic conductivity of an electric element.

【0015】また、本発明は、ドライバーICやドライ
バーIC以外の電気素子が混在・搭載された液晶ディス
プレイを作成することができる接着部材を提供すること
を目的とするものである。
Another object of the present invention is to provide an adhesive member capable of producing a liquid crystal display in which a driver IC and electric elements other than the driver IC are mixed and mounted.

【0016】さらに、本発明は、上述した種々の目的を
達成するマルチチップモジュールを提供することを目的
とするものである。
Further, another object of the present invention is to provide a multi-chip module that achieves the various objects described above.

【0017】またさらに、本発明は、上述した種々の目
的を達成する接着方法を提供することを目的とするもの
である。
Still another object of the present invention is to provide a bonding method that achieves the various objects described above.

【0018】[0018]

【課題を解決するための手段】本発明は上記事情を考慮
してなされたものであり、2つの電気部品における対向
する電極相互の導電性を確保した状態で、これら2つの
電気部品を接着する接着部材において、室温にて粘着性
を有する接着層と、樹脂に導電粒子を分散・混入して形
成された異方性導電層と、を備え、前記接着層が前記2
つの電気部品の接着を行い、かつ、前記異方性導電層
が、前記2つの電気部品における対向する電極相互の導
電性を確保すると共に他の電極との絶縁性を確保する、
ことを特徴とする。
SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and adheres two electric components to each other in a state where the opposing electrodes of the two electric components are kept electrically conductive. The adhesive member comprises: an adhesive layer having tackiness at room temperature; and an anisotropic conductive layer formed by dispersing and mixing conductive particles in a resin.
Bonding the two electrical components, and the anisotropic conductive layer secures the conductivity between the opposing electrodes in the two electrical components and ensures the insulation with the other electrodes,
It is characterized by the following.

【0019】また、本発明は、複数の電極を有する基板
と、電極を有する複数の電気素子と、これらの基板及び
電気素子における対向する電極相互の導電性を確保した
状態でこれらの基板及び電気素子を接着する接着部材
と、を備えたマルチチップモジュールにおいて、前記接
着部材は、前記電気素子側に配置されると共に室温にて
粘着性を有する接着層と、前記基板側に配置されると共
に樹脂に導電粒子を分散・混入して形成された異方性導
電層と、を備え、前記接着層が前記基板及び電気素子の
接着を行い、かつ、前記異方性導電層が、前記基板及び
電気素子における対向する電極相互の導電性を確保する
と共に他の電極との絶縁性を確保する、ことを特徴とす
る。
Further, the present invention provides a substrate having a plurality of electrodes, a plurality of electric elements having the electrodes, and these substrates and the electric elements with the electrical conductivity between the substrates and the opposing electrodes in the electric elements being ensured. A multi-chip module including an adhesive member for adhering an element, wherein the adhesive member is disposed on the electric element side and has an adhesive layer having tackiness at room temperature; And an anisotropic conductive layer formed by dispersing and mixing conductive particles into the substrate, wherein the adhesive layer bonds the substrate and the electric element, and the anisotropic conductive layer forms the substrate and the electric element. It is characterized in that the conductivity of the opposing electrodes of the element is ensured and the insulation of the other electrodes is ensured.

【0020】さらに、本発明は、基板及び電気素子にお
ける対向する電極相互の導電性を確保した状態で、これ
らの基板及び電気素子を接着する接着方法において、前
記基板及び電気素子における対向する電極相互の導電性
を確保すると共に他の電極との絶縁性を確保する異方性
導電層を、前記基板側の電極を覆うように配置する工程
と、室温にて粘着性を有する接着層を、前記異方性導電
層又は前記電気素子側の電極に配置する工程と、前記基
板側の電極と前記電気素子側の電極とが対向するように
これらの基板と電気素子とを重ね合わせる工程と、該重
ね合わせた後に前記基板と前記電気素子との接着箇所を
加圧し加熱する工程と、を備えたことを特徴とする。
Further, the present invention relates to a bonding method for bonding a substrate and an electric element in a state where the opposing electrodes of the substrate and the electric element are secured with each other. A step of disposing an anisotropic conductive layer that secures the conductivity of the other electrode while ensuring the conductivity of the electrode on the substrate side, and an adhesive layer having tackiness at room temperature, Disposing the anisotropic conductive layer or the electrode on the electric element side, and laminating these substrates and the electric element such that the electrode on the substrate side and the electrode on the electric element side face each other; Pressurizing and heating a bonding portion between the substrate and the electric element after the overlapping.

【0021】[0021]

【発明の実施の形態】以下、図4乃至図7を参照して、
本発明の実施の形態について説明する。なお、図1に示
すものと同一部分は同一符号を付して説明を省略する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to FIGS.
An embodiment of the present invention will be described. Note that the same parts as those shown in FIG.

【0022】本実施の形態に係る接着部材10は、図4
中に示すように、室温にて粘着性を有する接着層11
と、樹脂12aに導電粒子12bを分散・混入して形成
された異方性導電層12と、を備えており、前記接着層
11が前記2つの電気部品の接着を行い、前記異方性導
電層12が、前記2つの電気部品における対向する電極
相互の導電性を確保すると共に他の電極との絶縁性(す
なわち、異方導電性)を確保するようになっている。
The bonding member 10 according to the present embodiment is similar to that of FIG.
As shown in the figure, an adhesive layer 11 having tackiness at room temperature
And an anisotropic conductive layer 12 formed by dispersing and mixing conductive particles 12b in a resin 12a. The adhesive layer 11 bonds the two electric components to each other, and The layer 12 ensures conductivity between the electrodes facing each other in the two electric components and also ensures insulation from other electrodes (that is, anisotropic conductivity).

【0023】本発明において、粘着性を有する接着層1
1とは、硬化前に常温で流動するポリマー剤層からな
る。本発明では、この接着層11の材料としては、例え
ば、 * SBR、 * 天然ゴム、 * ポリアクリル酸ブチル、 * いわゆる感圧接着剤(すなわち、シリコン樹脂や合
成ゴムに粘着性付与剤を混合し、必要に応じて、可塑剤
や老化防止剤等を混合したもの) を用いることができる。
In the present invention, the adhesive layer 1 having tackiness is used.
1 consists of a polymer agent layer which flows at room temperature before curing. In the present invention, as a material of the adhesive layer 11, for example, * SBR, * natural rubber, * polybutyl acrylate, * a so-called pressure-sensitive adhesive (that is, a tackifier is mixed with a silicone resin or a synthetic rubber, And, if necessary, a mixture of a plasticizer and an antioxidant).

【0024】次に、上記接着部材を用いて形成したマル
チチップモジュール(以下、“MCM”とする)につい
て、同図を参照して説明する。
Next, a multi-chip module (hereinafter, referred to as “MCM”) formed using the above-mentioned adhesive member will be described with reference to FIG.

【0025】このMCM13は、複数の電極1a,1
b,1c,1dを有する基板1と、電極2a,3a,4
a,5aを有する複数の電気素子2,3,4,5と、こ
れらの基板1及び電気素子2,3,4,5における対向
する電極相互(1aと4a,1bと2a,1cと3a,
1dと5a)の導電性を確保した状態でこれらの基板1
及び電気素子2,3,4,5を接着する接着部材10
と、を備えている。なお、これらの基板1、電気素子
2,3,4,5及び接着部材10は、便宜上離れた状態
に図示している。また、基板側の電極1a,1b,1
c,1dは、電気素子2,3,4,5が接着された状態
で電気素子側の電極2a,3a,4a,5aに対向する
位置に形成されている。
The MCM 13 has a plurality of electrodes 1a, 1
b, 1c, 1d and electrodes 2a, 3a, 4
a, 5a and a plurality of electric elements 2, 3, 4, 5 facing each other (1a and 4a, 1b and 2a, 1c and 3a,
These substrates 1 are kept in a state where the conductivity of 1d and 5a) is secured.
And bonding member 10 for bonding electric elements 2, 3, 4, and 5
And The substrate 1, the electric elements 2, 3, 4, 5 and the adhesive member 10 are shown separated for convenience. Also, the electrodes 1a, 1b, 1 on the substrate side
c, 1d are formed at positions facing the electrodes 2a, 3a, 4a, 5a on the electric element side in a state where the electric elements 2, 3, 4, 5 are bonded.

【0026】また、このMCM13においては、前記接
着層11は前記電気素子2,3,4,5の側に配置され
て前記基板1及び電気素子2,3,4,5の接着を行
い、前記異方性導電層12は前記基板1の側に配置され
て前記基板1及び電気素子2,3,4,5における対向
する電極相互(1aと4a,1bと2a,1cと3a,
1dと5a)の導電性を確保すると共に他の電極との絶
縁性を確保するようになっている。
In the MCM 13, the adhesive layer 11 is disposed on the side of the electric elements 2, 3, 4, 5 to bond the substrate 1 and the electric elements 2, 3, 4, 5. The anisotropic conductive layer 12 is disposed on the side of the substrate 1 and opposing electrodes (1a and 4a, 1b and 2a, 1c and 3a,
1d and 5a) are ensured, and the insulation with other electrodes is ensured.

【0027】ここで、前記複数の電気素子の電極2a,
3a,4a,5aの厚さが互いに異なる場合には、これ
らの電気素子2,3,4,5の各接着箇所における接着
層11の厚さを、該接着箇所に接着される各電気素子の
電極の厚さ以上の厚さにすると良い。この場合、前記接
着層11の厚さを、最大の電極厚さ以上の厚さとして基
板1の全面においてほぼ均一にしてもよい。これによ
り、接着層11は、いずれの箇所(基板1の全面)にお
いても電気素子の電極の厚さ以上の厚さとなる。
Here, the electrodes 2a, 2a,
When the thicknesses of the electric elements 3a, 4a, and 5a are different from each other, the thickness of the adhesive layer 11 at each of the adhesion points of the electric elements 2, 3, 4, and 5 is changed to the thickness of each electric element adhered to the adhesion point. The thickness is preferably equal to or greater than the thickness of the electrode. In this case, the thickness of the adhesive layer 11 may be substantially uniform over the entire surface of the substrate 1 as a thickness greater than the maximum electrode thickness. As a result, the adhesive layer 11 has a thickness equal to or greater than the thickness of the electrode of the electric element at any location (the entire surface of the substrate 1).

【0028】また、同様に前記複数の電気素子の電極2
a,3a,4a,5aの厚さが互いに異なる場合におい
て、電気素子2,3,4,5の各接着箇所における接着
層の厚さが該接着箇所に接着される各電気素子2,3,
4,5の電極2a,3a,4a,5aの厚さ以上の厚さ
であれば(すなわち、電気素子2の接着箇所における接
着層の厚さが電極2aの厚さ以上の厚さであり、電気素
子3の接着箇所における接着層の厚さが電極3aの厚さ
以上の厚さであり、電気素子4の接着箇所における接着
層の厚さが電極4aの厚さ以上の厚さであり、電気素子
5の接着箇所における接着層の厚さが電極5aの厚さ以
上の厚さであれば)、図5及び図6に符号20及び30
で示すように、接着層の厚さは基板1の全面において均
一でなくとも良い。そして、電気素子4の電極4aや電
気素子5の電極5aが、他の電気素子2,3の電極2
a,3aよりも厚い場合には、電気素子4,5が接着さ
れる箇所の接着層を、電極4a,5aの厚さに応じて電
気素子2,3が接着される箇所よりも厚くしても良い。
Similarly, the electrodes 2 of the plurality of electric elements are
When the thicknesses of a, 3a, 4a, and 5a are different from each other, the thickness of the adhesive layer at each of the bonding points of the electric elements 2, 3, 4, and 5 is such that the electric elements 2, 3, and 3 are bonded to the bonding points.
If the thickness of the electrodes 2a, 3a, 4a, and 5a is equal to or greater than the thickness of the electrodes 4a and 5a (that is, the thickness of the bonding layer at the bonding portion of the electric element 2 is equal to or greater than the thickness of the electrode 2a, The thickness of the adhesive layer at the position where the electric element 3 is bonded is not less than the thickness of the electrode 3a, the thickness of the adhesive layer at the position where the electric element 4 is bonded is not less than the thickness of the electrode 4a, (If the thickness of the adhesive layer at the position where the electric element 5 is bonded is equal to or greater than the thickness of the electrode 5a), reference numerals 20 and 30 in FIGS.
As shown by, the thickness of the adhesive layer may not be uniform over the entire surface of the substrate 1. The electrode 4a of the electric element 4 and the electrode 5a of the electric element 5 are
When the thickness is larger than the thicknesses a and 3a, the thickness of the adhesive layer where the electric elements 4 and 5 are adhered is made thicker than the location where the electric elements 2 and 3 are adhered according to the thickness of the electrodes 4a and 5a. Is also good.

【0029】なお、電気素子としては、ICチップ等の
半導体素子、抵抗やコンデンサー等の受動素子、及びコ
ネクター等の機構部品を挙げることができる。
Examples of the electric element include a semiconductor element such as an IC chip, a passive element such as a resistor and a capacitor, and a mechanical component such as a connector.

【0030】また、電気素子2,3,4,5を接着する
基板としては、図7に示すような液晶ディスプレイパネ
ル50(正確には、液晶ディスプレイパネル50の構成
部品としてのガラス基板51)を挙げることができる。
As a substrate to which the electric elements 2, 3, 4, 5 are adhered, a liquid crystal display panel 50 (more precisely, a glass substrate 51 as a component of the liquid crystal display panel 50) as shown in FIG. 7 is used. Can be mentioned.

【0031】さらに、接着層11及び異方性導電層12
は、これらが電気素子2,3,4,5や基板1の側に配
置されていれば、2層に積層されていても(図4参
照)、積層されていなくても(すなわち、接着層11と
異方性導電層12との間に別の層が介装されていても)
良い。
Further, the adhesive layer 11 and the anisotropic conductive layer 12
If these are arranged on the side of the electric elements 2, 3, 4, 5 and the substrate 1, they may be laminated in two layers (see FIG. 4) or not (in other words, the adhesive layer 11 even if another layer is interposed between anisotropic conductive layer 12)
good.

【0032】次に、電気素子2,3,4,5を基板1に
接着する接着方法について説明する。
Next, a method of bonding the electric elements 2, 3, 4, and 5 to the substrate 1 will be described.

【0033】まず、前記基板側の電極1a,1b,1
c,1dを覆うように前記異方性導電層12を配置し、
該異方性導電層12又は前記電気素子側の電極2a,3
a,4a,5aを覆うように前記接着層11を配置す
る。
First, the electrodes 1a, 1b, 1
disposing the anisotropic conductive layer 12 so as to cover c and 1d;
The anisotropic conductive layer 12 or the electrodes 2a, 3 on the electric element side
The adhesive layer 11 is arranged so as to cover a, 4a and 5a.

【0034】次に、前記基板側の電極1a,1b,1
c,1dと前記電気素子側の電極2a,3a,4a,5
aとが対向するように、これらの基板1と電気素子2,
3,4,5とを重ね合わせる。これにより、基板1と電
気素子2,3,4,5との仮付けが行われる。
Next, the electrodes 1a, 1b, 1
c, 1d and the electrodes 2a, 3a, 4a, 5 on the electric element side
a, these substrates 1 and the electric elements 2,
Overlay 3, 4, and 5. Thereby, the substrate 1 and the electric elements 2, 3, 4, and 5 are temporarily attached.

【0035】さらに、該重ね合わせた後に、前記基板1
と前記電気素子2,3,4,5との接着箇所を加圧し加
熱する。
Further, after the overlapping, the substrate 1
And the electric elements 2, 3, 4, 5 are pressed and heated.

【0036】次に、本実施の形態の効果について説明す
る。
Next, effects of the present embodiment will be described.

【0037】本実施の形態によれば、接着層11は室温
にて粘着性を有しているため、電気素子2,3,4,5
の基板1への搭載(仮付け)の際には加圧しさえすれば
良く、加熱は不要となる。したがって、加熱が可能な特
殊なマウンターを使用しなくても(すなわち、半田付け
のマウンターのように加熱機能を有しない安価な装置で
あっても)仮付けが可能となり、製造コストの上昇を抑
えることができる。また、接着部材10が所定の温度
(上述したように80±10℃程度の温度)に加熱され
るまで電気素子2,3,4,5を保持しておく必要がな
いため、仮付けのための時間が、半田付けの場合と同じ
程度(0.1〜0.3秒程度)に短縮できる。さらに、
加熱に伴う仮付け位置精度の悪化を回避できる。
According to the present embodiment, since the adhesive layer 11 has tackiness at room temperature, the electric elements 2, 3, 4, 5
At the time of mounting (temporary attachment) on the substrate 1, it is only necessary to apply pressure, and heating is unnecessary. Therefore, even if a special mounter capable of heating is not used (that is, even if the device is inexpensive and does not have a heating function like a soldering mounter), temporary mounting is possible, and an increase in manufacturing cost is suppressed. be able to. Further, since it is not necessary to hold the electric elements 2, 3, 4, and 5 until the adhesive member 10 is heated to a predetermined temperature (about 80 ± 10 ° C. as described above), Can be reduced to the same level (about 0.1 to 0.3 seconds) as in the case of soldering. further,
It is possible to avoid deterioration of the tacking position accuracy due to heating.

【0038】さらに、仮付け時において加熱の必要がな
いことから、仮付け時間を短縮でき、生産性が向上され
る。
Further, since there is no need for heating at the time of temporary attachment, the time for temporary attachment can be shortened, and the productivity is improved.

【0039】一方、本実施例においては接着部材として
半田を用いていないため、半田固有の問題点を回避でき
る。すなわち、 Pbが含有されていることに伴う残滓や廃棄物の処
理が不要となり、該処理のための費用を節約して製品コ
ストの上昇を抑えることができる。 また、フラックスの使用や半田ボールの発生が無い
ため、これらを洗浄する工程が不要となり、製造コスト
の上昇を抑えることができる。 さらに、基板1のほぼ全面が接着層11や異方性導
電層12によって被覆されていることから湿気や塵埃か
ら保護されるため、別途樹脂を被覆する必要が無く、製
造コストの上昇を抑えることができる。 電極のピッチが0.3mm以下のものでも隣接される
電極相互間の絶縁性を確保できる。 不良品が発生しにくくなり、製造歩留りが向上され
る。
On the other hand, in this embodiment, since solder is not used as the adhesive member, problems inherent in solder can be avoided. That is, there is no need to treat residues and wastes due to the inclusion of Pb, so that costs for the treatment can be saved and an increase in product cost can be suppressed. Further, since there is no use of flux or generation of solder balls, a step of cleaning these is not required, and an increase in manufacturing cost can be suppressed. Further, since almost the entire surface of the substrate 1 is covered with the adhesive layer 11 and the anisotropic conductive layer 12, the substrate 1 is protected from moisture and dust. Can be. Even if the pitch of the electrodes is 0.3 mm or less, insulation between adjacent electrodes can be ensured. Defective products are less likely to occur, and the production yield is improved.

【0040】また一方、本実施の形態における接着部材
10は、2つの電気部品の接着を行う接着層11と、樹
脂12aに導電粒子12bを分散・混入して形成された
異方性導電層12と、が積層されて構成されたものであ
り、該異方性導電層12が、前記2つの電気部品におけ
る対向する電極相互の導電性を確保すると共に他の電極
との絶縁性を確保するようになっている。したがって、
電極2a,3a,4a,5aの厚さが互いに異なる複数
の電気素子2,3,4,5を接着する場合であっても、
導電粒子12bの粒子径を任意に選択すること等により
電気素子の接着性及び異方導電性(すなわち、対向する
電極相互の導電性並びに他の電極との間の絶縁性)の両
方を確保できる。なお、樹脂特性の選択は、電気素子の
材質や電極厚さによって決められる。
On the other hand, the adhesive member 10 according to the present embodiment includes an adhesive layer 11 for bonding two electric components, and an anisotropic conductive layer 12 formed by dispersing and mixing conductive particles 12b in a resin 12a. And an anisotropic conductive layer 12 is provided so that the anisotropic conductive layer 12 secures the conductivity between the electrodes facing each other in the two electrical components and also secures the insulation from the other electrodes. It has become. Therefore,
Even when a plurality of electric elements 2, 3, 4, 5 having different thicknesses from the electrodes 2a, 3a, 4a, 5a are bonded,
By arbitrarily selecting the particle size of the conductive particles 12b, it is possible to secure both the adhesiveness and the anisotropic conductivity of the electric element (that is, the conductivity between the opposing electrodes and the insulation between other electrodes). . The selection of the resin characteristics is determined by the material of the electric element and the electrode thickness.

【0041】したがって、液晶ディスプレイにおいて
は、ドライバーICと、ドライバーIC以外の電気素子
(例えば、コントローラIC等の半導体素子や、抵抗や
コンデンサー等の受動素子や、コネクター等の機構部
品)を混載実装でき、これらの電気素子が混在・搭載さ
れた液晶ディスプレイ(いわゆるシステム・オン・パネ
ル)を作成することができる。つまり、本実施の形態に
よれば、低価格で信頼性の高いMCMやシステム・オン
・パネルを得ることができる。
Therefore, in a liquid crystal display, a driver IC and an electric element other than the driver IC (for example, a semiconductor element such as a controller IC, a passive element such as a resistor and a capacitor, and a mechanical component such as a connector) can be mounted together. In addition, a liquid crystal display (a so-called system-on-panel) in which these electric elements are mixed and mounted can be produced. That is, according to the present embodiment, it is possible to obtain a low-cost and highly reliable MCM or system-on-panel.

【0042】一方、前記複数の電気素子の電極2a,3
a,4a,5aの厚さが互いに異なる場合であって、前
記接着層11の厚さを、最大の電極厚さ以上の厚さとし
基板1の全面においてほぼ均一にした場合には、電気素
子の接着性を良好に維持したまま製品コストを低減でき
る。
On the other hand, the electrodes 2a, 3 of the plurality of electric elements
In the case where the thicknesses of a, 4a, and 5a are different from each other, and the thickness of the adhesive layer 11 is equal to or more than the maximum electrode thickness and is made substantially uniform over the entire surface of the substrate 1, the electric element The product cost can be reduced while maintaining good adhesion.

【0043】[0043]

【実施例】(実施例1)本実施例においては、図7に示
すように、ドライバーICやコントローラIC等の電気
素子2,3,4,5を、液晶ディスプレイパネル50を
構成するガラス基板51の表面に接着した。
(Embodiment 1) In this embodiment, as shown in FIG. 7, electric elements 2, 3, 4, 5 such as a driver IC and a controller IC are connected to a glass substrate 51 constituting a liquid crystal display panel 50. Adhered to the surface.

【0044】本実施例によれば、種々の電気的機能をパ
ネル上に実現することが可能となり、小型・薄型で多機
能な液晶ディスプレイを安価に提供できる。その他、上
記実施の形態と同様の効果が得られた。 (実施例2)本実施例においては、図5(a) に示すAC
F(接着部材)を用いて、図4に示したように、電極厚
さの異なる複数の電気素子2,3,4,5を基板1に接
着した。
According to this embodiment, various electrical functions can be realized on the panel, and a small, thin, multifunctional liquid crystal display can be provided at low cost. In addition, the same effects as in the above embodiment were obtained. (Embodiment 2) In this embodiment, the AC shown in FIG.
As shown in FIG. 4, a plurality of electric elements 2, 3, 4, and 5 having different electrode thicknesses were bonded to the substrate 1 using F (adhesive member).

【0045】なお、このACFにおける接着層20は、
図5(a) に示すように、電気素子2,3,4,5の各接
着箇所における接着層の厚さが該接着箇所に接着される
各電気素子2,3,4,5の電極2a,3a,4a,5
aの厚さ以上の厚さとなるように、電極厚さが厚い電気
素子4,5を配置する箇所(符号20a及び20c参
照)を電極厚さが薄い電気素子2,3を配置する箇所
(符号20b参照)よりも厚くしている。また、接着層
20及び異方性導電層12は基板1の全面に形成してい
る。
The adhesive layer 20 in this ACF is
As shown in FIG. 5 (a), the thickness of the adhesive layer at each of the bonding points of the electric elements 2, 3, 4, and 5 is such that the electrode 2a of each of the electric elements 2, 3, 4, and 5 is bonded to the bonding point. , 3a, 4a, 5
The places where the electric elements 4 and 5 having a large electrode thickness are arranged (see reference numerals 20a and 20c) are arranged so that the electric elements 2 and 3 having a small electrode thickness are arranged so that the thickness becomes larger than the thickness of a. 20b). The adhesive layer 20 and the anisotropic conductive layer 12 are formed on the entire surface of the substrate 1.

【0046】なお、本実施例のような構成は、接着層を
厚くする領域20a,20cにおいては該接着層を2層
構成とし、それ以外の領域20bにおいては接着層を単
層構成とすることにより達成できる。
In the structure of this embodiment, the adhesive layer has a two-layer structure in the regions 20a and 20c where the adhesive layer is thickened, and the adhesive layer has a single-layer structure in the other regions 20b. Can be achieved by

【0047】また、このような構成は、接着層20と異
方性導電層12とを長尺のリール・トー・リールで形成
して貼り合わせることで達成できる。
Such a configuration can be achieved by forming the adhesive layer 20 and the anisotropic conductive layer 12 with a long reel-to-reel and bonding them together.

【0048】図5(b) は、本実施例にて使用したACF
の平面図であるが、接着層20を厚くする領域20a,
20cは図示のものに特に限定されるものでは無い。上
述以外の構成は上記実施例1と同様である。
FIG. 5B shows the ACF used in this embodiment.
Is a plan view, but regions 20a,
20c is not particularly limited to the illustrated one. The configuration other than the above is the same as that of the first embodiment.

【0049】ここで、接着層20の厚さt3は、下式の
関係を用いて決定した。
Here, the thickness t3 of the adhesive layer 20 was determined using the following equation.

【0050】[0050]

【式1】t21 + t3 ≒ t1 + t7 +α 但し、t21;異方性導電層12の厚さ t1 ;基板側電極1a,1b,1c,1dの厚さ t7 ;電気素子側電極2a,3a,4a,5aの厚さ なお、αの値は、接着層20の流れ出し量や電気素子へ
の封止効果等を勘案して決めるが、0〜10μm、理想
的には約5μmに設定するのが良い。
[Formula 1] t21 + t3 + t1 + t7 + α, where t21; thickness t1 of the anisotropic conductive layer 12; thickness t7 of the substrate-side electrodes 1a, 1b, 1c, 1d; and electric element-side electrodes 2a, 3a, The thickness of 4a and 5a is determined in consideration of the amount of the adhesive layer 20 flowing out and the effect of sealing the electric element, and is preferably set to 0 to 10 μm, and ideally to about 5 μm. good.

【0051】また、基板側電極の厚さt1は、液晶ディ
スプレイパネル用のガラス基板51のITO(インジウ
ム ティン オキサイド)電極の場合には0.1μm以
下なので、無視できる。
The thickness t1 of the substrate-side electrode is 0.1 μm or less in the case of an ITO (indium tin oxide) electrode of the glass substrate 51 for a liquid crystal display panel, and can be ignored.

【0052】さらに、電気素子の電極厚さt7は、電気
素子の種類によって異なるが、一般に、半導体素子のバ
ンプ電極の場合は15μm程度であり、抵抗やコンデン
サー等の受動素子の場合は25μm程度であり、機構部
品等のリードフレーム電極の場合は150μm程度であ
る。
Further, the electrode thickness t7 of the electric element varies depending on the type of the electric element, but is generally about 15 μm for a bump electrode of a semiconductor element and about 25 μm for a passive element such as a resistor or a capacitor. In the case of a lead frame electrode such as a mechanical component, the thickness is about 150 μm.

【0053】またさらに、異方性導電層12の厚さt2
1は8μmとした。
Further, the thickness t2 of the anisotropic conductive layer 12
1 was 8 μm.

【0054】つまり、本実施例においては、接着層20
の厚さt3を、半導体素子を配置する部分は12μmと
し、受動素子を配置する部分は22μmとし、機構部品
を配置する部分は147μmとした。
That is, in this embodiment, the adhesive layer 20
The thickness t3 of the semiconductor element was set to 12 μm, that of the passive element was set to 22 μm, and that of the mechanical component was set to 147 μm.

【0055】本実施例によれば、電気素子の電極厚さが
極端に異なる場合でも上記実施の形態と同様の効果を得
ることができる。
According to this embodiment, the same effect as in the above embodiment can be obtained even when the electrode thickness of the electric element is extremely different.

【0056】また、信頼性の高いMCMやシステム・オ
ン・パネルを、従来公知のACFを用いた場合と同じプ
ロセスで作成することができる。したがって、製造装置
や工程条件を従来のものから大幅に変更する必要なく、
生産上の効果は絶大となる。 (実施例3)本実施例においては、図6に示すように、
異方性導電層12を基板1の全面に形成し、電極厚さの
薄い電気素子2,3が接着される領域30bにおいては
接着層30を単層構成とし、電極厚さの厚い電気素子
4,5が接着される領域30a,30bにおいては接着
層30を2層構成とし、それ以外の領域においては接着
層を形成しなかった。それ以外の構成は実施例2と同様
である。
Further, a highly reliable MCM or system-on-panel can be created by the same process as that using a conventionally known ACF. Therefore, there is no need to significantly change the manufacturing equipment and process conditions from the conventional one,
The effect on production will be enormous. (Embodiment 3) In this embodiment, as shown in FIG.
An anisotropic conductive layer 12 is formed on the entire surface of the substrate 1. In a region 30b where the electric elements 2 and 3 having a small electrode thickness are adhered, the adhesive layer 30 has a single-layer structure, and the electric element 4 having a large electrode thickness is formed. , 5 are bonded to each other in the regions 30a and 30b, and the bonding layers are not formed in the other regions. Other configurations are the same as those of the second embodiment.

【0057】本実施例によれば、接着層30を形成する
領域を小さくしたため、使用する材料の消費量を低減す
ることができ、製品コストも低減できた。
According to the present embodiment, since the area where the adhesive layer 30 is formed is reduced, the consumption of materials used can be reduced, and the product cost can be reduced.

【0058】また、領域30a,30bにおける中間層
(接着層30と異方性導電層12との間の層)は電気素
子4,5に直接接触するものでは無いため、これら電気
素子4,5との接着性を考慮する必要がなく、生産上の
都合で材料を選択することができる。 (実施例4)本実施例は、上述した基板1と電気素子
2,3,4,5との接着方法に関するものである。
Since the intermediate layer (layer between the adhesive layer 30 and the anisotropic conductive layer 12) in the regions 30a and 30b does not directly contact the electric elements 4 and 5, It is not necessary to consider the adhesiveness with the material, and the material can be selected for convenience in production. (Embodiment 4) This embodiment relates to a method for bonding the above-described substrate 1 and the electric elements 2, 3, 4, and 5.

【0059】本実施例においては、図8に示すように、
電気素子2,3,4,5には、室温にて粘着性を有する
接着層を符号40a,40b,40cで示すように塗布
し、基板1の側には異方性導電層12を塗布した。
In this embodiment, as shown in FIG.
Adhesive layers having tackiness at room temperature were applied to the electric elements 2, 3, 4, and 5 as indicated by reference numerals 40a, 40b, and 40c, and an anisotropic conductive layer 12 was applied to the substrate 1 side. .

【0060】次に、基板側の電極1a,1b,1c,1
dと電気素子側の電極2a,3a,4a,5aとが対向
するように、基板1と電気素子2,3,4,5とを重ね
合わせて加圧した。接着層40a,40b,40cは室
温にて粘着性を有するため、基板1と電気素子2,3,
4,5との仮付けが完了した。
Next, the electrodes 1a, 1b, 1c, 1
The substrate 1 and the electric elements 2, 3, 4, and 5 were overlapped and pressed so that d and the electrodes 2a, 3a, 4a, and 5a on the electric element side faced each other. Since the adhesive layers 40a, 40b, and 40c have tackiness at room temperature, the substrate 1 and the electric elements 2, 3,
Temporary attachment with 4,5 was completed.

【0061】その後、加熱・圧着(本付け)を行った。
これにより、電気素子2,3,4,5は、対向する電極
相互の導電性が確保された状態で基板1に接着された。
ここで、異方性導電層12には従来公知の異方性導電接
着剤を使用した。
Thereafter, heating and pressure bonding (final attachment) were performed.
As a result, the electric elements 2, 3, 4, and 5 were bonded to the substrate 1 in a state where the opposing electrodes were kept electrically conductive.
Here, a conventionally known anisotropic conductive adhesive was used for the anisotropic conductive layer 12.

【0062】なお、接着層は、電極厚さの薄い電気素子
2,3に対しては符号40bで示すように薄く塗布し、
電極厚さの厚い電気素子4,5には接着層を符号40
a,40cで示すように厚く塗布するようにしてもよ
い。
The adhesive layer is thinly applied to the electric elements 2 and 3 having a small electrode thickness as indicated by reference numeral 40b.
An adhesive layer 40 is applied to the electric elements 4 and 5 having a large electrode thickness.
A thick coating may be applied as shown by a and 40c.

【0063】[0063]

【発明の効果】以上説明したように、本発明によると、
接着層は室温にて粘着性を有しているため、2つの電気
部品の加圧を行うだけでそれらの仮付けが完了し、仮付
け時の加熱は不要となる。したがって、加熱が可能な特
殊なマウンターを使用しなくても(すなわち、半田付け
のマウンターのように加熱機能を有しない安価な装置で
あっても)仮付けが可能となり、製造コストの上昇を抑
えることができる。また、接着部材が所定の温度に加熱
されるまで電気部品を保持しておく必要がないため、仮
付けのための時間が、半田付けの場合と同じ程度(0.
1〜0.3秒程度)に短縮できる。さらに、加熱に伴う
仮付け位置精度の悪化を回避できる。
As described above, according to the present invention,
Since the adhesive layer has tackiness at room temperature, the temporary attachment of the two electric components is completed only by pressing, and heating during the temporary attachment is unnecessary. Therefore, even if a special mounter capable of heating is not used (that is, even if the device is inexpensive and does not have a heating function like a soldering mounter), temporary mounting is possible, and an increase in manufacturing cost is suppressed. be able to. Further, since it is not necessary to hold the electric component until the adhesive member is heated to a predetermined temperature, the time for temporary attachment is about the same as that for soldering (0.
(About 1 to 0.3 seconds). Further, it is possible to avoid deterioration of the tacking position accuracy due to heating.

【0064】一方、接着部材として半田を用いていない
ため、半田固有の問題点を回避できる。すなわち、 Pbが含有されていることに伴う残滓や廃棄物の処
理が不要となり、該処理のための費用を節約して製品コ
ストの上昇を抑えることができる。 また、フラックスの使用や半田ボールの発生が無い
ため、これらを洗浄する工程が不要となり、製造コスト
の上昇を抑えることができる。 さらに、基板のほぼ全面が接着層や異方性導電層に
よって被覆されていることから湿気や塵埃から保護され
るため、別途樹脂を被覆する必要が無く、製造コストの
上昇を抑えることができる。 電極のピッチが0.3mm以下のものでも隣接される
電極相互間の絶縁性を確保できる。 不良品が発生しにくくなり、製造歩留りが向上され
る。
On the other hand, since solder is not used as the adhesive member, problems inherent in solder can be avoided. That is, it is not necessary to treat residues and wastes due to the inclusion of Pb, so that the cost for the treatment can be saved and the increase in product cost can be suppressed. Further, since there is no use of flux or generation of solder balls, a step of cleaning these is not required, and an increase in manufacturing cost can be suppressed. Further, since almost the entire surface of the substrate is covered with the adhesive layer or the anisotropic conductive layer, the substrate is protected from moisture and dust, so that there is no need to separately coat a resin, and an increase in manufacturing cost can be suppressed. Even if the pitch of the electrodes is 0.3 mm or less, insulation between adjacent electrodes can be ensured. Defective products are less likely to occur, and the production yield is improved.

【0065】また、本発明に係る接着部材は、2つの電
気部品の接着を行う接着層と、樹脂に導電粒子を分散・
混入して形成された異方性導電層と、が積層されて構成
されたものであり、該異方性導電層が、前記2つの電気
部品における対向する電極相互の導電性を確保すると共
に他の電極との絶縁性を確保するようになっている。し
たがって、電極の厚さが互いに異なる複数の電気素子を
接着する場合であっても、導電粒子の粒子径等を任意に
選択することにより電気素子の接着性及び異方導電性
(すなわち、対向する電極相互の導電性並びに他の電極
との間の絶縁性)の両方を確保できる。
Further, the adhesive member according to the present invention comprises an adhesive layer for bonding two electric components, and a resin in which conductive particles are dispersed.
And an anisotropic conductive layer formed by mixing the two electrical components. Insulation with the electrodes is ensured. Therefore, even when a plurality of electric elements having different electrode thicknesses are bonded to each other, the adhesiveness and anisotropic conductivity of the electric elements (that is, the opposing electric properties) Both the mutual conductivity of the electrodes and the insulation between other electrodes) can be ensured.

【0066】したがって、液晶ディスプレイにおいて
は、ドライバーICと、ドライバーIC以外の電気素子
(例えば、コントローラIC等の半導体素子や、抵抗や
コンデンサー等の受動素子や、コネクター等の機構部
品)とを共に実装でき、これらの電気素子が混在・搭載
された液晶ディスプレイ(いわゆるシステム・オン・パ
ネル)を作成することができる。つまり、本実施の形態
によれば、低価格で信頼性の高いMCMやシステム・オ
ン・パネルを得ることができる。
Therefore, in the liquid crystal display, both the driver IC and electric elements other than the driver IC (for example, semiconductor elements such as a controller IC, passive elements such as resistors and capacitors, and mechanical parts such as connectors) are mounted together. Thus, a liquid crystal display (a so-called system-on-panel) in which these electric elements are mixed and mounted can be produced. That is, according to the present embodiment, it is possible to obtain a low-cost and highly reliable MCM or system-on-panel.

【0067】さらに、前記複数の電気素子の電極の厚さ
が互いに異なる場合であって、前記接着層の厚さを、前
記基板の全面においてほぼ均一にすると共に最大の電極
厚さ以上の厚さとした場合には、電気素子の接着性を良
好に維持したまま製品コストを低減できる。
Further, in the case where the thicknesses of the electrodes of the plurality of electric elements are different from each other, the thickness of the adhesive layer is made substantially uniform over the entire surface of the substrate, and the thickness of the adhesive layer is not less than the maximum electrode thickness. In this case, the product cost can be reduced while maintaining good adhesion of the electric element.

【図面の簡単な説明】[Brief description of the drawings]

【図1】2つの電気部品(基板及び電気素子)を半田に
よって接着した従来構造の一例を示した図。
FIG. 1 is a diagram showing an example of a conventional structure in which two electric components (a substrate and an electric element) are bonded by solder.

【図2】電気素子の仮付け方法の一例を示す図。FIG. 2 is a diagram showing an example of a method of temporarily attaching an electric element.

【図3】電気素子の仮付け方法の他の例を示す図。FIG. 3 is a diagram showing another example of a method of temporarily attaching an electric element.

【図4】本発明に係る接着部材の構造の一例、並びにM
CMの構造の一例を示す図。
FIG. 4 shows an example of the structure of an adhesive member according to the present invention, and M
The figure which shows an example of the structure of CM.

【図5】接着部材の構造の他の例を示す図であり、(a)
は側面図、(b) は平面図。
5A and 5B are diagrams showing another example of the structure of the adhesive member, and FIG.
Is a side view, and (b) is a plan view.

【図6】接着部材の構造のさらに他の例を示す図であ
り、(a) は側面図、(b) は平面図。
6A and 6B are diagrams showing still another example of the structure of the adhesive member, wherein FIG. 6A is a side view, and FIG. 6B is a plan view.

【図7】接着部材を液晶ディスプレイに適用した例を示
す図。
FIG. 7 is a diagram showing an example in which an adhesive member is applied to a liquid crystal display.

【図8】接着部材を用いた接着方法を説明するための
図。
FIG. 8 is a diagram for explaining a bonding method using a bonding member.

【符号の説明】[Explanation of symbols]

1 基板(電気部品) 2 IC(電気部品、電気素子) 2a 電極 3 受動素子(電気部品、電気素子) 3a 電極 4,5 機構部品(電気部品、電気素子) 4a,5a 電極 10 ACF(接着部材) 11 接着層 12 異方性導電層 12a 樹脂 12b 導電粒子 13 MCM(マルチチップモジュール) 50 液晶ディスプレイパネル 51 ガラス基板 DESCRIPTION OF SYMBOLS 1 Substrate (electric part) 2 IC (electric part, electric element) 2a electrode 3 Passive element (electric part, electric element) 3a electrode 4,5 Mechanical part (electric part, electric element) 4a, 5a Electrode 10 ACF (adhesive member) 11) adhesive layer 12 anisotropic conductive layer 12a resin 12b conductive particles 13 MCM (multi-chip module) 50 liquid crystal display panel 51 glass substrate

Claims (10)

【特許請求の範囲】[Claims] 【請求項1】 2つの電気部品における対向する電極相
互の導電性を確保した状態で、これら2つの電気部品を
接着する接着部材において、 室温にて粘着性を有する接着層と、樹脂に導電粒子を分
散・混入して形成された異方性導電層と、を備え、 前記接着層が前記2つの電気部品の接着を行い、かつ、 前記異方性導電層が、前記2つの電気部品における対向
する電極相互の導電性を確保すると共に他の電極との絶
縁性を確保する、 ことを特徴とする接着部材。
An adhesive member for adhering two electric components in a state where the opposing electrodes of the two electric components are secured to each other, comprising: an adhesive layer having tackiness at room temperature; And an anisotropic conductive layer formed by dispersing and mixing the two components. The adhesive layer bonds the two electrical components, and the anisotropic conductive layer faces the two electrical components. An adhesive member, which ensures the mutual conductivity of the electrodes and the insulation of the other electrodes.
【請求項2】 前記接着層が、硬化前に常温で流動する
ポリマー剤層からなる、 ことを特徴とする請求項1に記載の接着部材。
2. The adhesive member according to claim 1, wherein the adhesive layer comprises a polymer agent layer that flows at room temperature before curing.
【請求項3】 複数の電極を有する基板と、電極を有す
る複数の電気素子と、これらの基板及び電気素子におけ
る対向する電極相互の導電性を確保した状態でこれらの
基板及び電気素子を接着する接着部材と、を備えたマル
チチップモジュールにおいて、 前記接着部材は、前記電気素子側に配置されると共に室
温にて粘着性を有する接着層と、前記基板側に配置され
ると共に樹脂に導電粒子を分散・混入して形成された異
方性導電層と、を備え、 前記接着層が前記基板及び電気素子の接着を行い、か
つ、 前記異方性導電層が、前記基板及び電気素子における対
向する電極相互の導電性を確保すると共に他の電極との
絶縁性を確保する、 ことを特徴とするマルチチップモジュール。
3. A substrate having a plurality of electrodes, a plurality of electric elements having the electrodes, and the substrate and the electric element are adhered to each other in a state in which conductivity between the electrodes facing each other in the substrate and the electric element is ensured. In a multi-chip module comprising: an adhesive member, the adhesive member is disposed on the electrical element side and has an adhesive layer having tackiness at room temperature, and is disposed on the substrate side and has conductive particles in a resin. An anisotropic conductive layer formed by dispersion and mixing, wherein the adhesive layer bonds the substrate and the electric element, and the anisotropic conductive layer faces the substrate and the electric element. A multi-chip module comprising: securing conductivity between electrodes and securing insulation from other electrodes.
【請求項4】 前記接着層が、硬化前に常温で流動する
ポリマー剤層からなる、 ことを特徴とする請求項3に記載のマルチチップモジュ
ール。
4. The multi-chip module according to claim 3, wherein the adhesive layer comprises a polymer agent layer that flows at room temperature before curing.
【請求項5】 前記複数の電気素子の電極の厚さが互い
に異なる場合には、 前記電気素子の各接着箇所における接着層の厚さが該接
着箇所に接着される各電気素子の電極の厚さ以上の厚さ
とした、 ことを特徴とする請求項3又は4に記載のマルチチップ
モジュール。
5. When the thicknesses of the electrodes of the plurality of electric elements are different from each other, the thickness of the adhesive layer at each adhesion point of the electric element is the thickness of the electrode of each electric element adhered to the adhesion point. The multi-chip module according to claim 3, wherein the multi-chip module has a thickness greater than or equal to the thickness.
【請求項6】 前記接着層の厚さを、前記基板の全面に
おいてほぼ均一にすると共に、最大の電極厚さ以上の厚
さとした、 ことを特徴とする請求項5に記載のマルチチップモジュ
ール。
6. The multichip module according to claim 5, wherein the thickness of the adhesive layer is made substantially uniform over the entire surface of the substrate and is equal to or greater than the maximum electrode thickness.
【請求項7】 前記基板が液晶ディスプレイパネルであ
る、 ことを特徴とする請求項3乃至6のいずれか1項に記載
のマルチチップモジュール。
7. The multi-chip module according to claim 3, wherein said substrate is a liquid crystal display panel.
【請求項8】 前記基板が、液晶ディスプレイパネルの
構成部品としてのガラス基板である、 ことを特徴とする請求項7に記載のマルチチップモジュ
ール。
8. The multichip module according to claim 7, wherein the substrate is a glass substrate as a component of a liquid crystal display panel.
【請求項9】 基板及び電気素子における対向する電極
相互の導電性を確保した状態で、これらの基板及び電気
素子を接着する接着方法において、 前記基板及び電気素子における対向する電極相互の導電
性を確保すると共に他の電極との絶縁性を確保する異方
性導電層を、前記基板側の電極を覆うように配置する工
程と、 室温にて粘着性を有する接着層を、前記異方性導電層又
は前記電気素子側の電極に配置する工程と、 前記基板側の電極と前記電気素子側の電極とが対向する
ようにこれらの基板と電気素子とを重ね合わせる工程
と、 該重ね合わせた後に前記基板と前記電気素子との接着箇
所を加圧し加熱する工程と、 を備えたことを特徴とする接着方法。
9. A bonding method for bonding a substrate and an electric element in a state where the electrodes and the opposing electrodes of the substrate and the electric element are secured to each other. Disposing an anisotropic conductive layer that secures and insulates from other electrodes so as to cover the electrode on the substrate side; and bonding the adhesive layer having tackiness at room temperature to the anisotropic conductive layer. Arranging the substrate or the electric element so that the electrode on the substrate side and the electrode on the electric element side face each other; and A step of pressing and heating a bonding portion between the substrate and the electric element, the bonding method comprising:
【請求項10】 前記異方性導電層が、樹脂に導電粒子
を分散・混入して形成された、 ことを特徴とする請求項9に記載の接着方法。
10. The bonding method according to claim 9, wherein the anisotropic conductive layer is formed by dispersing and mixing conductive particles in a resin.
JP9369101A 1997-12-27 1997-12-27 Bonding member, multichip module with the bonding member and bonding method using the bonding member Pending JPH11195860A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP9369101A JPH11195860A (en) 1997-12-27 1997-12-27 Bonding member, multichip module with the bonding member and bonding method using the bonding member
US09/221,142 US6172878B1 (en) 1997-12-27 1998-12-28 Multi-element module and production process thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9369101A JPH11195860A (en) 1997-12-27 1997-12-27 Bonding member, multichip module with the bonding member and bonding method using the bonding member

Publications (1)

Publication Number Publication Date
JPH11195860A true JPH11195860A (en) 1999-07-21

Family

ID=18493567

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WO2006112383A1 (en) * 2005-04-14 2006-10-26 Matsushita Electric Industrial Co., Ltd. Electronic circuit device and method for manufacturing same
JP2007281054A (en) * 2006-04-04 2007-10-25 Nec Corp Electronic component mounting structure, and its manufacturing method
JP2009191099A (en) * 2008-02-12 2009-08-27 Tatsuta System Electronics Kk Conductive adhesive sheet and circuit board having the same, method for producing conductive adhesive sheet
WO2020013622A1 (en) * 2018-07-12 2020-01-16 삼성전자주식회사 Led device and manufacturing method thereof

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