JP4593951B2 - Multi-chip package manufacturing method - Google Patents

Description

The present invention relates to a multichip package and a method for manufacturing the same , and more particularly to a technique for realizing a small and lightweight multichip package.

  Along with the downsizing of electronic devices, there is a demand for high-density mounting of semiconductor devices mounted on electronic devices. As part of this, a multi-chip package in which a plurality of IC chips are integrated and configured as a package has attracted attention. The multi-chip package is used for a portable terminal, a digital camera, and the like that are small and lightweight. As an example of a conventional multi-chip package, the one described in Patent Document 1 is shown in FIG.

  The multi-chip package 100 is provided on a lower chip 101 provided on a substrate, an upper chip 102 provided on the lower chip 101 and having a size smaller than that of the lower chip 101, and provided on the upper chip 102. And a metal wiring film 103 having a small size. The metal wiring film 103 is a film-like wiring material having a metal wiring pattern 104. Pads 105 and 106 are provided on one and other edges of the lower chip 101 and the upper chip 102, respectively.

In the multi-chip package 100, metal wires 108 are used to connect the lower chip pads 105 and the substrate stitches 107, and the upper chip pads 106 and the substrate stitches 107. Here, the wiring pattern 104 of the metal wiring film 103 is used in order to adjust the arrangement and arrangement order between the pad 105 of the lower chip and the pad 106 of the upper chip, thereby crossing the metal wires 108. To avoid. In this patent document, such a configuration can increase the degree of freedom in the arrangement and arrangement of pads.
JP 2000-332194 A (FIG. 1)

  By the way, in order to realize further miniaturization and weight reduction of a device using the multichip package, a smaller and lighter multipackage is required.

  The present inventor examined a structure of a multi-chip package in which an upper chip connecting surface is directed to a lower chip side and an inter-chip wiring composed of a metal bump and a wiring pattern is disposed between two IC chips. By adopting such a structure, space and materials required for wiring between chips can be reduced compared to the multi-chip package of Patent Document 1, thus realizing a smaller and lighter multi-chip package. It is considered possible. In the present invention, such a structure is called a chip-on-chip structure.

  As a chip-on-chip structure, a configuration in which additional wirings are formed on both IC chips and the additional wirings are connected can be considered. FIG. 9A is a plan view showing an example of this, and FIG. 9B is a cross-sectional view showing a BB cross section of FIG. 9A. The multi-chip package 40 includes a lower chip 41 fixed to the die pad 51 and an upper chip 42 having a size smaller than that of the lower chip 41. On the lower chip 41 and the upper chip 42, wirings 44 and 47 connected to terminals 43 and 46 are provided, respectively, and both wirings 44 and 47 are connected via metal bumps 45 and 48.

  By the way, when the multichip package 40 is manufactured, additional wiring is formed on the IC chip. Therefore, the manufacture of the multichip package 40 cannot be started unless the IC chip is prepared. In some cases, equipment manufacturers receive IC chips from outside to manufacture multi-chip packages. In such cases, the manufacture of multi-chip packages must be started after waiting for external IC chips to be provided. Therefore, a certain TAT is required for manufacturing the multichip package. However, many products that use multi-chip packages are exposed to intense competition in the market, such as mobile phones and digital cameras. There is a need for a shorter TAT.

  In order to shorten the TAT for manufacturing the multi-chip package 40, for example, when one of the IC chips is available first, an additional wiring can be formed in advance for the IC chip. However, in this case, it is necessary to form an insulating layer on the additional wiring in order to prevent oxidation of the additional wiring until the other IC chip is available. Further, when assembling into a multichip package, it is necessary to grind the insulating layer to expose the additional wiring. In this way, an extra process occurs, and for the other IC chip, additional wiring is formed after acquisition, so that TAT cannot be sufficiently shortened.

In view of the above, small, lightweight, and an object thereof is to provide a method of manufacturing a multi-chip package and its to and realizing the TAT of the manufacturing.

In order to achieve the above object, a multichip package according to the present invention is a multichip package in which a plurality of chips (IC chips) are accommodated in a single package.
A first chip having a terminal on the upper surface (lower chip), a second chip disposed on the first chip and having a terminal on the lower surface (upper chip), the first chip, and the second chip A wiring pattern disposed between the chip and the surface covered with an insulating layer having adhesiveness;
Each terminal of the first and second chips and the wiring pattern are connected by a conductor penetrating the insulating layer.

A manufacturing method of a multichip package according to the present invention is a method of manufacturing the multichip package,
The insulating layer is formed as a double-sided adhesive tape, and the first chip and the second chip are pressed against each other, thereby fixing both the chips.

  The interchip wiring material according to the present invention includes a wiring pattern and an insulating material that covers the wiring pattern, and the front surface and the back surface of the insulating material have adhesiveness.

  According to the multi-chip package of the present invention, the first chip and the second chip are connected by the wiring having the surface covered with the insulating layer having adhesiveness disposed between the first chip and the second chip. A lightweight multi-chip package can be easily realized. Further, it is possible to form an interchip wiring material without waiting for the completion of the first and second chips, and it is possible to realize a short TAT for manufacturing a multichip package.

  In the present invention, it is preferable that a lead frame connected to the wiring pattern via a bonding wire is disposed on the lower surface side of the first chip. In this case, by connecting the wiring pattern and the lead frame, wiring connection necessary for the multichip package can be achieved. It is also a preferred aspect that the insulating layer is formed of a material having thermoplasticity. In this case, when the multichip package is manufactured, the heated conductor can be pressed onto the insulating layer to open the connection hole. Furthermore, by forming the conductor with metal bumps or solder bumps, connection with the wiring pattern is facilitated.

  According to the method for manufacturing a multichip package according to the present invention, the chip can be fixed by pressing both the chips and the inter-chip wiring material, so that the multichip package can be easily manufactured. Preferably, the insulating layer is made of a material having thermoplasticity, the conductor is formed on the terminals of the first and second chips, respectively, and the conductor and the wiring pattern are joined by heating. At that time, the through hole can be formed by pressing both chips. In addition, when connecting between the conductor and the wiring pattern, it is also a preferable aspect that bonding is performed using ultrasonic waves while both are in contact with each other.

  According to the interchip wiring material according to the present invention, a multichip structure in which two chips are easily accommodated in one package can be obtained. The multichip package of the present invention can use a general-purpose memory chip as one chip and a logic circuit chip as the other chip. The effect of shortening TAT is particularly remarkable when two chips from different manufacturers are integrated into a single package.

  Hereinafter, embodiments of the present invention will be described specifically and in detail with reference to the accompanying drawings. FIG. 1 shows a configuration of a multi-chip package having a chip-on-chip structure according to a first embodiment of the present invention. The multichip package 10 includes a lower chip 11 provided on the die pad 24, an inter-chip wiring 13 provided on the lower chip 11, and an upper chip having a dimension smaller than that of the lower chip 11. Chip 12.

  FIG. 2 shows a cross section taken along line II-II in FIG. Metal bumps 15 and 17 made of gold or the like are provided on the terminal 14 of the lower chip and the terminal 16 of the upper chip, respectively. The inter-chip wiring 13 is disposed on the lower insulating film 18, the wiring layer 19 having a wiring pattern made of aluminum (Al), and the wiring layer 19 covering the wiring layer 19. The upper insulating film 20 is provided. Both the lower insulating film 18 and the upper insulating film 20 have a film thickness of about 10 μm, for example. A preferable film thickness is about 10 to 20 μm. The wiring layer 19 has a film thickness of about 3 μm, for example.

  The lower insulating film 18 and the upper insulating film 20 are made of the same material, have transparency, and have a sticky surface. In addition, it has rigidity against tensile stress. As the lower insulating film 18 and the upper insulating film 21 having such characteristics, for example, L series (product name) manufactured by Lintec Corporation can be used. The lower insulating film 18 and the upper insulating film 20 protect the wiring layer 19 and prevent the wiring layer 19 from being corroded.

  The lower insulating film 18 and the upper insulating film 20 are provided with connection holes 21 that pass through these films and have a diameter of about 100 μm. The metal bumps 15 and 17 are bonded to the wiring layer 19 in the connection hole 21. A connection portion, that is, a land portion, to be bonded to the metal bumps 15 and 17 of the wiring layer 19 has a diameter of about 10 μm.

  An external connection hole 22 penetrating the film is further provided at the edge of the upper insulating film 20, and an external connection metal bump 23 is provided on the wiring layer 19 in the external connection hole 22. The external connection metal bumps 23 are also made of gold or the like. If the external connection metal bumps 23 are provided via the wiring layer 19 almost directly above the metal bumps 15 provided on the lower chip 11, the strength of the land portion of the wiring layer 19 can be ensured. . The external connection metal bump 23 and the lead 25 are connected by a metal wire 26.

  Below, the manufacturing method of the multichip package 10 is demonstrated. In the manufacturing method of the multichip package 10 according to this embodiment, the interchip wiring 13 is formed independently of the lower chip 11 and the upper chip 12, and the formed interchip wiring 13, the lower chip 11 and the upper chip 12 are formed. The multi-chip package 10 is manufactured using

  3A to 3D show cross-sections at each manufacturing stage when the inter-chip wiring 13 is formed. First, as shown in FIG. 3A, a metal film 19 a made of aluminum is formed on the lower insulating film 18. Next, as shown in FIG. 3B, the metal film 19a is patterned by etching to form a wiring layer 19 having a desired wiring pattern. Subsequently, as shown in FIG. 3C, the upper insulating film 20 is bonded onto the lower insulating film 18 so as to cover the wiring layer 19. Depending on the shape of the wiring pattern of the wiring layer 19, the wiring layer 19 can be formed by pasting a thin film such as aluminum cut into a predetermined shape on the lower insulating film 18.

  Next, as shown in FIG. 3D, a connection hole 21 is formed in the lower insulating film 18 and the upper insulating film 20 and an external connection hole 22 is formed in the upper insulating film 20 by using laser light. At this time, the laser beam output and the irradiation time are set so that the adhesive film penetrates sufficiently and the adhesive film and the wiring layer are not excessively damaged. Instead of the formation using laser light, an upper insulating film and a lower insulating film in which the connection holes 21 or the external connection holes 22 are formed in advance can be used.

  When the multichip package 10 is assembled using the lower chip 11, the upper chip 12, and the formed interchip wiring 13, first, metal bumps 15 made of gold are formed on the terminals 14 of the lower chip. For forming the metal bump 15, a plating method, a stud bump method, or the like can be used. Next, as shown in FIG. 4A, the lower chip 11 is attached on the die pad 24. The formation of the metal bumps 15 may be performed after the lower chip 11 is attached to the die pad 24. Subsequently, as shown in FIG. 4B, metal bumps 17 made of gold are formed on the terminals 16 of the upper chip.

  Next, as shown in FIG. 5, the inter-chip wiring 13 is placed on the lower chip 11 so that the metal bumps 15 of the lower chip 11 are accommodated in the connection holes 21 of the lower insulating film 18. Subsequently, the upper chip 12 is placed on the inter-chip wiring 13 so that the metal bumps 17 of the upper chip 12 are accommodated in the connection holes 21 of the upper insulating film 20. Subsequently, ultrasonic waves are applied in a state where the metal bumps 15 and 17 and the wiring layer 19 are in contact, and the metal bumps 15 and 17 and the wiring layer 19 are joined. When the metal bumps 15 and 17 and the wiring layer 19 are joined, if the lower insulating film 18 and the upper insulating film 20 have heat resistance, reflow by heating may be performed. Furthermore, the use of a conductive adhesive or other methods can be used.

  Next, an external connection metal bump 23 made of gold is formed on the wiring layer 19 in the external connection hole 22. In forming the external connection metal bump 23, a plating method, a stud bump method, or the like can be used. Subsequently, by using the wire bonding method, the external connection metal bumps 23 and the leads 25 are connected by the metal wires 26, whereby the multichip package 10 shown in FIG. 1 can be completed.

  According to the present embodiment, by adopting the chip-on-chip structure, it is possible to easily realize a small and light multi-chip package by reducing the space and material required for wiring. Further, if the shapes of the lower chip 14 and the upper chip 17 are determined, the inter-chip wiring 13 can be formed independently of these before the manufacture thereof. Accordingly, it is possible to realize a short TAT for manufacturing the multichip package 10.

  In the present embodiment, the wiring layer 19 is protected by the lower insulating film 18 and the upper insulating film 20, so that the wiring layer 19 is not corroded even if the inter-chip wiring 13 is prepared, and is kept in a good state. I can do it.

  For the wiring layer 19, copper (Cu), an alloy, or the like can be used in addition to aluminum. In addition to the metal bumps 15 and 17 made of gold or the like, bumps made of an alloy such as solder can be used. When the sheet surfaces of the materials constituting the lower insulating film 18 and the upper insulating film 20 are not sticky, an adhesive layer can be formed by applying an adhesive solution or the like on the sheet surfaces.

  In the configuration of the multichip package 10, when it is necessary to cross a plurality of wirings between the lower chip 11 and the upper chip 12, the interchip wiring 13 may be formed of a plurality of layers. However, cost reduction can be realized by performing one wiring with a wire. FIG. 6 is a perspective view of a multichip package according to a modification of the present embodiment in which one wiring is performed using a wire. In the multi-chip package 27, a part of the wiring is constituted by the wiring metal wires 28 that connect the external connection metal bumps 23 that are not adjacent to each other.

  FIG. 7 is a cross-sectional view showing the configuration of a multichip package 29 according to the second embodiment of the present invention. In the multichip package 29 according to this embodiment, the lower insulating film 18 and the upper insulating film 20 have thermoplasticity, and there is no gap between the connection hole 21 and the metal bumps 15 and 17. The multi-chip package 10 according to the first embodiment has the same configuration. As a material of the lower insulating film 18 and the upper insulating film 21 having such characteristics, for example, there is a thermosetting epoxy resin manufactured by Lintec Corporation. The thermal softening temperature of this material is about 300 ° C.

  FIGS. 8A and 8B are cross-sectional views showing respective stages of manufacturing the multichip package 29 according to the present embodiment. In the manufacturing method of the multichip package according to this embodiment, the connection holes 21 are formed by the heated metal bumps 15 and 17 using the thermoplasticity of the lower insulating film 18 and the upper insulating film 20.

  When manufacturing the inter-chip wiring 13, the steps up to the step shown in FIG. 3C are performed in the same manner as in the first embodiment. Subsequently, the interchip wiring 13 is placed on the lower chip 11 with the horizontal position between the metal bump 15 and the land portion of the wiring layer 19 aligned. Subsequently, the upper chip 12 is placed on the inter-chip wiring 13 with the horizontal position between the metal bump 17 and the land portion of the wiring layer 19 aligned.

  Next, in the state shown in FIG. 8A, the lower chip 11 and the upper chip 12 are heated to 300 ° C. or higher, and pressure is applied from above the upper chip 12. As a result, as shown in FIG. 8B, the metal bumps 15 and 17 penetrate into the lower insulating film 18 and the upper insulating film 20, respectively, and come into contact with the wiring layer 19. Subsequently, the metal bumps 15 and 17 and the wiring layer 19 are joined by applying ultrasonic waves. In addition, when the lower insulating film 18 and the upper insulating film 20 have heat resistance, the metal bumps 15 and 17 and the wiring layer 19 may be reflowed by heating.

  The process from placing the inter-chip wiring 13 on the lower chip 11 to the process of joining the metal bumps 15 and 17 and the wiring layer 19 is a separate process, but by heating the lower chip 11 and the upper chip 12 in advance These steps can be performed at a time. In the present embodiment example, the land portion of the wiring layer 19 has a diameter of about 100 μm in consideration of the positional error between the land portion of the wiring layer 19 and the metal bumps 15 and 17 as compared with the first embodiment example. It is desirable to do.

  Next, the external connection hole 22 is opened using a laser beam. Subsequently, the multi-chip package 29 shown in FIG. 7 can be manufactured by forming the external connection metal bumps 23 and the metal wires 26 in the same manner as in the first embodiment. According to this embodiment, it is not necessary to provide openings in the lower insulating film 18 and the upper insulating film 20 in advance when the metal bumps 15 and 17 and the wiring layer 19 are joined as compared with the first embodiment. Therefore, a multichip package can be manufactured more easily. As the upper insulating film 20, a gel-like thermosetting resin can be used instead of the thermoplastic resin.

  As described above, the present invention has been described based on the preferred embodiment. However, the multichip package and the interchip wiring material according to the present invention are not limited to the configuration of the above embodiment, and the above embodiment. Multi-chip packages and inter-chip wirings that are variously modified and changed from the configuration of the example are also included in the scope of the present invention.

  For example, the present invention can be applied to a multi-chip package having a stack structure as long as at least a part thereof has a chip-on-chip structure. Further, one or both of the IC chips in which the additional wiring has already been formed can be connected using the interchip wiring material according to the present invention.

  The present invention can be suitably used for a multi-chip package having a chip-on-chip structure in which memory chips and logic circuit chips are connected to each other.

It is a perspective view which shows the structure of the multichip package which concerns on the example of 1st Embodiment. It is sectional drawing which shows the II-II cross section of FIG. FIGS. 3A to 3D are cross-sectional views showing respective manufacturing stages for manufacturing the interchip wiring of the multichip package according to the first embodiment. FIGS. 4A and 4B are cross-sectional views illustrating one manufacturing stage for manufacturing the lower chip and the upper chip of the multichip package according to the first embodiment. It is sectional drawing which shows one manufacturing step of the manufacturing method of the multichip package which concerns on the example of 1st Embodiment. It is a perspective view which shows the structure of the multichip package which concerns on the modification of the example of 1st Embodiment. It is sectional drawing which shows the structure of the multichip package which concerns on the example of 2nd Embodiment. FIGS. 8A and 8B are cross-sectional views showing respective stages of manufacturing the multichip package according to the second embodiment. FIG. 9A is a plan view showing a configuration of an example of a multi-chip package having a chip-on-chip structure, and FIG. 9B is a cross-sectional view showing a BB cross section of FIG. 9A. . 10 is a perspective view showing a configuration of a multichip package described in Patent Document 1. FIG.

Explanation of symbols

10, 27, 29, 40: Multichip package 11: Lower chip 12: Upper chip 13: Inter-chip wiring 14: Terminal pad 15: Metal bump 16: Terminal pad 17: Metal bump 18: Lower insulating film 19a: Metal film 19 : Wiring layer 20: Upper insulating film 21: Connection hole 22: External connection hole 23: External connection metal bump 24: Die pad 25: Lead 26: Metal wire 28: Wiring metal wire 41: Lower chip 42: Upper chip 43: Terminal 44: Wiring 45: Metal bump 46: Terminal 47: Wiring 48: Metal bump 49: Metal wire 50: Mold resin 51: Die pad 52: Lead

Claims (1)

In a method for manufacturing a multichip package, wherein a first chip having terminals on the upper surface and a second chip disposed on the first chip and having terminals on the lower surface are accommodated in a single package.
A first step of forming a desired wiring pattern on the first insulating layer having adhesiveness;
A second step of covering the wiring pattern with an adhesive second insulating layer;
Connection holes are formed so that the conductors formed on the terminals of the first and second chips fit in predetermined positions of the first and second insulating layers according to the first and second chips. A third step of forming and forming an interchip wiring layer comprising the first and second insulating layers and the wiring pattern;
A fourth step of attaching the first chip on a substrate and forming the conductor on the terminals of the first and second chips;
Placing the inter-chip wiring layer on the first chip, placing the second chip on the inter-chip wiring layer, so that the conductors of the first and second chips fit in the connection holes; A fifth step of joining the first and second chips;
A sixth step of forming an external connection hole at an edge of the second insulating layer and at a position directly above the connection hole in which the conductor of the first chip fits;
A seventh step of forming an external connection conductor on the wiring pattern in the external connection hole;
An eighth step of wire bonding the external connection conductor and the lead;
A method for manufacturing a multi-chip package.

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