JP2003078104A - Laminated semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which is composed of semiconductor devices laminated in a two-stage manner at a low cost, kept high in strength reliability, and capable of dissipating heat efficiently through the upper semiconductor device. SOLUTION: Semiconductor devices 101 and 102 are mounted on a multilayer circuit board 200, bringing their surfaces on which circuits are formed into contact with the circuit board 200, and a semiconductor device 103 is mounted on the semiconductor devices 101 and 102 bestriding them. The semiconductor device 103 is mounted on the semiconductor devices 101 and 102, making its circuit face toward them. Pads 113 formed on the circuit face of the semiconductor device 103 are connected to the primary pad 213 of the multilayer of the multilayer circuit 200 through the intermediary the wiring 51 of a TAB tape and a bonding wire 7. A metal heat dissipating plate 10 is formed on the surface of the semiconductor device 103 where no circuit is formed through the intermediary of a thermally conductive adhesive material 90. Therefore, all the rear of the semiconductor device 103 can be brought into contact with the heat sink 10, and a laminated semiconductor device of this design can be improved in heat dissipating properties.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high heat dissipation structure using an exposed heat dissipation plate in a compact, lightweight and highly functional laminated semiconductor package used in portable devices and the like.

[0002]

2. Description of the Related Art Mobile devices such as digital video and digital cameras are becoming more sophisticated and smaller and lighter. For this reason, in semiconductor packages to be mounted on mobile devices, system-in-package is being actively developed in which a memory, a microcomputer and the like are integrated into one package to increase added value and reduce the mounting area. In addition to two-dimensionally arranging a plurality of chips having different functions on a multilayer circuit board, a number of three-dimensionally laminated structures have been devised.

For example, as described in Japanese Patent Application Laid-Open No. 2000-349228, the first semiconductor chip is mounted on the first substrate via the protruding metal formed on the circuit surface of the first semiconductor chip, There is a method in which the second semiconductor chip is mounted on the second substrate formed on the back surface of the circuit surface of the first semiconductor chip via the protruding metal formed on the circuit surface of the second semiconductor chip. .

Further, as described in JP-A-9-186289, there is a method in which chips and bonding layers are alternately arranged to assemble a chip having a multilayer laminated structure and a substrate is arranged in the lowermost layer.

However, if the heat generation density is increased by mounting the chips three-dimensionally in this way, there is a concern that the chip temperature rises above a permissible value and the operating performance deteriorates. Therefore, it has become necessary to efficiently and highly radiate the package.

Particularly, in a package in which a microcomputer is mounted on SDRAM and Flash memory, 90% or more of heat is generated from the microcomputer, and the heat resistant temperature of the memory is lower than that of the microcomputer. I want to lower the temperature. For this reason, there is a demand to efficiently dissipate the heat of the microcomputer to the outside (for example, by connecting the housing and the microcomputer to a low thermal resistance).

The conventional three-dimensional laminated package has the following structure for high heat dissipation. For example, JP-A-5-27
As described in Japanese Patent Laid-Open No. 5611, the circuit board is provided with a step, and the surfaces of the semiconductor elements of all stages on which the circuits are formed are mounted on the circuit board via bumps. There is a structure in which a semiconductor element is connected to the uppermost part of a circuit board and a heat sink is adhered to the back surface of the element with a high thermal conductive adhesive.

Alternatively, as described in Japanese Patent Application Laid-Open No. 2000-294723, two semiconductor devices flip-chip mounted on one surface of a circuit board are laminated so that their chip back surfaces are laminated together, and the main semiconductor device of the upper semiconductor device is formed. There is a structure in which a metal plate for heat dissipation is provided on the back surface of the circuit board connected to the surface side and the metal plate is exposed from the sealing resin.

Further, as described in JP-A-5-136330, a capacitor (first-stage semiconductor element) is attached to one surface of a ceramic multilayer wiring board, and a second-stage capacitor is provided on the capacitor. There is a structure in which the above semiconductor element is attached face down, and a good heat conductive plate is attached to the back surface of the second stage semiconductor element via an adhesive material.

[0010] Also. As described in Japanese Patent Application Laid-Open No. 11-214448, semiconductor chips having integrated circuits on both upper and lower surfaces of a semiconductor substrate are bump-mounted on a circuit board, and the integrated circuit formed on the upper surface of the lower semiconductor substrate has the following structure. There is a structure in which a lower surface integrated circuit of a semiconductor substrate is bump-mounted and a heat spreader is installed on the upper semiconductor substrate.

[0011]

However, the above-mentioned Japanese Unexamined Patent Application Publication No.
000-349228 and JP-A-9-18628.
In the stacked semiconductor package described in Japanese Patent Publication No. 9, the heat dissipation of the chip is not considered.

Therefore, since the heat radiation path of the chip is only on the substrate side, when the heat generation amount of the uppermost chip is large, in the technique described in Japanese Patent Laid-Open No. 2000-349228, the first substrate and the first substrate The temperature rise of the first semiconductor chip sandwiched between the two substrates is inevitable. Further, in the technique described in Japanese Patent Laid-Open No. 9-186289,
The temperature rise of the semiconductor chip located in the lowermost layer is inevitable.

Further, in the technique disclosed in Japanese Patent Application Laid-Open No. 5-275611, it is necessary to process steps on the circuit board according to the size of the elements to be stacked, which results in higher cost and lower cost than a flat circuit board. It is not suitable as a method for mounting an inexpensive semiconductor device for mobile use.

Further, in the technique disclosed in Japanese Patent Laid-Open No. 2000-294723, a circuit board is interposed between a metal plate for heat dissipation and a semiconductor element. Therefore, when the metal plate is brought into contact with the housing to radiate heat, the heat radiating effect is lower than that in the case where the metal plate is directly attached to the chip. In addition, in the peripheral portion of the upper substrate circuit, there is a bonding region used for connection with the lower circuit substrate,
Since the metal plate cannot be provided on the entire upper circuit board or the entire upper surface of the semiconductor device, the heat diffusion effect is limited.

Further, the technique disclosed in Japanese Patent Laid-Open No. 5-136330 is difficult to apply because it has a fundamentally different member structure and assembly process from the resin-sealed semiconductor device for mobile use.

Further, in the technique disclosed in Japanese Patent Laid-Open No. 11-214448, it is premised that the integrated circuit is formed on both sides of the semiconductor substrate, which is a general method in which the integrated circuit is formed on one side of the semiconductor substrate. It is not possible to use different chips.

An object of the present invention is to stack low-cost general semiconductor elements for mobile use in two layers at low cost, and join a heat sink so that mechanical pressure is not applied to the semiconductor elements. It is to realize a semiconductor device that efficiently radiates heat from the upper semiconductor element while ensuring strength reliability.

[0018]

In order to achieve the above object, the present invention is configured as follows. (1) In a laminated semiconductor device in which a plurality of semiconductor elements are laminated on a multilayer circuit board having external terminals, and the circuit surfaces and electrical connection portions of these semiconductor elements are resin-sealed, at least the first semiconductor element and Two semiconductor elements of the second semiconductor element are arranged such that the circuit surfaces of these semiconductor elements face one surface of the multilayer circuit board.
And a third semiconductor element is arranged on the surface of the second semiconductor element opposite to the circuit surface, so that the circuit surface faces the third semiconductor element.
A means for electrically connecting the third semiconductor element and the multilayer circuit board, and a heat radiating plate contacting the surface of the third semiconductor element opposite to the circuit surface and exposed from the resin sealing surface are provided. Prepare

(2) Preferably, in the above (1),
Tape between the third semiconductor element and the multilayer circuit board
It is electrically connected by automated bonding tape.

(3) Further, preferably, in the above (1), the third semiconductor element and the multilayer circuit board are electrically connected by a lead frame.

(4) Further, in the above (1), preferably, the third semiconductor element and the multilayer circuit board are electrically connected to each other by using a silicon substrate formed by a wafer process.

The third semiconductor element is arranged such that the circuit surfaces thereof are on the first and second semiconductor element sides, and is electrically connected to the multilayer circuit board by wiring or the like. Therefore, the entire back surface of the third semiconductor element can be brought into contact with the heat dissipation plate, and heat dissipation efficiency can be improved.

[0023]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the accompanying drawings. FIG. 1 is a schematic sectional view of a laminated semiconductor device according to a first embodiment of the present invention. In FIG. 1, semiconductor elements 101 and 102 (first semiconductor element,
Second semiconductor element) is mounted face down on the multilayer circuit board 200, that is, the surface of the semiconductor element on which the circuit is formed is mounted on the multilayer circuit board 200.
03 (third semiconductor element) is two semiconductor elements 101,
It is mounted over 102. This semiconductor device 1
No. 03 is mounted on the semiconductor elements 101 and 102 so that the circuit surface thereof faces the semiconductor elements 101 and 102, that is, facedown.

The semiconductor element 101 is electrically connected to the primary side pad 211 of the multilayer circuit board 200 having the base material 250 by the gold bump 121 formed on the pad 111 of the semiconductor element 101. An adhesive resin 401 is interposed between the semiconductor element 101 and the multilayer circuit board 200.

The semiconductor element 102 is also electrically connected to the multilayer circuit board 200 in the same manner as the semiconductor element 101.

The pads 113 formed on the circuit surface of the semiconductor element 103 are formed on the surface of the multilayer circuit board 200 via the wirings 51 of the tape automated bonding (TAB) tape and the bonding wires 7. And is electrically connected to the primary side pad 213.

The wiring 51 of the TAB tape and the lower semiconductor elements 101 and 102 are electrically insulated by an insulating layer 52. Each primary side pad 211 of the multilayer circuit board 200,
Reference numeral 213 denotes through holes 221, 223, and secondary pads 241, 2 provided on the back surface of the circuit board 200, respectively.
It is electrically connected to the external terminals 261 and 263 via 43.

The semiconductor element mounting surface side of the multilayer circuit board 200 is sealed with resin 8. In addition, the upper semiconductor device 1
A metal heat sink 10 having a large semiconductor device projected area is mounted on the back surface (surface on which no circuit is formed) of 03 via a heat conductive adhesive material 90.

The following effects can be obtained by using the laminated semiconductor device according to the first embodiment of the present invention configured as described above. (1) The heat of the semiconductor element 103 arranged in the upper stage and having a large amount of heat generation can be efficiently diffused by the heat dissipation plate 10, and it is also suitable for heat dissipation to a housing or the like. That is, the semiconductor element 103 is mounted so that the circuit surface (front surface) faces the semiconductor elements 101 and 102, and is electrically connected to the multilayer circuit board 200 via the wiring 51 and the bonding wire 7. Therefore, the entire back surface of the semiconductor element 103 can be brought into contact with the heat dissipation plate 10, and heat dissipation efficiency can be improved.

(2) The heat dissipation plate 10 is bonded to the semiconductor element 10
Since the elements 1, 102, and 103 are sealed with resin, the element is not destroyed by the mechanical pressure at the time of joining.

(3) Since the TAB tape allows fine processing of wiring, it can be used even if the pad pitch of the semiconductor element is as narrow as several tens of μm.

That is, by mounting low-priced general semiconductor elements for mobile use in two layers at low cost and joining a heat sink so that mechanical pressure is not applied to the semiconductor elements, strength reliability is improved. It is possible to realize a semiconductor device that efficiently radiates heat from the upper semiconductor element while securing it.

FIG. 2 is a sectional view of a laminated semiconductor device according to the second embodiment of the present invention. In FIG. 2, semiconductor elements 101 and 102 are mounted face down on a multilayer circuit board 200, and a semiconductor element 103 is mounted face down on two semiconductor elements 101 and 102.

The semiconductor element 101 is a gold bump 121 formed on the pad 111 of the semiconductor element 101, and is bonded to the primary side pad 211 of the multilayer circuit board 200 via an anisotropic conductive resin 401.
It is electrically connected.

The semiconductor element 102 is also electrically connected to the multilayer circuit board 200 in the same manner as the semiconductor element 101.

Further, the pad 113 of the semiconductor element 103
Is Tape Automated Bonding (TAB)
Via the tape wiring 51 and the anisotropic conductive resin 404,
It is electrically connected to the primary side pad 213 of the multilayer circuit board 200.

The wiring 51 of the TAB tape and the lower semiconductor elements 101 and 102 are electrically insulated by the insulating layer 52. Each primary side pad 211 of the multilayer circuit board 200,
Reference numeral 213 denotes through holes 221, 223, and secondary pads 241, 2 provided on the back surface of the circuit board 200, respectively.
It is electrically connected to the external terminals 261 and 263 via 43.

The semiconductor element mounting surface side (front surface side) of the multilayer circuit board 200 is sealed with resin 8 and the upper semiconductor element 10 is sealed.
A metal heat sink 10 having a large semiconductor device projected area is mounted on the back surface (surface on which no circuit is formed) of 3 via a heat conductive adhesive material 90.

If the stacked semiconductor device according to the second embodiment of the present invention having the above-mentioned structure is used,
In addition to the effects (1) to (3) of the embodiment of (4), (4) when the TAB tape is pressure-bonded using the anisotropic conductive resin 404,
Since they can be connected in a lump, there is an effect that assembly is easier than when wire bonding is used.

FIG. 3 is a sectional view of a stacked semiconductor device according to the third embodiment of the present invention. In FIG. 3, the semiconductor elements 101 and 102 are mounted face down on the multilayer circuit board 200, and the semiconductor element 103 is mounted face down on the two semiconductor elements 101 and 102.

The semiconductor element 101 is electrically connected to the primary side pad 211 of the multilayer circuit board 200 by the gold bump 121 formed on the pad 111 of the semiconductor element 101. An adhesive resin 401 is interposed between the semiconductor element 101 and the multilayer circuit board 200.

The semiconductor element 102 is also electrically connected to the multilayer circuit board 200 in the same manner as the semiconductor element 101.

The pad 113 of the semiconductor element 103 is electrically connected to the primary side pad 213 of the multilayer circuit board 200 via the bonding wire 11, the lead frame 6, and the bonding wire 7.

The insulating film 1 is provided between the lead frame 6 and the back surface of the semiconductor element 101 and the circuit surface of the semiconductor element 103.
It is electrically insulated by 2. The primary pads 211 and 213 of the circuit board 200 are connected to the external terminals 261 and 2 via the through holes 221 and 223 and the secondary pads 241 and 243 provided on the back surface of the circuit board 200, respectively.
It is electrically connected to 63.

The semiconductor element mounting surface side (front surface side) of the multilayer circuit board 200 is sealed with resin 8. Further, the metal heat dissipation plate 10 having a large projected area of the semiconductor device is mounted on the back surface of the upper semiconductor element 103 via the heat conductive adhesive material 90.

If the stacked semiconductor device according to the third embodiment of the present invention configured as described above is used, the above first
In addition to the effects (1) and (2) of the embodiment described above, the following effects can be obtained.

That is, according to the third embodiment of the present invention, (5) since the lead frame 6 is used, the cost can be reduced as compared with the case where the TAB tape is used. However, the pad pitch of the device is limited to 120 μm or more, which is the pitch limit of the lead frame 6.

FIG. 4 is a sectional view of a stacked semiconductor device according to the fourth embodiment of the present invention. In FIG. 4, the semiconductor elements 101 and 102 are mounted face down on the multilayer circuit board 200, and the semiconductor element 103 is mounted face down on the two semiconductor elements 101 and 102.

The semiconductor element 101 is electrically connected to the primary side pad 211 of the multilayer circuit board 200 by the gold bump 121 formed on the pad 111 of the semiconductor element 101. An adhesive resin 401 is interposed between the semiconductor element 101 and the multilayer circuit board 200.

The semiconductor element 102 is also electrically connected to the multilayer circuit board 200 in the same manner as the semiconductor element 101.

The pad 113 of the semiconductor element 103 is electrically connected to the primary side pad 213 of the multilayer circuit board 200 via the bonding wire 11, the lead frame 6, and the anisotropic conductive resin 404.

The lead frame 6 and the back surface of the semiconductor element 101 and the circuit surface of the semiconductor element 103 are insulated from each other by the insulating film 1.
It is electrically insulated by 2. The primary pads 211 and 213 of the circuit board 200 are connected to the external terminals 261 and 2 via the through holes 221 and 223 and the secondary pads 241 and 243 provided on the back surface of the circuit board 200, respectively.
It is electrically connected to 63.

The semiconductor element mounting surface side (front surface side) of the multilayer circuit board 200 is sealed with resin 8. Further, the metal heat dissipation plate 10 having a large projected area of the semiconductor device is mounted on the back surface of the upper semiconductor element 103 via the heat conductive adhesive material 90.

If the stacked semiconductor device according to the fourth embodiment of the present invention having the above structure is used,
Effects (1) and (2) of the third embodiment, and effects of the third embodiment
In addition to (5), as in the second embodiment, (4) when the leads are pressure-bonded using an anisotropic conductive resin, they can be connected all at once, so assembly is easier than when wire bonding is used. Has the effect of becoming.

FIG. 5 is a sectional view of a laminated semiconductor device according to the fifth embodiment of the present invention. In FIG. 5, semiconductor elements 101 and 102 are mounted face down on a multilayer circuit board 200. The semiconductor element 101 is a gold bump 121 formed on the pad 111 of the semiconductor element 101.
00 is electrically connected to the primary side pad 211.
An adhesive resin 401 is interposed between the semiconductor element 101 and the multilayer circuit board 200.

The silicon substrate 30 on which the polyimide insulating layer 33 and the copper wiring 32 are formed by the wafer process is
It is mounted over the two semiconductor elements 101 and 102.

The semiconductor element 103 has the pad 1
13 are electrically connected to the pads 31 of the silicon substrate 30 by the gold bumps 123 formed on the metal bumps 13, and the primary side pads 2 of the multilayer circuit board 200 are further connected via the bonding wires 7.
It is electrically connected to 13. An adhesive resin 403 is interposed between the semiconductor element 103 and the multilayer circuit board 30.

The semiconductor element 101 has the pad 1
The gold bumps 121 formed on the multi-layer circuit board 20.
No. 0 primary side pad 211 is electrically connected via an anisotropic conductive resin 401. Also, the silicon substrate 3
The back surface of 0 and the back surface of the semiconductor element 101 are electrically insulated by an insulating adhesive material 91.

Similarly to the semiconductor element 101, the semiconductor element 102 is electrically connected to the multilayer circuit board 200 and insulated from the silicon substrate 30.

Each primary side pad 211 of the circuit board 200,
Reference numeral 213 denotes through holes 221, 223, and secondary pads 241, 2 provided on the back surface of the circuit board 200, respectively.
It is electrically connected to the external terminals 261 and 263 via 43.

The semiconductor element mounting surface side (front surface side) of the multilayer circuit board 200 is sealed with resin 8. Further, the metal heat dissipation plate 10 having a large projected area of the semiconductor device is mounted on the back surface of the upper semiconductor element 103 via the heat conductive adhesive material 90.

By using the laminated semiconductor device according to the fifth embodiment of the present invention configured as described above, the effects (1) and (2) of the first embodiment and the same effect as the TAB tape can be obtained.
(3) Since fine wiring can be processed on the silicon substrate, the pads of the upper semiconductor element can be used even at a narrow pitch of several tens of μm or less, and there are the following effects.

That is, (6) Since the upper element 101 and the silicon substrate 30 are silicon-to-silicon junctions, thermal strain is unlikely to occur and the reliability of the electrical junction is improved. (7)
When the silicon substrate 30 is used, the wiring layout has a high degree of freedom, so that a plurality of semiconductor elements having different sizes can be mounted on the upper stage.

A method of manufacturing the stacked semiconductor device according to the first embodiment of the present invention will be described with reference to FIGS. 6 and 7. Although the TAB tapes are continuous in FIGS. 6 and 7, the area of the TAB tape for one stacked semiconductor device is shown.

As shown in FIG. 6A, the TAB tape 5
An opening 53 and a copper wiring 51 are formed in the center of 0. Further, a large number of positioning holes 54 are formed on both edges of the TAB tape 50.

Further, the TAB tape 50 has a large opening other than the central portion, and the central portion is supported by the suspending portion 55.

The semiconductor element 103 is aligned with the TAB tape 50 shown in FIG. 6A, and the element pad and the central wiring tip of the TAB tape 50 are connected. FIG. 6B is a plan view seen from the back surface of the semiconductor element 103.

Next, as shown in FIG. 7A, the two semiconductor elements 101 and 102 are previously mounted on the multilayer circuit board 200 with an adhesive resin (not shown), and the multilayer circuit board 2
The positioning projection 13 penetrates through the positioning hole 270 of No. 00 and is supported. In this state, the two semiconductor elements 1
The semiconductor element 103 mounted on the TAB tape 50 is laminated on the upper surfaces of 01 and 102 (the surface opposite to the circuit surface).

At this time, as shown in FIG. 7B, the TAB tape 50 is placed in the positioning hole 270 of the multilayer circuit board 200.
Align the positioning holes 54 and insert.

Next, as shown in FIG. 7C, the wiring end (not shown) of the TAB tape 50 and the pad (not shown) of the multilayer circuit board 200 are connected to each other by the bonding wire 7, As shown in FIG. 7D, one surface of the multilayer circuit board 200, that is, the surface side on which the semiconductor elements 101, 102, 103 are arranged is sealed with the resin 8.

At this time, the resin 8 is prevented from entering the back surface of the semiconductor element 103 (the surface on which the circuit is not formed) by pasting a tape on the back surface of the element or applying a release agent. Alternatively, after the resin 8 is sealed, polishing is performed to expose the back surface of the semiconductor element 103.

Next, as shown in FIG. 7E, the heat dissipation plate 10 is bonded to the back surface of the upper semiconductor element 103 with an adhesive 90 having high thermal conductivity.

Subsequently, as shown in FIG. 7F, the laminated semiconductor device is divided into individual pieces.

Up to this point, that is, (a) to (f) in FIG.
Up to the section along the suspension 55 of the TAB tape 50 (see FIG. 6).
The cross section along the line AA ′ of FIG.
When viewed from the cross section (the cross section taken along the line BB 'in FIG. 6), the cross section shown in FIG.

Then, as shown in (h) of FIG. 7, a solder bump 260 is mounted on the multilayer circuit board 200 to complete a stacked semiconductor device in which three semiconductor elements 101, 102, 103 are built. .

As described above, the stacked semiconductor device according to the first embodiment of the present invention can be manufactured.

A method of manufacturing the stacked semiconductor device according to the second embodiment of the present invention will be described with reference to FIGS.

Although the TAB tape 50 is continuous in FIGS. 8 and 9, the area of the TAB tape 50 for one laminated semiconductor device is shown here.

As shown in FIG. 8A, the TAB tape 50
An opening 53 and a copper wiring 51 are formed in the center of the. The copper wiring 51 extends outside the central portion of the tape 50. A large number of positioning holes 54 are formed on both edges of the TAB tape 50.

The TAB tape 50 has a large opening other than the central portion, and the central portion is supported by the hanging portion 55.

The semiconductor element 103 is aligned with the TAB tape 50 shown in FIG. 8A, and the element pad and the wiring tip at the center of the TAB tape 50 are connected. FIG. 8B is a plan view seen from the back surface of the semiconductor element 103.

FIG. 9 shows a cross section (a cross section taken along the line BB 'in FIG. 8) of the portion without the hanging portion 55.

As shown in FIG. 9A, two semiconductor elements 101 and 102 are mounted in advance on the multilayer circuit board 200 with an adhesive resin (not shown), and the positioning holes 270 of the multilayer circuit board 200 are mounted in the positioning holes 270. The projection 13 for positioning is pierced to support the multilayer circuit board 200.

An anisotropic conductive resin 404 is provided on the multilayer circuit board 200. In this state, the semiconductor element 103 mounted on the TAB tape 50 is laminated on the upper surfaces of the two semiconductor elements 101 and 102.

At this time, as shown in FIG. 9B, the TAB tape 50 is placed in the positioning hole 270 of the multilayer circuit board 200.
Align the positioning holes 54 and insert.

Next, as shown in FIG. 9C, the crimping jig 14 is pressed against the end of the copper wiring 51 of the TAB tape 50, and the multi-layer circuit board is inserted through the anisotropic conductive resin 404. Two
00 pad (not shown).

Subsequently, as shown in FIG. 9D, one surface of the multilayer circuit board 200, that is, the semiconductor elements 101, 1
The surface on which 02 and 103 are arranged is sealed with resin 8.

At this time, the resin 8 is prevented from entering the back surface of the semiconductor element 103 by applying a tape to the back surface of the element or applying a release agent. Alternatively, after the resin 8 is encapsulated, the back surface of the semiconductor element 103 is exposed by polishing.

Next, as shown in FIG. 9E, the heat dissipation plate 10 is bonded to the back surface of the upper semiconductor element 103 with an adhesive 90 having high thermal conductivity.

Then, as shown in FIG. 9F, the laminated semiconductor device is divided into individual pieces, and solder bumps 260 are mounted on the multilayer circuit board 200 to form three semiconductor elements 101, 10.
A stacked semiconductor device in which 2, 103 are built is completed.

As described above, the stacked semiconductor device according to the second embodiment of the present invention can be manufactured.

The stacked semiconductor devices according to the third, fourth and fifth embodiments of the present invention can also be manufactured by the same method as shown in FIGS.

Further, although the above-mentioned example is an example in which two semiconductor elements are provided in the lower stage and one semiconductor element is provided in the upper stage, the present invention can be applied to an example in which three semiconductor elements are provided in the lower stage and one is provided in the upper stage. Is.

[0094]

EFFECTS OF THE INVENTION Since the present invention is constructed as described above, low-priced general semiconductor devices for mobile applications are stacked and mounted at low cost in two stages, and mechanical pressure is applied to the semiconductor devices. By joining the heat sink so that it is not loaded,
It is possible to realize a semiconductor device that efficiently radiates heat from the upper semiconductor element while ensuring strength reliability.

That is, the following effects are obtained. (1) The heat of the semiconductor element arranged in the upper stage and having a large amount of heat generation can be efficiently diffused by the heat radiating plate, and it is also suitable for radiating to the case.

(2) Since the heat dissipation plate is bonded after the resin sealing, the element is not destroyed by the mechanical pressure at the time of bonding.

(3) When using a TAB tape or a silicon substrate for wiring, it is possible to deal with a semiconductor device having a narrow pad pitch of several tens of μm.

(4) Leads and TAs using anisotropic conductive resin
When the wiring part of the B tape is crimped, they can be connected at once, so assembly is easier than when using wire bonding.

(5) When a lead frame is used, the pad pitch is limited to semiconductor elements having a pitch of 120 μm or more, but the cost can be reduced.

(6) When a silicon substrate is used, thermal strain with the upper element is less likely to occur and the reliability of the electrical junction is improved.

(7) When a silicon substrate is used, the degree of freedom in wiring layout is high, so that a plurality of semiconductor elements having different sizes can be mounted on the upper stage.

[Brief description of drawings]

FIG. 1 is a schematic sectional view of a stacked semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a schematic sectional view of a stacked semiconductor device according to a second embodiment of the present invention.

FIG. 3 is a schematic sectional view of a stacked semiconductor device according to a third embodiment of the present invention.

FIG. 4 is a schematic sectional view of a stacked semiconductor device according to a fourth embodiment of the present invention.

FIG. 5 is a schematic sectional view of a stacked semiconductor device according to a fifth embodiment of the present invention.

FIG. 6 is an explanatory diagram of the manufacturing method of the stacked semiconductor device according to the first embodiment of the present invention.

FIG. 7 is an explanatory diagram of the manufacturing method of the stacked semiconductor device according to the first embodiment of the present invention.

FIG. 8 is an explanatory diagram of the manufacturing method of the stacked semiconductor device according to the second embodiment of the present invention.

FIG. 9 is an explanatory diagram of the manufacturing method of the stacked semiconductor device according to the second embodiment of the present invention.

[Explanation of symbols]

6 Lead Frame 7 Bonding Wire 8 Sealing Resin 10 Heat Sink 11 Bonding Wire Between Lead Frame and Semiconductor Element 12 Insulating Film Between Lead Frame and Semiconductor Element 13 Positioning Protrusion 14 Crimping Jig 30 Silicon Substrate 31 Silicon Pad 32 Silicon substrate wiring 33 Silicon substrate insulating layer 50 TAB tape 51 TAB tape wiring 52 TAB tape insulating material 53 TAB tape central opening 54 TAB tape positioning hole 55 TAB tape hanging portion 90 Heat sink adhesive 91 Silicone substrate adhesive 101, 102 Lower semiconductor element 103 Upper semiconductor element 111 Lower semiconductor element pad 113 Upper semiconductor element pad 121, 123 Lower semiconductor element gold bump 200 Multilayer circuit board 211, 213 Multilayer Circuit board Primary pads 221, 223 Multi-layer circuit board through holes 241, 243 Multi-layer circuit board secondary pads 250 Multi-layer circuit board base materials 261, 263 Multi-layer circuit board secondary bumps 270 Multi-layer circuit board positioning holes 401, 403 Adhesion Resin 404 Anisotropic conductive resin

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Asao Nishimura             5-20-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Stock             Ceremony Company within Hitachi Semiconductor Group

Claims (4)

[Claims] 1. A laminated semiconductor device in which a plurality of semiconductor elements are laminated on a multilayer circuit board having external terminals, and a circuit surface and electrical connection portions of these semiconductor elements are resin-sealed, at least a first semiconductor. Two semiconductor elements, an element and a second semiconductor element, are arranged such that the circuit surfaces of these semiconductor elements face one surface of the multilayer circuit board;
On the surface opposite to the circuit surface of the first and second semiconductor elements,
The third semiconductor element is arranged such that the circuit surfaces thereof face each other, and means for electrically connecting the third semiconductor element and the multilayer circuit board to each other is provided on the side opposite to the circuit surface of the third semiconductor element. A laminated semiconductor device, comprising: a heat dissipation plate that is in contact with the surface and is exposed from the resin sealing surface. 2. The stacked semiconductor device according to claim 1, wherein the third semiconductor element and the multilayer circuit board are electrically connected by a tape automated bonding tape. Stacked semiconductor device. 3. The stacked semiconductor device according to claim 1, wherein a lead frame electrically connects the third semiconductor element and the multilayer circuit board. 4. The stacked semiconductor device according to claim 1, wherein the third semiconductor element and the multilayer circuit board are electrically connected using a silicon substrate formed by a wafer process. Stacked semiconductor device.