JP2006156438A - Manufacturing method of electronic component loading device and electronic component loading device - Google Patents
Manufacturing method of electronic component loading device and electronic component loading device Download PDFInfo
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Description
本発明は、微細化、多層化の容易な電子部品搭載装置の製造方法及び電子部品搭載装置に関する。 The present invention relates to a method for manufacturing an electronic component mounting apparatus that can be easily miniaturized and multilayered, and an electronic component mounting apparatus.
従来から、この種の、電子部品(半導体素子)を3次元的に配置構成し、電子部品相互間の電気接続を容易に可能とする電子部品搭載装置として、パッケージ内に半導体素子を樹脂で埋設して実装し、パッケージの両面に外部接続端子を設け、または外部接続端子が接続されるべき配線パターンの端子形成部分を露出させ、多層的に積み重ねることができるようにすることが知られている(例えば、特許文献1参照)。 Conventionally, this kind of electronic component (semiconductor element) is arranged and configured three-dimensionally, and as an electronic component mounting device that enables easy electrical connection between electronic components, the semiconductor element is embedded in the package with resin. It is known that external connection terminals are provided on both surfaces of the package, or terminal formation portions of the wiring pattern to which the external connection terminals are to be connected are exposed so that they can be stacked in multiple layers. (For example, refer to Patent Document 1).
このような電子部品搭載装置の製造方法について、図5を参照して説明する。先ず、図5(a)に示すように、ベース基板1上に半導体チップ2を実装し、その後、同図(b)に示すように、半導体チップ2を絶縁層3で埋設し、絶縁層3の表面に銅箔4を形成する。次いで、同図(c)に示すように、同チップ2の端子部を狙ってレーザー加工でビアホール(VH)5を形成し、その後、同図(d)に示すように、ビアホール5と銅箔4上にメッキ等により導体層6を形成し、その後、同図(e)に示すように、銅箔4に対してエッチングして配線パターン7を形成する。半導体チップ2は、その電極端子が、ビアホール5を形成してなる面側の配線パターン7の端子形成部分に導体層6を介して電気接続される。 A method for manufacturing such an electronic component mounting apparatus will be described with reference to FIG. First, as shown in FIG. 5A, the semiconductor chip 2 is mounted on the base substrate 1, and then, as shown in FIG. 5B, the semiconductor chip 2 is embedded in the insulating layer 3, and the insulating layer 3 A copper foil 4 is formed on the surface. Next, as shown in FIG. 4C, the via hole (VH) 5 is formed by laser processing aiming at the terminal portion of the chip 2, and then the via hole 5 and the copper foil are formed as shown in FIG. A conductor layer 6 is formed on the upper surface 4 by plating or the like, and thereafter, a wiring pattern 7 is formed by etching the copper foil 4 as shown in FIG. The electrode terminal of the semiconductor chip 2 is electrically connected to the terminal forming portion of the wiring pattern 7 on the surface side where the via hole 5 is formed via the conductor layer 6.
また、微細化した多層配線板の形成方法として、金属ナノペーストを用いることが知られている(例えば、特許文献2参照)。この文献には電子部品を基材上に接着層を介して搭載することは示されていない。 In addition, it is known to use a metal nano paste as a method for forming a miniaturized multilayer wiring board (see, for example, Patent Document 2). This document does not show that an electronic component is mounted on a substrate via an adhesive layer.
ところで、上述のような電子部品搭載装置及びその製造方法においては、
(1)半導体チップ2の厚みを(端子高さ)をなるべく合わせるために半導体チップ厚みを研磨や研削で処理する必要がある。
(2)さらに高さが変る表面実装用デバイス、例えばチップ抵抗やQFPの埋設に関しては不向きであり、搭載可能な電子部品に制約がある。
(3)ビアホール5へメッキ等により導体層6を形成し、さらにフォトリソ法等によりエッチングして配線パターン7を得ている。このように、配線パターン形成に、メッキやエッチングといった湿式法を用いるため、基板やチップの汚染が発生し、その洗浄なども含め工程が長くなるといった課題がある。
(1) In order to match the thickness of the semiconductor chip 2 (terminal height) as much as possible, it is necessary to process the thickness of the semiconductor chip by polishing or grinding.
(2) It is unsuitable for embedding a surface mounting device whose height changes further, for example, a chip resistor or QFP, and there are restrictions on mountable electronic components.
(3) A conductor layer 6 is formed on the via hole 5 by plating or the like, and further etched by a photolithography method or the like to obtain a wiring pattern 7. As described above, since a wet method such as plating or etching is used to form the wiring pattern, there is a problem that the substrate and the chip are contaminated, and the process including the cleaning is lengthened.
本発明は、上記問題を解消するものであり、搭載可能な電子部品に制約がなく、多様な電子部品を搭載可能で、配線パターン形成に際して基板や電子部品の汚染が発生することがなく、洗浄などの手間がかからず、工程が短く低コストな電子部品搭載装置の製造方法及び電子部品搭載装置を提供することを目的とする。 The present invention solves the above-mentioned problems, there are no restrictions on the electronic components that can be mounted, a variety of electronic components can be mounted, and contamination of the substrate and electronic components does not occur during wiring pattern formation, and cleaning is performed. It is an object of the present invention to provide a method for manufacturing an electronic component mounting apparatus and an electronic component mounting apparatus that do not require time and effort, and that have a short process and a low cost.
上述目的を達成するため、本発明は、電子部品を基材上に搭載した電子部品搭載装置の製造方法において、電子部品を基材の表面に接着層を介して接着して搭載する電子部品搭載工程と、前記基材の裏面に前記搭載した電子部品の端子が露出するように裏面側より基材に孔加工を施す孔加工工程と、金属ナノペーストを使用して、前記孔加工した孔内に、前記露出した電子部品の端子と電気接続する導電路を形成すると共に、基材裏面に前記孔内導電路と電気接続した回線パターンを形成する回路パターン形成工程と、を備えたものである。 In order to achieve the above-described object, the present invention provides an electronic component mounting method in which an electronic component is mounted on a surface of a base material by bonding it through an adhesive layer in a manufacturing method of an electronic component mounting device in which the electronic component is mounted on the base material. A hole processing step of drilling holes in the base material from the back surface side so that the terminals of the mounted electronic components are exposed on the back surface of the base material, and using the metal nanopaste, And a circuit pattern forming step of forming a circuit pattern electrically connected to the conductive path in the hole on the back surface of the base material while forming a conductive path electrically connected to the terminal of the exposed electronic component. .
前記電子部品搭載工程において、複数の電子部品の端子部は、端子接着面高さが略均一となるように、接着層を有するシート材を介して基材に接着されるものとすればよい。 In the electronic component mounting step, the terminal portions of the plurality of electronic components may be bonded to the base material via a sheet material having an adhesive layer so that the terminal bonding surface height is substantially uniform.
前記回路パターン形成工程において使用される金属ナノペーストは、導電性材料に300℃以下の熱処理またはプラズマ照射をして電気導通性が比抵抗1×10E−3Ω・cm以下となるものとすればよい。 The metal nanopaste used in the circuit pattern forming step may be such that the electrical conductivity becomes a specific resistance of 1 × 10E−3 Ω · cm or less by subjecting the conductive material to a heat treatment or plasma irradiation of 300 ° C. or less. .
前記電子部品搭載工程と孔加工工程との間に、搭載された電子部品を絶縁樹脂で埋設しプレート状にする工程をさらに備えたものとしてもよい。 A step of embedding the mounted electronic component with an insulating resin to form a plate shape may be further provided between the electronic component mounting step and the hole drilling step.
前記形成した回路パターン上に、さらに絶縁層を形成する工程と、前記形成された絶縁層に孔加工する工程と、前記加工された孔内に導電路を形成すると共に前記絶縁層上に前記導電路に電気接続した回路パターンを形成する多層回路形成工程とを、備えたものとすることができる。 A step of further forming an insulating layer on the formed circuit pattern, a step of forming a hole in the formed insulating layer, a conductive path in the processed hole, and the conductive layer on the insulating layer A multilayer circuit forming step of forming a circuit pattern electrically connected to the path.
また、本発明は、外部入力端子を持つ各種電子部品と、この電子部品の端子が接続される回路パターンが形成された絶縁性の基材とを備え、この基材上に前記電子部品を搭載した電子部品搭載装置において、前記回路パターンが前記基材の電子部品搭載側とは反対面に形成されており、前記基材の電子部品端子位置に施された孔の孔内導電路と、前記回路パターンとが、導電性材料に300℃以下の熱処理またはプラズマ照射をして電気導通性が比抵抗1×10E−3Ω・cm以下となる金属ナノペーストを用いて形成されている電子部品搭載装置である。 The present invention also includes various electronic components having external input terminals and an insulating base material on which a circuit pattern to which the terminals of the electronic components are connected is formed, and the electronic components are mounted on the base material. In the electronic component mounting apparatus, the circuit pattern is formed on the surface opposite to the electronic component mounting side of the base material, and the in-hole conductive path of the hole provided at the electronic component terminal position of the base material, An electronic component mounting apparatus in which a circuit pattern is formed by using a metal nano paste having a specific resistance of 1 × 10E−3 Ω · cm or less by performing heat treatment or plasma irradiation on a conductive material at 300 ° C. or less. It is.
本発明の電子部品搭載装置及びその製造方法によれば、プリント配線板を必要とせず、多品種な異形状の電子部品の実装が一度に同様な方法で実現でき、従来のフォトリソで使用するレジストや銅箔のエッチングが不要となり、廃棄物の削減が図れると共に、半田を使わないなど環境負荷が低い製造方法を提供することができる。また、工程が短く生産性に優れる。また、電子部品実装にインターコネクション技術を使うことが必要なくインフラが少なくて済み、安価に電子部品搭載装置を提供可能となり、ひいては、オンデマンドで電子部品搭載装置を製造することができる。 According to the electronic component mounting apparatus and the manufacturing method therefor of the present invention, a printed wiring board is not required, and various types of electronic components having different shapes can be mounted at once by the same method. Etching of copper foil and copper foil is not required, so that waste can be reduced and a manufacturing method with low environmental load such as not using solder can be provided. In addition, the process is short and the productivity is excellent. In addition, it is not necessary to use an interconnection technology for mounting electronic components, the infrastructure is small, an electronic component mounting device can be provided at low cost, and the electronic component mounting device can be manufactured on demand.
以下、本発明の実施形態に係る電子部品搭載装置の製造方法及び電子部品搭載装置を図面を参照して説明する。図1(a)〜(e)及び図2(f)〜(h)は、本実施形態の電子部品搭載装置を製造する方法についての製造工程を示す。 Hereinafter, a method for manufacturing an electronic component mounting apparatus and an electronic component mounting apparatus according to an embodiment of the present invention will be described with reference to the drawings. FIGS. 1A to 1E and FIGS. 2F to 2H show manufacturing steps for a method of manufacturing the electronic component mounting apparatus according to this embodiment.
まず、第1の工程(図1(a))では、絶縁材11(絶縁層)として、50μm厚みのポリイミドフィルム(ニカフレックスCISV)を用意して、その片面に熱硬化型絶縁性接着材であるエポキシ樹脂(ペルノックスXM−2100/XY−2110)を塗布して接着層12を形成したベース基材10(基材)を準備する。接着材にはUV硬化型樹脂や最初から粘着性のある片面熱可塑型粘着フィルムなどを用いてもよい。
First, in the first step (FIG. 1 (a)), a polyimide film (Nikaflex CISV) having a thickness of 50 μm is prepared as an insulating material 11 (insulating layer), and a thermosetting insulating adhesive material is provided on one surface thereof. A base substrate 10 (substrate) is prepared by applying an epoxy resin (Pernox XM-2100 / XY-2110) to form the
第2の工程(図1(b))では、この接着層12の上に所要の電子部品30(本例ではチップ部品31とQFP32)を適宜配置し、実装した後、エポキシ接着材の推奨硬化条件80℃、80分で硬化させ電子部品30を接着固定させた実装基板40を得る(電子部品搭載工程)。
In the second step (FIG. 1B), the required electronic component 30 (in this example, the
第3の工程(図1(c))では、実装基板40の部品搭載側にその実装基板40の外形の形状に樹脂流れ防止枠51を設けて熱硬化型絶縁性封止材であるエポキシ樹脂(ペルノックスXM−2100/XY−2110)を流し込み、その後、エポキシ樹脂の推奨硬化条件80℃、80分で硬化させ絶縁性の補強層13を形成し、ハンドリングしやすい実装基板41を得る。樹脂流れ防止枠51は後で取り外しても、そのまま付けた状態で用いてもよい。補強層13のエポキシ樹脂はUV硬化型の樹脂などを用いることもできる。
In the third step (FIG. 1C), an epoxy resin which is a thermosetting insulating sealing material by providing a resin
第4の工程(図1(d))では、実装基板41のベース基材10側の面に電子部品30の接続が必要な端子に達するようにCO2レーザーやエキシマレーザーなどで穴あけ処理により端子結線用ビアホール21aを形成する。すなわち、ベース基材10の裏面に搭載電子部品の端子が露出するように裏面側より同基材10に孔加工を施す(孔加工工程)。
In the fourth step (FIG. 1 (d)), terminal connection is performed by drilling with a CO2 laser, an excimer laser, or the like so as to reach a terminal that requires connection of the
第5の工程(図1(e))では、端子結線用ビアホール21a内に端子と電気接続する導電路21と、ビアホール21a間やベース基材10上(基材裏面)の配線となる回路パターン22を、金属ナノペースト(ハリマ化成ナノ銀ペーストNPS)をスクリーン印刷法で印刷し、その後、金属ナノペーストを処理する推奨条件である熱処理250℃、60分を与え、金属ナノペーストから安定分散材を除去し、金属ナノ粒子を露出させ、電気的導通性の比抵抗1×10E−3Ω・cm以下を得てパターン化する(回路パターン形成工程)。これにより、電子部品搭載用装置42を形成することができる。
In the fifth step (FIG. 1 (e)), a circuit pattern that becomes a
続いて、多層回路化の実施形態を説明する。
上記電子部品搭載用装置42において配線パターンが多層化を必要とする場合、第6の工程(図2(f))では、回路パターン22面の表層の最低限必要な場所に絶縁性樹脂であるエポキシ樹脂をスクリーン印刷で形成し、熱処理170℃、30分間、硬化させることで、絶縁層14を得る。
Next, a multi-layer circuit embodiment will be described.
In the case where the wiring pattern needs to be multilayered in the electronic
第7の工程(図2(g))では、絶縁層14面に回路パターン22の層に達するように、CO2レーザーやエキシマレーザーなどで穴あけ処理によりビアホール23を形成する。
In the seventh step (FIG. 2G), a
第8の工程(図2(h))では、この回路パターン22の層への結線や、ビアホール間やその他回路24を第5の工程と同様に形成し、多層型電子部品搭載用装置43を形成する。回路パターン形成においては、導電性材料をインクジェット、またはディスペンス、またはスクリーン印刷、または転写などで塗布して回路を描けばよい。
In the eighth step (FIG. 2 (h)), wiring to the layer of this
図3(a)(b)は、上記図1(e)に相当する電子部品搭載用装置42の具体例を示す。また、図4(a)(b)は、上記図2(h)に相当する多層回路化した多層型電子部品搭載用装置43の具体例を示す。なお、本発明は、上記実施例の構成に限られることなく、発明の趣旨を変更しない範囲で種々の変形が可能である。
3A and 3B show specific examples of the electronic
10 ベース基材(基材)
11 絶縁材
12 接着層(接着材)
14 絶縁層
21a 端子結線用ビアホール
21 導電路
22 回路パターン
23 ビアホール
30 電子部品(チップ部品31とQFP32)
40,41 実装基板
42 電子部品搭載用装置
43 多層型電子部品搭載用装置
10 Base substrate (base material)
11 Insulating
14
40, 41 Mounting
Claims (6)
電子部品を基材の表面に接着層を介して接着して搭載する電子部品搭載工程と、
前記基材の裏面に前記搭載した電子部品の端子が露出するように裏面側より基材に孔加工を施す孔加工工程と、
金属ナノペーストを使用して、前記孔加工した孔内に、前記露出した電子部品の端子と電気接続する導電路を形成すると共に、基材裏面に前記孔内導電路と電気接続した回線パターンを形成する回路パターン形成工程と、を備えたことを特徴とする電子部品搭載装置の製造方法。 In the manufacturing method of the electronic component mounting apparatus in which the electronic component is mounted on the substrate,
An electronic component mounting process in which an electronic component is bonded and mounted on the surface of the substrate via an adhesive layer;
A hole processing step of performing hole processing on the base material from the back surface side so that the terminals of the mounted electronic components are exposed on the back surface of the base material;
Using metal nano paste, a conductive path electrically connected to the terminal of the exposed electronic component is formed in the hole processed hole, and a line pattern electrically connected to the conductive path in the hole is formed on the back surface of the substrate. And a circuit pattern forming step for forming the electronic component mounting apparatus.
前記形成された絶縁層に孔加工する工程と、
前記加工された孔内に導電路を形成すると共に前記絶縁層上に前記導電路に電気接続した回路パターンを形成する多層回路形成工程とを、備えたことを特徴とする請求項1乃至請求項4のいずれかに記載の電子部品搭載装置の製造方法。 Forming an insulating layer on the formed circuit pattern; and
Drilling the formed insulating layer;
A multilayer circuit forming step of forming a conductive path in the processed hole and forming a circuit pattern electrically connected to the conductive path on the insulating layer. 5. A method for manufacturing an electronic component mounting apparatus according to any one of 4 above.
前記回路パターンが前記基材の電子部品搭載側とは反対面に形成されており、
前記基材の電子部品端子位置に施された孔の孔内導電路と、前記回路パターンとが、導電性材料に300℃以下の熱処理またはプラズマ照射をして電気導通性が比抵抗1×10E−3Ω・cm以下となる金属ナノペーストを用いて形成されていることを特徴とする電子部品搭載装置。 In an electronic component mounting apparatus comprising various electronic components having external input terminals and an insulating base material on which a circuit pattern to which terminals of the electronic components are connected is formed, and mounting the electronic components on the base material ,
The circuit pattern is formed on the surface opposite to the electronic component mounting side of the base material,
The in-hole conductive path of the hole provided at the electronic component terminal position of the base material and the circuit pattern are subjected to heat treatment or plasma irradiation at 300 ° C. or lower on the conductive material, and the electrical conductivity is a specific resistance of 1 × 10E. An electronic component mounting apparatus, characterized in that the electronic component mounting apparatus is formed using a metal nanopaste of −3 Ω · cm or less.
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JP2009283547A (en) * | 2008-05-20 | 2009-12-03 | Dainippon Printing Co Ltd | Forming method and forming apparatus for conductive pattern, and conductive substrate |
JP2010529657A (en) * | 2007-05-29 | 2010-08-26 | オッカム ポートフォリオ リミテッド ライアビリティ カンパニー | Solderless electronic device assembly and manufacturing method thereof |
JP2012044163A (en) * | 2010-08-18 | 2012-03-01 | Dyconex Ag | Method for embedding electrical component |
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JP2010529657A (en) * | 2007-05-29 | 2010-08-26 | オッカム ポートフォリオ リミテッド ライアビリティ カンパニー | Solderless electronic device assembly and manufacturing method thereof |
JP2009283547A (en) * | 2008-05-20 | 2009-12-03 | Dainippon Printing Co Ltd | Forming method and forming apparatus for conductive pattern, and conductive substrate |
JP2012044163A (en) * | 2010-08-18 | 2012-03-01 | Dyconex Ag | Method for embedding electrical component |
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