JPH04259232A - Method for mounting semiconductor chip - Google Patents
Method for mounting semiconductor chipInfo
- Publication number
- JPH04259232A JPH04259232A JP2062591A JP2062591A JPH04259232A JP H04259232 A JPH04259232 A JP H04259232A JP 2062591 A JP2062591 A JP 2062591A JP 2062591 A JP2062591 A JP 2062591A JP H04259232 A JPH04259232 A JP H04259232A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- film carrier
- hole
- inner lead
- mounting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 47
- 238000000034 method Methods 0.000 title claims abstract description 32
- 239000002184 metal Substances 0.000 claims abstract 4
- 229910052751 metal Inorganic materials 0.000 claims abstract 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 24
- 239000010931 gold Substances 0.000 claims description 24
- 229910052737 gold Inorganic materials 0.000 claims description 24
- 239000004020 conductor Substances 0.000 claims description 5
- 239000000853 adhesive Substances 0.000 claims 1
- 230000001070 adhesive effect Effects 0.000 claims 1
- 230000007423 decrease Effects 0.000 description 6
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 5
- 239000011888 foil Substances 0.000 description 3
- 239000010949 copper Substances 0.000 description 2
- 239000000969 carrier Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 230000002787 reinforcement Effects 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
- H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
- H01L2224/1134—Stud bumping, i.e. using a wire-bonding apparatus
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16235—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/1624—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting between the body and an opposite side of the item with respect to the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/9202—Forming additional connectors after the connecting process
Abstract
Description
【０００１】0001
【産業上の利用分野】本発明はフィルムキャリヤに半導
体チップを実装する方法に関する。半導体チップの実装
において従来のワイヤボンディングに代わる新しい技術
として、近年、ＴＡＢ（Ｔａｐｅ Ａｕｔｏｍａｔｅｄ
Ｂｏｎｄｉｎｇ）技術が広く利用されるようになって
きている。フレキシブルプリント板からなるフィルムキ
ャリヤに半導体チップを直接実装するＴＡＢ技術は、従
来のワイヤボンディングに比べて多端子半導体チップの
実装が極めて容易である。
しかも装置の薄型化やフィルムキャリヤによる立体配線
化を容易に実現できるという特長を具えている。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for mounting semiconductor chips on a film carrier. In recent years, TAB (Tape Automated
Bonding technology is becoming widely used. TAB technology, in which a semiconductor chip is directly mounted on a film carrier made of a flexible printed board, allows mounting of multi-terminal semiconductor chips much easier than conventional wire bonding. Moreover, it has the advantage of making the device thinner and easily realizing three-dimensional wiring using a film carrier.
【０００２】しかし、デバイスホールに突出したインナ
ーリード部を半導体チップに熱圧着するＴＡＢ技術には
限界があり、例えば半導体チップが更に小型化されると
同時に接続される電極の数が更に増加すると、高い信頼
度で半導体チップをフィルムキャリヤに実装することが
極めて困難になる。そこでかかる半導体チップを高い信
頼度でフィルムキャリヤに実装できる実装方法の確立が
要望されている。[0002] However, there are limits to TAB technology, which thermocompresses inner lead parts protruding into device holes onto semiconductor chips. It becomes extremely difficult to reliably mount semiconductor chips on film carriers. Therefore, it is desired to establish a mounting method that can mount such a semiconductor chip on a film carrier with high reliability.
【０００３】0003
【従来の技術】図２は従来のＴＡＢ技術を示す側断面図
である。図２（ａ） において従来の最も一般的なＴＡ
Ｂ技術は半導体チップ１をフィルムキャリヤ２に実装し
ており、フィルムキャリヤ２はベースフィルム２１に設
けられたデバイスホール２２に、３５μｍ程度の厚さを
有する銅（Ｃｕ）箔からなる導体パターン２３のインナ
ーリード部２４が突出している。半導体チップ１の電極
１１はそれぞれボール状の金バンプ１２を介してインナ
ーリード部２４に熱圧着され、補強のため半導体チップ
１とインナーリード部２４は樹脂３によって封止されて
いる。2. Description of the Related Art FIG. 2 is a side sectional view showing a conventional TAB technique. In Figure 2(a), the most common conventional TA
In technology B, a semiconductor chip 1 is mounted on a film carrier 2, and the film carrier 2 has a conductor pattern 23 made of copper (Cu) foil with a thickness of about 35 μm in a device hole 22 provided in a base film 21. The inner lead portion 24 protrudes. The electrodes 11 of the semiconductor chip 1 are each thermocompressed to the inner lead part 24 via a ball-shaped gold bump 12, and the semiconductor chip 1 and the inner lead part 24 are sealed with a resin 3 for reinforcement.
【０００４】また図２（ｂ） においてエリアＴＡＢ方
式といわれる技術では半導体チップ１をフィルムキャリ
ヤ４に実装している。デバイスホールを具えていないフ
ィルムキャリヤ４はスルーホール４２を有し、導体パタ
ーン４３のインナーリード部４４はスルーホール４２を
介し下部電極４５に接続されている。半導体チップ１の
電極１１はそれぞれボール状の金バンプ１２を介して下
部電極４５に熱圧着される。[0004] Also, in the technique called area TAB method shown in FIG. 2(b), a semiconductor chip 1 is mounted on a film carrier 4. The film carrier 4 which does not have a device hole has a through hole 42, and an inner lead portion 44 of a conductive pattern 43 is connected to a lower electrode 45 through the through hole 42. The electrodes 11 of the semiconductor chip 1 are thermocompression bonded to the lower electrode 45 via ball-shaped gold bumps 12, respectively.
【０００５】[0005]
【発明が解決しようとする課題】従来の最も一般的なＴ
ＡＢ技術を適用した場合は図２（ｃ） に示す如く、金
バンプ１２を介して電極１１をインナーリード部２４に
熱圧着する際に、ウエッジを押した跡２５がインナーリ
ード部２４に残りインナーリード部の機械的強度を低下
させる。しかし、従来の半導体チップの場合インナーリ
ード部の配列ピッチは １００μｍ 以上あり、３５μ
ｍ程度の厚さを有するＣｕ箔を用いて導体パターンを形
成することが充分可能である。即ち、ＴＡＢ技術を適用
したことによりインナーリード部の機械的強度が低下し
ても許容範囲である。[Problem to be solved by the invention] The most common conventional T
When the AB technique is applied, as shown in FIG. 2(c), when the electrode 11 is thermocompression bonded to the inner lead part 24 via the gold bump 12, a mark 25 from pressing the wedge remains on the inner lead part 24 and the inner Decreases the mechanical strength of the lead part. However, in the case of conventional semiconductor chips, the arrangement pitch of the inner lead part is more than 100μm, which is 35μm.
It is fully possible to form a conductive pattern using a Cu foil having a thickness of about 100 m. That is, even if the mechanical strength of the inner lead portion decreases due to the application of the TAB technique, this is within an acceptable range.
【０００６】しかるに半導体チップが更に小型化される
と同時に接続される電極の数が増加すると、導体パター
ンのインナーリード部を １００μｍ 以下のピッチで
配列する必要があり、露光やエッチングによるパターン
の抜け性を考慮するとＣｕ箔の厚さを１７μｍ程度にし
なければならない。しかも従来の半導体チップの場合と
同等のウエッジを押した跡がインナーリード部に残る。
即ち、例えばインナーリード部の幅を等しくしても機械
的強度が大幅に低下するという問題があった。However, as semiconductor chips are further miniaturized and the number of connected electrodes increases, it is necessary to arrange the inner lead portions of the conductor pattern at a pitch of 100 μm or less, which reduces the tendency of the pattern to come out during exposure and etching. Considering this, the thickness of the Cu foil must be approximately 17 μm. Furthermore, the same marks left on the inner leads by pressing the wedge as in the case of conventional semiconductor chips. That is, for example, even if the widths of the inner lead portions were made equal, there was a problem in that the mechanical strength was significantly reduced.
【０００７】なお、エリアＴＡＢ方式といわれる技術で
はインナーリード部の機械的強度の低下が小さく、例え
ばＣｕ箔の厚さを１７μｍ程度にしても実装の信頼度が
低下することはない。しかしフィルムキャリヤの下部電
極と半導体チップの電極との位置合わせが極めて難しい
という問題があった。[0007] In the technique called area TAB method, the decrease in mechanical strength of the inner lead portion is small, and even if the thickness of the Cu foil is set to about 17 μm, for example, the reliability of mounting will not decrease. However, there was a problem in that it was extremely difficult to align the lower electrode of the film carrier and the electrode of the semiconductor chip.
【０００８】本発明の目的はインナーリード部の配列ピ
ッチが １００μｍ 以下になる半導体チップを、高い
信頼度でしかも容易にフィルムキャリヤに実装できる実
装方法を提供することにある。An object of the present invention is to provide a mounting method that allows semiconductor chips whose inner lead portions are arranged at a pitch of 100 μm or less to be easily mounted on a film carrier with high reliability.
【０００９】[0009]
【課題を解決するための手段】図１は本発明になる半導
体チップの実装方法を示す側断面図である。なお全図を
通し同じ対象物は同一記号で表している。[Means for Solving the Problems] FIG. 1 is a side sectional view showing a semiconductor chip mounting method according to the present invention. The same objects are represented by the same symbols throughout the figures.
【００１０】上記課題はデバイスホールを具えていない
フィルムキャリヤ５に半導体チップ１を実装する方法で
あって、半導体チップ１の電極１１にフィルムキャリヤ
５を貫通可能な金バンプ１３を熱圧着する工程と、フィ
ルムキャリヤ５のベースフィルム５１に設けられた貫通
孔５２に金バンプ１３を嵌挿する工程と、貫通孔５２の
側方両側、または側方片側に形成されてなるフィルムキ
ャリヤ５のインナーリード部５４に、貫通孔５２を貫通
した金バンプ１３の先端を熱圧着する工程を有する本発
明になる半導体チップの実装方法によって達成される。The above-mentioned problem is a method of mounting a semiconductor chip 1 on a film carrier 5 that does not have a device hole, which includes a step of thermocompression bonding gold bumps 13 that can penetrate the film carrier 5 to electrodes 11 of the semiconductor chip 1; , a step of fitting the gold bumps 13 into the through holes 52 provided in the base film 51 of the film carrier 5; and an inner lead portion of the film carrier 5 formed on both sides or one side of the through holes 52. This is achieved by the semiconductor chip mounting method according to the present invention, which includes the step of thermocompression bonding the tips of the gold bumps 13 that have passed through the through holes 52 in step 54 .
【００１１】[0011]
【作用】図１において半導体チップの電極にフィルムキ
ャリヤを貫通可能な金バンプを熱圧着する工程と、フィ
ルムキャリヤのベースフィルムに設けられた貫通孔に金
バンプを嵌挿する工程と、貫通孔の側方両側、または側
方片側に形成されてなるフィルムキャリヤのインナーリ
ード部に、貫通孔を貫通した金バンプの先端を熱圧着す
る工程を有する本発明になる半導体チップの実装方法は
、例えばＣｕ箔の厚さを１７μｍ程度にしてもインナー
リード部の機械的強度が低下することはない。しかもベ
ースフィルムの貫通孔に金バンプを嵌挿するため半導体
チップの位置合わせが容易である。即ち、インナーリー
ド部の配列ピッチが １００μｍ 以下になる半導体チ
ップを、高い信頼度でしかも容易にフィルムキャリヤに
実装できる実装方法を実現することができる。[Function] In FIG. 1, there are a process of thermocompression-bonding a gold bump that can penetrate a film carrier to an electrode of a semiconductor chip, a process of inserting the gold bump into a through-hole provided in a base film of a film carrier, and a process of inserting a gold bump into a through-hole provided in a base film of a film carrier. The semiconductor chip mounting method according to the present invention includes the step of thermocompression bonding the tips of gold bumps passing through through holes to the inner lead portions of a film carrier formed on both side sides or one side side. Even if the thickness of the foil is set to about 17 μm, the mechanical strength of the inner lead portion does not decrease. Moreover, since the gold bumps are inserted into the through holes of the base film, it is easy to align the semiconductor chips. That is, it is possible to realize a mounting method that can easily mount a semiconductor chip whose inner lead portions are arranged at a pitch of 100 μm or less on a film carrier with high reliability.
【００１２】0012
【実施例】以下添付図により本発明の実施例について説
明する。図１において本発明になる実装方法は半導体チ
ップ１をフィルムキャリヤ５に実装しており、図１（ａ
） に示す如く半導体チップ１はそれぞれの電極１１に
金バンプ１３が熱圧着されている。また、フィルムキャ
リヤ５はベースフィルム５１の前記電極１１と対向する
位置に貫通孔５２が設けられ、半導体チップ１を実装す
る面の反対側に厚さが１７μｍ程度のＣｕ箔からなる導
体パターン５３が形成されている。なお導体パターン５
３のインナーリード部５４は途中で分割され貫通孔５２
の側方両側に配設されている。DESCRIPTION OF THE PREFERRED EMBODIMENTS Examples of the present invention will be described below with reference to the accompanying drawings. In FIG. 1, the mounting method according to the present invention mounts a semiconductor chip 1 on a film carrier 5.
), the semiconductor chip 1 has gold bumps 13 bonded to each electrode 11 by thermocompression. The film carrier 5 is provided with a through hole 52 at a position facing the electrode 11 of the base film 51, and a conductor pattern 53 made of Cu foil with a thickness of about 17 μm is provided on the opposite side of the surface on which the semiconductor chip 1 is mounted. It is formed. Note that conductor pattern 5
The inner lead portion 54 of No. 3 is divided in the middle and has a through hole 52.
are placed on both sides of the
【００１３】かかるフィルムキャリヤ５に半導体チップ
１を実装する際は図１（ｂ） に示す如く、接着剤６に
よって半導体チップ１をフィルムキャリヤ５に接着する
と同時に、電極１１に熱圧着された金バンプ１３をベー
スフィルム５１の貫通孔５２に嵌挿する。電極１１に熱
圧着された金バンプ１３はベースフィルム５１の貫通孔
５２を貫通可能な高さを有し、先端をインナーリード部
５４に熱圧着することによって半導体チップ１のフィル
ムキャリヤ５への実装が完了する。When mounting the semiconductor chip 1 on such a film carrier 5, as shown in FIG. 13 is inserted into the through hole 52 of the base film 51. The gold bumps 13 thermocompression bonded to the electrodes 11 have a height that allows them to pass through the through holes 52 of the base film 51, and the semiconductor chip 1 is mounted on the film carrier 5 by thermocompression bonding the tips to the inner lead portions 54. is completed.
【００１４】ボールボンダーによって半導体チップ１の
電極１１に熱圧着された金バンプ１３は、一般に図１（
ａ） に示す如く断面が凸字状になった金バンプ１３の
先端に髭状の突起１４が形成されている。図１（ｂ）
に示す如く突起１４を溶かし金バンプ１３の先端と共に
インナーリード部５４に熱圧着しても良いが、図１（ｃ
） に示す如く貫通孔５２の側方片側に形成されてなる
インナーリード部５４に突起１４を熱圧着しても良い。The gold bumps 13 thermocompressed to the electrodes 11 of the semiconductor chip 1 by a ball bonder are generally shown in FIG.
As shown in a), a whisker-like projection 14 is formed at the tip of a gold bump 13 having a convex cross section. Figure 1(b)
As shown in FIG.
), the protrusion 14 may be thermocompression bonded to the inner lead portion 54 formed on one side of the through hole 52.
【００１５】このように半導体チップの電極にフィルム
キャリヤを貫通可能な金バンプを熱圧着する工程と、フ
ィルムキャリヤのベースフィルムに設けられた貫通孔に
金バンプを嵌挿する工程と、貫通孔の側方両側、または
側方片側に形成されてなるフィルムキャリヤのインナー
リード部に、貫通孔を貫通した金バンプの先端を熱圧着
する工程を有する本発明になる半導体チップの実装方法
は、例えばＣｕ箔の厚さを１７μｍ程度にしてもインナ
ーリード部の機械的強度が低下することはない。しかも
ベースフィルムの貫通孔に金バンプを嵌挿するため半導
体チップの位置合わせが容易である。即ち、インナーリ
ード部の配列ピッチが １００μｍ 以下になる半導体
チップを、高い信頼度でしかも容易にフィルムキャリヤ
に実装できる実装方法を実現することができる。[0015] As described above, there are a step of thermocompression bonding a gold bump capable of penetrating the film carrier to an electrode of a semiconductor chip, a step of fitting the gold bump into a through hole provided in a base film of the film carrier, and a step of inserting the gold bump into a through hole provided in a base film of the film carrier. The method for mounting a semiconductor chip according to the present invention includes the step of thermocompression bonding the tips of gold bumps passing through through holes to the inner lead portions of a film carrier formed on both side sides or one side side. Even if the thickness of the foil is set to about 17 μm, the mechanical strength of the inner lead portion does not decrease. Moreover, since the gold bumps are inserted into the through holes of the base film, it is easy to align the semiconductor chips. That is, it is possible to realize a mounting method that can easily mount a semiconductor chip whose inner lead portions are arranged at a pitch of 100 μm or less on a film carrier with high reliability.
【００１６】[0016]
【発明の効果】上述の如く本発明によればインナーリー
ド部の配列ピッチが １００μｍ 以下になる半導体チ
ップを、高い信頼度でしかも容易にフィルムキャリヤに
実装できる実装方法を提供することができる。As described above, according to the present invention, it is possible to provide a mounting method that can easily mount a semiconductor chip whose inner lead portions are arranged at a pitch of 100 μm or less on a film carrier with high reliability.
【図１】 本発明になる半導体チップの実装方法を示
す側断面図である。FIG. 1 is a side sectional view showing a semiconductor chip mounting method according to the present invention.
【図２】 従来のＴＡＢ技術を示す側断面図である。FIG. 2 is a side sectional view showing conventional TAB technology.
Claims (2)
ムキャリヤ（５） に半導体チップ（１） を実装する
方法であって、該半導体チップ（１） の電極（１１）
に該フィルムキャリヤ（５） を貫通可能な金バンプ（
１３）を熱圧着する工程と、該フィルムキャリヤ（５）
のベースフィルム（５１）に設けられた貫通孔（５２
）に該金バンプ（１３）を嵌挿する工程と、該貫通孔（
５２）の側方両側、または側方片側に形成されてなる導
体パターン（５３）のインナーリード部（５４）に、該
貫通孔（５２）を貫通した該金バンプ（１３）の先端を
熱圧着する工程を有することを特徴とした半導体チップ
の実装方法。1. A method of mounting a semiconductor chip (1) on a film carrier (5) that does not have a device hole, the method comprising: an electrode (11) of the semiconductor chip (1);
gold bumps (5) that can penetrate the film carrier (5)
13) and the step of thermocompression bonding the film carrier (5).
The through hole (52) provided in the base film (51) of
) and inserting the gold bump (13) into the through hole (
The tip of the gold bump (13) that has passed through the through hole (52) is thermocompression bonded to the inner lead part (54) of the conductor pattern (53) formed on either side or one side of the metal bump (52). A method for mounting a semiconductor chip, comprising a step of:
法において貫通孔（５２）に金バンプ（１３）を嵌挿す
るに際し、半導体チップ（１） を接着剤（６） によ
ってフィルムキャリヤ（５） に接着することを特徴と
した半導体チップの実装方法。2. In the semiconductor chip mounting method according to claim 1, when inserting the gold bumps (13) into the through holes (52), the semiconductor chip (1) is attached to the film carrier (5) using an adhesive (6). A semiconductor chip mounting method characterized by adhesion to a semiconductor chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2062591A JPH04259232A (en) | 1991-02-14 | 1991-02-14 | Method for mounting semiconductor chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2062591A JPH04259232A (en) | 1991-02-14 | 1991-02-14 | Method for mounting semiconductor chip |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04259232A true JPH04259232A (en) | 1992-09-14 |
Family
ID=12032424
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2062591A Withdrawn JPH04259232A (en) | 1991-02-14 | 1991-02-14 | Method for mounting semiconductor chip |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04259232A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE4446471A1 (en) * | 1994-12-23 | 1996-06-27 | Fraunhofer Ges Forschung | Chip contacting method and electronic circuit produced therewith |
-
1991
- 1991-02-14 JP JP2062591A patent/JPH04259232A/en not_active Withdrawn
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE4446471A1 (en) * | 1994-12-23 | 1996-06-27 | Fraunhofer Ges Forschung | Chip contacting method and electronic circuit produced therewith |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A300 | Application deemed to be withdrawn because no request for examination was validly filed |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 19980514 |