JP2823242B2 - The film carrier - Google Patents

The film carrier

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Publication number
JP2823242B2
JP2823242B2 JP1145788A JP14578889A JP2823242B2 JP 2823242 B2 JP2823242 B2 JP 2823242B2 JP 1145788 A JP1145788 A JP 1145788A JP 14578889 A JP14578889 A JP 14578889A JP 2823242 B2 JP2823242 B2 JP 2823242B2
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Prior art keywords
circuit pattern
internal circuit
film
carrier
semiconductor element
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JP1145788A
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Japanese (ja)
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JPH0311646A (en
Inventor
則雄 和田
克哉 深瀬
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新光電気工業株式会社
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Priority to JP1145788A priority Critical patent/JP2823242B2/en
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Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明はエリアTABと称されるTAB(Tape Automated B BACKGROUND OF THE INVENTION (FIELD OF THE INVENTION) The present invention TAB is referred to as area TAB (Tape Automated B
onding)用に用いられるフィルムキャリアに関する。 onding) it relates to a film carrier used for.

(従来の技術) エリアTAB(AREA−TAB)は第4図および第5図に示すように、ポリイミド等の耐熱性を有するキャリアフィルム12の片面側に外部接続用の回路パターン14が形成され、キャリアフィルム12の他面側に、スルーホールめっき層16を介して上記回路パターン14に導通する内部回路パターン18が形成されて、該内部回路パターン18上にバンプ26を介して半導体素子20が接続されるようになっている。 (Prior art) area TAB (AREA-TAB), as shown in FIGS. 4 and 5, the circuit pattern 14 for external connection on one side of the carrier film 12 having heat resistance such as polyimide is formed, on the other side of the carrier film 12, is the internal circuit pattern 18 is formed to be electrically connected to the circuit pattern 14 via the through hole plating layer 16, the semiconductor device 20 via the bumps 26 on the internal circuit pattern 18 is connected It is adapted to be.

このようにエリアTABは、外部接続用の回路パターン1 Thus area TAB, the circuit pattern 1 for external connection
4に重ねて内部回路パターン18を形成しうるため、複雑な回路パターンの設計が自由に行え、特に半導体素子の接続用電極の位置に合わせて内部回路パターンの設計することが可能となり、半導体素子の回路配置がTAB側の接続ピン位置に制約されることなく行えるので、半導体素子の回路配置の自由度が増し、一層の高集積化が可能となる利点を有している。 Order to be able to form an internal circuit pattern 18 superimposed on the 4, the design is free to do a complicated circuit pattern, it is possible to design the internal circuit patterns, especially according to the position of the connecting electrodes of the semiconductor element, a semiconductor element since the circuit arrangement of made without being restricted by the connection pin position of the TAB-side degree of freedom in circuit layout of the semiconductor device increases, has the advantage that it is possible to further highly integrated.

(発明が解決しようとする課題) しかしながら従来のエリアTABには次のような問題点がある。 There are the following problems in the (0006) However conventional area TAB.

すなわち、キャリアフィルム12とこれに搭載される半導体素子20とでは熱膨張係数に大きな差があるために、 That is, because of the large difference in thermal expansion coefficient between the carrier film 12 and the semiconductor device 20 mounted thereto,
高温で半導体素子20がキャリアフィルム12の内部回路パターン18上に接続されたのち、両者の熱収縮の差異による応力、および半導体素子20の発熱冷却の際に、半導体素子20とキャリアフィルム12との熱膨張係数の差によって発生する応力が半導体素子20と内部回路パターン18の接合部であるバンプに集中し、接合部の剥がれが生じ、 After the semiconductor element 20 is connected on the internal circuit pattern 18 of the carrier film 12 at a high temperature, stress due to the difference of both thermal contraction, and the time of heating the cooling of the semiconductor device 20, the semiconductor element 20 and the carrier film 12 stress generated by the difference in thermal expansion coefficients is concentrated on the bump is a junction of the semiconductor element 20 and the internal circuit pattern 18, peeling occurs in the joint,
接合不良が発生するなど、信頼上大きな問題点を有していた。 Such as bonding failure occurs, it had confidence on big problems.

また、半導体素子と内部回路パターンとの接合部が半導体素子の陰に隠れてしまうため、接合部の良、不良が目視できず、信頼性の上で問題となっていた。 Further, since the junction between the semiconductor element and the internal circuit pattern is hidden behind the semiconductor elements, good joints, failure can not be visually has been a problem in reliability.

そこで本発明は上記問題点を解消すべくなされたものであり、その目的とするところは、半導体素子と内部回路パターンとの接合が確実となり、またその良、不良も容易に確認でき、信頼性を高めることのできるフィルムキャリアを提供するにある。 The present invention has been made to solve the above problems, it is an object of the junction between the semiconductor element and the internal circuit pattern is ensured, also its good, also easily be confirmed poor reliability to provide a film carrier which can be enhanced.

(課題を解決するための手段) 上記目的を達成するため、本発明に係るフィルムキャリアでは、搭載面の周辺および内側の部位に複数の接続用電極が形成されている半導体素子が搭載されるフィルムキャリアであって、キャリアフィルムの片面側に外部接続用の回路パターンが接続され、キャリアフィルムの他面側に前記回路パターンに導通して、前記半導体素子の接続用電極に対応する位置に先端部が延出するよう配線される内部回路パターンが形成され、該内部回路パターン先端部上にバンプを介して半導体素子が搭載されるフィルムキャリアにおいて、前記半導体素子が接合される部位の内部回路パターンの各先端部に対応するキャリアフィルムのそれぞれの部位に透孔が形成され、該内部回路パターン先端部が前記キャリアフィルム To achieve (solutions for the problem) above object, in a film carrier according to the present invention, a semiconductor device in which a plurality of connecting electrodes to the site periphery and inside of the mounting surface is formed is mounted a film a carrier, a circuit pattern for external connection is connected to one side of the carrier film, and electrically connected to the circuit pattern on the other side of the carrier film, the tip portion at a position corresponding to the connection electrodes of the semiconductor element There is an internal circuit pattern is wired to extend is formed in a film carrier semiconductor devices via the bump to the internal circuit pattern tip on are mounted, the internal circuit pattern of a portion the semiconductor element is bonded holes in each of the portions of the carrier film corresponding to the tip end portion is formed, the carrier film is internal circuit pattern tip と分離されて前記透孔内に所要長さ突出することを特徴としている。 Is characterized in that protruding required length is separated into said through hole and.

(作用) 本発明によれば、半導体素子と接合される部位の内部回路パターンの各先端部がキャリアフィルムから完全に分離されて透孔内に所要長さフリー状態に突出しているから、搭載される半導体素子とキャリアフィルムの熱膨張係数の差などによる応力が当該部位によってほぼ完全に吸収され、接合部が剥離するという不具合が解消される。 According to (action) the present invention, since each distal end of the internal circuit pattern of the site to be bonded to the semiconductor device protrudes required length free state within hole is completely isolated from the carrier film, it is mounted that the stress caused by the difference between the semiconductor element and the thermal expansion coefficient of the carrier film is almost completely absorbed by the portion, the joint is eliminated disadvantageously peeled.

また、搭載される半導体素子に隠れてしまって外部から見にくい内側の部位の、半導体素子と内部回路パターン先端部の接合部の接続状態、例えば金−シリコン共晶合金によるバンプのメニスカス形状などを、前記各透孔から内部回路パターンに邪魔されることなく目視にて確認することができ、半導体素子と内部回路パターンの接合の良否を容易に判定でき、したがって信頼性の高いフィルムキャリアが提供できる。 Also, the site of the inner hard to see from the outside got hidden semiconductor element is mounted, the connection state of the joint portion of the semiconductor element and the internal circuit patterns tip, such as gold - and meniscus of the bumps of silicon eutectic alloy, wherein from the respective through holes it can be confirmed visually without being disturbed by the internal circuit pattern, the quality of the bonding of the semiconductor element and the internal circuit pattern easily determined, thus providing a highly reliable film carrier.

(実施例) 以下では本発明の好適な実施例を添付図面に基づいて詳細に説明する。 In EXAMPLES The following will be described in detail with reference to preferred embodiments of the present invention in the accompanying drawings.

第1図はTAB用フィルムキャリア10の部分平面図、第2図は部分断面図である。 Figure 1 is a partial plan view of a TAB film carrier 10, FIG. 2 is a partial cross-sectional view.

ポリイミド等の耐熱性を有するキャリアフィルム12の片面側に外部接続用の回路パターン14が形成され、キャリアフィルム12の他面側に、スルーホールめっき皮膜16 Circuit pattern 14 for external connection on one side of the carrier film 12 having heat resistance such as polyimide is formed, on the other side of the carrier film 12, through-hole plating film 16
を介して上記回路パターン14に導通する内部回路パターン18が形成されている点は従来と同じである。 That the internal circuit pattern 18 electrically connected to the circuit pattern 14 through the formed are the same as the conventional.

なお、TAB用フィルムキャリア10に搭載される半導体素子20は、公知のように搭載面の周辺および内側の部位に複数の接続用電極が形成されている。 The semiconductor element 20 is mounted on the TAB film carrier 10, a plurality of connecting electrodes are formed in a portion near and inside the mounting surface in a known manner. そして、キャリアフィルム10の上部内部回路パターン18の各先端部は、 Each tip of the upper inner circuit patterns 18 of the carrier film 10,
この搭載すべき半導体素子20の搭載面に形成されている接続用電極に対応する位置まで延出するよう配線されているものである。 Are those wires to extend to a position corresponding to the connection electrodes formed on the mounting surface of the semiconductor element 20 to be this mounting.

本実施例で特徴とする点は、半導体素子20が接合される部位の内部回路パターン18の各先端部に対応するキャリアフィルム12のそれぞれの部分に透孔22が形成されている点にある。 Point, wherein in this embodiment is that the through hole 22 is formed in each of the portions of the carrier film 12 on which the semiconductor element 20 correspond to the respective distal end portions of the internal circuit pattern 18 of the site to be bonded. したがって、内部回路パターン18の各先端部はそれぞれ透孔22内に所要長さ突出し、キャリアフィルム12とは離れた状態にある。 Therefore, the distal end portion of the internal circuit pattern 18 required length protrude respectively in the through hole 22 in a state apart from the carrier film 12.

内部回路パターン18の先端部は、半導体素子20との接続エリアを広く確保するためにランド24に形成するとよい。 Tip of the internal circuit pattern 18 may be formed on the land 24 in order to secure a wide connection area of ​​the semiconductor element 20.

また内部回路パターン18先端部は第2図に明確なように、ランド24がキャリアフィルム12面からはさらに外方に離反するように中途において曲折されている。 The internal circuit pattern 18 tip so clear in Figure 2, the land 24 is bent in the middle so further away outwardly from the 12 surface carrier film.

上記のTAB用フィルムキャリア10を形成するには、まずキャリアフィルム12に上記の透孔22およびその他の必要な透孔などを打ち抜き、しかる後、該キャリアフィルム上に接着剤により銅箔を接着して所要のエッチング加工を施して回路パターン14、内部回路パターン18を形成するか、あるいはキャリアフィルム12上に蒸着もしくはスパッタリングにより銅層を形成し、この銅層をエッチング加工して回路パターン14、内部回路パターン18に形成してのち、上記透孔22等をキャリアフィルム12をエッチング加工することによって形成するとよい。 To form the TAB film carrier 10 described above, first punching and said through holes 22 and other necessary holes on the carrier film 12, and thereafter, bonding the copper foil with an adhesive on the carrier film the circuit pattern 14 is subjected to required etching Te, or to form an internal circuit pattern 18, or a copper layer was formed by vapor deposition or sputtering on the carrier film 12, the circuit pattern 14 of the copper layer by etching, internal later formed on the circuit pattern 18, may the through hole 22 or the like formed by the carrier film 12 are etched. なおスルーホールめっき皮膜16は通常のごとく無電解めっきおよび電解めっきによって形成する。 Incidentally through-hole plating film 16 is formed by conventional electroless plating and electrolytic plating as described.

上記のように構成されているので、半導体素子20を半導体素子20に形成されているバンプ26によってランド24 Which is configured as described above, the land 24 by the bumps 26 formed of the semiconductor element 20 to the semiconductor element 20
上に接合して搭載することができる。 It can be mounted by bonding to the above.

なお、バンプ26は、第3図に示すように内部回路パターン18先端部のランド24上にあらかじめ形成しておいてもよい。 Incidentally, the bumps 26 may be preliminarily formed on the land 24 of the internal circuit pattern 18 tip as shown in Figure 3.

上記のように、半導体素子20と接合される内部回路パターン18の先端部はキャリアフィルム12とは離れた状態にあるので、半導体素子20とキャリアフィルム12の熱膨張係数の差などによって発生する応力は内部回路パターン18の先端部によって吸収され、したがって半導体素子 As described above, the tip portion of the internal circuit patterns 18 to be bonded to the semiconductor element 20 is in a state away from the carrier film 12, caused by such difference in thermal expansion coefficient of the semiconductor element 20 and the carrier film 12 Stress It is absorbed by the tip portion of the internal circuit pattern 18, thus the semiconductor device
20と内部回路パターン18先端部の接合部への応力集中を緩和でき、該接合部の剥離という不具合を解消できる。 20 and the internal circuit pattern 18 can reduce stress concentration on the joint portion of the distal end portion, it can be eliminated a problem that peeling of the joint portion.

上記のように内部回路パターン18の先端部を曲折させることで応力緩衝部分が形成されるので、より応力集中を回避できるが、曲折せずともキャリアフィルム12に対して離れた状態になっていればよい。 Since the stress buffer portions by causing bent tip portion of the internal circuit pattern 18 is formed as described above, it can be avoided more stress concentration, if in a state apart against the carrier film 12 without bending Bayoi.

また上記のように内部回路パターン18の各先端部に対応するキャリアフィルム12のそれぞれの部分に透孔22が形成されているので、該透孔22から接合部の接続状態、 Since the through hole 22 to the respective portions of the carrier film 12 corresponding to the respective distal end portions of the internal circuit pattern 18 as described above is formed, the joint portion from the transparent hole 22 connected state,
例えば金−シリコン共晶合金によるバンプ26のメニスカス形状などを確認することができ、半導体素子20と内部回路パターン18の接合の良否を目視にて容易に判定でき、一層信頼性を高めることができる。 Such as gold - like meniscus of the bumps 26 by the silicon eutectic alloy can be confirmed, easily determine the quality of the bonding of the semiconductor element 20 and the internal circuit pattern 18 visually, it is possible to further enhance a reliability .

以上本発明につき好適な実施例を挙げて種々説明したが、本発明はこの実施例に限定されるものではなく、発明の精神を逸脱しない範囲内で多くの改変を施し得るのはもちろんである。 Has been variously described as a preferred embodiment per the present invention above, the present invention is not limited to this embodiment, it is of course may subjected to many modifications without departing from the scope and spirit of the invention .

(発明の効果) 以上のように、本発明によれば、半導体素子と接合される部位の内部回路パターンの各先端部がキャリアフィルムから完全に分離されて透孔内に所要長さフリー状態に突出しているから、搭載される半導体素子とキャリアフィルムの熱膨張係数の差などによる応力が当該部位によってほぼ完全に吸収され、接合部が剥離するという不具合が解消される。 As above (Effect of the Invention) According to the present invention, the required length free state completely separated by the through hole from the tip carrier film of the internal circuit pattern of the site to be bonded to the semiconductor element since projects, stress due to difference in thermal expansion coefficient of the semiconductor element and the carrier film mounted is almost completely absorbed by the portion, the junction is a disadvantage that peeling is eliminated.

また、搭載される半導体素子に隠れてしまって外部から見にくい内側の部位の、半導体素子と内部回路パターン先端部の接合部の接続状態、例えば金−シリコン共晶合金によるバンプのメニスカス形状などを、前記各透孔から内部回路パターンに邪魔されることなく目視にて確認することができ、半導体素子と内部回路パターンの接合の良否を容易に判定でき、したがって信頼性の高いフィルムキャリアが提供できる。 Also, the site of the inner hard to see from the outside got hidden semiconductor element is mounted, the connection state of the joint portion of the semiconductor element and the internal circuit patterns tip, such as gold - and meniscus of the bumps of silicon eutectic alloy, wherein from the respective through holes it can be confirmed visually without being disturbed by the internal circuit pattern, the quality of the bonding of the semiconductor element and the internal circuit pattern easily determined, thus providing a highly reliable film carrier.

【図面の簡単な説明】 BRIEF DESCRIPTION OF THE DRAWINGS

第1図は本発明に係るTAB用のフィルムキャリアの一例を示す部分平面図、第2図はその部分断面図、第3図はバンプを内部回路パターン側に形成した実施例の部分断面図を示す。 Partial plan view showing an example of a film carrier for TAB according to Figure 1 the present invention, Figure 2 is a partial cross-sectional view, a partial cross-sectional view of Figure 3 is performed to form the bumps on the internal circuit pattern side Example show. 第4図は従来のTAB用のフィルムキャリアの平面図、第5図はその部分断面図を示す。 Figure 4 is a plan view of a film carrier for conventional TAB, Fig. 5 shows the partial cross-sectional view. 10……フィルムキャリア、12……キャリアフィルム、14 10 ...... film career, 12 ...... carrier film, 14
……回路パターン、18……内部回路パターン、20……半導体素子、22……透孔、26……バンプ。 ...... circuit pattern, 18 ...... internal circuit pattern, 20 ...... semiconductor device, 22 ...... holes, 26 ...... bumps.

フロントページの続き (56)参考文献 特開 昭60−154536(JP,A) 特開 昭56−26448(JP,A) 特開 昭64−4037(JP,A) 実開 昭63−167733(JP,U) 実開 昭62−112144(JP,U) (58)調査した分野(Int.Cl. 6 ,DB名) H01L 21/60 311 Front page of the continuation (56) Reference Patent Sho 60-154536 (JP, A) JP Akira 56-26448 (JP, A) JP Akira 64-4037 (JP, A) JitsuHiraku Akira 63-167733 (JP , U) JitsuHiraku Akira 62-112144 (JP, U) (58 ) investigated the field (Int.Cl. 6, DB name) H01L 21/60 311

Claims (1)

    (57)【特許請求の範囲】 (57) [the claims]
  1. 【請求項1】搭載面の周辺および内側の部位に複数の接続用電極が形成されている半導体素子が搭載されるフィルムキャリアであって、キャリアフィルムの片面側に外部接続用の回路パターンが形成され、キャリアフィルムの他面側に前記回路パターンに導通して、前記半導体素子の接続用電極に対応する位置に先端部が延出するよう配線される内部回路パターンが形成され、該内部回路パターン先端部上にバンプを介して半導体素子が搭載されるフィルムキャリアにおいて、 前記半導体素子が接合される部位の内部回路パターンの各先端部に対応するキャリアフィルムのそれぞれの部位に透孔が形成され、該内部回路パターン先端部が前記キャリアフィルムと分離されて前記透孔内に所要長さ突出することを特徴とするフィルムキャリア。 1. A film carrier semiconductor device in which a plurality of connecting electrodes to the site periphery and inside of the mounting surface is formed is mounted, the circuit pattern for external connection on one side of the carrier film is formed is, conducts to the circuit pattern on the other side of the carrier film, the internal circuit pattern tip position corresponding to the connection electrodes of the semiconductor element is wired to extend is formed, the internal circuit pattern in the film carrier semiconductor device via a bump on the tip it is mounted, through holes are formed in respective portions of the carrier film the semiconductor element corresponding to each tip of the internal circuit pattern of the site to be joined, film carrier internal circuit pattern tip and wherein the projecting required length on said carrier film and separated by said through hole.
JP1145788A 1989-06-08 1989-06-08 The film carrier Expired - Lifetime JP2823242B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1145788A JP2823242B2 (en) 1989-06-08 1989-06-08 The film carrier

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1145788A JP2823242B2 (en) 1989-06-08 1989-06-08 The film carrier

Publications (2)

Publication Number Publication Date
JPH0311646A JPH0311646A (en) 1991-01-18
JP2823242B2 true JP2823242B2 (en) 1998-11-11

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JP1145788A Expired - Lifetime JP2823242B2 (en) 1989-06-08 1989-06-08 The film carrier

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Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2673043B1 (en) * 1991-02-20 1997-07-04 Telecommunications Sa System of electric components, an interconnection and a base network.
JP2757594B2 (en) * 1991-07-17 1998-05-25 日立電線株式会社 Film carrier device
JP2764518B2 (en) * 1993-04-23 1998-06-11 ローム株式会社 The carrier tape and tape carrier package using the same for Tab
JP2833996B2 (en) * 1994-05-25 1998-12-09 日本電気株式会社 Flexible film and a semiconductor device having this

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5626448A (en) * 1979-08-13 1981-03-14 Chiyou Lsi Gijutsu Kenkyu Kumiai Semiconductor device
JPS60154536A (en) * 1984-01-24 1985-08-14 Toshiba Corp Wiring process of integrated circuit element
JPS62112144U (en) * 1985-12-28 1987-07-17
JPS63167733U (en) * 1987-04-20 1988-11-01

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