JP2001035997A - Semiconductor device and manufacture therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device responsive to a reduction in thickness, size and pitch, and to be fabricated in a stable process. SOLUTION: A semiconductor device has a wiring board (top side) 40 and a wiring board (bottom side) 40 whose obverse surface 41a is opposed to the reverse surface 41b of the wiring board (top side) 40. The total sum of the thicknesses of connecting land 44, plating layer 46, and soldering layer 47 of the wiring board (top side) 40 and the thicknesses of connecting land 44, plating layer 46, and soldering layer 47 of the wiring board (bottom side) 40 is determined such that the gap between the semiconductor element 50 of the wiring board (top side) 40 and the wiring board (bottom side) 40 is a predetermined value.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a semiconductor device suitable for stacking and connecting semiconductor packages and a method of manufacturing the same.

[0002]

2. Description of the Related Art In recent years, a small memory card equipped with a flash memory has been rapidly expanding its market for portable information devices such as digital still cameras and portable information terminals. In particular, in the field of digital cameras, it is already becoming mainstream, and is trying to solidify its position as an alternative to MD and floppy (registered trademark) disks.

[0003] Against this background, there is a need for a small memory card composed of only a flash memory to have a larger recording capacity, a smaller size, a lighter weight, and a lower cost. The structure is considered.

In general, a method of soldering a thin mold package such as TSOP to a base substrate, and a method of directly connecting a bare chip to a base substrate by wire bonding, flip chip mounting, or the like are used. However, since the capacity that can be mounted in the same area is determined by the chip size, in order to further increase the capacity,
It is necessary to consider a mounting structure in which chips are stacked three-dimensionally.

FIG. 7 shows a semiconductor device 10 having a conventional stacked mounting structure in which, for example, four semiconductor elements packaged by a so-called TAB mounting method are stacked and connected to a base substrate.

The semiconductor device 10 is formed by bonding a semiconductor element 13 to a predetermined portion of a wiring pattern 12 made of copper or the like formed on a wiring substrate 11 made of polyimide or the like by a thermocompression bonding method, an ultrasonic method, or the like. 14. Next, sealing is performed with a resin 15 such as epoxy so as to cover the surface and side surfaces of the semiconductor element 13. After each of the four semiconductor elements 13 is packaged in the same manner, the four packages are respectively placed on predetermined connection lands 17 of the base substrate 16, and the leads 18 for connection to the outside are made of solder or the like. The connection is performed sequentially or simultaneously by the connection member 19.

Here, the four packages are connected to the base substrate 1.
6, it is necessary to form the connection leads 18. At this time, since it is necessary to adjust the height to be arranged, each of them must be formed into a different shape.

[0008] Therefore, in the case of stacking and connecting four, four different forming dies are prepared, and since four types of packages are formed after forming, process management is difficult and cost increases. There was a problem of doing.

Further, when memory ICs are stacked and connected, all the terminals except the chip select terminal are common terminals. Therefore, as shown in FIG.
Will be connected. When arranged in such a manner, connection failure due to misalignment or the like is likely to occur,
There was a problem that the yield was reduced. In order to improve the yield, there is also a method of connecting each of the connection leads 18 to the base substrate 16 by shifting them. In this case, since the four connection leads 18 are arranged side by side, the mounting area is 4 This makes it difficult to cope with a narrow pitch.

Further, since a space for forming the connection lead 18 is required, it is difficult to cope with miniaturization.

On the other hand, as a method corresponding to the miniaturization and narrowing of the pitch as described above, a method of connecting the respective packages via bumps without using connection leads is used. FIG. 8 shows a semiconductor device 2 having a structure in which an IC chip is connected to a thin printed circuit board by a flip chip method.
FIG.

In a semiconductor device 20, a semiconductor element 23 is flip-chip connected to a predetermined portion of a wiring pattern 22 made of copper or the like formed on a wiring board 21 made of polyimide or the like via a bump 24 made of gold or the like. Next, sealing is performed with a resin 25 such as epoxy so as to cover the gap between the semiconductor element 23 and the wiring board 22 and the side surface of the semiconductor element 23. After packaging the four semiconductor elements 23 in the same manner,
Are connected to the predetermined connection lands 2 of the base substrate 26.
7, each of which is disposed on a connection member 28 such as a solder ball, and is connected to each connection land 21 a formed on both surfaces of the wiring board 21 by a reflow method, a thermocompression bonding method, or the like. It is.

As described above, for example, in the case of connecting the respective packages by solder, there are a method of supplying solder, a method of mounting solder balls, and a method of forming a solder paste by printing. In either case, melting the solder once by reflow or the like and forming it into a solder bump shape before connecting ensures the stability of the process.

However, once passing through a reflow furnace, there has been a problem that the subsequent process stability and reliability are adversely affected, such as damage to a connection portion of a semiconductor element and warpage of a wiring substrate.

[0015]

In the above-described conventional semiconductor device and the method of manufacturing the same, it is necessary to change the shape of the package to be laminated for each layer, so that process management is difficult. However, there is a problem that it is difficult to cope with small-sized and narrow pitch.

Further, in the solder bump connection method, since it is necessary to pass through a reflow furnace, damage to a connection portion of a semiconductor element and warpage of a wiring board adversely affect the subsequent process stability and reliability. There was a problem.

Accordingly, the present invention provides a semiconductor device and a method of manufacturing a semiconductor device which can cope with thinning, miniaturization and narrow pitch and can be manufactured by a stable process.

[0018]

In order to solve the above-mentioned problems and achieve the object, a semiconductor device according to the present invention is configured as follows.

(1) A first wiring board is provided, and a second wiring board is disposed on the back surface of the first substrate with its front surface facing the first wiring board. A wiring pattern formed on the surface, a first semiconductor element connected to the wiring pattern and disposed on the back surface side, and a first connection portion formed on the front surface side and connected to the outside. A second connection portion formed on the back surface side and provided for connection to the outside, wherein the second wiring board has a wiring pattern formed on at least one surface and a wiring pattern connected to the wiring pattern. A second semiconductor element disposed on the back surface side, a third connection portion formed on the front surface side for connection to the outside, and a third connection portion formed on the back surface side for connection to the outside. And the thickness of the second connection part and the third connection part. The total thickness is formed to have a predetermined distance between the first semiconductor element and the second wiring substrate and to be thicker than other wiring pattern portions. I do.

(2) In the semiconductor device described in the above (1), a third wiring substrate is disposed on the back surface of the second wiring substrate with its front surface facing the third wiring substrate. The third wiring board has a fifth connection portion formed on the front surface side and provided for connection to the outside, and the total of the thickness of the fourth connection portion and the thickness of the fifth connection portion is: The semiconductor device is characterized in that it is formed to have a predetermined distance between the second semiconductor element and the third wiring board.

(3) The semiconductor device according to (1), wherein the second connection portion is formed thicker than the first connection portion.

(4) The semiconductor device according to (1), wherein the wiring pattern is formed on a surface.

(5) The semiconductor device according to (1), wherein the connecting portion is formed by attaching a metal foil to the wiring board.

(6) The semiconductor device according to the above (1), wherein the connection portion is formed by plating a metal layer on the wiring pattern.

(7) In the semiconductor device described in (1), the connection portion is formed by plating a plurality of metal layers on the wiring pattern, and the outermost layer is a solder layer. There is a feature.

(8) The semiconductor device according to (1), wherein the connection portions are connected to each other via solder.

(9) The semiconductor device according to (1), wherein the connecting portions are connected to each other via an anisotropic conductor.

(10) The semiconductor device according to (1), wherein the connecting portions are connected by pressure welding.

(11) A first semiconductor element mounting step of mounting a semiconductor element on the back side of the first wiring board, a second semiconductor element mounting step of mounting a semiconductor element on the back side of the second wiring board, The first wiring board provided on the back surface of the first wiring board
And a second portion provided on the surface of the second wiring board.
A positioning step of positioning the connection portion so as to face the connection portion,
A joining step of joining the first connection portion and the second connection portion.

(12) The semiconductor device is characterized in that a semiconductor device having a wiring pattern having a thickness different between a land portion contributing to connection and another wiring pattern portion contributing to power distribution is stacked. Device manufacturing method.

As a result of taking the above measures, the connection portion for making the connection between the wiring boards is formed thick, so that the lamination connection can be performed by a simple process without newly forming a bump or the like. Further, the thickness can be reduced as compared with a case where a bump or the like is newly added. Therefore, it is possible to cope with miniaturization and narrowing of the pitch, and it is possible to manufacture in a stable process without lowering the yield.

[0032]

FIG. 1 is a sectional view showing a semiconductor device 30 according to a first embodiment of the present invention. FIGS. 2A and 2B are essential figures. It is sectional drawing which shows a part.

As shown in FIG. 1, the semiconductor device 30 has four wiring boards (a first wiring board and a second wiring board) 40.
The layers and the base substrate (third wiring substrate) 60 are stacked and arranged.

The wiring board 40 includes a board member 41 made of, for example, a polyimide material having a thickness of 25 μm. In FIG. 1, reference numeral 41a denotes the front surface of the substrate member 41, and 41b denotes the back surface. On the back surface 41b of the substrate member 41, a wiring pattern 42 of, for example, copper having a thickness of 18 μm is formed. Further, connection lands 43 and 44 having a diameter of 500 μm and provided for connection to the outside are formed on the front surface 41 a and the back surface 41 b of the substrate member 41, respectively.
The connection lands 43 are formed at opposing positions on both sides of the substrate member 41 via the through holes 45.

On a part of the connection lands 43 and 44, for example, a plating film 4 made of copper or nickel having a thickness of 20 to 40 μm is formed.
6 is formed by plating or the like. Further, as shown in FIG. 2A, a thickness of 10
A solder layer 47 of about 20 μm is formed by plating or the like.

The wiring pattern 42 has a thickness of, for example, 50 μm.
The semiconductor device 50 having a thickness of m is flip-chip connected via a bump 51 made of gold or the like having a height of 10 to 30 μm. In the flip-chip connection, an electrical connection is performed by a thermocompression bonding method at a temperature of, for example, 180 ° C., with an anisotropic conductive film 52 (ACF) in which conductive particles are dispersed and arranged in a resin therebetween. Even resin sealing is performed. In addition,
As the flip chip connection method, other methods such as a solder connection method and a crimp connection method may be used.

The base substrate 60 has a substrate member 61, and a surface 61a of the substrate member 61 has a diameter of 500 μm.
Connection land 62 having dimensions of
Are formed.

The semiconductor device 30 thus configured is
It is manufactured as follows. That is, the semiconductor element 50
Are mounted on the wiring pattern 42 of the substrate member 41, respectively.
Four wiring boards 40 are formed.

Next, as shown in FIG. 2A, the connection lands 44 of another wiring board (upper) 40 are positioned on the connection lands 43 of one wiring board (lower) 40. Then, from above the connection land 43 of the wiring board (upper side) 40,
For example, thermocompression bonding is performed using a heater tool at about 250 ° C., and as shown in FIG. 2B, the solder layer 47 is melted to make electrical connection. Similarly, four wiring boards 40
Join everything.

The connection lands 43 and 44, the plating layer 4
6 and the thickness of the solder layer 47
Is set so that a certain gap is formed between the semiconductor element 50 of the wiring board (upper) 40 and the substrate member 41 of the wiring board (lower) 40 in a state where the metal is melted and solidified. Even in the bonded state, the semiconductor element 50 and the wiring board 40 do not interfere.

The connection between the base substrate 60 and the four wiring boards 40 is made by plating solder in the same manner as the connection between the four wiring boards 40.

The semiconductor device 30 configured as described above
The total thickness of the semiconductor device 50 mounting portion is 80-100
μm, the gap between each wiring board 40 is 100 to 160 μm
m, and the semiconductor element 50
Are connected in a form in which is stored.

Connection land 4 formed on wiring board 40
Since the stacked connection is performed by using the connection lands 3 and 44, the thickness and the size can be reduced, and the connection lands 43 and 44 can be formed in an area.
Can be formed, it is possible to cope with a multi-pin semiconductor element.

Further, since the connection lands 43 and 44 for the lamination connection can be formed in the wiring board manufacturing process, there is no need to form connection bumps, and the mounting process can be simplified. Therefore, manufacturing at a high yield becomes possible.

(Second Embodiment) FIGS.
(B) shows a semiconductor device 7 according to the second embodiment of the present invention.
FIG. 4 is a cross-sectional view illustrating a main part of a wiring board 71 incorporated in the wiring board 71. In this figure, the same functional portions as those in FIGS. 1 and 2 are denoted by the same reference numerals, and detailed description thereof will be omitted.

Only on the connection lands 44 formed on the back surface 41b of the substrate member 41, for example, copper, nickel, or the like having a thickness of 40 to 80 μm is partially plated by plating or the like.
Form 2 Further, the partially formed plating layer 7
A solder layer 73 having a thickness of 10 to 20 μm is formed on the second and connection lands 43 by a plating method or the like.

The wiring boards 71 having such a structure are stacked, and the solder of the solder layer 73 is melted by thermocompression bonding, and the connection lands 43 and 44 are melted by the melted solder.
The connection is made electrically.

In the semiconductor device 70 thus configured, in the semiconductor device 70 according to the second embodiment, the plating layers 72 are formed only on the connection lands 44 on the back surface 41b, so that each wiring board 71 The dimension of the gap between them is the same as that of the semiconductor device 30, but the amount of protrusion of the connection land 43 on the back surface of the semiconductor package arranged at the top can be minimized. The semiconductor device 30 can be made thinner and smaller than the semiconductor device 30 according to the first embodiment.

(Third Embodiment) FIG. 4 is a sectional view showing a main part of a wiring board 81 incorporated in a semiconductor device 80 according to a third embodiment of the present invention. In this figure, the same functional portions as those in FIGS. 1 and 2 are denoted by the same reference numerals, and detailed description thereof will be omitted.

On the connection lands 43 and 44, for example, a thickness of 30
A plating layer 82 is formed by partially forming copper, nickel, or the like of about 50 μm by plating or the like. After that, using a paste-like or film-like anisotropic conductive material 83 in which conductive particles 83b such as nickel or gold are dispersed and arranged in a resin 83a such as epoxy, each connection land 4 is formed by thermocompression bonding.
Connect between 3 and 44. In the semiconductor device 80 according to the third embodiment, the same effects as those of the semiconductor device 30 according to the above-described first embodiment are obtained, and the solder plating process becomes unnecessary, and the process is further simplified. You.

(Fourth Embodiment) FIG. 5 is a sectional view showing a main part of a wiring board 91 incorporated in a semiconductor device 90 according to a fourth embodiment of the present invention. In this figure, the same functional portions as those in FIGS. 1 and 2 are denoted by the same reference numerals, and detailed description thereof will be omitted.

For example, a thickness of 30
A plating layer 92 is formed by partially forming copper, nickel, or the like having a thickness of about 50 μm by a plating method or the like. Then, after the plating layers 92 are brought into contact with each other, the plating layers 92 are brought into pressure contact with each other by the shrinkage force of a resin 93 such as epoxy, thereby electrically connecting the plating layers 92 to each other.

Semiconductor device 90 according to the fourth embodiment.
Also, the same effects as those of the semiconductor device 80 according to the third embodiment described above can be obtained. (Fifth Embodiment) FIG. 6 is a sectional view showing a semiconductor device 100 according to a fifth embodiment of the present invention.

In the semiconductor device 100, four layers of wiring boards (first and second wiring boards) 110 and a base substrate (third wiring board) 120 are stacked.

The wiring substrate 110 has a substrate member 111 made of, for example, a polyimide material having a thickness of 25 μm. In FIG. 6, reference numeral 111a denotes the surface of the substrate member 111;
Indicates the back surface. On the surface 111a of the substrate member 111, for example, a wiring pattern 112 such as a 18-μm-thick copper foil
Are formed. Also, the surface 111 of the substrate member 111
a and a back surface 111b having a diameter of 500 μm and a connection land 11 made of copper foil or the like to be connected to the outside.
3, 114 are formed respectively.

The connection lands 113 and 114 are formed at opposing positions on both sides of the substrate member 111 via the through holes 115. The connection land 113 is formed to have a thickness of, for example, 25 μm, and the connection land 114 is formed to have a thickness of, for example, 35 μm. Further, a thickness of 1
A solder layer 116 having a thickness of 0 to 20 μm is formed by plating or the like.

The wiring pattern 112 has a thickness of, for example, 50
μm thin semiconductor element 120 has a height of 10 to 30 μm
Flip chip connection via a bump 121 made of gold or the like. In the flip-chip connection, an electrical connection is performed by a thermocompression bonding method at a temperature of, for example, 180 ° C. with an anisotropic conductive film 122 (ACF) in which conductive particles are dispersed and arranged in a resin interposed therebetween. Even resin sealing is performed.
The flip-chip connection method may be another method such as a solder connection method or a crimp connection method.

The base substrate 130 has a substrate member 131, and a surface 131 a of the substrate member 131 has a diameter of 5 mm.
A connection land 132 having a size of 00 μm and provided for connection to the outside is formed.

The semiconductor device 100 thus configured
Is manufactured as follows. That is, the substrate member 1
11, a wiring pattern 112 and a connection land 113 are formed on the front surface 111a, and the connection land 11 is formed on the back surface 111b.
4 is formed on the entire surface.

Next, only the portion where the wiring pattern 112 for connecting the semiconductor element 120 is formed is removed from the back surface 111b side of the substrate member 111 by using a laser or the like to form an opening 111c. And this opening 1
11c, the bump 121 of the semiconductor element 120 is inserted,
Electrical connection is made to the wiring pattern 112. Similarly, another wiring board 110 is formed.

Next, the connection lands 114 of another wiring board (upper) 110 are positioned on the connection lands 113 of one wiring board (lower) 110. Then, for example, about 250 m from the connection land 113 of the wiring board (upper) 110
Thermocompression bonding using a heater tool of
16 is melted to make an electrical connection. Similarly, all four wiring boards 40 are joined.

The thicknesses of the connection lands 113 and 114 and the solder layer 116 are such that the semiconductor element 120 of the wiring board (upper) 110 and the wiring board (lower) in a state where the solder layer 116 is melted and solidified. 110 substrate member 111
Is set so that a constant gap is formed between the semiconductor element 120 and the wiring board 110 even in the joined state.

The base substrate 130 and the four wiring substrates 110
The connection is made by plating solder in the same manner as the connection between the four wiring boards 110.

As described above, according to the semiconductor device 100 according to the fifth embodiment, the same effects as those of the semiconductor device 30 according to the above-described first embodiment can be obtained, and the connection lands 113 and 114 can be obtained. Since the foil-like copper that can be formed with a uniform thickness is attached, the thickness variation is small, and a stable stacked connection is possible.

The present invention is not limited to the above embodiment. In the above-described embodiment, the semiconductor element is flip-chip connected. However, the semiconductor element may be die-bonded to a substrate member and connected to a wiring pattern via a wire. In addition, it goes without saying that various modifications can be made without departing from the spirit of the present invention.

[0066]

According to the present invention, since the connecting portion for connecting the wiring boards is formed thick, the stacked connection can be performed by a simple process without newly forming a bump or the like. . Also, compared to adding a new bump, etc.
Thinning is possible. Therefore, it is possible to cope with miniaturization and narrowing of the pitch, and it is possible to manufacture in a stable process without lowering the yield.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view illustrating a main part of the semiconductor device.

FIG. 3 is a sectional view showing a main part of a semiconductor device according to a second embodiment of the present invention.

FIG. 4 is a sectional view showing a main part of a semiconductor device according to a third embodiment of the present invention.

FIG. 5 is a sectional view showing a main part of a semiconductor device according to a fourth embodiment of the present invention.

FIG. 6 is a sectional view showing a semiconductor device according to a fifth embodiment of the present invention.

FIG. 7 is a cross-sectional view illustrating an example of a conventional semiconductor device.

FIG. 8 is a sectional view showing another example of a conventional semiconductor device.

[Explanation of symbols]

 30, 70, 80, 90, 100 ... semiconductor devices 40, 71, 81, 91, 110 ... wiring boards 42, 112 ... wiring patterns 43, 44, 113, 114 ... connection lands 46 ... plating films 47, 116 ... solder layers 50, 120: semiconductor element 60, 130: base substrate

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Masayuki Arakawa 3-3-9, Shimbashi, Minato-ku, Tokyo F-term in Toshiba Abu E Co., Ltd. 5E344 AA01 AA22 BB01 BB06 CC23 CD09 DD02 DD10 EE12

Claims (12)

[Claims] 1. A first wiring board, comprising: a first wiring board; and a second wiring board disposed on a back surface of the first board with its front surface facing the first wiring board, wherein the first wiring board has at least one surface. A first semiconductor element connected to the wiring pattern and disposed on the back side, and a first connection portion formed on the front side and provided for connection to the outside; A second connection portion formed on the back surface side for connection to the outside; and the second wiring board is connected to the wiring pattern formed on at least one surface and the wiring pattern. In addition, a second semiconductor element disposed on the back surface side, a third connection portion formed on the front surface side for connection to the outside, and a fourth connection portion formed on the back surface side for connection to the outside And a thickness of the second connection portion and a thickness of the third connection portion. Wherein the semiconductor device is formed to have a dimension having a predetermined distance between the first semiconductor element and the second wiring board, and to be thicker than other wiring pattern portions. apparatus. 2. A third wiring board, having a front surface facing the third wiring board, is disposed on the back surface of the second wiring board, and the third wiring board is formed on the front surface side and connected to the outside. A fifth connection portion provided for connection, wherein the sum of the thickness of the fourth connection portion and the thickness of the fifth connection portion is equal to the second semiconductor element and the third wiring board; The semiconductor device according to claim 1, wherein the semiconductor device is formed to have a dimension having a predetermined interval between the semiconductor devices. 3. The semiconductor device according to claim 1, wherein said second connection part is formed thicker than said first connection part. 4. The semiconductor device according to claim 1, wherein said wiring pattern is formed on a surface. 5. The semiconductor device according to claim 1, wherein said connection portion is formed by attaching a metal foil to said wiring board. 6. The semiconductor device according to claim 1, wherein the connection portion is formed by plating a metal layer on the wiring pattern. 7. The semiconductor device according to claim 1, wherein the connecting portion is formed by plating a plurality of metal layers on the wiring pattern, and the outermost layer is a solder layer. 8. The semiconductor device according to claim 1, wherein said connecting portions are connected to each other via solder. 9. The semiconductor device according to claim 1, wherein said connecting portions are connected via an anisotropic conductor. 10. The semiconductor device according to claim 1, wherein said connecting portions are connected by pressure welding. 11. A first semiconductor element mounting step of mounting a semiconductor element on a back side of a first wiring board; a second semiconductor element mounting step of mounting a semiconductor element on a back side of a second wiring board; A positioning step of positioning a first connection portion provided on the back surface of the first wiring board and a second connection portion provided on the front surface of the second wiring board so as to face each other; A method of manufacturing a semiconductor device, comprising: a joining step of joining a portion and the second connection portion. 12. A semiconductor device comprising a semiconductor device having a wiring pattern having a thickness different from that of a land portion contributing to connection and another wiring pattern portion contributing to power distribution. Manufacturing method.