JPH08213427A - Semiconductor chip and multi-chip semiconductor module - Google Patents

Abstract

PURPOSE: To provide a multi-chip semiconductor module in which the mounting density per unit volume can be enhanced and which has excellent response characteristics, low cost, small restrictions in chip design and product design with repair of a defective chip. CONSTITUTION: A semiconductor chip 16A is formed with a through hole 7 reaching the rear surface of an electrode pad 9 from the rear surface side of a substrate 1, and with a metal bump 10 protruding to the rear side via the hole 7 in contact with the rear surface of the pad 9. The chip 16A is provided in the state that stacked on another semiconductor chip 15A having an electrode pad 14 at the front side of a substrate 6. The metal bump 10 of the chip 16A is connected to the pad 14 of the chip 15A via an anisotropic conductive film 13 opposed to each other.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-chip semiconductor module having a structure in which a plurality of semiconductor chips are stacked. It also relates to a semiconductor chip used to construct such a multi-chip semiconductor module.

The multi-chip semiconductor module of the present invention is characterized in that the semiconductor chips are stacked one on the other.
This is different from a device in which semiconductor chips are arranged on both sides of a single lead frame. The multi-chip semiconductor module of the present invention is a so-called multi-chip semiconductor module, in which each semiconductor chip is formed as an individual chip by a wafer process, and a so-called wiring layer or interlayer insulating layer is sequentially laminated on one semiconductor substrate. It is different from a three-dimensional IC (integrated circuit).

[0003]

2. Description of the Related Art Multi-chip semiconductor modules are roughly classified into those in which semiconductor chips are arranged two-dimensionally, those in which semiconductor chips are stacked three-dimensionally, and those in which these are combined. It In addition, it is also classified according to how the electrodes of each semiconductor chip are connected.

A two-dimensionally arranged multi-chip semiconductor module is, for example, a COB in which electrodes of a semiconductor chip are directly connected to a printed board by wire bonding.
A (chip on board) type is known.
This COB method has been used for a long time in relatively inexpensive consumer products such as memory cards. Further, a semiconductor chip mounted once by a TAB (Tape Automated Bonding) system and its leads connected to a printed circuit board, a ceramic substrate, or a silicon substrate by soldering or alloy bonding has been put into practical use. It is also known that metal bumps made of solder, gold, nickel-copper, etc. are formed on the electrode pads of a semiconductor chip, and are connected by face-down bonding to a printed circuit board, a ceramic substrate, or a silicon substrate (flip chip method). There is. This flip-chip method is used in devices ranging from computer devices to consumer products such as memory cards (Japanese Patent Laid-Open No. 63-42157). Of course, there are many implementations by combining a plurality of these connection technologies (Japanese Patent Laid-Open No. 04-44256, etc.).

As a multi-chip semiconductor module having a three-dimensional array, a small-sized semiconductor chip is stacked on a large-sized semiconductor chip developed by N-CHIP (US), and an adhesive or the like is used. It is famous that the electrode pads of the chip are connected by wire bonding. There is also a stack of TCPs (tape carrier packages) and the leads of each TCP are connected to each other (Japanese Patent Laid-Open No. 01-309362,
02-134859). In addition, a semiconductor wafer having through holes provided on a semiconductor wafer is stacked, the through holes are filled with metal, and electrodes of respective chips are connected to each other (Japanese Patent Laid-Open No. 63-213943), or a metal is formed on the semiconductor wafer. There is one in which semiconductor wafers having through holes buried in are stacked and electrodes of each chip are connected by this metal (Japanese Patent Laid-Open No. 05-55454). Further, a proposal has been proposed in which some or all of these through holes are replaced with trenches (grooves) (Japanese Patent Laid-Open No. 05-4147).
8, JP-A-05-198738).

[0006]

The above conventional multi-chip semiconductor module has the following problems.

First of all, the two-dimensionally arranged multi-chip semiconductor module has a limit in the mounting density per unit area in any of the above methods. Even the flip-chip type, which has the highest density, does not reach the three-dimensional array type. In addition, since the wiring connected to the electrodes of the chip extends in the plane direction and becomes long, there is a problem that the response characteristics to high frequencies are not good.

Further, among the three-dimensionally arranged multi-chip semiconductor modules, those in which semiconductor chips are stacked and the electrodes of the upper and lower chips are connected to each other by wire bonding (above), a wire is used when a defective chip exists. There is a problem that it cannot be removed easily and repair (work such as replacement) of a defective chip cannot be performed. Further, since it is necessary to form an electrode pad at a position where wire bonding is possible, that is, at the periphery of the chip, restrictions on the chip design become large. Further, there is a problem that the mounting time becomes relatively long and the mounting cost becomes high as the number of wire connections increases.

Also, in the case where TCPs are stacked and the leads of each TCP are connected to each other (above), defective chips can be repaired, but since each semiconductor chip is mounted on the TCP once, the mounting density becomes low, and There is a problem that the implementation cost is high. In addition, it is difficult to stack a plurality of TCPs of different sizes, which greatly limits product design.

Also, in the case of stacking semiconductor wafers and connecting the electrodes of the chips with the metal in the through holes or trenches (above ,,), since the through holes and trenches are filled with metal, the defective chips can be repaired. I can't. Further, since the laminated structure is formed by the wafer process, the wafer process is complicated and the chip cost is high. Moreover, there is no freedom to combine various types of semiconductor chips in the assembly process, which limits the product design.

Therefore, an object of the present invention is to increase the packaging density per unit volume, to have excellent response characteristics, to repair defective chips, to reduce the cost, and in terms of chip design and product design. An object of the present invention is to provide a multi-chip semiconductor module that can reduce the above restrictions. Another object is to provide a semiconductor chip suitable for forming such a multi-chip semiconductor module.

[0012]

In order to achieve the above object, a semiconductor chip according to claim 1 comprises a substrate and an electrode pad provided on a front surface side of the substrate, and the substrate is provided on the substrate. A through hole reaching from the back surface side to the back surface of the electrode pad is formed, and a metal bump that contacts the back surface of the electrode pad and projects to the back surface side of the substrate through the through hole is provided. .

A semiconductor chip according to a second aspect is
The semiconductor chip according to claim 1 is characterized in that an exposed surface of the metal bump on the back surface side of the substrate is covered with a plating layer made of a material having a melting point lower than that of the material of the metal bump.

According to a third aspect of the multi-chip semiconductor module, one semiconductor chip of the first or second aspect is stacked on another semiconductor chip having an electrode pad on the front surface side of the substrate. The metal bumps on the back surface side of the one semiconductor chip and the electrode pads on the front surface side of the semiconductor chip existing under the one semiconductor chip are opposed to each other via an anisotropic conductive film. It is characterized by being connected by.

Further, a multi-chip semiconductor module according to a fourth aspect is provided with the one semiconductor chip according to the second aspect in a state of being stacked on another semiconductor chip having an electrode pad on the front surface side of the substrate. The metal bump and the electrode pad are connected via the plating layer.

The multi-chip semiconductor module according to a fifth aspect is the multi-chip semiconductor module according to the fourth aspect, wherein the metal bump plating layer is formed on the surface of the electrode pad of the semiconductor chip existing on the lower side. A plating layer made of a material capable of forming an alloy with the above material is provided.

[0017]

The semiconductor chip according to the present invention has the electrode pads on the front surface side of the substrate and the metal bumps protruding on the back surface side of the substrate. Therefore, for example, by stacking this semiconductor chip on another semiconductor chip having an electrode pad on the front surface side of the substrate with an anisotropic conductive film interposed therebetween, the multi-chip semiconductor module according to claim 3 can be easily and easily manufactured. Composed. Further, a plurality of stacked semiconductor chips may be stacked on another semiconductor chip having an electrode pad on the front surface side of the substrate or a wiring substrate. Other combinations are possible.
As described above, according to this semiconductor chip, various types of multi-chip semiconductor modules can be easily and easily configured.

In the semiconductor chip of the second aspect, the exposed surface of the metal bump on the back surface side of the substrate is covered with a plating layer made of a material having a melting point lower than that of the material of the metal bump.
Therefore, for example, this semiconductor chip is stacked on another semiconductor chip having an electrode pad on the front surface side of the substrate,
By heating to a temperature at which the plating layer melts,
A multi-chip semiconductor module as claimed in claim 4 is simply and easily constructed. Further, a plurality of stacked semiconductor chips may be stacked on another semiconductor chip having an electrode pad on the front surface side of the substrate or a wiring substrate. Other combinations are possible. As described above, according to this semiconductor chip, various types of multi-chip semiconductor modules can be easily and easily configured.

Since the multi-chip semiconductor module of claim 3 is provided with the one semiconductor chip of claim 1 or claim 2 and another semiconductor chip in a stacked state, the semiconductor chips are two-dimensionally arranged. When arranging or once TC
The mounting density per unit volume is higher than that in the case of mounting on P. In addition, since the metal bumps are wirings that connect the electrodes of the chip to each other, the length of the wirings is shorter than that in the case where the wirings are provided in the plane direction, and the response characteristics to high frequencies are improved. Further, the connection between the metal bump of one semiconductor chip and the electrode pad of the underlying semiconductor chip can be released by melting the anisotropic conductive film used for the connection. Therefore, a defective chip can be easily repaired. Further, since the laminated structure is formed by the assembly process rather than the wafer process, the chip cost is reduced. Moreover, since the electrodes of the chips are bonded together by the metal bumps, the mounting time is shortened. Further, this multi-chip semiconductor module is constructed by directly stacking the semiconductor chips without mounting the semiconductor chips on the TCP once. Therefore, the chip cost and the mounting cost are reduced. Further, since wire bonding is not performed, the electrode pad may be provided in an arbitrary area in the chip, and there are few restrictions on the chip design. Moreover, since various types of semiconductor chips can be combined in the assembly process, restrictions on product design are reduced.

Since the multi-chip semiconductor module according to claim 4 is provided with one semiconductor chip according to claim 2 and another semiconductor chip in a stacked state, when the semiconductor chips are arranged two-dimensionally, The mounting density per unit volume is increased as compared with the case where the mounting is once performed on the TCP. In addition, since the metal bumps are wirings that connect the electrodes of the chip to each other, the length of the wirings is shorter than that in the case where the wirings are provided in the plane direction, and the response characteristics to high frequencies are improved. Further, by heating the semiconductor chip existing on the lower side from the back surface side to melt the plating layer covering the metal bump, the metal bump of the one semiconductor chip and the electrode pad of the semiconductor chip existing on the lower side. Can be disconnected. Therefore, a defective chip can be easily repaired. Further, since the laminated structure is formed by the assembly process rather than the wafer process, the chip cost is reduced. Moreover, since the electrodes of the chips are bonded together by the metal bumps, the mounting time is shortened. Further, this multi-chip semiconductor module is constructed by directly stacking the semiconductor chips without mounting the semiconductor chips on the TCP once. Therefore, the chip cost and the mounting cost are reduced. Further, since wire bonding is not performed, the electrode pad may be provided in an arbitrary area in the chip, and there are few restrictions on the chip design. Moreover, since various types of semiconductor chips can be combined in the assembly process, restrictions on product design are reduced.

According to a fifth aspect of the multi-chip semiconductor module, a plating layer made of a material capable of forming an alloy with the material of the plating layer of the metal bump is provided on the surface of the electrode pad of the semiconductor chip existing on the lower side. ing. Therefore, at the time of assembly, the plating layer of the metal bump of the one semiconductor chip and the plating layer of the electrode pad of the semiconductor chip existing on the lower side are brought into contact with each other and easily heated or pressed or both to connect. Is done.

[0022]

EXAMPLES The present invention will be described in detail below with reference to examples.

First, a semiconductor chip according to an embodiment of the present invention will be described.

FIG. 1 shows a manufacturing process of a semiconductor chip of an embodiment.

First, as shown in FIG.
An active element such as a MOS transistor (not shown) is formed on the surface side of the 5 μm silicon substrate 1 by a CMOS (complementary MOS) process, and the first element made of Al is formed.
The metal wiring layer 2, the interlayer insulating film 3, the second metal wiring layer 4, and the protective film 5 are formed. The numeral 9 indicates the electrode pad portion of the first metal wiring layer 2, and the numeral 41 indicates the electrode pad portion of the second metal wiring layer 4.

Next, as shown in FIG. 2B, the silicon substrate 1 is polished to a predetermined thickness, preferably 40 μm. As the polishing method, first, mechanical polishing is performed by a normal back surface polishing device (not shown) until the substrate 1 has a thickness of 200 μm, and then the front surface side of the substrate 1 is protected with wax 90 or the like. Then, the back side of the substrate 1 is further chemically etched by using KOH, NaOH, hydrofluoric nitric acid or the like. At this time, if the scribe line of the chip is also etched, it is not necessary to perform dicing during mounting.

Next, a photoresist 9 is formed on the back surface of the substrate 1.
1 is coated, exposed and developed to remove a portion of the photoresist 91 corresponding to the electrode pad 9 to form an opening 91a. Then, as shown in FIG. 3C, the substrate 1 is selectively etched using KOH, NaOH, hydrofluoric nitric acid, etc., and the substrate 1 is attached to the back surface of the electrode pads 9 and 9 from the back surface side of the substrate. Through holes 7,7
To form. At this time, the through holes 7, 7 are finished in a tapered shape in which the cross-sectional dimension gradually decreases from the back surface side to the front surface side. Here, when the opening 91a is formed so as to be located in the electrode pad 9, the area of the opening 91a becomes smaller than the area of the electrode pad 9, and when a through hole perpendicular to the substrate is formed, a metal bump to be formed later is formed. The area of the projecting portion is also small, and the contact area with electrodes of other chips, wiring boards, etc. is also small, and there is a possibility that an appropriate contact resistance cannot be obtained. In the present invention, the area of the contact portion can be optimized by making the opening of the through hole larger than the exposed portion of the electrode pad 9. Further, if the through hole is formed in a vertical shape, the area of the electrode pad 9 must be equal to or larger than the desired contact area in order to secure the contact area between the other electrode and the metal bump, which is suitable for miniaturization. Although not provided, the area of the electrode pad 9 can be reduced by forming the taper shape as in the present invention. It is also possible that the load is concentrated on a specific metal bump due to the variation in the thickness of the substrate or the variation in the height of the metal bump with respect to the pressure applied when the electrode is connected to another chip or the like.
Even when a load higher than usual is applied, the through hole has a taper, so that not only the electrode 9 but also the tapered surface can receive the load, and damage to the electrode 9 can be mitigated.

Next, as shown in FIG. 2 (d), after removal by peeling off the resist 91, by CVD (chemical vapor deposition) method or the like, made of SiO _2, SiN, or the like on the rear surface of the substrate 1 an insulating The film 8 is formed on the entire surface (including the inner wall of the through hole 7). The insulating film 8 serves as a protective film on the back surface of the chip. Then, the same figure
As shown in (e), the insulating film 8 is formed by dry etching.
A portion corresponding to the electrode pad 9 is removed to expose the back surface of the electrode pad 9.

As a method of forming a protective film on the back surface of the substrate 1, a resin such as photosensitive polyimide is coated on the back surface of the substrate 1, exposed and developed to remove only the portion corresponding to the electrode pad 9. There is also a way to do it.

Next, the substrate 1 in this state is dipped in an electroless plating solution of Zn to have a thickness of 0.3 on the back surface of the electrode pad 9.
˜0.5 μm Zn plating (not shown) is formed. By this treatment, the oxide film on the Al surface can be removed, and a clean Al surface can be secured at the Zn plating interface. After this, the same figure (f)
As shown in, the temperature of the substrate 1 in this state is 90 ° C., ph 4.
It is immersed in the Ni electroless plating solution No. 5 for 2 hours to grow the electroless Ni plating 10 on the back surface of the electrode pad 9. This makes it possible to form the Ni bump 10 that contacts the back surface of the electrode pad 9 and projects through the through hole 7 toward the back surface of the substrate 1 by 10 μm. Furthermore, the Ni bumps 10, 10
0.2 μm thick Au is formed on the exposed surface by electroless Au plating.
The plated layers 11 and 11 are formed. Ni as metal bump
Although it uses bumps, it can also be used as wiring,
It is possible to use a metal, such as gold, which does not deform when connected to other electrodes.

Finally, the protective wax 90 on the front surface side of the substrate 1 is removed to complete the semiconductor chip 16. The electrical test of the semiconductor chip 1 can be performed by a normal tester by bringing the prober into contact with the bumps 10, 10 (more precisely, the plating layers 11, 11) on the back surface side of the chip.

According to the semiconductor chip 16, various kinds of multi-chip semiconductor modules can be easily and easily constructed.

Next, a multi-chip semiconductor module according to an embodiment of the present invention will be described.

As shown in FIG. 2 (b), this multi-chip semiconductor module 20A comprises a semiconductor chip 16A and another type of semiconductor chip 15A in a stacked state.

The semiconductor chip 16A is the same as the semiconductor chip 16 shown in FIG. On the other hand, the semiconductor chip 15A
On the surface side of the silicon substrate 6, active elements such as MOS transistors (not shown) are formed, and electrode pads 14, 14 made of Al are formed. The electrode pads 14 and 14 are the Ni bumps 1 of the semiconductor chip 16A.
It is provided at a position corresponding to 0 and 10. A portion of the surface of the substrate 6 around the electrode pad 14 is covered with the protective film 12.

This multi-chip semiconductor module 20A
2A, first, an anisotropic conductive film 13 having a thermosetting resin as a base material is temporarily attached to the surface side of the semiconductor chip 15A so as to cover the electrode pads 14 and 14, as shown in FIG. To do. Next, the semiconductor chip 15A is placed on the stage 99.
Is placed, and the semiconductor chip 16A is moved above it. Then, the horizontal position of the semiconductor chip 16A is finely adjusted so that the Ni bumps 10, 10 projecting to the back surface side of the semiconductor chip 16A and the electrode pads 14, 1 of the semiconductor chip 15A.
4 are positioned so as to face each other. Then, the semiconductor chip 16A is moved downward to move the semiconductor chip 15A.
Press on A and perform main pressure bonding. The pressure bonding conditions are, for example, a pressure of 20 kg / cm ² , a temperature of 200 ° C., and a time of 20 seconds. As a result, as shown in FIG. 2B, the Ni bumps 10, 10 of the semiconductor chip 16A and the electrode pads 14, 14 of the semiconductor chip 15A are connected via the anisotropic conductive film 13. In this way, the assembly is easily performed.

After the assembly is completed, the prober is brought into contact with the external electrode pads 41, 41 of the semiconductor chip 15A to perform an electrical test. If any of the semiconductor chips is found to be defective as a result of the test, a repair solvent is injected between the semiconductor chips 16A and 15A to remove the anisotropic conductive film 1.
3 is peeled off and removed. Thereby, the semiconductor chip 16
The connection between the Ni bumps 10, 10 of A and the electrode pads 14, 14 of the semiconductor chip 15A is released. Therefore, the defective chip can be easily repaired.

Further, since the multi-chip semiconductor module 20A is provided with the semiconductor chips 16A and 15A in a stacked state, compared with the case where the semiconductor chips are arranged two-dimensionally or the case where the semiconductor chips are once mounted on the TCP. It is possible to increase the packaging density per unit volume. That is,
Since the semiconductor chip 16A is polished to a thickness of about 40 μm, the thickness after the semiconductor chips 16A and 15A are superposed can be made considerably thinner than that of the TCP superposed structure. Therefore, when this multi-chip semiconductor module is mounted and used in a product,
The product can be miniaturized.

The metal bumps 10 are electrodes 14 of the chip.
Since the wiring is formed by connecting the wirings to each other, the length of the wiring can be shortened and the response characteristics to high frequency can be improved as compared with the case where the wiring is provided in the plane direction.

Further, since the substrate material of the semiconductor chips 15A and 16A is silicon, even if the ambient temperature changes to some extent, thermal expansion, particularly distortion between the chips 15A and 16A due to linear expansion in the substrate surface direction occurs. Hateful. Therefore, the reliability of the connection can be improved as compared with the case of connecting the chips made of different substrate materials.

Further, since the laminated structure is formed by the assembly process instead of the wafer process, the chip cost can be reduced. Moreover, since the electrodes 14 of the chips are collectively bonded by the metal bumps 10 in the assembly process,
Mounting time can be shortened. In addition, this multi-chip semiconductor module 20A has a semiconductor chip
Each semiconductor chip 16A, 15 is not mounted on the CP.
It is constructed by directly stacking A. Therefore, the chip cost and the mounting cost can be reduced.

Further, since wire bonding is not performed in the assembly process, the electrode pad 14 may be provided in any area in the chip, and there are few restrictions on the chip design. Moreover, since various semiconductor chips can be combined in the assembly process, restrictions on product design can be reduced.

Next, a modified example 20B of the multi-chip semiconductor module will be described.

As shown in FIG. 3B, this multi-chip semiconductor module 20B includes a semiconductor chip 16B and
It is provided with another type of semiconductor chips 15B in a stacked state.

The semiconductor chip 16B is substantially the same as the semiconductor chip 16 shown in FIG. However, Ni bump 1
The only difference is that, on the exposed surfaces of 0 and 10, instead of the Au plating layers 11 and 11, solder plating layers 11B and 11B having a thickness of 5 μm are formed by electroless solder plating.

On the other hand, the semiconductor chip 15B is substantially the same as the semiconductor chip 15A shown in FIG. 2B. A
On the surfaces of the electrode pads 14 and 14 made of
/ W barrier metal layer 19 and A with a thickness of 0.5 μm
The only difference is that the u-plated layer 18 is formed. Reference numeral 17 denotes the entire electrode pad having the Ti / W layer 19 and the Au layer 18 on the Al layer 14.

This multi-chip semiconductor module 20B
As shown in Fig. 3 (a), the temperature of 280
The semiconductor chip 15B is placed on the stage 99 held at the temperature, and the semiconductor chip 16B is moved above the semiconductor chip 15B.
Then, finely adjust the horizontal position of the semiconductor chip 16B,
The Ni bumps 10, 10 of the semiconductor chip 16B and the electrode pads 17, 17 of the semiconductor chip 15B are positioned so as to face each other. Subsequently, the semiconductor chip 16B is moved downward and placed on the semiconductor chip 15B. Then, as shown in FIG. 3 (b), the Ni bump is not deformed and
The solder plating layer 11B covering the bumps 10, 10 is melted, and the Ni bumps 10, 10 of the semiconductor chip 16B and the electrode pads 17, 17 of the semiconductor chip 15B are soldered 11B.
Connected via In this way, the assembly is easily performed.

After the assembly is completed, the prober is brought into contact with the external electrode pads 41, 41 of the semiconductor chip 15B to perform an electrical test. If the test result shows that one of the semiconductor chips is defective, the stage 99 is set to 300.
The semiconductor chip 16B and the semiconductor chip 15B are separated from each other in a state where the solder 11B is melted by being heated to ℃. As a result, the defective chip can be easily repaired.

Further, this multi-chip semiconductor module 20B, like the multi-chip semiconductor module 20A shown in FIG. 2, can increase the packaging density per unit volume, have excellent response characteristics, and can reduce the cost, and It is possible to reduce restrictions on chip design and product design.

FIG. 4 shows a multi-chip semiconductor module 20 constructed by providing three laminated structures 20A, 20B, 20C on one large semiconductor chip 15.

Here, on the surface of the silicon substrate 6 which constitutes the semiconductor chip 15, the laminated structures 20A, 20B, 20 are formed.
In addition to the electrode pad 14 used to construct C,
Electrode pads 21 and 21 are provided on the outermost periphery.

Of the three laminated structures, the laminated structures 20A and 20B provided on both sides have the same structure as that shown in FIGS.

The laminated structure 20C provided in the center is composed of two semiconductor chips 16 stacked on the silicon substrate 6.
E, 16D. In this region, electrode pads 17, 17 composed of an Al layer 14, a Ti / W layer 19 and an Au layer 20 are formed on the surface side of the silicon substrate 6.
The electrode pads 17, 17 are provided at positions corresponding to the Ni bumps 10, 10 of the semiconductor chip 16E. The semiconductor chip 16E is substantially the same as the semiconductor chip 16B shown in FIG. However, the only difference is that an opening is provided in the protective film 5 on the second metal wiring layer 4. The semiconductor chip 16D is the same as the semiconductor chip 16 of FIG.

When assembling this laminated structure 20C, first, as for the semiconductor chip 16E, the semiconductor chip 16E is placed on the stage 99, and the semiconductor chip 16D is moved above the semiconductor chip 16E so that the Ni bumps 10 and 1 of the semiconductor chip 16D are formed.
0 and the electrode pads 14 of the semiconductor chip 16E are positioned so as to face each other. Then, the semiconductor chip 16D is moved downward and pressed against the semiconductor chip 16E to perform thermocompression bonding. Next, the stacked semiconductor chips 1
6E and 16D are Ni bumps 1 of the semiconductor chip 16E
0, 10 and the electrode pads 17, 17 on the side of the substrate 6 are positioned so as to face each other, and placed on the substrate 6 heated to a temperature of 280 ° C. Then, N of the semiconductor chip 16E
The solder plating layer 11B covering the i bumps 10, 10 is melted, and the Ni bumps 10, 10 of the semiconductor chip 16E and the electrode pads 17, 17 of the substrate 6 are connected via the solder 11B. In this way, the laminated structure 20C is easily assembled.

Laminated structure 20A, 20B provided on both sides
Is also easy to assemble as already mentioned. Therefore, the entire multi-chip semiconductor module 20 can be easily assembled.

After the assembly is completed, each laminated structure 20A, 20B,
Regarding 20C, the semiconductor chips 1 present on the upper side, respectively
An electric test is performed by bringing the prober into contact with the external electrode pads 41, 41 of 6A, 16B, 16D. As a result of the test, when it is found that the laminated structure 20A includes a defective chip, a repair solvent is injected between the semiconductor chip 16A and the substrate 6 to remove the anisotropic conductive film 13. Remove. As a result, the connection between the Ni bumps 10, 10 of the semiconductor chip 16A and the electrode pads 14, 14 of the substrate 6 is released. When it is determined that the laminated structure 20B includes a defective chip, the substrate 6 is set to 300.
The semiconductor chip 16B and the substrate 6 are separated from each other in a state where the solder 11B is melted by being heated to ℃. In addition, the laminated structure 2
If it is found that 0C contains a defective chip, the semiconductor chip 16D, 16E is removed from the substrate 6 with the semiconductor chips 16D and 16E stacked in the same manner while the substrate 6 is heated to 300 ° C. to melt the solder 11B. Separate. As a result, the defective chip can be easily repaired.

Further, this multi-chip semiconductor module 20 can increase the mounting density per unit volume, have an excellent response characteristic, and can be manufactured at the same cost as in the case of the laminated structures 20A and 20B alone (FIGS. 2 and 3). Can be reduced and restrictions on chip design and product design can be reduced.

FIG. 5 shows a state in which the multichip semiconductor module 20 shown in FIG. 4 is mounted by transfer molding. Module 20 is semiconductor chip 1
The connector 5 is attached to the header portion 24a of the lead frame 24 with the connecting member 25 in the state in which 5 is on the lower side. The outermost peripheral electrode pad 21 of the semiconductor chip 15 and the pin portion 24b of the lead frame 24 are connected by a wire 22 by a wire bonding method. Then, the module 20 and the lead frame 24 have the pin portion 24a.
The resin 23 is molded except for the tip.

FIG. 6 shows a TCP (tape carrier package) of the multi-chip semiconductor module 20 shown in FIG.
It shows the mounted state. As the module 20, a module in which Au bumps 29, 29 are provided in advance on the surfaces of the outermost peripheral electrode pads 21, 21 of the semiconductor chip 15 is used. The outermost peripheral electrode pads 21, 21 are Au bumps 2
The Cu leads 26, 26 attached to the polyimide film 27 are connected via 9, 29 by the thimble point bonding method. Then, the laminated structure side of the module 20, that is, the front surface side of the semiconductor chip 15 is sealed with the resin 28.

FIG. 7 shows a state in which the multi-chip semiconductor module 20 shown in FIG. 4 is mounted in a ceramic package. The module 20 is attached by a connecting member 25 in an envelope 30 of the package with the semiconductor chip 15 facing down. The outermost peripheral electrode pad 21 of the semiconductor chip 15 and an unillustrated inner lead (connected to the outer lead 32) are connected by a wire 22 by a wire bonding method.
Then, this package includes an envelope 30 and a glass plate 31.
It is sealed by pasting.

As described above, various products can be manufactured using the multi-chip semiconductor module 20 to which the present invention is applied.

FIG. 8 shows the multi-chip semiconductor module 5
An example in which 0 is mounted on a PWB (printed circuit board) 51 by a face-down bonding method is shown.

This multi-chip semiconductor module 50
Is a semiconductor chip 15 in the lowermost layer of the multi-chip semiconductor module 20 shown in FIG. 4 provided with metal bumps 10 protruding to the back surface side. That is, the semiconductor chip 15 has a plurality of Ni bumps 10 that are in contact with the back surface of the wiring layer on the front surface side and project to the back surface side of the substrate 6 through the through holes. The exposed surface of each Ni bump 10 on the back surface side of the substrate is
It is covered with the solder plating layer 11B. Semiconductor chips 16A, 16B, 15 stacked on the semiconductor chip 15
6E and 16D are the same as those shown in FIG.

On the other hand, on the front surface side of the PWB 51, Al is placed at a position corresponding to the Ni bump 10 of the semiconductor chip 15.
Layer 17, Ti / W layer and Au layer composed of electrode layers 17, 1
7 are formed.

For mounting, the PWB 51 is placed on the stage, the multi-chip semiconductor module 50 is moved in the horizontal direction, and the Ni bumps 10, 10, of the semiconductor chip 15 are moved.
... and the electrode pads 17, 17 on the PWB 51 side are positioned so as to face each other and placed on the PWB 51. Then, by reflow, the Ni bumps 10, 10, ... Of the semiconductor chip 15 are connected to the electrode pads 17, 17 on the PWB 51 side via the solder 11B. In this way, the mounting can be easily performed.

When it is determined by the electrical test after the mounting is completed that the multi-chip semiconductor module 50 includes a defective chip, the defective chip can be easily repaired as in the case of the multi-chip semiconductor module 20. it can.

Further, the multi-chip semiconductor module 50 can increase the packaging density per unit volume, has excellent response characteristics, can reduce the cost, and can reduce restrictions on chip design and product design. it can.

In this embodiment, the plated layer on the exposed surface of each semiconductor chip metal bump 10 is Au 11 or solder 11B, but the present invention is not limited to this.
It may be Su or the like. Further, the plating layer on the outermost surface of the electrode pad 14 is Au 18, but the plating layer is not limited to this, and may be Zn, Ni or Cu or a combination thereof.

Further, the metal bumps 10 are connected to the electrode pads 14
However, the present invention is not limited to this. Instead of providing the metal bump on the side of the through hole 7, the metal bump may be erected on the surface side of the electrode pad 14 with a height dimension exceeding the thickness dimension of the substrate. For example, when stacking such semiconductor chips to form a multi-chip semiconductor module, metal bumps erected on the front surface side of one semiconductor chip are used as through holes of another semiconductor chip existing above the one semiconductor chip. And the tip of the metal bump of the one semiconductor chip is connected to the back surface of the electrode pad of the semiconductor chip on the upper side. In this case, as in the case where the metal bumps are provided on the through hole side, the mounting density per unit volume can be increased, the response characteristics are excellent, the defective chip can be repaired, and the cost can be reduced. In addition, the restrictions on chip design and product design can be reduced.

[0070]

As is apparent from the above, the semiconductor chip according to claim 1 has electrode pads on the front surface side of the substrate and also has metal bumps protruding on the rear surface side of the substrate, so that various types of semiconductor chips can be obtained. The multi-chip semiconductor module can be configured easily and easily.

Further, in the semiconductor chip of claim 2, since the exposed surface of the metal bump on the back surface side of the substrate is covered with a plating layer made of a material having a melting point lower than that of the material of the metal bump, the plating is performed. By heating to a temperature at which the layers melt, the metal pads can be connected to the electrode pads of another semiconductor chip, and various types of multichip semiconductor modules can be easily and easily configured.

Since the multi-chip semiconductor module of claim 3 is provided with one semiconductor chip of claim 1 or claim 2 and another semiconductor chip in a stacked state, the semiconductor chips are two-dimensionally arranged. When arranging or once TC
The mounting density per unit volume can be increased as compared with the case of mounting on P. In addition, since the metal bumps are wirings that connect the electrodes of the chip, the length of the wirings can be shortened and the response characteristics to high frequencies can be improved as compared with the case where wirings are provided in the planar direction. Further, since the connection between the metal bump of one semiconductor chip and the electrode pad of the semiconductor chip located below can be released by melting the anisotropic conductive film used for the connection, the repair of the defective chip can be facilitated. It can be carried out. Also, since the laminated structure is formed by the assembly process rather than the wafer process,
The chip cost can be reduced. Moreover, since the electrodes of the chips are collectively bonded by the metal bumps, the mounting time can be shortened. Further, this multi-chip semiconductor module is constructed by directly stacking the semiconductor chips without mounting the semiconductor chips on the TCP once. Therefore, the chip cost and the mounting cost can be reduced. Further, since wire bonding is not performed, the electrode pad may be provided in an arbitrary area in the chip, and the restrictions on the chip design can be reduced. Moreover, since various kinds of semiconductor chips can be combined in the assembly process, restrictions on product design can be reduced.

Since the multi-chip semiconductor module of claim 4 is provided with one semiconductor chip of claim 2 and another semiconductor chip in a stacked state, the semiconductor chips may be arranged two-dimensionally. The mounting density per unit volume can be increased as compared with the case of once mounting on TCP. In addition, since the metal bumps are wirings that connect the electrodes of the chip, the length of the wirings can be shortened and the response characteristics to high frequencies can be improved as compared with the case where wirings are provided in the planar direction. Further, by heating the semiconductor chip existing on the lower side from the back surface side to melt the plating layer covering the metal bump, the metal bump of the one semiconductor chip and the electrode pad of the semiconductor chip existing on the lower side. Since the connection to and can be released, the defective chip can be easily repaired. Also, since the laminated structure is formed by the assembly process rather than the wafer process,
The chip cost can be reduced. Moreover, since the electrodes of the chips are collectively bonded by the metal bumps, the mounting time can be shortened. Further, this multi-chip semiconductor module is configured by directly combining the semiconductor chips without once mounting the semiconductor chips on the TCP.
Therefore, the chip cost and the mounting cost can be reduced. Further, since wire bonding is not performed, the electrode pad may be provided in an arbitrary area in the chip, and the restrictions on the chip design can be reduced. Moreover, since various types of semiconductor chips can be combined in the assembly process, restrictions on product design can be reduced.

According to a fifth aspect of the multi-chip semiconductor module, a plating layer made of a material capable of forming an alloy with the material of the plating layer of the metal bump is provided on the surface of the electrode pad of the semiconductor chip existing on the lower side. Therefore, at the time of assembly, the plating layer of the metal bump of the one semiconductor chip and the plating layer of the electrode pad of the semiconductor chip existing on the lower side can be brought into contact with each other and heated or pressed or both of them can be easily used. Can be connected to.

[Brief description of drawings]

FIG. 1 is a diagram showing a manufacturing process of a semiconductor chip according to an embodiment of the present invention.

FIG. 2 is a diagram showing an assembling process of a multi-chip semiconductor module according to an embodiment of the present invention.

FIG. 3 is a diagram showing an assembling process of a multi-chip semiconductor module according to another embodiment of the present invention.

FIG. 4 is a diagram showing a multi-chip semiconductor module according to another embodiment of the present invention.

FIG. 5 is a diagram showing an example in which the multichip semiconductor module of FIG. 4 is molded and mounted.

FIG. 6 is a schematic diagram showing the multi-chip semiconductor module of FIG.
It is a figure which shows the example mounted in P.

FIG. 7 is a diagram showing an example in which the multi-chip semiconductor module of FIG. 4 is mounted in a ceramic package.

FIG. 8 is a diagram showing an example in which a multi-chip semiconductor module of another embodiment of the present invention is mounted on a PWB.

[Explanation of symbols]

1,6 Silicon substrate 7 Through hole 9,14,17 Electrode pad 10 Ni bump 11,18 Au plating layer 11B Solder plating layer 15,15A, 15B, 16,16A, 16B, 16D, 16
E Semiconductor chip 20, 20A, 20B, 50 Multi-chip semiconductor module

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification number Office reference number FI technical display location H01L 25/18 H01L 25/04 Z

Claims (5)

[Claims] 1. A substrate, and a plurality of electrode pads provided on the front surface side of the substrate, wherein a through hole is formed in the substrate from the back surface side of the substrate to at least one of the electrode pads reaching the back surface. The semiconductor chip is provided with a metal bump that is in contact with the back surface of the electrode pad and projects to the back surface side of the substrate through the through hole. 2. The semiconductor chip according to claim 1, wherein the exposed surface of the metal bump on the back surface side of the substrate is covered with a plating layer made of a material having a melting point lower than that of the material of the metal bump. Characteristic semiconductor chip. 3. The semiconductor chip according to claim 1 or 2 is provided in a state of being stacked on another semiconductor chip having an electrode pad on the front surface side of the substrate, and the back surface side of the one semiconductor chip is provided. The multi-chip, wherein the metal bump and the electrode pad on the front surface side of the semiconductor chip existing under the one semiconductor chip are opposed to each other and are connected through an anisotropic conductive film. Semiconductor module. 4. The semiconductor chip according to claim 2,
A multi-chip semiconductor module, which is provided in a state of being stacked on another semiconductor chip having an electrode pad on the front surface side of the substrate, and the metal bump and the electrode pad are connected via the plating layer. . 5. The multi-chip semiconductor module according to claim 4, wherein the surface of the electrode pad of the semiconductor chip on the lower side is plated with a material capable of forming an alloy with the material of the plating layer of the metal bump. A multi-chip semiconductor module, characterized in that layers are provided.