JP2001319995A - Manufacturing method of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device which gives a compact package where a packaging area is reduced, at the same time, uses a silicon substrate, does not have any via holes, and can manufacture inexpensively. SOLUTION: A sticking electrode 44a that is buried into a silicon substrate 41, and a demountable electrode 44b are formed, a semiconductor chip 45 is die-bonded on the sticking electrode 44a, the electrode 46 of a semiconductor chip 45 is electrically connected to the demountable electrode 44b, and covering is made by an insulating resin 49 for removing the silicon substrate 41 from a back surface, thus achieving the manufacturing method of the semiconductor device for appropriately packaging an extremely thin and inexpensive, minute semiconductor chip.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device in which a semiconductor chip is assembled using fixed electrodes and extraction electrodes provided on a silicon substrate.

[0002]

2. Description of the Related Art In a conventional semiconductor device assembling process, a semiconductor chip separated by dicing from a wafer is fixed to a lead frame, and the semiconductor chip is sealed by a transfer mold using a mold and resin injection. Cutting and separating into individual semiconductor devices,
Is performed. In the semiconductor device obtained by this method, as shown in FIG. 9, the periphery of a semiconductor chip 1 is covered with a resin layer 2, and lead terminals 3 for external connection are led out from the side of the resin layer 2. (For example, JP-A-05-129473).

[0003] This structure reduces the external dimensions and the mounting area due to the protrusion of the lead terminals 3 outside the resin layer 2, the problem of the processing accuracy of the lead frame and the problem of the positioning accuracy with the mold. Was seeing the limits.

In recent years, attention has been paid to a wafer-scale CSP (chip size package) capable of reducing an outer dimension to a size similar to or close to a semiconductor chip size. In this, referring to FIG. 10A, a large number of semiconductor chips 12 are formed by performing various pretreatments such as diffusion on a semiconductor wafer 11, and an upper portion of the semiconductor wafer 11 is formed as shown in FIG. Is covered with a resin layer 13, electrodes 14 for external connection are led out on the surface of the resin layer 13, and then the semiconductor chips 11 are divided along dicing lines of the semiconductor wafer 11, as shown in FIG. It is a finished product. The resin layer 13 is the semiconductor chip 1
2 only covers the front surface (which may cover the back surface) of the semiconductor chip 12, and the silicon substrate is exposed on the side wall of the semiconductor chip 12. The electrode 14 is electrically connected to an integrated circuit network formed below the resin layer 13, and the semiconductor device is mounted by bonding the electrode 14 to a conductive pattern formed on a mounting substrate. .

[0005] Such a semiconductor device has the advantage that the package size of the device is equivalent to the chip size of the semiconductor chip, and the device can be adhered to the mounting substrate by opposing, so that the area occupied by the mounting can be greatly reduced. Further, there is an advantage that the cost associated with the post-process can be significantly reduced. (For example, Japanese Patent Application Laid-Open No. 9-64049) Therefore, chips having a chip size of less than 1 mm square are mounted as shown in FIGS. 11A, 11B, and 11C.

In FIG. 1, reference numeral 21 denotes an insulating substrate made of ceramic, glass epoxy, or the like, and one or several of them are superposed to have a thickness of 250 to 350 μm, which can maintain the mechanical strength in the manufacturing process. Has a rectangular shape with a long side × short side of about 1.0 mm × 0.8 mm.

On the surface of the insulating substrate 21, a conductive pattern is formed by printing a metal paste such as tungsten and gold plating on the metal paste by an electrolytic plating method to form an island portion 22 and electrode portions 23a and 23b. are doing. A semiconductor chip 25 is fixed on the island portion 22 by a conductive adhesive 24 such as an Ag paste.

An aluminum electrode pad 26 is formed on the surface of the semiconductor chip 25, and the electrode pad 26 and the electrode portion 23a are formed.
23b are electrically connected to each other by a bonding wire 27. 1st bond on electrode pad 26 side, electrode section 23
A 2nd bond is struck on the side. If it is a bipolar transistor, the electrode portions 23a and 23b correspond to the emitter and the base, and if it is a power MOSFET, it corresponds to the source and the gate.

A first external connection electrode 28 and second external connection electrodes 29a and 29b are formed on the back surface of the insulating substrate 21 by the same gold plating layer. A circular first via hole 30 and a second
Are formed, and the inside of each via hole 30, 31a, 31b is buried with a conductive material such as tungsten. The material is buried with a material having excellent electrical and thermal conductivity. The via hole 3
0, 31a and 31b, the island portion 22 and the first
Of the external connection electrode 28 and the electrode portions 23a and 23b and the second
Are electrically connected to the external connection electrodes 29a and 29b, respectively. The first external connection electrodes 28 are, for example, collector electrodes, and the second external connection electrodes 29a, 29b are, for example, base and emitter electrodes.

The semiconductor chip 25 is located above the insulating substrate 21.
And the bonding wire 27 is covered with a resin layer 32. The resin layer 32 forms an outer shape of the package together with the insulating substrate 21. The four sides around the package are resin layers 32
The upper surface of the package is formed on the flattened surface of the resin layer 32, and the lower surface of the package is formed on the back surface side of the insulating substrate 21.

[0011]

However, there are various problems in the mounting structure shown in FIG. First
In addition, since an expensive substrate material such as ceramic or glass epoxy is used, and an expensive metal paste such as tungsten is used, the mounting structure cannot be said to be low cost. Second
In addition, in order to connect electrodes and the like on both sides, a via hole penetrating the insulating substrate is indispensable, and the processing accuracy is 0.15.
The limit of about mm is an obstacle to further miniaturization. Third, since the inside of the via hole is filled with a metal paste, workability is extremely poor, which causes an increase in cost. Fourth, the process is divided into a pre-process for forming a semiconductor chip and a post-process for assembling a semiconductor chip using an insulating substrate, which causes many problems such as a long lead time and a high manufacturing cost.

[0012]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned various problems, and comprises a step of forming a trench in a portion of a surface of a silicon substrate which is to be a fixed electrode and an extraction electrode. Forming an oxide film on at least a side surface and a bottom surface of the trench groove, removing the oxide film on the side surface of the trench groove, and forming the fixed electrode and the extraction electrode made of a conductive metal embedded in the trench groove. Forming a semiconductor chip on the fixed electrode, electrically connecting the electrode of the semiconductor chip and the extraction electrode, and including an insulating resin on the surface of the silicon substrate including the semiconductor chip. Coating, removing the silicon substrate from the back surface to expose the back surface of the fixed electrode and the extraction electrode,
Dicing the insulating resin to separate into individual semiconductor elements.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A method for manufacturing a semiconductor device according to the present invention will be described in detail with reference to FIGS.

According to the present invention, there is provided a step of forming a trench groove 42 in a portion of a surface of a silicon substrate 41 which is to be a fixed electrode 44a and an extraction electrode 44b.
Forming an oxide film 43 on at least the side and bottom surfaces of the trench 2, removing the oxide film 43 on the bottom surface of the trench groove 42, and removing the fixed electrode 44 a made of a conductive metal embedded in the trench groove 42. Extraction electrode 4
4b, die bonding a semiconductor chip 45 on the fixed electrode 44a, and electrically connecting an electrode 46 of the semiconductor chip 45 to the extraction electrode 44b. A step of coating the surface of the substrate 41 with an insulating resin 49; a step of removing the silicon substrate 41 from the back surface to expose the back surfaces of the fixed electrodes 44a and the extraction electrodes 44b; Of the semiconductor device.

In the first step of the present invention, as shown in FIG.
The purpose of the present invention is to form a trench 42 in a portion of the surface of the silicon substrate 41 where the fixed electrode 44a and the extraction electrode 44b are to be formed.

In this step, a silicon substrate 41 having a thickness of about 200 μm is prepared, the portions to be the fixed electrodes 44a and the extraction electrodes 44b are exposed, and the other portions are covered with a photoresist layer. A trench 4 having a depth of about 10 to 50 μm by selective dry etching
Form 2 The trench 42a for forming the planned fixed electrode 44a is formed slightly larger than the semiconductor chip, and the planned extraction electrode 44b is formed in a square shape of 200 μm on a side so that a bonding wire can be fixed.
2b is formed.

In the second step of the present invention, as shown in FIGS. 2 and 3, an oxide film 43 is formed on at least the side and bottom surfaces of the trench groove 42, and then the oxide film 43 on the bottom surface of the trench groove 42 is removed. It is in.

In this step, the surface of the silicon substrate 41 is thermally oxidized to form a thick oxide film 43 having a thickness of about 5000 to 10000 (FIG. 2). Therefore, the oxide film 43 is formed on the surface of the silicon substrate 41 and the side and bottom surfaces of the trench 42. Subsequently, the oxide film 43 is anisotropically dry-etched to perform etching on the surface of the silicon substrate 41 and the trench 42.
The oxide film 43 on the bottom surface is selectively removed (FIG. 3). As a result, the oxide film 43 remains on the side surface of the trench 42.

In the third step of the present invention, as shown in FIG.
The purpose is to form a fixed electrode 44a and a lead-out electrode 44b made of a conductive metal buried in the trench 42.

In this step, at least the trench 42 is filled by electroplating a conductive metal such as copper or gold.
After the conductive metal plating film is formed on the entire surface of the silicon substrate 41 including the trench groove 42, the conductive metal plating film is removed by photoetching while leaving the conductive metal plating film in the trench groove 42.

In the fourth step of the present invention, as shown in FIG.
A semiconductor chip 45 is die-bonded on the fixed electrode 44a,
The purpose is to electrically connect the electrode 46 of the semiconductor chip 45 and the extraction electrode 44b.

In this step, the semiconductor chip 45 is fixed to the surface of the fixed electrode 44a by a conductive adhesive 48 such as an Ag paste, and the electrode pad 46 of the semiconductor chip 45 and the extraction electrode 44b are connected to each other by a bonding wire 47 by ball bonding. I do.

The semiconductor chip 45 has a high-concentration impurity layer on the back side like an N + / N type structure, and through the high-concentration layer, if it is a diode element, one of an anode and a cathode. In this structure, the collector terminal is derived from a bipolar transistor, and the drain terminal is derived from a power MOSFET. Then, the high concentration layer is electrically connected to the fixed electrode 44 a via the conductive adhesive 48.

An aluminum electrode pad 46 is formed on the surface of the semiconductor chip 45, and the electrode pad 46 and the extraction electrode 4 are formed.
4b is electrically connected by a bonding wire 47. A first bond is formed on the electrode pad 46 side, and a second bond is formed on the extraction electrode 44b side. In the case of a bipolar transistor, the extraction electrode 44b corresponds to the emitter and the base, respectively, and in the case of the power MOSFET, it corresponds to the source and the gate.

In the fifth step of the present invention, as shown in FIG.
The object is to cover the surface of the silicon substrate 41 including the semiconductor chip 45 with the insulating resin 49.

In this step, a predetermined amount of epoxy liquid resin is dropped (potted) from a dispenser (not shown) transferred above the silicon substrate 41, and all the semiconductor chips 45 are covered with a common resin layer 49. . For example, CV576AN (manufactured by Matsushita Electric Works) was used as the liquid resin. Since the dropped liquid resin has relatively high viscosity and surface tension, its surface is curved. In order to process the curved surface of the resin layer 49 into a flat surface, a method of pressing a flat molded member before the resin is cured to process the flat surface,
A method is considered in which after the dropped resin layer 49 is cured by heat treatment (curing) at 100 to 200 degrees for several hours, the curved surface is processed into a flat surface by, for example, grinding with a dicing blade.

In the sixth step of the present invention, as shown in FIG.
The silicon substrate 41 is removed from the back surface to expose the back surfaces of the fixed electrode 44a and the extraction electrode 44b.

This step is a feature of the present invention.
The silicon substrate 41 is ground from the back surface. Silicon substrate 4
1 has a thickness of about 200 μm, so most of it is mechanically ground by back grinding, and the remaining 10 to 20 μm
Is chemically removed by spin etching. Since the surface of the silicon substrate 41 is covered with the resin layer 49, the silicon substrate 41 does not break due to the mechanical strength of the resin layer 49. As a result, the back surfaces of the fixed electrode 44a and the extraction electrode 44b are exposed on the back surface side of the resin layer 49.
At this time, the oxide film 43 functions as an electrical insulating material for the fixed electrode 44a and the extraction electrode 44b.

The final step of the present invention is to separate the insulating resin 49 into individual semiconductor elements by dicing as shown in FIG.

In this step, the resin layer 49 and the silicon substrate 41 are cut for each semiconductor chip 45 to separate each semiconductor element. The dicing device is used for the cutting, and the resin layer 49 and the silicon substrate 41 are simultaneously cut by the dicing blade 51 along the dicing line 50 shown by the dotted line, thereby forming a semiconductor device divided for each semiconductor chip 45. In the dicing process, the silicon substrate 41 is used.
A blue sheet (for example, trade name: UV sheet, manufactured by Lintec Co., Ltd.) is attached to the back surface of the substrate, and cut at a cutting depth such that the dicing blade reaches the surface of the blue sheet.

[0031]

As described above, according to the present invention, there is an advantage that it is possible to provide a package structure that can be further reduced in size than a semiconductor device using a lead frame. At this time, since the structure is such that the lead terminals do not project, the occupied area when mounting is reduced, and high-density mounting can be realized.

Further, since the substrate to which the semiconductor chip is fixed can be formed of a silicon substrate, the cost can be greatly reduced as compared with a conventional ceramic substrate.

Further, the silicon substrate can be processed by existing equipment, and no new equipment is required. Since the silicon substrate can also be processed in the pre-process, the post-process is extremely short, and the lead time can be greatly reduced.

Further, since no via hole is required, the through-hole process can be entirely eliminated, and the process can be greatly reduced.

Further, if a silicon substrate having a larger diameter than a substrate for forming a semiconductor chip is used, it is advantageous for mass production.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view for explaining the present invention.

FIG. 2 is a cross-sectional view for explaining the present invention.

FIG. 3 is a cross-sectional view for explaining the present invention.

FIG. 4 is a cross-sectional view for explaining the present invention.

FIG. 5 is a cross-sectional view for explaining the present invention.

FIG. 6 is a cross-sectional view for explaining the present invention.

FIG. 7 is a cross-sectional view for explaining the present invention.

FIG. 8 is a plan view for explaining the present invention.

FIG. 9 is a cross-sectional view for explaining a conventional example.

FIG. 10 is a diagram for explaining a conventional example.

FIG. 11 is a diagram for explaining another conventional example.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification code FI Theme coat ゛ (Reference) H01L 21/301 H01L 21/78 L 23/12 23/12 L

Claims (4)

[Claims] 1. A step of forming a trench on a portion of a surface of a silicon substrate that is to be a fixed electrode and an extraction electrode, and forming an oxide film on at least side surfaces and a bottom surface of the trench groove, and then forming a bottom surface of the trench groove. Removing the oxide film, forming the fixed electrode and the extraction electrode made of a conductive metal embedded in the trench groove, and die-bonding a semiconductor chip on the fixed electrode to form an electrode of the semiconductor chip. Electrically connecting the substrate and the extraction electrode; covering the surface of the silicon substrate including the semiconductor chip with an insulating resin; removing the silicon substrate from the rear surface and the rear surface of the fixed electrode and the extraction electrode. Exposing the insulating resin, and dicing the insulating resin into individual semiconductor elements. Semiconductor device manufacturing method. 2. The method according to claim 1, wherein the conductive metal is formed by plating gold or copper. 3. The method according to claim 1, wherein the electrode of the semiconductor chip and the extraction electrode are connected by a bonding wire. 4. The method according to claim 1, wherein the silicon substrate is removed from a back surface by grinding.