JP2005353997A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce the chip area of a semiconductor device having an SOI substrate. <P>SOLUTION: The semiconductor device is provided with the SOI substrate 7 having a support substrate layer 1 formed of silicon, an insulating layer 3 formed on the support substrate layer 1, and an active layer 5 formed on the insulating layer 3. The semiconductor device is provided with an impurity diffusion layer 17 formed in the active layer 3, a first connection hole 31 formed on the insulating layer 3 in accordance with the impurity diffusion layer 17, a second connection hole formed in the support substrate layer in accordance with the impurity diffusion layer 31 and the first connection hole 31, and a pad electrode 37 which is formed on a face 1b opposite to the insulating layer 3 of the support substrate layer 1 and is electrically connected to the impurity diffusion layer 17 through the first connection hole 31 and the second connection hole 27. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device and a method for manufacturing the same, and particularly includes a SOI substrate having a supporting substrate layer made of silicon, an insulating layer formed on the supporting substrate layer, and an active layer formed on the insulating layer. The present invention relates to a semiconductor device and a manufacturing method thereof.

  In recent semiconductor devices, line widths have been miniaturized in order to improve arithmetic processing speed. In addition to miniaturization, various capacitances (metal wiring capacitances, source and drain capacitances, etc.) also affect the calculation processing speed, so that the capacitance is reduced. One example is a semiconductor device using an SOI (Silicon On Insulator) substrate in order to reduce the junction capacitance of the source and drain (see, for example, Patent Document 1 and Patent Document 2). At present, speed improvement experiments using an SOI substrate and a strained transistor are being actively conducted.

In Patent Document 1, in a semiconductor device provided with a MOSFET (Metal Oxide Field Effect Transistor) on a thin film SOI substrate, a gate electrode that exerts an electric field effect and a metal wiring layer are formed so as to sandwich a semiconductor layer serving as a channel. In addition, after the diffusion layer electrode is formed in the semiconductor layer in a self-aligned manner with respect to the gate electrode, the semiconductor layer is polished to form a thin film SOI structure, and then the opposite side of the gate electrode is formed. A semiconductor device in which wirings are collectively formed on a semiconductor layer is disclosed. This enables effective high-temperature processing when the substrates are bonded together or post-processing after polishing, etc., because the substrate has a high melting point and low reactivity system, and the wiring process is completely flattened. It is said that fine processing becomes possible because it is carried out on the processed substrate.
Further, in Patent Document 2, a first SOI chip and a second SOI chip are arranged so that their surfaces face each other, and a semiconductor chip having a large area corresponding to a large current and a high breakdown voltage. Discloses a semiconductor device in which the semiconductor device is divided and overlaid on the first and second SOI chips. As a result, the package containing the chip is not increased in size.

JP-A-6-275803 JP 2002-26237 A

When an SOI substrate is used, it is advantageous for speed, power consumption, etc., but the effect can be obtained only by reducing the line width by thinning the chip size.
For example, in the semiconductor device described in Patent Document 1, it is advantageous in microfabrication with good flatness by forming all the steps after the metal wiring forming step on a flattened semiconductor layer. There is a problem in that the chip area cannot be effectively reduced because it is necessary to increase the margin due to alignment misalignment, processing accuracy, and the like when connecting to the portion.
In the semiconductor device described in Patent Document 2, the size of the entire package can be reduced by arranging the first SOI chip and the second SOI chip so as to overlap each other. Has a problem that the chip size cannot be reduced.

  Accordingly, an object of the present invention is to reduce a chip area in a semiconductor device including an SOI substrate and a manufacturing method thereof.

  A semiconductor device according to the present invention is a semiconductor device including an SOI substrate having a support substrate layer made of silicon, an insulating layer formed on the support substrate layer, and an active layer formed on the insulating layer. An impurity diffusion layer formed in the active layer, a first connection hole formed in the insulating layer corresponding to the impurity diffusion layer, and corresponding to the impurity diffusion layer and the first connection hole. The second diffusion hole formed in the support substrate layer and the surface of the support substrate layer opposite to the insulating layer are formed, and the impurity diffusion is performed through the first connection hole and the second connection hole. A pad electrode electrically connected to the layer;

In the semiconductor device of the present invention, the second connection hole may be formed in a tapered shape.
Furthermore, the pad electrode may be formed on the inclined surface of the tapered second connection hole.
The pad electrode may be formed on a flat portion of the surface of the support substrate layer opposite to the insulating layer.

A manufacturing method of a semiconductor device according to the present invention includes a semiconductor including an SOI substrate having a supporting substrate layer made of silicon, an insulating layer formed on the supporting substrate layer, and an active layer formed on the insulating layer. The device manufacturing method includes the following steps (A) to (C).
(A) a second connection hole forming step of forming a second connection hole in the support substrate layer corresponding to the impurity diffusion layer in a state where the impurity diffusion layer is formed in the active layer;
(B) a first connection hole forming step of forming a first connection hole in the insulating layer corresponding to the impurity diffusion layer and the second connection hole;
(C) a pad electrode for forming a pad electrode electrically connected to the impurity diffusion layer through the second connection hole and the second connection hole on a surface opposite to the insulating layer of the support substrate layer; Forming process.

  In the method for manufacturing a semiconductor device of the present invention, an example in which the second connection hole is formed by crystal plane anisotropic etching of silicon in the second connection hole forming step (A) can be given.

  In the semiconductor device of the present invention, in a semiconductor device comprising an SOI substrate having a supporting substrate layer made of silicon, an insulating layer formed on the supporting substrate layer, and an active layer formed on the insulating layer, An impurity diffusion layer formed in the active layer; a first connection hole formed in the insulating layer corresponding to the impurity diffusion layer; and the support substrate corresponding to the impurity diffusion layer and the first connection hole. A second connection hole formed in the layer and a surface of the support substrate layer opposite to the insulating layer, and electrically connected to the impurity diffusion layer via the first connection hole and the second connection hole. Since the pad electrodes connected to each other are provided, the pad electrode region can be reduced and the chip area can be reduced.

  In the semiconductor device of the present invention, if the second connection hole is formed in a tapered shape, the opening area on the first connection hole side of the first connection hole and the second connection hole can be reduced, and the second connection hole can be reduced. Since the opening area of the connection hole on the side opposite to the first connection hole side (the back side of the support substrate layer) can be increased, the opening area of the first connection hole and the second connection hole on the first connection hole side can be increased. A conductive material for electrically connecting the pad electrode and the impurity diffusion layer can be easily formed in the first connection hole and the second connection hole while reducing the size of the pad electrode and the impurity diffusion layer. Electrical connection can be obtained.

  Further, if the pad electrode is formed on the inclined surface of the tapered second connection hole, the bump-like external connection terminal is formed on the pad electrode without using the flat surface on the back surface of the support substrate layer. The area occupied by the pad electrode on the back surface of the support substrate layer can be reduced, and the chip area can be further reduced.

  Further, if the pad electrode is formed on the flat portion of the surface of the support substrate layer opposite to the insulating layer, it can cope with electrical connection with the outside by wire bonding technology. .

According to a method of manufacturing a semiconductor device of the present invention, a semiconductor device including an SOI substrate having a supporting substrate layer made of silicon, an insulating layer formed on the supporting substrate layer, and an active layer formed on the insulating layer. In the manufacturing method of
(A) a second connection hole forming step of forming a second connection hole in the support substrate layer corresponding to the impurity diffusion layer in a state where the impurity diffusion layer is formed in the active layer;
(B) a first connection hole forming step of forming a first connection hole in the insulating layer corresponding to the impurity diffusion layer and the second connection hole;
(C) a pad electrode for forming a pad electrode electrically connected to the impurity diffusion layer through the second connection hole and the second connection hole on a surface opposite to the insulating layer of the support substrate layer; Forming process,
Thus, the pad electrode region can be reduced and the chip area can be reduced.

  Furthermore, if the second connection hole is formed by crystal plane anisotropic etching of silicon in the second connection hole forming step (A), a tapered second connection hole can be formed.

1A and 1B are schematic configuration diagrams showing an embodiment of a semiconductor device, in which FIG. 1A is a plan view, FIG. 1B is an enlarged plan view showing the vicinity of one pad electrode, and FIG. It is sectional drawing in a XX 'position.
For example, an insulating layer 3 made of a silicon oxide film having a film thickness of 2 to 3 μm, for example, is formed on one surface a of the support substrate layer 1 made of silicon having a film thickness of 200 to 300 μm (micrometer), and further, for example, a film An SOI substrate 7 in which an active silicon layer (active layer) 5 having a thickness of 100 to 900 μm is formed is used.
A groove is formed in the active silicon layer 5, and, for example, a silicon oxide film is buried in the groove to form an STI (Shallow Trench Isolation) 9. The active silicon layer 5 is separated into a plurality of regions by the STI 9.

Impurities are implanted into the transistor region of the active silicon layer 5 separated by the STI 9, and a source diffusion layer 11s and a drain diffusion layer 11d having an LDD (Lightly doped drain) structure, for example, are formed at intervals. A gate electrode 13 is formed on the active silicon layer 5 between the source diffusion layer 11s and the drain diffusion layer 11d via a gate insulating film (not shown). A side wall 15 made of, for example, a silicon oxide film is formed on the side surface of the gate electrode 13. Here, the transistor formed on the SOI substrate 7 may be a fully depleted type or a partially depleted type.
Impurities are introduced into a region of the active silicon layer 5 separated by the STI 9 and different from the transistor region to form a wiring diffusion layer (impurity diffusion layer) 17.

An interlayer insulating film 19 made of, for example, a silicon oxide film is formed on the entire surface of the active silicon layer 5 including the region on the STI 9. Connection holes are formed in the interlayer insulating film 19 corresponding to predetermined regions of the source diffusion layer 11s, the drain diffusion layer 11d, the gate electrode 13 and the wiring diffusion layer 17, and tungsten is buried in each connection hole, for example. Thus, conductive plugs 21 are respectively formed.
A metal wiring pattern 23 made of, for example, aluminum is formed in a predetermined region on the interlayer insulating film 19 including the region on the conductive plug 21. In FIG. 1C, the source diffusion layer 11 s is electrically connected to the wiring diffusion layer 17 through the conductive plug 21, the metal wiring pattern 23, and the conductive plug 21.
A protective insulating film 25 made of, for example, a passivation film is formed on the entire surface of the interlayer insulating film 19 including the region on the metal wiring pattern 23.

  A plurality of tapered second connection holes 27 are formed in the supporting substrate layer 1 of the SOI substrate 9 so as to correspond to the wiring diffusion layer 17. The dimension of the second connection hole 27 is, for example, an opening area on the surface 1a of the support substrate layer 1 of 1 × 1 to 10 × 10 μm, and a back surface (surface opposite to the insulating layer 3) 1b of the support substrate layer 1. The opening area is 100 × 100 to 2000 × 2000 μm. An insulating film 29 made of, for example, a silicon oxide film is formed on the back surface 1b of the support substrate layer 1 including the inner wall surface of the second connection hole 27 and the surface of the insulating layer 3 exposed at the bottom of the second connection hole 27 (nano Meter).

Corresponding to a predetermined region of the wiring diffusion layer 17, a first connection hole 31 is formed for each second connection hole 27 in the insulating film 29 and the insulating layer 3 located at the bottom of the second connection hole 27. The opening area of the first connection hole 31 is at least a dimension equal to or smaller than the opening area of the second connection hole 27 on the surface 1a of the support substrate layer 1 and is, for example, 100 × 100 nm to 30 × 30 μm. For example, tungsten is buried in the first connection hole 31 to form a conductive plug 33.
In this embodiment, the first connection hole 31 has an opening area of 1 × 1 μm. Further, the opening shape of the first connection hole 31 may be another shape such as a circle.

  A plurality of metal wiring patterns 35 made of, for example, aluminum are formed in a predetermined region on the insulating film 29 including the formation region of the second connection hole 27 on the conductive plug 33 and the flat portion region on the back surface of the support substrate layer 1. Each connection hole 27 is formed. The thickness of the metal wiring pattern 35 is 1 μm, for example. The metal wiring pattern 35 disposed on the flat portion of the back surface 1 b of the support substrate layer 1 constitutes a pad electrode 37. The dimension of the pad electrode 37 is, for example, 100 × 100 μm. In this embodiment, a plurality of pad electrodes 37 are arranged near the periphery of the chip.

  In (C), the pad electrode 37 is electrically connected to the source diffusion layer 11s through the metal wiring pattern 35, the conductive plug 31, the impurity diffusion layer 17, the conductive plug 21, the metal wiring pattern 23, and the conductive plug 21. It is connected to the. The pad electrodes 37 in regions other than the regions shown in (B) and (C) are also electrically connected to the individual impurity diffusion layers 17 via the metal wiring patterns 35 and the conductive plugs 31, respectively.

In this embodiment, since the pad electrode 37 is disposed on the flat portion of the back surface 1b of the support substrate layer 1, electrical connection with the outside by wire bonding technology can be supported.
It is electrically connected to the transistor and metal wiring formed on the active silicon layer. As shown in FIGS. 1 and 2, by forming the pad metal according to claim 3 on the flat surface of the supporting silicon substrate, it is possible to cope with the connection to the external electrode by the wire bonding technique.
Conventionally, in a semiconductor device provided with a large number of pad electrodes, there are chips that could not be further reduced due to restrictions on the size and arrangement of pad electrodes. Conventionally, an area of about 50 × 50 μm (2500 μm ² ) to 100 × 100 μm (10000 μm ² ) per pad electrode is required on the active silicon layer side, but the back surface of the support substrate layer 1 as in the present invention. By forming the pad electrode 37 on 1b, 5 × 5 μm (25 μm ² ) to 10 × 10 μm (100 μm) even in consideration of alignment misalignment or the like in the photolithography process for defining the formation region of the second connection hole 27 ² ), the chip size can be reduced.

  FIG. 2 is a process cross-sectional view for explaining a pad electrode forming process of the semiconductor device shown in FIG. 1 as an embodiment of the manufacturing method. An embodiment of the manufacturing method will be described with reference to FIGS.

(1) The SOI substrate 7 shown in FIG. 1 is formed on the STI 9, the source diffusion layer 11s, the drain diffusion layer 11d, the gate electrode 13, the sidewall 15 wiring diffusion layer 17, and the interlayer insulation by using a known semiconductor device manufacturing technique. A film 19, a conductive plug 21, a metal wiring pattern 23, and a protective insulating film 25 are formed.
A masking film, for example, a silicon oxide film, is formed on the back surface 1b of the support substrate layer 1 of the SOI substrate 7, and a resist pattern for defining the formation region of the second connection hole 27 is further formed thereon by photolithography. Form. Using the resist pattern as a mask, the silicon oxide film is patterned to form a mask pattern 39 for defining the formation region of the second connection hole 27 (see (a)).

(2) Crystal plane anisotropy of silicon with respect to the support substrate layer 1 using an alkaline aqueous solution such as a KOH (potassium hydroxide) aqueous solution or a TMAH (tetramethylammonium hydroxide) aqueous solution, using the mask pattern 39 as a mask. Etching is performed to form second connection holes 27 in the support substrate layer 1. Thereafter, the mask pattern 39 is removed (see (b)).

(3) An insulating film 29 made of a silicon oxide film is formed to a thickness of 100 nm on the back surface 1b of the support substrate layer 1 including the formation region of the second connection hole 27.
A mask for demarcating the formation region of the first connection hole on the insulating film 29 by photolithography, and an opening corresponding to a predetermined region at the bottom of the impurity diffusion layer 17 and the second connection hole 27 A resist pattern 41 is formed.
For example, the first connection hole 31 is formed by selectively removing predetermined regions of the insulating film 29 and the insulating layer 3 using the resist pattern 41 as a mask by a dry etching technique (see (c)).

(4) The resist pattern 41 is removed. Using a known tungsten filling technique, tungsten is buried in the first connection hole 31 to form the conductive plug 33. A metal film, for example, an aluminum film is formed on the insulating film 29 including the formation region of the first connection hole 31 and the second connection hole 27, and the aluminum film is patterned to form the metal wiring pattern 35 and the pad electrode 37. (See FIG. 1). Thereby, the manufacturing process of the semiconductor device is completed.

In this embodiment of the manufacturing method, the second connection holes 27 are formed by anisotropic crystal plane anisotropic etching of silicon, but the manufacturing method of the present invention is not limited to this, but wet etching technology or dry etching. The second connection hole may be formed in the support substrate layer of the SOI substrate by another etching technique such as a technique. For example, if the second connection hole is formed by dry etching technique using SiCl ₄ gas and setting the processing pressure at a high level, for example, about 200 mTorr (millitorr), the tapered second connection hole can be formed.

  3A and 3B are schematic configuration diagrams showing another embodiment of the semiconductor device, in which FIG. 3A is a plan view, FIG. 3B is an enlarged plan view showing the vicinity of one pad electrode, and FIG. It is sectional drawing in YY 'position. The same parts as those in FIG. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted.

This embodiment differs from the embodiment described with reference to FIG. 1 in that the material of the metal wiring pattern 43 that is formed on the insulating film 29 and in which a part of the region constitutes the pad electrode 37 is made of the first connection hole 31. It is a point embedded in.
In (C), the pad electrode 37 is electrically connected to the source diffusion layer 11s through the metal wiring pattern 43, the impurity diffusion layer 17, the conductive plug 21, the metal wiring pattern 23, and the conductive plug 21. . The pad electrodes 37 in regions other than the regions shown in (B) and (C) are also electrically connected to the individual impurity diffusion layers 17 via the metal wiring patterns 43, respectively.

Also in this embodiment, the same effect as the embodiment described with reference to FIG. 1 can be obtained.
The semiconductor device shown in FIG. 3 performs the same steps as steps (1) to (3) of the embodiment of the manufacturing method described with reference to FIGS. 1 and 2 (see FIG. 2), and then an insulating film. 29 and in the first connection hole 31, and a conductive material film can be formed by patterning the conductive material film.

  4A and 4B are schematic configuration views showing still another embodiment of the semiconductor device, wherein FIG. 4A is a plan view, FIG. 4B is an enlarged plan view showing the vicinity of one pad electrode, and FIG. It is sectional drawing in the ZZ 'position. The same reference numerals are given to the same parts as those in FIG.

  An SOI substrate 7 having a supporting substrate layer 1, an insulating layer 3 and an active silicon layer 5, an STI 9, a source diffusion layer 11s, a drain diffusion layer 11d, a gate electrode 13, a sidewall 15 a wiring diffusion layer 17, an interlayer insulating film 19, A conductive plug 21, a metal wiring pattern 23, and a protective insulating film 25 are formed. A second connection hole 27 is formed in the support substrate layer 1, and an insulating film 29 is formed on the back surface 1 b of the support substrate layer 1. A first connection hole 31 is formed in the insulating layer 3 and the insulating film 29. A conductive plug 33 is formed in the first connection hole 31.

A plurality of pad electrodes 45 made of, for example, aluminum are formed for each second connection hole 27 in a predetermined region on the insulating film 29 including the formation region of the second connection hole 27 on the conductive plug 33. The thickness of the pad electrode 45 is 1 μm, for example.
An insulating film 47 made of, for example, a passivation film is formed on the insulating film 29 and on the peripheral edge of the pad electrode 45. In the insulating film 47, an opening having a planar shape, for example, a rectangle, here a square, is formed corresponding to the pad electrode 45. The length of one side of the opening is, for example, 70 μm.
A bump electrode (external connection terminal) 49 made of, for example, solder is mounted on the pad electrode 45. The tip of the bump electrode 49 (the end opposite to the pad electrode) is disposed at a position protruding from the surface of the insulating film 47. The length of one side of the bump electrode 49 is, for example, 70 μm.

  In this embodiment, since the pad electrode 45 is formed on the inclined surface of the tapered second connection hole 27, the region corresponding to the flat surface of the back surface 1 b of the support substrate layer 1 is used without using the region on the pad electrode 45. The bump electrode 49 can be formed on the back surface, and the area occupied by the pad electrode 45 on the back surface 1b of the support substrate layer 1 can be reduced to further reduce the chip area.

  The embodiment shown in FIG. 4 is the same as the step (4) described with reference to FIG. 1 after performing the same steps as the steps (1) to (3) described with reference to FIG. Then, the conductive plug 33 is formed in the first connection hole 31, the pad electrode 45 is formed on the insulating film 29, and then the insulating film 47 and the bump electrode 49 are formed.

In the embodiment shown in FIG. 4, the conductive plug 33 is provided in the first connection hole 31. However, the present invention is not limited to this, and as in the embodiment shown in FIG. 2,
The metal material embedded in the first connection hole 31 may be the same as the pad electrode.

  As mentioned above, although the Example of this invention was described, this invention is not limited to the said Example, A dimension, a shape, arrangement | positioning, a material, etc. are examples, and the scope of the invention described in the claims Various modifications within the range are possible.

BRIEF DESCRIPTION OF THE DRAWINGS It is a schematic block diagram which shows one Example of a semiconductor device, (A) is a top view, (B) is a top view which expands and shows the one pad electrode vicinity, (C) is XX of (B). It is sectional drawing in a 'position. FIG. 6 is a process cross-sectional view for explaining a pad electrode forming process of the semiconductor device shown in FIG. 1 as an example of the manufacturing method. It is a schematic block diagram which shows the other Example of a semiconductor device, (A) is a top view, (B) is a top view which expands and shows the vicinity of one pad electrode, (C) is Y- of (B). It is sectional drawing in a Y 'position. FIG. 6 is a schematic configuration diagram showing still another embodiment of the semiconductor device, in which (A) is a plan view, (B) is an enlarged plan view showing the vicinity of one pad electrode, and (C) is a Z in (B). It is sectional drawing in a -Z 'position.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Support substrate layer 1a Front surface of support substrate layer 1b Back surface of support substrate layer 3 Insulating layer 5 Active silicon layer (active layer)
7 SOI substrate 9 STI
11s Source diffusion layer 11d Drain diffusion layer 13 Gate electrode 15 Side wall 17 Diffusion layer for wiring (impurity diffusion layer)
19 Interlayer insulating film 21 Conductive plug 23 Metal wiring pattern 25 Protective insulating film 27 Second connection hole 29 Insulating film 31 First connection hole 33 Conductive plug 35 Metal wiring pattern 37 Pad electrode 39 Mask pattern 41 Resist pattern 43 Metal wiring Pattern 45 Pad electrode 47 Insulating film 49 Bump electrode (external connection terminal)

Claims (6)

In a semiconductor device comprising an SOI substrate having a support substrate layer made of silicon, an insulating layer formed on the support substrate layer, and an active layer formed on the insulating layer,
An impurity diffusion layer formed in the active layer; a first connection hole formed in the insulating layer corresponding to the impurity diffusion layer; and the support corresponding to the impurity diffusion layer and the first connection hole. A second connection hole formed in the substrate layer; and the impurity diffusion layer formed on the surface of the support substrate layer opposite to the insulating layer, through the first connection hole and the second connection hole. A semiconductor device comprising a pad electrode electrically connected.   The semiconductor device according to claim 1, wherein the second connection hole is formed in a tapered shape.   The semiconductor device according to claim 2, wherein the pad electrode is formed on an inclined surface of the tapered second connection hole.   The semiconductor device according to claim 1, wherein the pad electrode is formed on a flat portion of a surface of the support substrate layer opposite to the insulating layer. In a method of manufacturing a semiconductor device including a SOI substrate having a support substrate layer made of silicon, an insulating layer formed on the support substrate layer, and an active layer formed on the insulating layer, the following steps (A To (C). A method for manufacturing a semiconductor device, comprising:
(A) a second connection hole forming step of forming a second connection hole in the support substrate layer corresponding to the impurity diffusion layer in a state where the impurity diffusion layer is formed in the active layer;
(B) a first connection hole forming step of forming a first connection hole in the insulating layer corresponding to the impurity diffusion layer and the second connection hole;
(C) a pad electrode that forms a pad electrode electrically connected to the impurity diffusion layer through the second connection hole and the second connection hole on a surface of the support substrate layer opposite to the insulating layer; Forming process.   The manufacturing method according to claim 5, wherein, in the second connection hole forming step (A), the second connection hole is formed by crystal plane anisotropic etching of silicon.

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