JPH01129441A - Semiconductor device - Google Patents

Abstract

PURPOSE:To conduct ohmic bonding easily and positively by forming a low- resistance ohmic region reaching from the main surface side of a substrate to the rear and transmitting a signal between the main surface and the rear through the region. CONSTITUTION:The main surface side and rear side of a substrate 1 are connected electrically by a low-resistance ohmic region 6 insulated from a period. Consequently, an Si gate 11 is connected to rear electrodes 7A, 7B through main-surface side electrodes 12A, 12B and the low-resistance ohmic region 6, and an independent connecting terminal insulated from other sections is also shaped on the rear side besides terminals on the main surface side. According to said constitution, voltage is applied to the electrodes 7A, 7B on the rear, thus driving an N channel MOS transistor on the main surface of the substrate 1. Connection to main-surface side electrodes such as a source, a drain, etc., is also enabled besides the case of connection from the rear side with the Si gate 11. As a result, the transmission of a signal between the rear and main surface of the substrate which has been difficult is enabled.

Description

Detailed Description of the Invention [Field of Application of the Invention] The present invention relates to a semiconductor substrate for a three-dimensional device in which a plurality of semiconductor substrates are stacked and bonded at desired parts, and a three-dimensional device using the same. An example of a conventional three-dimensional device in which a plurality of semiconductor substrates are stacked and bonded is described in IEEE Computer, 1984, Jan., p. 69. Jan, Grinberg.

In the above three-dimensional device, the ohmic wiring means that penetrates the substrate uses p-type dopant diffusion in the n-type substrate by heat transfer diffusion by M dots, and penetrates the P+ portion into the n-type substrate. ing. Further, the interconnection between the substrates is made by intersecting two microbridges made of contact metal and bringing them into contact.

[Problem that the invention seeks to solve]

In the conventional three-dimensional structure using multiple substrates as described above, the feed through portion (feed through) is p 4P.
Since it is made of n-junction Pl and uses P+n junction separation, it is difficult to control the upper and lower resistance values of the 8-bin and 21-section distributions by junction. Furthermore, since the microbridge portions are not fused to each other, the stability of the mechanical structure that connects the two substrates does not sufficiently meet the requirements. In addition, there were various problems such as non-ideal isolation from other parts.The present invention was made to solve the problems of the prior art as described above. It is an object of the present invention to provide a configuration that allows easy and reliable ohmic coupling between the main surface side and the back side of a semiconductor substrate on which an IC is fabricated.

[Means to solve the problem]

In order to achieve the above object, in the present invention, at least one recess is formed in a part of the back surface of the semiconductor substrate opposite to the main surface on which the active device is formed, and from the main surface to the bottom of the recess ( At least one low-resistance ohmic region (for example, a poly-Si layer) is formed that reaches the bottom surface when viewed from the back side, that is, the part closest to the main surface side among the four parts, and a separate layer is formed around the low-resistance ohmic region. layer(
For example, an insulating film) is formed, and at least one low resistance member for wiring ( For example, metal film wiring) is formed, and the inner surface of the recess excluding the end of the low-resistance ohmic region on the bottom side of the recess, that is, the contact portion on the bottom side of the recess, and the desired portion of the back surface of the semiconductor substrate are formed using an insulating film. at least one layer of low resistance member for wiring (e.g., metal film wiring) insulated from the semiconductor substrate is formed on the insulating film from the contact portion on the bottom side of the recess to a predetermined location on the back surface of the semiconductor substrate. It is configured so that

With the above configuration, in the present invention,
The main surface side and the back surface side of the semiconductor substrate are ohmically coupled via the low resistance ohmic region, and it becomes possible to transmit signals between the main surface side and the back surface side.

[Embodiments of the invention]

FIG. 1 is a diagram showing one embodiment of the present invention, and shows a cross-sectional view of a semiconductor substrate for a substrate-fused three-dimensional device.

In FIG. 1, a field oxide film 2 is formed on the main surface of a p-type semiconductor substrate 1 by a conventional method. In addition, on the back surface opposite to the main surface, a recess 2z is formed by etching or other method.
form. This recess 22 can be formed using a method similar to that used in manufacturing Si pressure sensors, for example.

Further, after forming the recess 22, the insulating film 3 is formed on the inner surface of the recess 22 and a desired portion of the back surface of the semiconductor substrate 1.

Furthermore, a low-resistance ohmic region 6 extending from the main surface to the bottom surface of the recess 22 is formed in the thinned portion 4 of the semiconductor substrate 1 where the recess is provided. Note that the bottom surface of the recessed portion 22 means the bottom surface viewed from the back surface side, that is, the portion closest to the main surface side among the four portions.

An isolation insulating film 5 is formed around the low resistance ohmic region 6, and the semiconductor substrate 1 and the low resistance ohmic region 6 are separated from each other.
and are electrically insulated.

The isolation insulating film 5 is formed by, for example, a process of digging a narrow groove and an oxidation process, and the low resistance ohmic region 6 is formed of, for example, poly-Si, or a single crystal SL is doped with impurities at a high concentration. Formed by doping. Note that if the manufacturing process is modified, the low resistance ohmic region 6 can be formed using high melting point gcMo, Ta, or the like.

Further, back electrodes 7A and 7B are formed from the end of the low resistance ohmic region 6 on the bottom side of the recess, that is, from the contact portion on the bottom side of the recess to a desired portion of the back surface. This back electrode 7
Forming contact holes for A, 7B, and 7A requires a special manufacturing method because there is a considerable height difference between the back surface and the bottom surface. This manufacturing method involves, for example, patterning by using an optical system that creates a parallel light beam using a laser light source, etc., and performing a photolithography process using ultraviolet or far ultraviolet exposure while the substrate and mask are in close contact with each other. law can be used. Also,
It is also possible to directly etch the metal electrode by causing a direct photochemical reaction in an excitation etching gas atmosphere using a laser beam collimated by a far-ultraviolet optical system currently under development and using a mask. be.

On the other hand, on the main surface side of the semiconductor substrate 1 on which a device is fabricated, there are, for example, an n1 source 8, an n+ drain 9, a gate oxide film 10. A Si gate 11 is formed.

Further, the ends of the low resistance ohmic region 6 on the main surface side, that is, the main surface side contact portions, and the above-mentioned Si gate 11 are coupled by the main surface side electrodes 12A, 12B.

As mentioned above, in the configuration shown in FIG.
The main surface side and the back surface side are electrically connected by a low resistance ohmic region 6 insulated from the surroundings. Therefore, the Si gate 11 is connected to the back electrodes 7A, 7B via the main surface side electrodes 12A, 12B and the low resistance ohmic region 6.
In addition to the terminal on the main surface side, the back side also has an independent connection terminal insulated from other parts.

With the above configuration, by applying a voltage to the electrodes 7A and 7B on the back surface, the N-channel MOS on the main surface of the substrate is
Can drive transistors. It is possible to provide functions that were previously not possible.

Although FIG. 1 illustrates the case where the Si gate 11 is connected from the back side, it is of course possible to connect to other parts, for example, electrodes on the main surface side such as the source and drain.

Next, FIG. 2 is a diagram showing another embodiment of the present invention, and shows a sectional view of a three-dimensional device structure in which two substrates are fused using the semiconductor substrate of the present invention.

The device of FIG. 2 includes a semiconductor substrate 101 of the present invention and a conventional
After aligning an IC with an MO8 structure with a second semiconductor substrate 102 formed on its main surface at a desired electrode portion, the electrode portions are fused by thermocompression bonding using the upper and lower electrodes. It is.

Note that the first semiconductor substrate 101 serving as the upper substrate in FIG.
This embodiment is partially similar to the embodiment shown in FIG. 1, except that an SOI substrate is used instead of the semiconductor substrate 1 shown in FIG.

In FIG. 2, a semiconductor substrate IA serving as an upper substrate 101
An insulating film 14 is provided on top of the insulating film 14, and a monocrystalline Si
Membranes 13 are formed and they form an SOI structure.

In addition, field oxide film 2, insulating film 39 isolation insulating film 5, low resistance ohmic region 6, back electrodes 7A, 7B, n
+ sauce 8. n+ drain9. Gate oxide film 10, S
i-gate 11. Main surface side electrode 12A.

12B, recess 22, etc. are the same as in FIG. 1, but in FIG. An example is shown below.

That is, this example shows the case where an N-channel MOS transistor is formed, and the n+ source 15, the n+
A drain 16, a Si gate 18, a source electrode 19, and drain electrodes 20.21A and 21B are formed. The drain 16 is formed deep to reach the bottom of the recess 22, and is extended to the back surface of the substrate, with the electrode 20 serving as a terminal on the main surface of the substrate, and the electrodes 21A and 21B serving as terminals on the back surface of the substrate.

Further, the second semiconductor substrate 102 at the bottom is a normal CMOS.
This is a semiconductor substrate in which inverters, etc. are built, including a field oxide film 2', an n-type substrate 27, a P-well 28, and a p-well 28.
+well contact 29, n1 substrate contact 30, p
+ source 31, p+ drain 32, n+ drain 33,
n+ source 34, high concentration silicon gates 35, 36, gate oxide films 37, 38, inter-wiring insulating film 39, Voo? u
Extreme 40. Vss electrode 41.0 MO8 output electrode 42,
It is composed of 1ti43A for CMOS gate input.

As shown in FIG. 2, as a method of fusing the upper semiconductor substrate and the lower semiconductor substrate at desired electrode parts, for example,
Technical Digest of the International Electronic Devices Meeting
ational、Electron Device
sMeeting Technical Diges
t, 1984. p816. M.

“PromiSsinHneti” by Yasumoto et al.
fabrication process
opened for 5 tacked LSI’s”)
There is a method described in

FIG. 2 shows a case in which a laminated structure is formed by a fusion method substantially similar to the method described in the above-mentioned literature.

In this method, first, go to
Form a u/Ti layer. Next, a polyimide layer is coated to the same height as the electrodes of the Au/Ti layer described above, and after etching with plasma 02, the Au/Ti electrodes are exposed and planarization is also performed at the same time. Such an electrode configuration is applied to the back surface of the first semiconductor substrate 101 and the second semiconductor substrate 1 in FIG.
02 main surface. Next, the above two substrates are aligned at desired positions and fused together by thermocompression bonding.

This will be further explained with reference to FIG.

When fusing the electrode 21B on the back surface of the upper first semiconductor substrate 101 and the gate electrode m43A of the lower second semiconductor substrate 102, a polyimide layer 4 is placed on the electrode 21B of AQ.
An A11 alloy layer 46U having the same level as that of A11 alloy layer 46U was formed.

Similarly, an AI3 alloy layer 46L whose level matches that of the polyimide layer 45 is also formed on the gate electrode 43A of the second semiconductor substrate 102. The first semiconductor substrate 10 can also be used at other locations.
1 and the second semiconductor substrate 102 at, for example, the electrode 7B and the electrode 43B, the Au alloy layers 47U and 4
By forming 7L and thermocompression bonding, multiple locations can be fused at the same time.

Further, the polyimide layers 44 and 45 function effectively in both stress relief and insulation. Furthermore, if the manufacturing method is devised, it is possible to fill the recess 22 with polyimide.

Note that the method of fusing the electrodes arranged on the two substrates described above is just one example, and it is clear that the device configuration of the present invention is not limited to this fusing method.

In the configuration shown in FIG. 2 as described above, the CMO5 common gate 43 in the lower substrate is
A can be driven.

Although it is not shown where the lower wiring electrode 43B is connected in the figure, for example, when this electrode is connected to the vOut electrode of another CMOS inverter on the lower substrate, the lower wiring electrode 43B V. The gate electrode 11 of the N-channel MOS transistor on the right side of the upper substrate can be driven by the ut output.

In the configuration of the present invention, the method of bonding or fusing the upper and lower substrates is not particularly limited, and other bonding or fusing methods may be used.

The basic configuration of the present invention is 7B-7A-6- in Figure 2.
As shown in the path 12B-12A, there is a connection means between the main surface and the back surface of the substrate via the recess formed by the low resistance ohmic region 6. However, if three or more active terminals are removed by using the same recess, one active terminal (the third terminal) of an active device (in the example of FIG. 2, a MOS transistor having source 15, drain 16, gate 18) It is also possible to connect the main surface and the back surface of the substrate via a drain in FIG. 2 in a manner that includes a switch mechanism.

The diversity of means for coupling the main surface and back surface of the substrate based on the configuration of the present invention as described above can be effectively utilized when constructing a three-dimensional device consisting of N semiconductor substrates.

Next, FIG. 3 is an embodiment diagram showing a configuration in which two or more electrode wirings are provided in one recess.

Note that FIG. 3 shows the structure of FIG. 1 upside down, and (A) and (B) are cross-sectional views, and (C) is a cross-sectional view.
shows a perspective view.

First, FIG. 3(A) shows a state in which a recess 22 is formed in a channel shape in a semiconductor substrate 54. As shown in FIG.

Further, FIG. 3(B) shows a state in which the electrode is drawn out from the recess, and the insulating film 55 on the back surface where the recess 22 is located, the insulating film 56 on the main surface, and the low resistance ohmic region 57 are separated. Insulating film 53, back electrode contact portion 58A
, a 75-plane electrode extension part 58B, a main surface electrode contact part 59A, a main surface electrode extension part 59B, etc. are provided.

Moreover, FIG. 3(C) shows a case where two structures as described above are provided in one recess.

In this case, two electrodes 58A-58B and 58A'-
58B' is shown, but the number of electrodes can be increased if electrical isolation is achieved within the recess.

In addition, in FIG. 3, isolation by the insulating film 53 is used as a means to isolate the low resistance ohmic region 57 from the surroundings, but if the surrounding voltage distribution is appropriately selected and designed,
It is not impossible to utilize reverse bias isolation of the +P junction.

Further, as shown in the embodiment of FIG. 2, active device terminals such as the drain output of a MOS transistor may be mixed. The point is that the contact terminals on the bottom of the recess provided on the back of the substrate only need to meet configuration and bias conditions that allow the voltages applied to each terminal to be independently set.

Next, FIG. 4 is an example diagram in which there are a plurality of recesses in one board, and in the recesses there are a plurality of four-part back terminals as described above, as seen from the back of the board. A top view is shown.

In FIG. 4, 8×2 contact terminals 62 are provided in each of the recesses A, B, C, and D. With this configuration, 16-bit signals can be transferred between the main surface and the back surface of the substrate.

In the example shown in FIG. 4, there are four quadrants each having a 16-bit terminal. Among these, for example, all of the recesses A may be coupled by low resistance ohmic regions. Furthermore, for example, all of the recesses B may be formed by one terminal of an active device such as the drain terminal of a MOS transistor.

Also, when considering the exchange of upper and lower signals with multiple boards,
As considered in the embodiment of FIG. 2, there is a flow of signals going from top to bottom and a flow of signals going from bottom to top. therefore,
The recesses C and D in FIG. 4 may be recesses that respectively share and transmit the flow of these signals.

Next, FIG. 5 shows a case where four substrates 71 to 74 as shown in FIG. 4 are stacked. When a plurality of substrates are stacked and used in this manner, the concave portions of the substrates that are in contact with each other are set at shifted positions so that they do not overlap.

With the 4-layer configuration as shown in Figure 5, the 2x8 bits of the etch channel switch connector as shown in Figure 4 can be connected to A, B,
If configured as shown in C and D, a 32-bit downward signal (
It is possible to simultaneously process parallel signals (signals from the upper substrate to the lower substrate) and 32-bit upward signals (signals from the lower substrate to the upper substrate), making it possible to effectively utilize the characteristics of the three-dimensional stacked device.

The semiconductor device of the present invention is effective when a three-dimensional device is formed by fusing a plurality of substrates as described above.

In addition, in the embodiments described so far, the case where a Si substrate and an SOI substrate were used as the semiconductor substrate was exemplified, but Si on Glass substrate and 5OS (Si on
Even in the case of a 5apphire) substrate, the structure of the present invention can be created using the 81 layer portion. Also,
Glass substrates and SaPPhire substrates are also made with 5iWI by making holes on the back side of the substrates by etching, RIE, etc.
It is possible to make a recess up to

In addition, although the case of SoI (Si-3jO2-3i) substrate is shown in Fig. 2, Si on Si on Si
The structure of the present invention can be applied to a substrate, which has already been made into a monolithic three-layer (in some cases n-layer) three-dimensional device by a method such as laser annealing.

In the above case, if the bottom substrate of the nM monolithic multilayer three-dimensional device is thick, the back surface of the bottom substrate can be etched to form a recess, so that the features of the present invention can be applied to the semiconductor substrate. It can be considered as Therefore, the semiconductor substrate in the description of the present invention can be broadly defined as a substrate containing a semiconductor layer in all cases as described above.

〔Effect of the invention〕

As explained above, according to the present invention, a low resistance ohmic region extending from the main surface side of the substrate to the back surface is provided,
By configuring the device so that signals can be transmitted between the main surface and the back surface through it, various effects as described below can be obtained.

0,) It has become possible to transmit signals between the back side of the board and the main surface of the board, which was previously difficult. This signal transmission is simple and basic, in addition to wiring connections using low-resistance ohmic regions, and also uses the same recess to transmit signals, control, and switch functions using active terminals of active devices such as the drains of MOS transistors. It can also be shared with

(2) Problems with conventional highly integrated planar ICs, namely:
It is possible to improve problems such as: - Chip size increases and wiring length increases within the chip, causing signal delays; - There are many restrictions on cell placement and wiring layout; and - Low yield.

It should be noted that metal wiring used in current LSI wiring inevitably has wiring resistance3.For example,
There is a problem in that the wiring from the contact 21A at the bottom of the recess 22 to the contact 21B on the back surface of the wafer shown in the embodiment of FIG. 2 is longer than in the case of a planar IC in terms of distance. To solve this problem, it is conceivable to make the thickness of the substrate as thin as possible and to make the wiring material even lower in resistance.

Furthermore, as a means to significantly solve the problem of relatively long wiring as described above, it is conceivable to arrange a thin film of superconducting material as a wiring with a width of several microns. Examples of wiring using a thin film of superconducting material include Josephson junction superconductor 1 IC (or J, J.

It is known to use a superconducting strip line in which a superconducting ground plane (superconducting computer system) is covered with an insulating film and a superconducting film with a width of several microns is laid out on top of the insulating film.

The perfect diamagnetic property of superconductors makes it possible to suppress the lateral spread of the magnetic field due to line current to a minimum when used as a ground plane (OP), allowing for high-density wiring and reducing tallostoke between adjacent lines even in the case of high-density wiring. play a role.

Furthermore, the signal attenuation constant of a superconducting strip line is expressed by surface resistance loss and dielectric loss. And the surface resistance is extremely small compared to a normal core line. Further, the dielectric loss can be considerably reduced by reducing the tan δ of the insulating film between the GP and the strip line. Therefore, even if there is a delay due to L and C, the signal attenuation can be considerably reduced if the impedances are matched.

Currently, in the above-mentioned field, experimental studies up to cross wiring are being conducted on Nb wiring on sin, film on Nb ground plane, etc.

The operation of the above-mentioned superconducting film wiring is carried out at the liquid helium temperature, but the structure and composition of these are difficult to understand.

In principle, it can also be constructed using a film of a new high-temperature superconductor such as the Y-Ba-Cu-0 system, which is currently being developed.

Further, improvements in performance are expected from future advances in the manufacturing process.

Therefore, the second rl! Even for relatively long wiring parts such as 21A-21B of I, the process will increase slightly, but first cover the specified part of the Si etch hole with an insulating film, then cover it with a superconducting GP surface in the same way, and then cover it with a superconducting GP surface. The top was covered with an insulating film, and then a strip line several microns wide was laid out, including on the slope.

It is also possible to connect to a drain contact or the like.

Note that it goes without saying that the above-mentioned lines can also be used for wiring on the main surface of the substrate.

If the above-mentioned design measures are taken into account, the three-dimensional multilayer device using a plurality of semiconductor substrates having the device configuration of the present invention can significantly alleviate the problems of conventional planar ICs as described above. I can do it.

(3) Compared to a completely monolithic multilayer three-dimensional structure formed by laser annealing or the like, the bonding or fusion method requires fewer steps, so the manufacturing yield can be increased.

(4) Connect the first board to the sensor IC (A,, A2, A3
), the second board is a memory IC (B,,B,,B3), and the third board is
By separately designing the first board with calculation ICs (cx, Cz, C3), the fourth board with comparison ICs (Dl, D, , Dl), etc., and combining them appropriately, it is possible to achieve different performances and functions. It is possible to construct a three-dimensional device, increasing the degree of freedom in design.

(5) Application of this three-dimensional device will enable high functionality and high integration through parallel processing in fields such as microprocessors that process large amounts of information. Further, it is possible to provide an intelligent sensor with multiple sensor functions at a relatively low cost.

Incidentally, when attempting to increase the integration of planar ICs, the following problems arise. Namely.

■Higher integration leads to longer wiring lengths, which causes signal delays and attenuation.

■If you try to form device configurations with different structures on the same semiconductor main surface, it will be difficult because the processes are different, such as in the case of sensors.

■Since the layout is done within a plane, there is less freedom in cell placement.

(2) Parallel processing of signals is more difficult than in three-dimensional devices. (1) By using a three-dimensional device using a semiconductor substrate having the structure of the present invention, the above-mentioned problems of planar ICs can be significantly alleviated.

Because of the useful features described above, the three-dimensional device according to the present invention can be effectively utilized in fields such as intelligent sensors and large-capacity signal processing ICs for parallel processing.

[Brief explanation of the drawing]

FIG. 1 shows an embodiment of the present invention, and is a cross-sectional view of a device in which a MOS transistor on the main surface of the substrate and the back wiring are interconnected in a low-resistance ohmic region using a semiconductor substrate having a recess on the back surface. is another embodiment of the present invention, showing a semiconductor substrate of the present invention having a recessed portion on the back surface and another CMO.
A cross-sectional view of a three-dimensional device in which a substrate including an S inverter and the like is fused together; FIG. 3 is an example of a configuration with multiple wirings in one recess; FIG. FIG. 5 is an example diagram of a three-dimensional structure in which four layers of semiconductor substrates of the present invention are stacked. <Explanation of symbols> 1. IA...Semiconductor substrate 2. 2'...Field oxide film 3...Back surface insulating film 4...Thin Si layer 5.
...Isolation insulating film 6...Low resistance ohmic regions 7A, 7B...Backside electrode wiring 8...0+ source 9...n+ drain 11...Si gate 12A, 12B...main surface Electrode wiring 13...SO
Si crystal film in I 14-8 5in2 film for OI 15-n+source 16
...n1 drain 17...gate oxide film 1
8...Si gate 19...source wiring 20...
Drain wiring 21A...Contact part 21B of back side active device terminal electrode...Leaning part 2 of back side active device terminal electrode
2...Concave portion 3B...Interlayer insulating film 39 on the back surface of the upper substrate...Glabella insulating film 43A on the lower substrate...CMOS gate junction electrode 43B on the lower semiconductor substrate...Other parts on the lower substrate Electrode 44... Polyimide layer for upper substrate 45... Polyimide layer for lower substrate 46U, 47U... Au alloy two-layer electrode for fusion for upper substrate 46L, 47L... Au alloy two for fusion for lower substrate Heavy electrode 3... Separation insulating film 54... Semiconductor substrate 55... Insulating film 56 on the back surface with recess 22...
Insulating film 57 on the main surface...Low resistance ohmic region 58A...Contact part 58B of back electrode...Leading part 59A of back electrode...Contact part 59B of main surface electrode... Pull-out parts 71, 74...semiconductor substrate 10]...upper first semi-dedicated substrate I02...lower second semiconductor substrate

Claims (1)

[Claims] In a structure in which at least one semiconductor layer is arranged substantially parallel to the substrate surface on a plate-shaped semiconductor substrate, at least one recess is provided in a part of the back surface of the semiconductor substrate opposite to the main surface on which the active device is formed. is formed, at least one low resistance ohmic region reaching from the main surface to the bottom of the recess is formed, a separation layer is formed around the low resistance ohmic region, and a separation layer is formed on the main surface side of the low resistance ohmic region. At least one layer of low-resistance wiring member insulated from other parts is formed from the terminal end, that is, the contact part on the main surface side, to a desired location on the main surface side, and The inner surface of the recess excluding the contact portion on the bottom side of the recess and a desired portion of the back surface of the semiconductor substrate are covered with an insulating film, and a predetermined portion of the back surface of the semiconductor substrate is coated on the insulating film from the contact portion on the bottom side of the recess. The semiconductor substrate has a structure in which at least one layer of low resistance member for wiring is insulated from the semiconductor substrate, and the main surface side and the back side of the semiconductor substrate are ohmically coupled via the low resistance ohmic region. A semiconductor device characterized by: