JP2008053429A

JP2008053429A - Semiconductor device

Info

Publication number: JP2008053429A
Application number: JP2006227747A
Authority: JP
Inventors: Masanobu Saruta; 正暢猿田; Tatsuo Suemasu; 龍夫末益
Original assignee: Fujikura Ltd
Current assignee: Fujikura Ltd
Priority date: 2006-08-24
Filing date: 2006-08-24
Publication date: 2008-03-06

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device improved in the reliability of electric connection between a conduction and an electrode, by preventing damage such as the destruction of the conduction part, disconnection of the electrode or the like. <P>SOLUTION: The semiconductor device 1 includes an electrode unit 3 arranged on one side surface 2a of a substrate 2, a through hole 4 provided in the substrate so as to expose at least a part of the electrode unit from the other side surface 2b of the substrate, and a conduction unit 7 arranged so as to cover the side surface in the through hole and the exposed electrode unit while being connected electrically to the electrode unit. In this case, the sectional configuration R of the conduction unit is the shape of arc or a polygonal shape at a corner whereat the inside surface of the through hole is intersected with the electrode unit. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

本発明は、貫通電極を備えた半導体装置に係る。より詳細には、貫通電極を構成する導電部と電極部との電気的な接続信頼性に優れた半導体装置に関する。 The present invention relates to a semiconductor device provided with a through electrode. More specifically, the present invention relates to a semiconductor device having excellent electrical connection reliability between a conductive portion and an electrode portion constituting a through electrode.

近年、携帯電話等の電子機器の高機能化が進み、これらの機器に用いられるＩＣやＬＳＩ等の電子デバイス、及びＯＥＩＣや光ピックアップ等の光デバイスにおいて、デバイス自体の小型化や高機能化を図るための開発が各所で進められている。例えば、このようなデバイスを積層して設ける技術が提案されており、具体的には、何らかの機能素子が一方の面に設けられている基板に対し、該基板の一方の面から他方の面に貫通してなる貫通電極を用いる技術が挙げられる。 In recent years, electronic devices such as mobile phones have been improved in functionality, and in electronic devices such as ICs and LSIs and optical devices such as OEICs and optical pickups used in these devices, the devices themselves have been reduced in size and functionality. Development for planning is underway at various locations. For example, a technique of stacking such devices has been proposed. Specifically, a substrate on which one functional element is provided on one surface is provided from one surface of the substrate to the other surface. A technique using a penetrating electrode that penetrates may be mentioned.

また、こられの基板の配線材料として、銅や銀等が次世代材料として期待されている。特に、銅は比抵抗が低いこと、エレクトロマイグレーション耐性がアルミニウム系合金に比べて高いこと、銀に比べて安価である等の理由により、最も期待され、配線材料として用いられている。 In addition, copper, silver, and the like are expected as next-generation materials as wiring materials for these substrates. In particular, copper is most expected and used as a wiring material because of its low specific resistance, high electromigration resistance compared to aluminum alloys, and low cost compared to silver.

図１０は、従来の基板を用いた半導体装置の一例を概略説明する部分断面図である。
図１０に示す半導体装置１０１においては、セラミックスやシリコン等の硬質材からなる基板１０２と、基板１０２の両面を貫通して設けられた貫通孔１０４と、貫通孔１０４の孔内に充填され、銅材等からなる導電部１０７と、貫通孔１０４内に露呈するようにして半導体基板１０２の一方の面１０２ａに配される電極部１０３と、半導体基板１０２上に配されるＩＣチップや光素子等の機能素子１１０と、基板１０２の一方の面１０２ａ上において電極部１０３および機能素子１１０と電気的に接続されてなる配線部１０９とから概略構成されている。ここで、１０８は貫通電極と呼ぶことにする。 FIG. 10 is a partial cross-sectional view schematically illustrating an example of a semiconductor device using a conventional substrate.
In the semiconductor device 101 shown in FIG. 10, a substrate 102 made of a hard material such as ceramics or silicon, a through hole 104 provided through both surfaces of the substrate 102, a hole filled in the through hole 104, and copper A conductive portion 107 made of a material, an electrode portion 103 disposed on one surface 102a of the semiconductor substrate 102 so as to be exposed in the through hole 104, an IC chip, an optical element, etc. disposed on the semiconductor substrate 102 The functional element 110 and a wiring portion 109 electrically connected to the electrode portion 103 and the functional element 110 on one surface 102 a of the substrate 102 are roughly configured. Here, 108 is referred to as a through electrode.

半導体基板１０２は、電極部１０３と機能素子１１０との間が配線部１０９によって電気的に接続されているとともに、電極部１０３と電気的に接続された導電部１０７を介して基板両面（一方の面１０２ａと他方の面１０２ｂ）が電気的に接続可能となっている。 The semiconductor substrate 102 is electrically connected between the electrode portion 103 and the functional element 110 by the wiring portion 109, and both surfaces of the substrate (one of the substrates) via the conductive portion 107 electrically connected to the electrode portion 103. The surface 102a and the other surface 102b) can be electrically connected.

例えば、図１０に示すような半導体装置１０１を製造する場合は、半導体基板１０２に予め貫通孔１０４を形成し、この貫通孔１０４の内側面と半導体基板１０２の両面１０２ａ、１０２ｂとを覆う絶縁部１０５、１０６を設ける。この絶縁部１０６で被覆された貫通孔１０４に銅メッキ等により導電部１０７の形成を行う。このとき、貫通孔内部を金属で完全充填せずにメッキを終了させるコンフォーマルメッキによる導電部形成が行われている。この銅メッキ処理によって基板１０２の両面１０２ａ、１０２ｂを貫通してなる導電部１０７を形成することにより、半導体装置１０１が得られる。 For example, when manufacturing the semiconductor device 101 as shown in FIG. 10, a through hole 104 is formed in the semiconductor substrate 102 in advance, and an insulating portion that covers the inner side surface of the through hole 104 and both surfaces 102 a and 102 b of the semiconductor substrate 102. 105 and 106 are provided. A conductive portion 107 is formed in the through hole 104 covered with the insulating portion 106 by copper plating or the like. At this time, the conductive portion is formed by conformal plating that finishes plating without completely filling the inside of the through hole with metal. By forming the conductive portion 107 penetrating the both surfaces 102a and 102b of the substrate 102 by this copper plating process, the semiconductor device 101 is obtained.

また、導電部１０７を形成した後、半導体基板１０２の表面上に形成した銅メッキ層をパターニングすることで、配線部として使用することができ、その配線部の保護層として樹脂を基板表面に塗布して用いている（例えば、特許文献１，２，３を参照）。 In addition, after forming the conductive portion 107, the copper plating layer formed on the surface of the semiconductor substrate 102 is patterned so that it can be used as a wiring portion, and a resin is applied to the substrate surface as a protective layer for the wiring portion. (See, for example, Patent Documents 1, 2, and 3).

しかしながら、導電部と貫通孔内壁との密着性の面で、貫通孔形状や密着強度のバラツキにより熱履歴後の剥離等、信頼性の低下が懸念されている。
例えば、導電部形成工程の後に、熱プロセスを含む工程が有る場合、導電部の膨張破壊およびこれに伴う電極部の断線、更にはウエハ（基板）の破断が生じる虞があった。
このような導電部の破壊や電極部の断線等の損傷は、導電部と電極部との電気的な接続信頼性を低下させる原因となってしまう。
特開平５−１７５６５２号公報特開平１１−３５４６７１号公報特開２００１−３３９１６５号公報 However, in terms of the adhesion between the conductive part and the inner wall of the through hole, there is a concern about reliability degradation such as peeling after thermal history due to variations in the shape of the through hole and the adhesion strength.
For example, when there is a step including a thermal process after the conductive portion forming step, there is a possibility that expansion failure of the conductive portion, disconnection of the electrode portion accompanying this, and breakage of the wafer (substrate) may occur.
Such damage such as destruction of the conductive part or disconnection of the electrode part causes a decrease in the reliability of electrical connection between the conductive part and the electrode part.
Japanese Patent Laid-Open No. 5-175652 Japanese Patent Laid-Open No. 11-354671 JP 2001-339165 A

本発明は、このような実情に鑑みて考案されたものであり、貫通電極を構成する導電部の破壊や電極部の断線等の損傷を防止して、導電部と電極部との電気的な接続信頼性の向上を図った半導体装置を提供することを目的とする。 The present invention has been devised in view of such a situation, and prevents electrical damage between the conductive portion and the electrode portion by preventing damage to the conductive portion constituting the through electrode and breakage of the electrode portion. An object is to provide a semiconductor device with improved connection reliability.

本発明の請求項１に記載の半導体装置は、基板の一方の面に配された電極部と、前記基板の他方の面から前記電極部の少なくとも一部が露呈するように、前記基板内に設けられた貫通孔と、前記貫通孔内の側面および露呈された前記電極部を覆うように配され、前記電極部と電気的に接続される導電部と、を備え、前記貫通孔の内側面と前記電極部とが交わる角部において、前記導電部の断面形状が、円弧状または多角状であることを特徴とする。
本発明の請求項２に記載の半導体装置は、請求項１において、前記角部における前記導電部の厚さｄは、前記貫通孔内の他の部位における導電部の厚さに比べて厚くなっていることを特徴とする。
本発明の請求項３に記載の半導体装置は、請求項２において、前記ｄは、前記貫通孔内の他の部位における導電部の厚さの１．２倍以上、３．０倍以下であることを特徴とする。
本発明の請求項４に記載の半導体装置は、請求項１において、前記角部における導電部は、その内面および外面とも円弧状をなしており、前記貫通孔の内側面と前記電極部との交点である第一の点は、前記貫通孔の内側面に配された導電部の延長線と前記電極部との交点である第二の点よりも、貫通孔の中央側にあることを特徴とする。 According to a first aspect of the present invention, there is provided a semiconductor device comprising: an electrode portion disposed on one surface of a substrate; and at least a part of the electrode portion exposed from the other surface of the substrate. An inner surface of the through-hole, comprising: a through-hole provided; and a conductive portion arranged to cover the side surface in the through-hole and the exposed electrode portion and electrically connected to the electrode portion. In the corner portion where the electrode portion and the electrode portion intersect, the cross-sectional shape of the conductive portion is an arc shape or a polygonal shape.
A semiconductor device according to a second aspect of the present invention is the semiconductor device according to the first aspect, wherein the thickness d of the conductive portion at the corner is thicker than the thickness of the conductive portion at another portion in the through hole. It is characterized by.
According to a third aspect of the present invention, in the semiconductor device according to the second aspect, the d is not less than 1.2 times and not more than 3.0 times the thickness of the conductive portion in the other part in the through hole. It is characterized by that.
A semiconductor device according to a fourth aspect of the present invention is the semiconductor device according to the first aspect, wherein the conductive portion in the corner portion has an arc shape on both the inner surface and the outer surface, and the inner surface of the through hole and the electrode portion The first point that is the intersection is located closer to the center of the through hole than the second point that is the intersection between the extension line of the conductive part arranged on the inner surface of the through hole and the electrode part. And

本発明では、貫通孔の角部における導電部の形状を制御することで、導電部の破壊や電極部の断線等の損傷を防止して、導電部と電極部との電気的な接続信頼性を向上した半導体装置を提供することができる。 In the present invention, by controlling the shape of the conductive portion at the corner portion of the through hole, it is possible to prevent damage to the conductive portion and breakage of the electrode portion, and reliability of electrical connection between the conductive portion and the electrode portion. It is possible to provide a semiconductor device with improved characteristics.

以下、本発明に係る半導体装置の一実施形態を図面に基づいて説明する。 Hereinafter, an embodiment of a semiconductor device according to the present invention will be described with reference to the drawings.

図１は、本発明の半導体装置の一例を示す断面図である。
半導体装置１は、半導体基板２の一方の面２ａに配され、この一方の面２ａにある機能素子１０と配線部９を介して電気的に接続された電極部３と、半導体基板２の他方の面２ｂ側から電極部３が露呈するように配された貫通孔４と、半導体基板２と電極部３との間に配され両者を電気的に絶縁する第一絶縁層５と、貫通孔４の内壁面および開口部周辺に配された第二絶縁層６と、この第二絶縁層６上に配され前記電極部３と電気的に接続される導電部７と、を備える。
このように、半導体基板２の一方の面２ａから他方の面２ｂに向かう貫通孔４が形成され、この貫通孔４に第二絶縁層６を介して導電部７を設けることにより貫通電極８が形成されている。 FIG. 1 is a cross-sectional view showing an example of a semiconductor device of the present invention.
The semiconductor device 1 is disposed on one surface 2 a of the semiconductor substrate 2, the electrode unit 3 electrically connected to the functional element 10 on the one surface 2 a via the wiring unit 9, and the other of the semiconductor substrate 2. A through hole 4 disposed so that the electrode portion 3 is exposed from the surface 2b side of the first insulating layer 5 disposed between the semiconductor substrate 2 and the electrode portion 3 to electrically insulate the two, and a through hole 4 includes a second insulating layer 6 disposed on the inner wall surface and the periphery of the opening, and a conductive portion 7 disposed on the second insulating layer 6 and electrically connected to the electrode unit 3.
Thus, a through hole 4 is formed from one surface 2 a of the semiconductor substrate 2 to the other surface 2 b, and the through electrode 8 is formed by providing the through hole 4 with the conductive portion 7 through the second insulating layer 6. Is formed.

そして本発明の半導体装置１は、図２および図３に拡大して示すように、前記貫通孔４の内側面と前記電極部３とが交わる角部において、前記導電部６の断面形状Ｒ、Ａが、円弧状（図２参照）または多角状（図３参照）であることを特徴とする。
本発明では、貫通孔４の底部における導電部６の形状を制御することで、貫通孔４の形状によらず、熱変化等により角部にかかる応力を分散、緩和することができる。その結果、角部における導電部６の破壊ひいては電極部の断線等の損傷を防止して、導電部６および電極部３における電気的な接続信頼性を向上することができる。 2 and 3, the semiconductor device 1 of the present invention has a cross-sectional shape R of the conductive portion 6 at the corner where the inner surface of the through hole 4 and the electrode portion 3 intersect, A is characterized in that it is arcuate (see FIG. 2) or polygonal (see FIG. 3).
In the present invention, by controlling the shape of the conductive portion 6 at the bottom of the through hole 4, the stress applied to the corner portion due to thermal change or the like can be dispersed and relaxed regardless of the shape of the through hole 4. As a result, the electrical connection reliability in the conductive part 6 and the electrode part 3 can be improved by preventing breakage of the conductive part 6 in the corner part and thus damage such as disconnection of the electrode part.

図１１および図１２は、従来の半導体装置（図１０）において、貫通孔１０４の前記角部を拡大したものである。図１１に示すように、導電部１０７の内側面の形状が直線同士一点で交わるような形状（矢印Ｘで示した箇所の形状）の場合、あるいは図１２のように内壁と底面との接点に向かって導電部１０７の厚さが薄くなっているような形状（矢印Ｙで示した箇所の形状）の場合は、熱をかけた場合の応力が角部に集中するため、導電部１０７の破壊ひいては電極部１０３の断線等の損傷が発生しやすい。その結果、導電部１０７および電極部１０３における電気的な接続信頼性が低下してしまう。 11 and 12 are enlarged views of the corner portion of the through hole 104 in the conventional semiconductor device (FIG. 10). As shown in FIG. 11, when the shape of the inner surface of the conductive portion 107 intersects at a single point between the straight lines (the shape indicated by the arrow X), or at the contact point between the inner wall and the bottom surface as shown in FIG. In the case of a shape in which the thickness of the conductive portion 107 is becoming thinner (the shape of the portion indicated by the arrow Y), the stress when heat is applied is concentrated on the corner portion. As a result, damage such as disconnection of the electrode portion 103 is likely to occur. As a result, the electrical connection reliability in the conductive portion 107 and the electrode portion 103 is lowered.

一方、図２に示すように、前記角部における導電部６の断面形状が円弧状、あるいは図３に示すように貫通孔４の内側に向かって厚く形成された多角状である場合には、熱変化等により角部にかかる応力を分散、緩和することができる。その結果、角部における導電部６の破壊ひいては電極部３の断線等の損傷を防止して、導電部６および電極部３における電気的な接続信頼性を向上することができる。 On the other hand, as shown in FIG. 2, when the cross-sectional shape of the conductive portion 6 at the corner is an arc shape or a polygon formed thick toward the inside of the through hole 4 as shown in FIG. It is possible to disperse and relieve the stress applied to the corners due to thermal changes or the like. As a result, the electrical connection reliability in the conductive part 6 and the electrode part 3 can be improved by preventing breakage of the conductive part 6 at the corners and thus damage such as disconnection of the electrode part 3.

さらに、前記角部における前記導電部６の厚さｄは、前記貫通孔４内の他の部位における導電部６の厚さ（図２および図３に示すように、貫通孔４の内壁における導電部６の厚さａおよび孔底部における導電部６の厚さｂ）に比べて厚くなっていることが好ましい。角部における前記導電部６の厚さｄを、他の部位よりも厚くすることで、他の部位が薄くても、熱変化等により角部にかかる応力を分散し、導電部６の破壊ひいては電極部３の断線等の損傷を抑制する効果が得られる。 Furthermore, the thickness d of the conductive portion 6 at the corner portion is the thickness of the conductive portion 6 at other portions in the through hole 4 (as shown in FIGS. It is preferable that the thickness is larger than the thickness a of the portion 6 and the thickness b) of the conductive portion 6 at the bottom of the hole. By making the thickness d of the conductive part 6 at the corners thicker than other parts, even if the other parts are thin, the stress applied to the corners is dispersed due to thermal changes or the like. The effect which suppresses damage, such as a disconnection of the electrode part 3, is acquired.

具体的に、前記ｄは、前記貫通孔４内の他の部位における導電部３の厚さの１．２倍以上、３．０倍以下であることが好ましい。
前記ｄが、他の部位における導電部６の厚さの１．２倍以下では、熱変化等により角部にかかる応力を分散し、導電部６の破壊ひいては電極部３の断線等の損傷を抑制する効果が十分に得られない。一方、３．０倍を超えると、応力集中による電極部３への亀裂発生を抑制することが困難となる。１．２倍以上、３．０倍以下とすることで、熱変化等により角部にかかる応力をより効果的に分散し、導電部６の損傷を抑制するとともに、応力集中による電極部３のへの亀裂発生をより確実に抑制することができる。その結果、導電部６および電極部３における電気的な接続信頼性をより向上することができる。 Specifically, the d is preferably 1.2 times or more and 3.0 times or less the thickness of the conductive portion 3 in another part in the through hole 4.
If d is 1.2 times or less the thickness of the conductive part 6 in other parts, the stress applied to the corners is dispersed due to thermal change or the like, and the conductive part 6 is broken and thus the electrode part 3 is broken. The inhibitory effect cannot be obtained sufficiently. On the other hand, if it exceeds 3.0 times, it will be difficult to suppress the generation of cracks in the electrode part 3 due to stress concentration. By setting it to 1.2 times or more and 3.0 times or less, the stress applied to the corners due to thermal change or the like is more effectively dispersed, and the damage of the conductive part 6 is suppressed, and the electrode part 3 due to stress concentration is suppressed. It is possible to more reliably suppress the occurrence of cracks. As a result, the electrical connection reliability in the conductive part 6 and the electrode part 3 can be further improved.

また、図４に示すように、前記角部における導電部６は、その内面および外面とも円弧状をなしており、前記貫通孔４の内側面と前記電極部３との交点である第一の点Ｐ_１は、前記貫通孔４の内側面に配された導電部６の延長線と前記電極部３との交点である第二の点Ｐ_２よりも、貫通孔４の中央側にあることが好ましい。
これにより、熱変化等により角部にかかる応力をより効果的に分散し、導電部６の損傷を抑制するとともに、応力集中による電極部３のへの亀裂発生をより確実に抑制することができる。その結果、導電部６および電極部３における電気的な接続信頼性をさらに向上することができる。 As shown in FIG. 4, the conductive portion 6 in the corner portion has an arc shape on both the inner surface and the outer surface, and is a first intersection that is the intersection of the inner surface of the through hole 4 and the electrode portion 3. The point P ₁ is located closer to the center of the through hole 4 than the second point P _2, which is the intersection of the extension line of the conductive part 6 disposed on the inner surface of the through hole 4 and the electrode part 3. Is preferred.
As a result, the stress applied to the corners due to thermal changes or the like can be more effectively dispersed, the damage to the conductive part 6 can be suppressed, and the occurrence of cracks in the electrode part 3 due to the stress concentration can be more reliably suppressed. . As a result, the electrical connection reliability in the conductive portion 6 and the electrode portion 3 can be further improved.

図１に例示するように半導体装置１は、半導体基板２の一方の面２ａに配され、この一方の面２ａにある機能素子１０と電気的に接続された電極部３と、半導体基板２の他方の面２ｂ側から電極部３が露呈するように配された貫通孔４と、半導体基板２と電極部３との間に配され両者を電気的に絶縁する第一絶縁層５と、貫通孔４の内壁面および開口部周辺（半導体基板２の他方の面２ｂ側）に配された第二絶縁層６と、この第二絶縁層６上に配され前記電極部３と電気的に接続される導電部７と、を備える。
このように、半導体基板２の一方の面２ａから他方の面２ｂに向かう貫通孔４が形成され、この貫通孔４に第二絶縁層６を介して導電部７を設けることにより貫通電極８が形成されている。 As illustrated in FIG. 1, the semiconductor device 1 is disposed on one surface 2 a of the semiconductor substrate 2, and an electrode portion 3 electrically connected to the functional element 10 on the one surface 2 a and the semiconductor substrate 2. A through hole 4 disposed so that the electrode portion 3 is exposed from the other surface 2b side, a first insulating layer 5 disposed between the semiconductor substrate 2 and the electrode portion 3 to electrically insulate the two, and a through hole A second insulating layer 6 disposed on the inner wall surface of the hole 4 and the periphery of the opening (on the other surface 2b side of the semiconductor substrate 2), and disposed on the second insulating layer 6 and electrically connected to the electrode unit 3 A conductive portion 7.
Thus, a through hole 4 is formed from one surface 2 a of the semiconductor substrate 2 to the other surface 2 b, and the through electrode 8 is formed by providing the through hole 4 with the conductive portion 7 through the second insulating layer 6. Is formed.

基板２は、硬質材料の基材であり、例えばシリコン（Ｓｉ）等からなる導電性の半導体基材、あるいは絶縁性のガラス基材やセラミック基材、等が挙げられる。
基板２の厚さは、例えば数百μｍ程度である。
図１には、基板２をＳｉ等の半導体基材から構成し、基板２の一方の面２ａと電極部３との間には第一絶縁層５を、基板２に設けた貫通孔４と導電部７との間には第二絶縁層６をそれぞれ配し、基板２と導電部７とを電気的に絶縁した構成例を示しているが、基板２として半導体基材に代えて上述した絶縁性材料を採用する場合には、貫通孔４内の側面が絶縁体なので、貫通孔４と導電部６とが直接に接する構成（不図示）としてもよい。 The substrate 2 is a hard material base, and examples thereof include a conductive semiconductor base made of silicon (Si) or the like, or an insulating glass base or ceramic base.
The thickness of the substrate 2 is, for example, about several hundred μm.
In FIG. 1, the substrate 2 is made of a semiconductor base material such as Si, and a first insulating layer 5 is provided between one surface 2 a of the substrate 2 and the electrode portion 3, and through holes 4 provided in the substrate 2. Although the 2nd insulating layer 6 is distribute | arranged between the electroconductive parts 7 and the board | substrate 2 and the electroconductive part 7 are electrically insulated, the structural example is shown instead of the semiconductor base material as the board | substrate 2 mentioned above. In the case where an insulating material is employed, since the side surface in the through hole 4 is an insulator, the through hole 4 and the conductive portion 6 may be in direct contact with each other (not shown).

貫通孔４は、図１に示すように、基板２において、他方の面２ｂから一方の面２ａに配された後述する電極部３が孔内に露呈するように、基板２内に開けられてなる。
貫通孔４の口径は、例えば数十μｍ程度である。
また、基板２上に設けられる貫通孔４の数は、特に限定されない。 As shown in FIG. 1, the through hole 4 is opened in the substrate 2 so that an electrode portion 3 (described later) arranged from the other surface 2 b to the one surface 2 a is exposed in the hole. Become.
The diameter of the through hole 4 is, for example, about several tens of μm.
Further, the number of through holes 4 provided on the substrate 2 is not particularly limited.

電極部３は、基板２の一方の面２ａに設けられ、露呈部が貫通孔４の一方の開口部から孔内に露呈するようにして設けられている。
電極部３は、後述の配線回路８を介して、該一方の面内にある後述の機能素子９と電気的に接続されている。
電極部３の材質としては、例えばアルミニウム（Ａｌ）や銅（Ｃｕ）、アルミニウム−シリコン（Ａｌ−Ｓｉ）合金、アルミニウム−シリコン−銅（Ａｌ−Ｓｉ−Ｃｕ）合金等の導電性に優れる材質が好適に用いられる。 The electrode portion 3 is provided on one surface 2 a of the substrate 2, and the exposed portion is provided so as to be exposed in the hole from one opening portion of the through hole 4.
The electrode unit 3 is electrically connected to a later-described functional element 9 in the one surface via a later-described wiring circuit 8.
Examples of the material of the electrode part 3 include materials having excellent conductivity such as aluminum (Al), copper (Cu), aluminum-silicon (Al-Si) alloy, and aluminum-silicon-copper (Al-Si-Cu) alloy. Preferably used.

機能素子９は、本実施形態では、例えばＩＣチップや、ＣＣＤ素子等の光素子からなる。
また、機能素子９の他の例としては、例えばマイクロリレー、マイクロスイッチ、圧力センサ、加速度センサ、高周波フィルタ、マイクロミラー、マイクロリアクター、μ−ＴＤＳ、ＤＮＡチップ、ＭＥＭＳデバイス、マイクロ燃料電池等が挙げられる。 In the present embodiment, the functional element 9 is composed of an optical element such as an IC chip or a CCD element.
Other examples of the functional element 9 include a micro relay, a micro switch, a pressure sensor, an acceleration sensor, a high frequency filter, a micro mirror, a micro reactor, a μ-TDS, a DNA chip, a MEMS device, a micro fuel cell, and the like. It is done.

導電部６は、貫通孔４内の側面の少なくとも一部に配されることにより、導電体として有効に働く。
図１の断面図に示す例では、導電部６は、側面の全体を覆うように配されているが、これには限定されない。例えば、導電部６が、側面の一部に、基板２の一方の面２ａと他方の面２ｂとの間に渡って配された構成としてもよい。
導電部６の材質としては、導電性に優れた材料を用いることが好ましい。また、導電部６は、電極との密着性に優れるとともに、導電部６を構成する元素が電極や基板２内に拡散しない材料を用いれば、さらに好ましい。
例えば、図１に示すように導電部６が単層である場合には、電極と同材料であることが望ましく、Ａｌ、Ｃｕ、Ｎｉ、Ａｕ等の金属材料を用いれば、導電性や電極との密着性等の点で好ましい。
また、導電部６を、２種類以上の金属材料からなる多層構造、あるいは材料の異なる膜を積層した構造とした場合、外側の層には、電極をなす材質との密着性に優れる材料や、導電部６と、電極または基板２との間で元素移動（拡散）が生じるのを防止できる金属材料（バリアメタル）を配し、内側の層には、導電性の高い金属を配した構成とすることが好ましい。 The conductive part 6 works effectively as a conductor by being disposed on at least a part of the side surface in the through hole 4.
In the example shown in the cross-sectional view of FIG. 1, the conductive portion 6 is disposed so as to cover the entire side surface, but is not limited thereto. For example, the conductive part 6 may be configured to be disposed on a part of the side surface between the one surface 2 a and the other surface 2 b of the substrate 2.
As the material of the conductive portion 6, it is preferable to use a material having excellent conductivity. Further, it is more preferable that the conductive part 6 is made of a material that is excellent in adhesiveness with the electrode and that does not diffuse into the electrode or the substrate 2.
For example, when the conductive portion 6 is a single layer as shown in FIG. 1, it is desirable to use the same material as the electrode. If a metal material such as Al, Cu, Ni, Au is used, the conductivity and the electrode It is preferable in terms of adhesion.
In addition, when the conductive portion 6 has a multilayer structure composed of two or more kinds of metal materials, or a structure in which films of different materials are laminated, a material having excellent adhesion with the material forming the electrode, A metal material (barrier metal) that can prevent element movement (diffusion) from occurring between the conductive portion 6 and the electrode or the substrate 2 is arranged, and a metal having high conductivity is arranged in the inner layer. It is preferable to do.

配線回路８は、基板２上に配され、電極部３や機能素子９等を電気的に接続して回路をなす。
配線回路８の材質としては、電極部３と同様の材料を用いればよく、例えばアルミニウム（Ａｌ）や銅（Ｃｕ）、アルミニウム−シリコン（Ａｌ−Ｓｉ）合金、アルミニウム−シリコン−銅（Ａｌ−Ｓｉ−Ｃｕ）合金等の導電性に優れる材質が好適に用いられる。 The wiring circuit 8 is arranged on the substrate 2 and electrically connects the electrode unit 3 and the functional element 9 to form a circuit.
The material of the wiring circuit 8 may be the same material as that of the electrode part 3. For example, aluminum (Al), copper (Cu), aluminum-silicon (Al-Si) alloy, aluminum-silicon-copper (Al-Si). A material having excellent conductivity such as a (Cu) alloy is preferably used.

なお、本発明は、図５（ａ）、（ｂ）に示すように、貫通孔４の内壁形状が底部に対して垂直でない形状の場合についても同様で、図５（ｃ）、（ｄ）に示すように、孔底部の形状が貫通孔４の内側に向かって厚く形成された形状あるいは内側に曲線を持った形状の場合にも信頼性が向上する。
また図５（ｅ）、（ｆ）に示すように、貫通孔４の内壁における導電部６の厚さａと孔底部における導電部６の厚さｂとが異なっている場合も同様である。
また、図６に示すように貫通孔４を形成した基板２Ａに対して、孔底部側に別の基板２Ｂを貼り合わせた構造においても同様である。基板２Ａと基板２Ｂの貼り合せ方法は接着剤を用いたり、陽極接合を用いたりと一般的な接合方法が考えられる。 The present invention is the same in the case where the inner wall shape of the through hole 4 is not perpendicular to the bottom, as shown in FIGS. 5 (a) and 5 (b). As shown in FIG. 6, the reliability is improved even when the shape of the bottom of the hole is thicker toward the inner side of the through hole 4 or has a curved shape on the inner side.
The same applies to the case where the thickness a of the conductive portion 6 on the inner wall of the through hole 4 is different from the thickness b of the conductive portion 6 at the bottom of the hole, as shown in FIGS.
The same applies to a structure in which another substrate 2B is bonded to the bottom of the substrate 2A in which the through holes 4 are formed as shown in FIG. As a method for bonding the substrates 2A and 2B, general bonding methods such as using an adhesive or anodic bonding are conceivable.

次に、上述したような半導体装置１の製造方法について、図７および図８を用いて説明する。
まず、図７（ａ）に示すように、基板２を用意し、第一絶縁層５の形成されたその一方の面２ａに電極部３（Ｉ／Ｏパッド）を形成する。 Next, a method for manufacturing the semiconductor device 1 as described above will be described with reference to FIGS.
First, as shown in FIG. 7A, the substrate 2 is prepared, and the electrode portion 3 (I / O pad) is formed on the one surface 2a on which the first insulating layer 5 is formed.

基板２は、シリコンウエハ等の半導体ウエハでもよく、半導体ウエハをチップ寸法に切断（ダイシング）した半導体チップであってもよい。基板２が半導体チップである場合は、まず、半導体ウエハの上に、各種半導体素子やＩＣ、機能素子等を複数組、形成した後、チップ寸法に切断することで複数の半導体チップを得ることができる。また、基板２が半導体ウエハの場合には、電極部３と基板２の間には、絶縁層（例えばＳｉＯ_２）を形成してもよい。
電極部３としては、例えばＡｌパッドが用いられる。 The substrate 2 may be a semiconductor wafer such as a silicon wafer, or may be a semiconductor chip obtained by cutting (dicing) the semiconductor wafer into chip dimensions. When the substrate 2 is a semiconductor chip, first, a plurality of sets of various semiconductor elements, ICs, functional elements, etc. are formed on a semiconductor wafer and then cut into chip dimensions to obtain a plurality of semiconductor chips. it can. When the substrate 2 is a semiconductor wafer, an insulating layer (for example, SiO ₂ ) may be formed between the electrode unit 3 and the substrate 2.
As the electrode part 3, for example, an Al pad is used.

次いで、図７（ｂ）に示すように、基板２に、貫通孔４を形成する。
この貫通孔４は、前記基板２の他方の面２ｂ側から、前記電極部３が露呈するように形成される。孔の縦断面形状は、基板２の表面に対して９０°（垂直）であることが理想的だが、８０〜１００°程度であってもよい。
貫通孔４の形成にはドライエッチング、レーザー加工、ＰＡＥＣＥ（Photo Assisted Electro-Chemical Etching）など、孔を垂直に形成できる方法を用いることができる。
貫通孔４を、基板２に対して垂直に形成するため、後述する工程において、孔底面に形成された絶縁層５のエッチングの際に、側壁面に形成された絶縁層５がエッチングされないので、貫通電極と基板２との絶縁を確実に取ることができる。 Next, as illustrated in FIG. 7B, the through hole 4 is formed in the substrate 2.
The through hole 4 is formed so that the electrode part 3 is exposed from the other surface 2 b side of the substrate 2. The vertical cross-sectional shape of the hole is ideally 90 ° (perpendicular) with respect to the surface of the substrate 2, but may be about 80 to 100 °.
The through hole 4 can be formed by a method that can form the hole vertically, such as dry etching, laser processing, and PAECE (Photo Assisted Electro-Chemical Etching).
Since the through hole 4 is formed perpendicular to the substrate 2, the insulating layer 5 formed on the side wall surface is not etched when the insulating layer 5 formed on the bottom surface of the hole is etched in the process described later. Insulation between the through electrode and the substrate 2 can be ensured.

次いで、図７（ｃ）に示すように、少なくとも前記貫通孔４の内壁面および開口部周辺に第二絶縁層６を形成する。
この第一絶縁層５としては、例えばＳｉＯ_２をプラズマＣＶＤ等により成膜される。 Next, as shown in FIG. 7C, the second insulating layer 6 is formed at least around the inner wall surface of the through hole 4 and the opening.
As the first insulating layer 5, for example, SiO ₂ is formed by plasma CVD or the like.

次いで、図７（ｄ）に示すように、前述した第一絶縁層５のうち、前記貫通孔４の底面を覆う部分を除去する。
第一絶縁層５を設ける際には、孔底面にも第一絶縁層５が形成されてしまうため、孔底面を覆う部分のみをドライエッチング法によりエッチングして除去する。
孔底面の第一絶縁層５に対するエッチングは、イオン性の高い反応性イオンエッチング（ＲＩＥ）で行うことが一般的だが、物理的にイオンを照射するようなイオンミリングや逆スパッタのような方法も使用可能である。 Next, as shown in FIG. 7D, the portion of the first insulating layer 5 that covers the bottom surface of the through hole 4 is removed.
When the first insulating layer 5 is provided, since the first insulating layer 5 is also formed on the bottom surface of the hole, only the portion covering the bottom surface of the hole is etched and removed by the dry etching method.
Etching for the first insulating layer 5 at the bottom of the hole is generally performed by reactive ion etching (RIE) with high ionicity, but there are also methods such as ion milling and reverse sputtering in which ions are physically irradiated. It can be used.

貫通孔４は、基板２に対して略垂直に形成されているため、孔底面に形成された第一絶縁層５を除去する際に行われる、ドライプロセスのエッチングにおいて、側壁面に形成された絶縁層５はイオン照射を受けにくい（受けない）ためエッチングされない。これにより貫通電極８と基板２との絶縁を確実に取ることができる。 Since the through hole 4 is formed substantially perpendicular to the substrate 2, the through hole 4 is formed on the side wall surface in the dry process etching performed when the first insulating layer 5 formed on the bottom surface of the hole is removed. The insulating layer 5 is not etched because it is difficult (not) to receive ion irradiation. Thereby, insulation between the through electrode 8 and the substrate 2 can be surely taken.

次いで、図８に示すように、第一絶縁層５を覆うように、貫通孔４内に導電部７を形成するとともに、導電部７を電極部３と電気的に接続する。
導電部６の形成は、メッキなどで行うことができる。これにより半導体装置１が作製される。
このとき、メッキ液の基本組成や添加剤およびメッキ時間を制御することで、貫通孔４の内側面と電極部３とが交わる角部において、形成される導電部７の断面形状を、円弧状または多角状とすることができる。
例えば、メッキ液の基本組成は硫酸濃度に対して銅濃度が高くなるような、硫酸銅：１００〜５００ｇ／Ｌ、硫酸：２０〜１００ｇ／Ｌ、塩素イオン：１０〜１００ｍｇ／Ｌの範囲で建浴することが好ましい。 Next, as shown in FIG. 8, the conductive portion 7 is formed in the through hole 4 so as to cover the first insulating layer 5, and the conductive portion 7 is electrically connected to the electrode portion 3.
The conductive portion 6 can be formed by plating or the like. Thereby, the semiconductor device 1 is manufactured.
At this time, by controlling the basic composition of the plating solution, the additive, and the plating time, the cross-sectional shape of the conductive portion 7 formed at the corner where the inner surface of the through-hole 4 and the electrode portion 3 intersect is an arc shape. Or it can be polygonal.
For example, the basic composition of the plating solution is copper sulfate: 100 to 500 g / L, sulfuric acid: 20 to 100 g / L, and chloride ions: 10 to 100 mg / L so that the copper concentration is higher than the sulfuric acid concentration. It is preferable to bathe.

以上、本発明の半導体装置について説明してきたが、本発明は上記の例に限定されるものではなく、必要に応じて適宜変更が可能である。 Although the semiconductor device of the present invention has been described above, the present invention is not limited to the above example, and can be appropriately changed as necessary.

例えば、本発明は、機能素子の有無にかかわらず、貼り合わせ基板等についても適用可能である。また、貼り合わせのない基板に対してもこの方法は適用可能である。
また、本発明の半導体装置では、前記基板の他方の面側に、機能素子が配されていてもよい。機能素子が配されていない基板に対しても、この方法は適用できるが、基板の片面に機能素子が形成され、且つ、その機能素子が保護されているような基板に対しても適用可能である。 For example, the present invention can be applied to a bonded substrate or the like regardless of the presence or absence of a functional element. This method can also be applied to a substrate without bonding.
In the semiconductor device of the present invention, a functional element may be disposed on the other surface side of the substrate. This method can be applied to a substrate on which a functional element is not arranged, but can also be applied to a substrate in which the functional element is formed on one side of the substrate and the functional element is protected. is there.

（サンプル作製）
基板として、厚さが２００μｍ、大きさが６インチのシリコン半導体基板を用い、一方の面に電極、機能素子および配線回路を配した。電極としてＡｌパッドを用いた。
そして基板の他方の面から一方の面に配した電極が露呈するようにして、基板内に孔径が８０μｍの貫通孔をＤＲＩＥ（ドライエッチング処理）によって形成した。貫通孔内の側面には絶縁層として、ＳｉＯ_２の被膜を形成した。そして、貫通孔内の側面および電極の露呈部を覆うようにしてシード層を形成し、硫酸銅メッキによる導電部を形成後、導電部の内面に熱硬化性エポキシ樹脂を充填するように埋設して補強材を形成し、半導体装置を得た。 (Sample preparation)
A silicon semiconductor substrate having a thickness of 200 μm and a size of 6 inches was used as the substrate, and electrodes, functional elements, and wiring circuits were arranged on one surface. An Al pad was used as the electrode.
Then, a through hole having a hole diameter of 80 μm was formed in the substrate by DRIE (dry etching treatment) so that the electrode arranged on one surface was exposed from the other surface of the substrate. A SiO ₂ film was formed as an insulating layer on the side surface in the through hole. Then, a seed layer is formed so as to cover the side surface in the through hole and the exposed portion of the electrode, and after forming the conductive portion by copper sulfate plating, the inner surface of the conductive portion is embedded so as to be filled with a thermosetting epoxy resin. Thus, a reinforcing material was formed to obtain a semiconductor device.

なお、今回、メッキ液の基本組成を硫酸銅：２００ｇ／Ｌ、硫酸：５０ｇ／Ｌ、塩素イオン：５０ｍｇ／Ｌとしてメッキを行った。その結果、貫通孔底部における導電部の形状は、図３に示すような形状となった。 In addition, this time, plating was performed with the basic composition of the plating solution being copper sulfate: 200 g / L, sulfuric acid: 50 g / L, and chlorine ions: 50 mg / L. As a result, the shape of the conductive portion at the bottom of the through hole was as shown in FIG.

（導電部に働く応力についての考察）
上記硫酸銅メッキ工程において、メッキ液の基本組成や添加剤およびメッキ時間を調整することで、導電部の角部Ａにおける長さ（図３中、ｃで示す寸法）を変化させたサンプルを作製し、長さｃと角部（図３中、Ｂで示す部位）において導電部に働いている応力との関係を調査した。
ここでの応力とは、角部における導電部に働く、図３における横方向の圧縮、引っ張り応力である。温度を上昇させると導電部には圧縮応力がかかり、温度を下降させると引っ張り応力がかかる。 (Consideration of stress acting on conductive part)
In the copper sulfate plating step, a sample in which the length of the conductive portion at the corner A (the dimension indicated by c in FIG. 3) is changed by adjusting the basic composition, additives, and plating time of the plating solution. Then, the relationship between the length c and the stress acting on the conductive portion at the corner portion (portion indicated by B in FIG. 3) was investigated.
Here, the stress is the compressive and tensile stress in the lateral direction in FIG. 3 that acts on the conductive portion at the corner. When the temperature is raised, compressive stress is applied to the conductive portion, and when the temperature is lowered, tensile stress is applied.

図９に、一例として温度を１２５℃にした場合について、導電部の角部における長さＡと、導電部の角部において働く圧縮応力との関係をグラフにした。応力は２０℃のときの応力を０（ゼロ）とした相対値である。またグラフは省略するが、温度がマイナス（例えば−４０℃）の時には引っ張り応力として同様の関係があることがわかった。これらの応力は図３の横方向の力であるため、熱サイクルを繰り返すことによって導電部と基板間に剥離を引き起こす力が働き、信頼性を低下させる要因となる。 FIG. 9 is a graph showing the relationship between the length A at the corner of the conductive portion and the compressive stress acting at the corner of the conductive portion when the temperature is 125 ° C. as an example. The stress is a relative value with the stress at 20 ° C. being 0 (zero). Although the graph is omitted, it was found that when the temperature is negative (for example, −40 ° C.), the tensile stress has the same relationship. Since these stresses are lateral forces in FIG. 3, by repeating the thermal cycle, a force that causes peeling between the conductive portion and the substrate acts, which causes a decrease in reliability.

図９の結果から、Ａが０（ゼロ）つまり図１１に示すような形状より、図３に示すように内側に厚い多角状のほうが導電部にかかる圧縮応力が緩和されていることがわかる。この傾向は図５に示すような、貫通孔底部において内壁が垂直方向に対して±４５°以内の角度をもった形状や、内壁部と底面部とのメッキ厚が異なっている場合についても同様の効果が得られる。また、Ａは直線である必要は無く、図２に示すように全体が曲線あるいは一部が曲線であってもよい。 From the result of FIG. 9, it can be seen that A is 0 (zero), that is, the compressive stress applied to the conductive portion is relaxed in the thicker polygonal shape as shown in FIG. 3 than in the shape as shown in FIG. This tendency is the same as shown in FIG. 5 in the case where the inner wall has an angle within ± 45 ° with respect to the vertical direction at the bottom of the through-hole, or when the inner wall portion and the bottom surface have different plating thicknesses. The effect is obtained. Further, A need not be a straight line, and may be entirely curved or partially curved as shown in FIG.

（実施例１）
上記硫酸銅メッキ工程において、メッキ条件を調整する（添加剤の割合を減らす）ことで、貫通孔底部の角部における導電部の断面形状を、図２に示すような円弧状として、上記方法により半導体装置を作製した。 (Example 1)
In the copper sulfate plating step, by adjusting the plating conditions (decreasing the proportion of the additive), the cross-sectional shape of the conductive portion at the corner of the bottom of the through hole is changed to an arc shape as shown in FIG. A semiconductor device was manufactured.

（実施例２）
上記硫酸銅メッキ工程において、メッキ条件を調整する（添加剤の割合を変更する）ことで、貫通孔底部の角部における導電部の断面形状を、図３に示すような多角状として、上記方法により半導体装置を作製した。 (Example 2)
In the copper sulfate plating step, by adjusting the plating conditions (changing the ratio of the additive), the cross-sectional shape of the conductive portion at the corner of the bottom of the through hole is made polygonal as shown in FIG. Thus, a semiconductor device was manufactured.

（比較例）
上記硫酸銅メッキ工程において、メッキ条件を調整する（硫酸銅濃度をほぼ半減する）ことで、貫通孔底部の角部における導電部の断面形状を、図１１に示すような形状として、上記方法により半導体装置を作製した。 (Comparative example)
In the copper sulfate plating step, by adjusting the plating conditions (copper sulfate concentration is almost halved), the cross-sectional shape of the conductive portion at the corner of the bottom of the through hole is changed to the shape shown in FIG. A semiconductor device was manufactured.

（評価試験）
以上のようにして得られた各サンプルを、−４０℃：３０分、１２５℃：３０分の計１時間を１サイクルとして、熱サイクル試験を計１００サイクル：１００時間行った。
熱サイクル試験終了後、各サンプルの電極の破断の有無を、顕微鏡で観察、確認した。 (Evaluation test)
Each sample obtained as described above was subjected to a thermal cycle test for a total of 100 cycles: 100 hours, with a total of 1 hour at −40 ° C .: 30 minutes and 125 ° C .: 30 minutes as one cycle.
After the thermal cycle test, the presence or absence of breakage of the electrode of each sample was observed and confirmed with a microscope.

（評価結果）
本発明の半導体装置は、上記条件の熱サイクル試験を行った場合であっても、導電部や電極部の破断等が発生せず、初期状態に対して変化が見られなかった。実施例のサンプル２００台中、電極の破断が生じたサンプルは無かった。 (Evaluation results)
Even when the semiconductor device of the present invention was subjected to a thermal cycle test under the above conditions, the conductive portion and the electrode portion did not break, and no change was observed with respect to the initial state. Of the 200 samples of the example, there was no sample in which electrode breakage occurred.

一方、従来の半導体装置は、上記条件の熱サイクル試験を行った後、比較例のサンプル２４０台中、２００台に導電部や電極部の破断が生じた。
初期状態においては、導電部や電極部に破断は見られないが、熱サイクル試験後、電極面に、貫通孔および導電部に沿った円形の破断痕が生じている。また、電極部の導電部と接している部分と、基板に接触している部分とが完全に破断している。 On the other hand, in the conventional semiconductor device, after conducting the thermal cycle test under the above conditions, the conductive portion and the electrode portion were broken in 200 of the 240 samples of the comparative example.
In the initial state, no breakage is observed in the conductive portion and the electrode portion, but after the thermal cycle test, circular break marks along the through hole and the conductive portion are generated on the electrode surface. In addition, the portion of the electrode portion that is in contact with the conductive portion and the portion that is in contact with the substrate are completely broken.

以上の結果により、本発明に係る半導体装置が、熱サイクルや高温環境下において使用される場合であっても、基板材料と電極および導電部材料との間の熱膨張係数の差に起因して生じる熱ひずみに対し、角部における前記導電部の断面形状を、円弧状または多角状とすることで応力を緩和でき、電極の破断等が生じず、高い信頼性を有することが明らかとなった。 From the above results, even when the semiconductor device according to the present invention is used in a thermal cycle or a high temperature environment, it is caused by the difference in thermal expansion coefficient between the substrate material and the electrode and conductive part material. It was clarified that the stress can be relieved by making the cross-sectional shape of the conductive part at the corner part an arc shape or a polygonal shape with respect to the generated thermal strain, and the electrode is not broken and has high reliability. .

本発明は、貫通電極を備えた半導体装置に広く適用可能である。 The present invention is widely applicable to semiconductor devices provided with through electrodes.

本発明の半導体装置の一例を示す断面図である。It is sectional drawing which shows an example of the semiconductor device of this invention. 本発明の半導体装置において、導電部の角部を拡大して示す断面図である。In the semiconductor device of this invention, it is sectional drawing which expands and shows the corner | angular part of an electroconductive part. 本発明の半導体装置において、導電部の角部を拡大して示す断面図である。In the semiconductor device of this invention, it is sectional drawing which expands and shows the corner | angular part of an electroconductive part. 本発明の半導体装置において、導電部の角部を拡大して示す断面図である。In the semiconductor device of this invention, it is sectional drawing which expands and shows the corner | angular part of an electroconductive part. 本発明の半導体装置の他の一例を示す断面図である。It is sectional drawing which shows another example of the semiconductor device of this invention. 本発明の半導体装置の他の一例を示す断面図である。It is sectional drawing which shows another example of the semiconductor device of this invention. 図１に示す半導体装置の製造方法の一例を工程順に示す断面図である。FIG. 2 is a cross-sectional view showing an example of a method for manufacturing the semiconductor device shown in FIG. 図７に続く工程を示す断面図である。FIG. 8 is a cross-sectional view showing a step that follows FIG. 7. 角部において、導電部の長さと働く応力との関係を示すグラフである。It is a graph which shows the relationship between the length of an electroconductive part, and the stress which acts in a corner | angular part. 従来の半導体装置の一例を示す断面図である。It is sectional drawing which shows an example of the conventional semiconductor device. 従来の半導体装置において、導電部の角部を拡大して示す断面図である。In the conventional semiconductor device, it is sectional drawing which expands and shows the corner | angular part of an electroconductive part. 従来の半導体装置において、導電部の角部を拡大して示す断面図である。In the conventional semiconductor device, it is sectional drawing which expands and shows the corner | angular part of an electroconductive part.

Explanation of symbols

Ｒ断面形状、１半導体装置、２基板、３電極部、４貫通孔、５第一絶縁層、６第二絶縁層、７導電部、８貫通電極、９配線部、１０機能素子。
R cross-sectional shape, 1 semiconductor device, 2 substrate, 3 electrode part, 4 through hole, 5 first insulating layer, 6 second insulating layer, 7 conductive part, 8 through electrode, 9 wiring part, 10 functional element.

Claims

An electrode portion disposed on one surface of the substrate;
A through-hole provided in the substrate such that at least a part of the electrode portion is exposed from the other surface of the substrate;
A conductive portion disposed so as to cover the side surface in the through hole and the exposed electrode portion, and electrically connected to the electrode portion;
A semiconductor device, wherein a cross-sectional shape of the conductive portion is an arc shape or a polygonal shape at a corner portion where an inner surface of the through hole and the electrode portion intersect.

2. The semiconductor device according to claim 1, wherein a thickness d of the conductive portion at the corner portion is larger than a thickness of the conductive portion at another portion in the through hole.

3. The semiconductor device according to claim 2, wherein d is 1.2 times or more and 3.0 times or less the thickness of the conductive portion in another part in the through hole.

The conductive portion in the corner portion has an arc shape on the inner surface and the outer surface,
The first point that is the intersection of the inner surface of the through hole and the electrode part is the second point that is the intersection of the extension line of the conductive part arranged on the inner surface of the through hole and the electrode part. The semiconductor device according to claim 1, further comprising a central portion of the through hole.