JP2007096233A - Semiconductor device and manufacturing method therefor - Google Patents

Semiconductor device and manufacturing method therefor Download PDF

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JP2007096233A
JP2007096233A JP2005287075A JP2005287075A JP2007096233A JP 2007096233 A JP2007096233 A JP 2007096233A JP 2005287075 A JP2005287075 A JP 2005287075A JP 2005287075 A JP2005287075 A JP 2005287075A JP 2007096233 A JP2007096233 A JP 2007096233A
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electrode
substrate
hole
conductive portion
semiconductor device
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JP4593427B2 (en
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Masanobu Saruta
正暢 猿田
Tatsuo Suemasu
龍夫 末益
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Fujikura Ltd
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device that will not generate expansion failures, electrode disconnections and substrate damages, and that is superior in resistance to heat, and to provide a method for manufacturing the device. <P>SOLUTION: This semiconductor device has an electrode 4, which is placed on a surface 2a of a substrate 2 and is electrically connected to a function element 5 within the corresponding surface, a through-hole 3 drilled on the substrate 2, to expose the electrode 4 from the other surface 2b to the surface 2a on the substrate 2, a conductive region which is formed to cover the side 3a within the through-hole 3 and the exposed region 4a of the electrode 4 and is connected electrically to the electrode 4, and a reinforcing material provided adjacent to the corresponding conductive region. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は、半導体基板の一面に配された機能素子と、該機能素子と電気的に接続するように設けられた貫通電極とを備えてなる半導体装置及び半導体装置の製造方法に関する。   The present invention relates to a semiconductor device including a functional element disposed on one surface of a semiconductor substrate, and a through electrode provided so as to be electrically connected to the functional element, and a method for manufacturing the semiconductor device.

近年、携帯電話等の電子機器の高機能化が進み、これらの機器に用いられるICやLSI等の電子デバイス、及びOEICや光ピックアップ等の光デバイスにおいて、デバイス自体の小型化や高機能化を図るための開発が各所で進められている。例えば、このようなデバイスを積層して設ける技術が提案されており、具体的には、何らかの機能素子が一方の面に設けられている基板に対し、該基板の一方の面から他方の面に貫通してなる貫通電極を用いる技術が挙げられる。   In recent years, electronic devices such as mobile phones have been improved in functionality, and in electronic devices such as ICs and LSIs and optical devices such as OEICs and optical pickups used in these devices, the devices themselves have been reduced in size and functionality. Development for planning is underway at various locations. For example, a technique of stacking such devices has been proposed. Specifically, a substrate on which one functional element is provided on one surface is provided from one surface of the substrate to the other surface. A technique using a penetrating electrode that penetrates may be mentioned.

また、これらの基板の配線材料として、銅や銀等が次世代材料として期待されている。
特に、銅は比抵抗が低いこと、エレクトロマイグレーション耐性がアルミニウム系合金に比べて高いこと、銀に比べて安価である等の理由により、最も期待され、配線材料として用いられている。
In addition, copper, silver, and the like are expected as next-generation materials as wiring materials for these substrates.
In particular, copper is most expected and used as a wiring material because of its low specific resistance, high electromigration resistance compared to aluminum alloys, and low cost compared to silver.

一般に、銅めっきを用いた配線形成方法として、ダマシンプロセスが従来から用いられている。このダマシンプロセスを用いて得られる基板は、絶縁層に形成する孔の開口径を小さくすることにより、実装基板の一層の高集積化を図っている。   In general, a damascene process is conventionally used as a wiring forming method using copper plating. In a substrate obtained by using this damascene process, the mounting substrate is further integrated by reducing the opening diameter of the hole formed in the insulating layer.

図9は、従来の基板を用いた半導体装置の一例を概略説明する部分断面図である。
図9(a)に示す半導体基板100においては、セラミックスやシリコン等の硬質材からなる基板101と、基板101の両面を貫通して設けられた貫通孔102と、貫通孔102の孔内に充填され、銅材等からなる導電部103と、貫通孔102内に露呈するようにして半導体基板100の一方の面に配される電極104と、半導体基板100上に配されるICチップや光素子等の機能素子105と、基板101上において電極104及び機能素子105と電気的に接続されてなる配線回路106とから概略構成されている。
半導体基板100は、電極104と機能素子105とが配線部106によって電気的に接続されているとともに、電極104と電気的に接続された導電部103を介して基板両面が電気的に接続可能となっている。
FIG. 9 is a partial cross-sectional view schematically illustrating an example of a semiconductor device using a conventional substrate.
In the semiconductor substrate 100 shown in FIG. 9A, a substrate 101 made of a hard material such as ceramics or silicon, a through hole 102 provided through both surfaces of the substrate 101, and a hole in the through hole 102 are filled. A conductive portion 103 made of copper or the like; an electrode 104 disposed on one surface of the semiconductor substrate 100 so as to be exposed in the through hole 102; and an IC chip or an optical element disposed on the semiconductor substrate 100 And a wiring circuit 106 electrically connected to the electrode 104 and the functional element 105 on the substrate 101.
In the semiconductor substrate 100, the electrode 104 and the functional element 105 are electrically connected by the wiring portion 106, and both surfaces of the substrate can be electrically connected via the conductive portion 103 electrically connected to the electrode 104. It has become.

例えば、ダマシンプロセスを用いて図9(a)に示すような半導体基板100を製造する場合は、基板101に予め貫通孔102を形成し、該貫通孔102に銅材を埋め込む方法(例えば、特許文献1を参照)によって孔内への銅配線形成を行う。この銅めっき処理によって貫通孔102内を金属で完全に充填し、基板101の両面を貫通してなる導電部103を形成して半導体基板100が得られる。   For example, when manufacturing the semiconductor substrate 100 as shown in FIG. 9A using a damascene process, a method of forming a through hole 102 in the substrate 101 in advance and embedding a copper material in the through hole 102 (for example, a patent) The copper wiring is formed in the hole according to Reference 1). Through this copper plating process, the inside of the through hole 102 is completely filled with metal, and the conductive portion 103 penetrating both surfaces of the substrate 101 is formed to obtain the semiconductor substrate 100.

また、導電部103を形成した後、基板101表面上に形成した銅めっき層をパターニングすることで配線回路として使用することができ、その配線の保護層として樹脂を基板表面に塗布して用いている(例えば、特許文献2、3、4を参照)。   Further, after forming the conductive portion 103, the copper plating layer formed on the surface of the substrate 101 can be patterned to be used as a wiring circuit, and a resin is applied to the surface of the substrate as a protective layer for the wiring. (For example, see Patent Documents 2, 3, and 4).

ところで、上述のような基板を用いた半導体装置等においては、更なる高集積化に伴い、貫通孔102のアスペクト比(孔の開口直径に対する孔深さの比)が大きくなる傾向にある。このため、銅めっきを行った際に貫通孔102内が完全に充填されず、内部に閉鎖された空間が生じたボイド107(図9(b))や、外部に繋がった空間が生じたシーム108(図9(c))と呼ばれるめっき不良が発生してしまうという問題があった。   By the way, in a semiconductor device or the like using the substrate as described above, the aspect ratio of the through hole 102 (ratio of the hole depth to the hole diameter) tends to increase with further integration. For this reason, when the copper plating is performed, the inside of the through hole 102 is not completely filled, and a void 107 (FIG. 9B) in which a closed space is generated or a seam in which a space connected to the outside is generated is generated. There was a problem that a plating defect called 108 (FIG. 9C) occurred.

上述のボイド107やシーム108は、以下に説明するようなメカニズムで発生する。
貫通孔102に、銅めっきによって導電部103を形成する際に、貫通孔102内において、めっきが内壁に沿って均一に成長しない状態で、開口部側が先に閉じてしまった際に、ボイド107(図9(b))が発生し、めっきが内壁に沿って均一に成長しつつも、最終的に完全には充填することができず、開口部から貫通孔底部に向かって直線状に空間が残ってしまった際にシーム108(図9(c))が発生する。
通常、銅めっきを行う際は酸性のめっき液を用いることが多いが、上述のボイド107やシーム108にめっき液が残留すると、めっき液が時間の経過とともに銅(導電部103)を溶解して変質させることにより、基板の長期的な信頼性が低下する虞がある。また、導電部103の形成工程の後に熱プロセスを含む工程がある場合、内部の液体(めっき液)が急激に気化して容積が膨張することにより、導電部103の膨張破壊及びこれに伴う電極104の断線、更にはウェハ(基板101)の破壊が生じるという問題があった。
特開2003−178999号公報 特開平5−175652号公報 特開平11−354671号公報 特開2001−339165号公報
The above-described void 107 and seam 108 are generated by the mechanism described below.
When the conductive portion 103 is formed in the through hole 102 by copper plating, the void 107 is formed when the opening side is first closed in a state where the plating does not grow uniformly along the inner wall in the through hole 102. (FIG. 9B) occurs, and the plating grows uniformly along the inner wall, but cannot be completely filled in the end, and the space is linear from the opening toward the bottom of the through hole. Seam 108 (FIG. 9C) is generated.
Usually, when performing copper plating, an acidic plating solution is often used. However, when the plating solution remains in the void 107 or the seam 108, the plating solution dissolves copper (the conductive portion 103) with the passage of time. By changing the quality, the long-term reliability of the substrate may be lowered. In addition, when there is a process including a thermal process after the formation process of the conductive part 103, the internal liquid (plating solution) is rapidly vaporized and the volume expands. There was a problem that breakage of the wire 104 and breakage of the wafer (substrate 101) occurred.
JP 2003-178999 A Japanese Patent Laid-Open No. 5-175652 Japanese Patent Laid-Open No. 11-354671 JP 2001-339165 A

本発明は上述の問題に鑑みてなされたものであり、導電部と電極との間の電気的な接続不良が発生しにくい半導体装置及び半導体装置の製造方法を提供することを目的とする。   The present invention has been made in view of the above-described problems, and an object of the present invention is to provide a semiconductor device and a method for manufacturing the semiconductor device in which poor electrical connection between a conductive portion and an electrode is unlikely to occur.

前記課題を解決するため、本発明の請求項1に係る半導体装置は、基板の一方の面に配され、該面内にある機能素子と電気的に接続された電極と、前記基板の他方の面から一方の面に配した電極が露呈するように、基板内に開けられた貫通孔と、前記貫通孔内の側面及び前記電極の露呈部を覆うように配され、前記電極と電気的に接続された導電部と、 前記導電部に接するように配された補強材と、を具備したことを特徴としている。
本発明の請求項2に係る半導体装置は、請求項1に記載の半導体装置において、前記補強材が、前記導電部によって覆われた貫通孔内部に埋設されていることを特徴としている。
本発明の請求項3に係る半導体装置は、請求項1又は2に記載の半導体装置において、前記導電部が、前記他方の面上まで延設されていることを特徴としている。
本発明の請求項4に係る半導体装置は、請求項3に記載の半導体装置において、前記補強材が、前記導電部の延設された少なくとも一部を覆うように配されていることを特徴としている。
本発明の請求項5に係る半導体装置は、請求項1乃至4のいずれか1項に記載の半導体装置において、前記貫通孔内の側面と前記導電部との間に絶縁部を配したことを特徴としている。
本発明の請求項6に係る半導体装置の製造方法は、基板の一方の面に配され、該面内にある機能素子と電気的に接続された電極と、前記基板の他方の面から一方の面に配した電極が露呈するように、基板内に開けられた貫通孔と、前記貫通孔内の側面及び前記電極の露呈部を覆うように配され、前記電極と電気的に接続された導電部と、前記導電部に接するように配された補強材とを具備してなる半導体装置の製造方法であって、前記基板の他方の面から一方の面に配した電極が露呈するように、基板内に貫通孔を形成する工程と、前記貫通孔内の側面及び前記電極の露呈部を覆うように、前記電極と電気的に接続するように導電部を形成する工程と、前記導電部を覆うように補強材を形成する工程と、を少なくとも具備してなることを特徴としている。
本発明の請求項7に係る半導体装置の製造方法は、請求項6に記載の半導体装置の製造方法において、前記導電部を形成する工程が、前記貫通孔内の側面及び前記電極の露呈部とともに、前記他方の面上まで前記導電部が覆うように設ける方法としたことを特徴としている。
In order to solve the above-described problem, a semiconductor device according to claim 1 of the present invention is provided on one surface of a substrate and electrically connected to a functional element in the surface, and on the other surface of the substrate. A through hole opened in the substrate, a side surface in the through hole and an exposed portion of the electrode so as to expose the electrode disposed on one surface from the surface, and electrically connected to the electrode It is characterized by comprising a connected conductive part, and a reinforcing material arranged so as to be in contact with the conductive part.
A semiconductor device according to a second aspect of the present invention is the semiconductor device according to the first aspect, wherein the reinforcing material is embedded in a through hole covered with the conductive portion.
A semiconductor device according to a third aspect of the present invention is the semiconductor device according to the first or second aspect, wherein the conductive portion extends to the other surface.
A semiconductor device according to a fourth aspect of the present invention is the semiconductor device according to the third aspect, wherein the reinforcing material is arranged so as to cover at least a part of the conductive portion that is extended. Yes.
According to a fifth aspect of the present invention, in the semiconductor device according to any one of the first to fourth aspects, an insulating portion is disposed between the side surface in the through hole and the conductive portion. It is a feature.
According to a sixth aspect of the present invention, there is provided a method for manufacturing a semiconductor device, comprising: an electrode disposed on one surface of a substrate and electrically connected to a functional element in the surface; A through hole opened in the substrate so that the electrode disposed on the surface is exposed, a conductive surface that is disposed so as to cover the side surface in the through hole and the exposed portion of the electrode, and is electrically connected to the electrode And a reinforcing device disposed so as to be in contact with the conductive portion, wherein the electrode disposed on one surface is exposed from the other surface of the substrate, Forming a through hole in the substrate, forming a conductive part so as to be electrically connected to the electrode so as to cover a side surface in the through hole and the exposed part of the electrode, and the conductive part. And a step of forming a reinforcing material so as to cover It is.
The method for manufacturing a semiconductor device according to claim 7 of the present invention is the method for manufacturing a semiconductor device according to claim 6, wherein the step of forming the conductive portion is performed together with the side surface in the through hole and the exposed portion of the electrode. The method is characterized in that the conductive portion is provided so as to cover the other surface.

本発明の半導体装置によれば、基板の一方の面に配され、該面内にある機能素子と電気的に接続された電極と、前記基板の他方の面から一方の面に配した電極が露呈するように、基板内に開けられた貫通孔と、前記貫通孔内の側面及び前記電極の露呈部を覆うように配され、前記電極と電気的に接続された導電部と、前記導電部に接するように配された補強材と、を具備した構成としている。
また、本発明の半導体装置の製造方法によれば、前記基板の他方の面から一方の面に配した電極が露呈するように、基板内に貫通孔を形成する工程と、前記貫通孔内の側面と、前記電極の露呈部とを覆うように、前記電極と電気的に接続するように導電部を形成する工程と、前記導電部を覆うように補強材を形成する工程と、を少なくとも具備してなる。
これにより、半導体基板が熱サイクルや高温環境下において使用される場合であっても、基板材料と電極及び導電部材料との間の熱膨張係数の差に起因して生じる熱ひずみに対して応力を緩和することができ、電極の破断等が生じることが無い。
また、補強材によって導電部が覆われることにより、該導電部の酸化や変形、劣化を防止することができる。
また、貫通孔内におけるボイドやシーム等が生じることに伴うめっき液の残留や、該残留液が熱プロセスを含む工程において急激に気化し、電極や基板を破壊するのを防止することができる。
従って、導電部と電極との間の電気的な接続不良や、基板の破壊等を生じることが無く、信頼性の高い半導体装置を得ることができる。
According to the semiconductor device of the present invention, the electrode disposed on one surface of the substrate and electrically connected to the functional element in the surface, and the electrode disposed on the one surface from the other surface of the substrate are provided. A through hole opened in the substrate so as to be exposed, a conductive part disposed so as to cover a side surface in the through hole and the exposed part of the electrode, and electrically connected to the electrode; and the conductive part And a reinforcing material arranged so as to be in contact with.
According to the method of manufacturing a semiconductor device of the present invention, the step of forming a through hole in the substrate so that the electrode disposed on the one surface from the other surface of the substrate is exposed, At least a step of forming a conductive portion so as to be electrically connected to the electrode so as to cover the side surface and the exposed portion of the electrode, and a step of forming a reinforcing material so as to cover the conductive portion. Do it.
As a result, even when the semiconductor substrate is used in a thermal cycle or in a high temperature environment, stress is applied to the thermal strain caused by the difference in thermal expansion coefficient between the substrate material and the electrode and conductive part material. Can be relaxed, and the electrode is not broken.
In addition, since the conductive portion is covered with the reinforcing material, oxidation, deformation, and deterioration of the conductive portion can be prevented.
Further, it is possible to prevent the plating solution from remaining due to the formation of voids, seams, and the like in the through-holes, and the residual solution from being rapidly vaporized in a process including a thermal process, thereby destroying the electrode and the substrate.
Accordingly, a highly reliable semiconductor device can be obtained without causing poor electrical connection between the conductive portion and the electrode, destruction of the substrate, and the like.

以下、本発明に係る半導体装置の実施するための最良の形態について、図面を参照して説明する。
図1乃至図5は、本実施形態の半導体装置10の一例を示す断面図である。
The best mode for carrying out a semiconductor device according to the present invention will be described below with reference to the drawings.
1 to 5 are cross-sectional views showing an example of the semiconductor device 10 of this embodiment.

図1に示すように、半導体装置10は、基板2の一方の面2aに配され、該一方の面2a内にある機能素子5と電気的に接続された電極4と、基板2の他方の面2bから、一方の面2aに配された電極4が露呈するように、基板2内に開けられた貫通孔3と、該貫通孔3内の側面3a及び電極4の露呈部4aを覆うように配され、電極4と電気的に接続された導電部16と、導電部16に接するように配された補強材17と、を具備して概略構成されている。
図1では、導電部16によって貫通孔3の側面3aを全て被覆した場合の例を示している。
また、図1に示す例では、補強材17を、導電部16に接しながら、貫通孔3内に充填するようにして配している。
As shown in FIG. 1, the semiconductor device 10 is disposed on one surface 2 a of the substrate 2, the electrode 4 electrically connected to the functional element 5 in the one surface 2 a, and the other of the substrate 2. The through hole 3 opened in the substrate 2, the side surface 3a in the through hole 3, and the exposed portion 4a of the electrode 4 are covered so that the electrode 4 disposed on the one surface 2a is exposed from the surface 2b. The conductive portion 16 is electrically connected to the electrode 4 and the reinforcing member 17 is disposed so as to be in contact with the conductive portion 16.
In FIG. 1, an example in which the side surface 3 a of the through hole 3 is entirely covered with the conductive portion 16 is shown.
In the example shown in FIG. 1, the reinforcing material 17 is disposed so as to fill the through hole 3 while being in contact with the conductive portion 16.

基板2は、例えば、シリコン(Si)等からなる半導体基材や、ガラス基材、セラミック基材等、絶縁性の硬質材料からなる。
基板2の厚さは、例えば数百μm程度である。
図1に示す例では、基板2をSi等の半導体基材から構成し、基板2の一方の面2a及び他方の面2bに加え、貫通孔3の側面3aの表層部2cが絶縁化された領域をなすように構成されている。また、基板を半導体基板から構成する場合は、図4に示す例のように、貫通孔3と導電部16との間に絶縁部9を配し、半導体基板12と導電部16とを電気的に絶縁した構成としても良い。
また、基板材料が、上述の絶縁性硬質材料からなる場合には、貫通孔3内の側面3aが絶縁体なので、図2に示す例のように、基板21に設けられた貫通孔3と導電部26とが接した構成とすることができる。
The substrate 2 is made of an insulating hard material such as a semiconductor base material made of silicon (Si), a glass base material, a ceramic base material, or the like.
The thickness of the substrate 2 is, for example, about several hundred μm.
In the example shown in FIG. 1, the substrate 2 is made of a semiconductor base material such as Si, and the surface layer portion 2 c of the side surface 3 a of the through hole 3 is insulated in addition to the one surface 2 a and the other surface 2 b of the substrate 2. It is configured to form an area. Further, when the substrate is formed of a semiconductor substrate, as in the example shown in FIG. 4, the insulating portion 9 is disposed between the through hole 3 and the conductive portion 16, and the semiconductor substrate 12 and the conductive portion 16 are electrically connected. It is good also as a structure insulated.
Further, when the substrate material is made of the above-described insulating hard material, the side surface 3a in the through hole 3 is an insulator, so that the through hole 3 provided in the substrate 21 and the conductive material are electrically conductive as in the example shown in FIG. It can be set as the structure which the part 26 contact | connected.

貫通孔3は、図1に示すように、基板2において、他方の面2bから、一方の面2aに配された後述する電極4が孔内に露呈するように、基板2内に開けられてなる。
貫通孔3の口径は、例えば数十μm程度である。
また、基板2上に設けられる貫通孔3の数は、特に限定されない。
As shown in FIG. 1, the through hole 3 is opened in the substrate 2 so that an electrode 4 (described later) arranged on the one surface 2a is exposed in the hole from the other surface 2b. Become.
The diameter of the through hole 3 is, for example, about several tens of μm.
Further, the number of through holes 3 provided on the substrate 2 is not particularly limited.

電極4は、基板2の一方の面2aに配され、露呈部4aが貫通孔3の一方の開口部31から孔内に露呈するようにして設けられている。
電極4は、後述の配線回路8を介して、該一方の面2a内にある後述の機能素子5と電気的に接続されている。
電極4の材質としては、例えばアルミニウム(Al)や銅(Cu)、アルミニウム−シリコン(Al−Si)合金、アルミニウム−シリコン−銅(Al−Si−Cu)合金等の導電性に優れる材料が好適に用いられる。
The electrode 4 is disposed on one surface 2 a of the substrate 2, and is provided so that the exposed portion 4 a is exposed from the one opening portion 31 of the through hole 3 into the hole.
The electrode 4 is electrically connected to a later-described functional element 5 in the one surface 2a through a later-described wiring circuit 8.
The material of the electrode 4 is preferably a material having excellent conductivity such as aluminum (Al), copper (Cu), an aluminum-silicon (Al-Si) alloy, an aluminum-silicon-copper (Al-Si-Cu) alloy, or the like. Used for.

機能素子5は、本実施形態では、例えばICチップや、CCD素子等の光素子からなる。
また、機能素子5の他の例としては、例えばマイクロリレー、マイクロスイッチ、圧力センサ、加速度センサ、高周波フィルタ、マイクロミラー、マイクロリアクター、μ−TAS、DNAチップ、MEMSデバイス、マイクロ燃料電池等が挙げられる。
In this embodiment, the functional element 5 is composed of an optical element such as an IC chip or a CCD element.
Other examples of the functional element 5 include a micro relay, a micro switch, a pressure sensor, an acceleration sensor, a high frequency filter, a micro mirror, a micro reactor, a μ-TAS, a DNA chip, a MEMS device, a micro fuel cell, and the like. It is done.

導電部16は、貫通孔3内の側面3aの少なくとも一部に配されることにより、導電体として有効に働く。
図1の断面図に示す例では、導電部16は、側面3aの全体を覆うように配されているが、これには限定されない。例えば、導電部16が、側面3aの一部に、基板2の一方の面2aと他方の面2bとの間に渡って配された構成としても良い。
The conductive portion 16 works effectively as a conductor by being disposed on at least a part of the side surface 3 a in the through hole 3.
In the example shown in the cross-sectional view of FIG. 1, the conductive portion 16 is disposed so as to cover the entire side surface 3 a, but is not limited thereto. For example, the conductive part 16 may be configured to be disposed on a part of the side surface 3 a between the one surface 2 a and the other surface 2 b of the substrate 2.

導電部16の材質は、導電性に優れた材料を用いることが好ましい。また、導電部16は、電極4との密着性に優れるとともに、導電部16を構成する元素が電極4や基板2内に拡散しない材料を用いれば、さらに好ましい。
例えば、図1に示す例のように導電部16が単層である場合には、電極4と同材料であることが望ましく、Al、Cu、Ni、Au等の金属材料を用いれば、導電性や電極4との密着性等の点で好ましい。
また、導電部16を、2種類以上の金属材料からなる多層構造、あるいは材料の異なる膜を積層した構造とした場合、外側の層には、電極4を成す材質との密着性に優れる材料や、導電部16と、電極4又は基板2との間で元素移動(拡散)が生じるのを防止できる金属材料(バリアメタル)を配し、内側の層には、導電性の高い金属を配した構成とすることが好ましい。
また、導電部16と貫通孔3(もしくは絶縁部9)との間、又は導電部16と後述の補強材17との間に、例えば、応力緩和作用のある材料や、元素移動を防止するバリアメタル、又は密着性に優れた材料等を配した多層構造の中間層を設けた構成としても良い。
例えば、導電部16がCuの場合、バリアメタルとしてTaN、Ta、W、WN、TiN、TiSiN等が挙げられ、それぞれ密着性に優れている。また、それらの材料以外にも、Cr、TiW等が、密着性の高いバリアメタルとして挙げられる。
As the material of the conductive portion 16, it is preferable to use a material having excellent conductivity. Further, it is more preferable that the conductive portion 16 is excellent in adhesiveness with the electrode 4 and a material that does not diffuse the elements constituting the conductive portion 16 into the electrode 4 or the substrate 2 is used.
For example, when the conductive portion 16 is a single layer as in the example shown in FIG. 1, it is desirable to use the same material as the electrode 4. If a metal material such as Al, Cu, Ni, or Au is used, the conductive portion 16 is conductive. And the adhesiveness with the electrode 4 is preferable.
In addition, when the conductive portion 16 has a multilayer structure composed of two or more kinds of metal materials or a structure in which films of different materials are laminated, a material having excellent adhesion to the material forming the electrode 4 can be formed on the outer layer. A metal material (barrier metal) that can prevent element movement (diffusion) from occurring between the conductive portion 16 and the electrode 4 or the substrate 2 is disposed, and a metal having high conductivity is disposed in the inner layer. A configuration is preferable.
Further, between the conductive portion 16 and the through-hole 3 (or the insulating portion 9) or between the conductive portion 16 and the reinforcing material 17 described later, for example, a material having a stress relaxation action or a barrier for preventing element movement. A configuration in which an intermediate layer having a multilayer structure in which metal or a material having excellent adhesion is arranged may be provided.
For example, when the conductive portion 16 is Cu, examples of the barrier metal include TaN, Ta, W, WN, TiN, TiSiN, etc., and each has excellent adhesion. In addition to these materials, Cr, TiW, and the like can be cited as barrier metals with high adhesion.

補強材17は、貫通孔3内において、導電部16の内面に接するように配され、非導電材料からなる。
補強材17は、導電部16に熱歪み等によって生じる応力に対して緩衝材として機能するとともに、導電部16が外気へ剥き出しにならないようにオーバーコートする。
補強材17は、導電部16の内面全体を完全に覆うように形成することが、上述した導電部16をオーバーコートする点で好ましく、また、図1に示す例のように、充填(埋設)して配することが、後述の、導電部16に生じる応力を緩和する点から好ましい。
The reinforcing member 17 is disposed in the through hole 3 so as to be in contact with the inner surface of the conductive portion 16 and is made of a nonconductive material.
The reinforcing material 17 functions as a buffer material against stress generated by thermal strain or the like on the conductive portion 16 and overcoats the conductive portion 16 so as not to be exposed to the outside air.
The reinforcing member 17 is preferably formed so as to completely cover the entire inner surface of the conductive portion 16 in terms of overcoating the conductive portion 16 described above, and is filled (embedded) as in the example shown in FIG. It is preferable from the point of relieving the stress which arises in the electroconductive part 16 mentioned later.

補強材17の材質としては、導電部16を成す金属材料と異なり、樹脂等の応力緩和作用を有する非導電性材料、または金属粉末を含有した導電性樹脂等を用いることが好ましく、例えば、熱硬化性エポキシ樹脂等の樹脂材料を用いれば良い。
また、補強剤17の材質に導電性樹脂を用いた場合、導電部16に亀裂が生じて電気的断絶に至る様な状態となった場合でも、導電部16の内面側に配した補強材17(導電性樹脂)により、電気的接続状態を維持することができる。
また、補強材17の材質に無溶剤性樹脂を用い、真空印刷によって補強材17を配する方法とした場合には、補強材17の形成工程、作業がスムーズになり、また、ボイド等の不具合を防止することができる。この場合、真空印刷装置として、例えばサンユレック社製の特殊真空印刷システム(型番:VPES−HA−IV)等を用いることができる。
As the material of the reinforcing member 17, unlike the metal material forming the conductive portion 16, it is preferable to use a non-conductive material having a stress relaxation action such as a resin or a conductive resin containing a metal powder. A resin material such as a curable epoxy resin may be used.
Further, when a conductive resin is used as the material of the reinforcing agent 17, the reinforcing material 17 disposed on the inner surface side of the conductive portion 16 even when the conductive portion 16 is cracked and becomes electrically disconnected. The electrically connected state can be maintained by (conductive resin).
In addition, when a solvent-free resin is used as the material of the reinforcing material 17 and the reinforcing material 17 is arranged by vacuum printing, the forming process and the operation of the reinforcing material 17 become smooth, and there are defects such as voids. Can be prevented. In this case, for example, a special vacuum printing system (model number: VPES-HA-IV) manufactured by Sanyu Rec Co., Ltd. can be used as the vacuum printing apparatus.

本実施形態の半導体装置10では、貫通孔3内に導電部16を形成する際、金属材料を完全に充填せず、開口を配した構成としている(図1参照)。ボイドやシーム等の不良(図9参照)は、開口がなく閉じられた状態で発生する可能性が高いものであるため、開口を配した構成とすれば、これらの不良は発生しない。また、開口を配することにより、内部に液体が溜まった場合でも、洗浄及び除去することが可能となる。
さらに、半導体装置10は、貫通孔3内において、導電部16を覆うようにして補強材17を配した構成とし、図1に示す例では、貫通孔3内に充填するようにして設けられている。これにより、導電部16に生じる応力を緩和するとともに、導電部16が外気に剥き出しになることによって生じる酸化や変形を防止することができる。
In the semiconductor device 10 of the present embodiment, when the conductive portion 16 is formed in the through hole 3, the metal material is not completely filled, and an opening is provided (see FIG. 1). Defects such as voids and seams (see FIG. 9) are highly likely to occur in a closed state with no openings, so these defects do not occur if the configuration is provided with openings. Further, by providing the opening, it is possible to clean and remove the liquid even when the liquid is accumulated inside.
Furthermore, the semiconductor device 10 has a configuration in which the reinforcing material 17 is disposed so as to cover the conductive portion 16 in the through hole 3. In the example illustrated in FIG. 1, the semiconductor device 10 is provided so as to fill the through hole 3. Yes. As a result, stress generated in the conductive portion 16 can be relieved, and oxidation and deformation caused by the conductive portion 16 being exposed to the outside air can be prevented.

また、半導体装置が熱サイクルや高温環境にさらされる場合、基板2の材質と導電部16の材質との間の熱膨張係数の差に起因して熱歪みが生じることがある。本実施形態の半導体装置1では、導電部16の内面側に形成された空間3bに、金属とは異なる別材料、詳細には樹脂材料からなる補強材を配することによって応力緩和が可能となり、導電部16や電極4の破断等を防止し、信頼性を飛躍的に向上させることができる。   Further, when the semiconductor device is exposed to a thermal cycle or a high temperature environment, thermal distortion may occur due to a difference in thermal expansion coefficient between the material of the substrate 2 and the material of the conductive portion 16. In the semiconductor device 1 of the present embodiment, stress can be relieved by arranging a different material different from metal, specifically a reinforcing material made of a resin material, in the space 3b formed on the inner surface side of the conductive portion 16, The breakage of the conductive portion 16 and the electrode 4 can be prevented, and the reliability can be dramatically improved.

なお、補強材は、図3(a)に示す例のように、導電部36を該導電部36の内面に沿って被覆した補強材37として構成しても良いし、図3(b)に示す例のように、貫通孔3内の下部のみに充填した補強材47として構成としても良い。
また、図4(b)に示す例のように、導電部66の内面に沿って被覆して配した補強材67bの内面に、補強材67aを充填して配した補強材67として構成しても良い。この場合には、外層となる補強材67bに、より応力緩和作用の大きな材料を用いることが好ましい。
The reinforcing material may be configured as a reinforcing material 37 in which the conductive portion 36 is covered along the inner surface of the conductive portion 36 as in the example shown in FIG. Like the example shown, it is good also as a structure as the reinforcing material 47 with which only the lower part in the through-hole 3 was filled.
Further, as shown in the example shown in FIG. 4B, the inner surface of the reinforcing member 67b disposed so as to be covered along the inner surface of the conductive portion 66 is configured as a reinforcing member 67 that is disposed by filling the reinforcing member 67a. Also good. In this case, it is preferable to use a material having a greater stress relaxation effect for the reinforcing material 67b as the outer layer.

配線回路8は、基板2上に配され、電極4や機能素子5等を電気的に接続して回路をなす。
配線回路8の材質としては、電極4と同様の材質を用いれば良く、アルミニウム(Al)や銅(Cu)、アルミニウム−シリコン(Al−Si)合金、アルミニウム−シリコン−銅(Al−Si−Cu)合金等の導電性に優れる材料が好適である。
The wiring circuit 8 is disposed on the substrate 2 and electrically connects the electrodes 4 and the functional elements 5 to form a circuit.
As the material of the wiring circuit 8, the same material as that of the electrode 4 may be used. Aluminum (Al), copper (Cu), aluminum-silicon (Al-Si) alloy, aluminum-silicon-copper (Al-Si-Cu) ) A material having excellent conductivity such as an alloy is suitable.

本実施形態の半導体装置10は、必要に応じて基板2の一方の面2aにガラス基板等のような別基板を接合した構成としても良い。   The semiconductor device 10 of the present embodiment may have a configuration in which another substrate such as a glass substrate is bonded to one surface 2a of the substrate 2 as necessary.

以下、本実施形態の半導体装置10の製造方法について、図6を用いて説明する。
なお、図6は、本実施形態の半導体装置10を工程順に示した断面模式図であり、一部は分かりやすいように上面から眺めた図も添付してある。
本実施形態の半導体装置10の製造方法では、基板2の一方の面2aに配され、該面内にある機能素子5と電気的に接続された電極4と、基板2の他方の面2bから、一方の面2aに配された電極4が露呈するように、基板2内に開けられた貫通孔3と、貫通孔3内の側面3a及び電極4の露呈部4aを覆うように配され、電極4と電気的に接続された導電部16と、導電部16に接するように配された補強材17とを具備してなる半導体装置10の製造方法であって、基板2の他方の面2bから、一方の面2aに配された電極4が露呈するように、基板2内に貫通孔3を形成する工程Aと(図6(a)、(b)参照)、貫通孔3内の側面3a及び電極4の露呈部4aを覆うように、電極2と電気的に接続するように導電部16を形成する工程Bと(図6(c)参照)、導電部16を覆うように補強材17を形成する工程Cと(図6(d)参照)、を少なくとも具備してなることを特徴としている。
Hereinafter, a method for manufacturing the semiconductor device 10 of the present embodiment will be described with reference to FIGS.
FIG. 6 is a schematic cross-sectional view showing the semiconductor device 10 of this embodiment in the order of steps, and a part of the semiconductor device 10 is also viewed from the top for easy understanding.
In the manufacturing method of the semiconductor device 10 of the present embodiment, the electrode 4 disposed on one surface 2a of the substrate 2 and electrically connected to the functional element 5 in the surface, and the other surface 2b of the substrate 2 are used. The through-hole 3 opened in the substrate 2 and the side surface 3a in the through-hole 3 and the exposed portion 4a of the electrode 4 are arranged so as to expose the electrode 4 arranged on the one surface 2a. A method for manufacturing a semiconductor device 10 comprising a conductive portion 16 electrically connected to an electrode 4 and a reinforcing member 17 disposed so as to be in contact with the conductive portion 16, wherein the other surface 2 b of the substrate 2 is provided. Step A for forming the through hole 3 in the substrate 2 so that the electrode 4 disposed on the one surface 2a is exposed (see FIGS. 6A and 6B), and the side surface in the through hole 3 3a and a process for forming the conductive portion 16 so as to be electrically connected to the electrode 2 so as to cover the exposed portion 4a of the electrode 4 B (see FIG. 6 (c)), a step C of forming a reinforcing member 17 so as to cover the conductive portion 16 (see FIG. 6 (d)), is characterized by comprising at least comprises a.

上述の構成により、図1に示すような、貫通孔3内の側面3aの少なくとも一部と電極4の露呈部4aとを覆うようにして導電部16を設け、該導電部16の内面を覆うように充填して補強材17を設けた半導体装置10を効率良く製造することが可能となる。
また、貫通孔3を形成した後、剥き出しになった電極4の露呈部4aを導電部16で覆い、次いで、補強材17で導電部16を覆う工程としているため、導電部16が外気に剥き出しになることなくオーバーコートされ、保護することができる。
With the above-described configuration, as shown in FIG. 1, the conductive portion 16 is provided so as to cover at least a part of the side surface 3 a in the through hole 3 and the exposed portion 4 a of the electrode 4, and covers the inner surface of the conductive portion 16. Thus, it is possible to efficiently manufacture the semiconductor device 10 that is filled and provided with the reinforcing material 17.
In addition, since the exposed portion 4a of the exposed electrode 4 is covered with the conductive portion 16 and then the conductive portion 16 is covered with the reinforcing material 17 after the through hole 3 is formed, the conductive portion 16 is exposed to the outside air. It can be overcoated and protected without becoming.

なお、以下の説明においては、半導体装置10の基板2の材質に、ガラスやセラミック材料等の非導電性材料を用いた例について説明する。   In the following description, an example in which a non-conductive material such as glass or ceramic material is used as the material of the substrate 2 of the semiconductor device 10 will be described.

(イ) 工程A
図6(a)には、通常の製造工程プロセスが終了して完成した、ガラスやセラミック材料からなる基板2、外部と電気的な接続をするための電極4、フォトダイオード群やマイクロレンズ群、或いはICチップなどからなる機能素子5、電極4と機能素子5とを電気的に接続するための配線回路8等が配された半導体装置を示している。
本例においては、基板2の厚さは200μmであり、また、電極4及び配線回路8はアルミニウム(Al)金属からなっている。また、電極4は、100μm×100μmの正方形である。
(A) Process A
FIG. 6A shows a substrate 2 made of glass or ceramic material, completed after a normal manufacturing process, an electrode 4 for electrical connection with the outside, a photodiode group or a microlens group, Alternatively, a semiconductor device is shown in which a functional element 5 made of an IC chip or the like, and a wiring circuit 8 for electrically connecting the electrode 4 and the functional element 5 are arranged.
In this example, the thickness of the substrate 2 is 200 μm, and the electrode 4 and the wiring circuit 8 are made of aluminum (Al) metal. The electrode 4 is a square of 100 μm × 100 μm.

まず、図6(b)に示すように、機能素子5等が配されている一方の面2aと他方の面2bとの間において、他方の面2b上の電極4に対向する位置から、電極4の裏面(つまり、電極4の一方の面2aと重なり合っていた面)に達するまで、基板2を貫通する貫通孔3を形成する。この時、電極4の裏面の内の少なくとも一部が露呈部4aとして、開口部31から孔内に露呈するようにして、貫通孔3を形成する。   First, as shown in FIG. 6B, an electrode is formed from a position facing the electrode 4 on the other surface 2b between the one surface 2a on which the functional element 5 and the like are arranged and the other surface 2b. Through-holes 3 penetrating the substrate 2 are formed until reaching the back surface of 4 (that is, the surface overlapping the one surface 2a of the electrode 4). At this time, the through hole 3 is formed so that at least a part of the back surface of the electrode 4 is exposed as the exposed portion 4a from the opening 31 into the hole.

本例では、基板2をなす非導電材料の内、電極4が配された部分をエッチング処理によって除去することにより、孔径80μm、深さ200μmの微細な孔である貫通孔3を形成した。   In this example, through holes 3 which are fine holes having a hole diameter of 80 μm and a depth of 200 μm are formed by removing the portion of the non-conductive material forming the substrate 2 where the electrodes 4 are disposed by etching.

(ロ)工程B
次いで、図6(c)に示すように、貫通孔3内の側面3a、及び電極4の露呈部4aを覆うようにして、金属材料からなる導電部16のシード層を形成する。本例では、前記シード層をなす金属材料として、側面3aと接する外側にCrを、内面側にCuを用い、スパッタ法によって形成したが、その他、MOCVD、無電解めっき等によって形成しても良い。これにより、貫通孔3内の側面3a及び電極4の露呈部4aは、前記シード層によって被覆される。そして、上記シード層の内面側にCuをめっき処理することにより、導電部16が形成される。
なお、本例では、導電部16が、露呈部4a及び側面3a全体を被覆するようにして形成された例を説明しているが、導電部16は、基板2の一方の面2aと他方の面2bとの間で連なって配され、電極4と電気的に接続されていれば良く、例えば、側面3aの表面に線状に形成された導電部であっても良い。
(B) Process B
Next, as shown in FIG. 6C, a seed layer of the conductive portion 16 made of a metal material is formed so as to cover the side surface 3 a in the through hole 3 and the exposed portion 4 a of the electrode 4. In this example, the metal material forming the seed layer is formed by sputtering using Cr on the outer side in contact with the side surface 3a and Cu on the inner side, but may be formed by MOCVD, electroless plating, or the like. . Thereby, the side surface 3a in the through-hole 3 and the exposed portion 4a of the electrode 4 are covered with the seed layer. And the electroconductive part 16 is formed by plating Cu to the inner surface side of the said seed layer.
In this example, an example in which the conductive portion 16 is formed so as to cover the entire exposed portion 4a and the side surface 3a has been described. However, the conductive portion 16 includes the one surface 2a of the substrate 2 and the other side. What is necessary is just to be distribute | arranged between the surface 2b, and to be electrically connected with the electrode 4, for example, the electroconductive part formed in linear form on the surface of the side surface 3a may be sufficient.

(ハ)工程C
次いで、図6(d)に示すように、貫通孔3内に形成された導電部16の内面側を、樹脂材料で覆うようにして補強材17を形成する。本例で説明する補強材17は、樹脂材料として、熱硬化性エポキシ樹脂を用いるとともに、他方の面2bに向けて開口部17aを有して形成されている。
補強材17を形成する方法としては、例えば、導電部16を形成した基板2上に、真空印刷法によって無溶剤性樹脂等の樹脂材料を印刷することにより、貫通孔3内の導電部16内面へ樹脂を押し込む方法を用いれば良い。
また、ノズルを用い、貫通孔3内の導電部16内面に、樹脂を直接塗布する方法を用いれば、樹脂材料を適量だけ塗布し、基板2ごと減圧することによって補強材17を形成することができる。
(C) Process C
Next, as shown in FIG. 6D, the reinforcing material 17 is formed so as to cover the inner surface side of the conductive portion 16 formed in the through hole 3 with a resin material. The reinforcing material 17 described in this example is formed using a thermosetting epoxy resin as a resin material and having an opening 17a toward the other surface 2b.
As a method of forming the reinforcing member 17, for example, a resin material such as a solvent-free resin is printed on the substrate 2 on which the conductive portion 16 is formed by a vacuum printing method, thereby the inner surface of the conductive portion 16 in the through hole 3 is formed. A method of pushing the resin into the substrate may be used.
Further, if a method of directly applying resin to the inner surface of the conductive portion 16 in the through-hole 3 using a nozzle is used, the reinforcing material 17 can be formed by applying an appropriate amount of the resin material and reducing the pressure together with the substrate 2. it can.

上述した各工程により、本実施形態の半導体装置10を効率良く製造することができる。   Through the above-described steps, the semiconductor device 10 of this embodiment can be manufactured efficiently.

なお、本例では、電極4の大きさ及び形状を100μm角の正方形としたが、電極4の形状はこれに限定されず、円形、楕円形、三角形、矩形などいかなる形状でもよく、その大きさも電気的配線に用いる電極としての機能が保持できれば、如何なる大きさでも良い。更に、電極4及び配線回路8の材質も、本例ではAlとしているが、これには限定されず、銅(Cu)、アルミニウム−シリコン(Al−Si)、アルミニウム−シリコン−銅(Al−Si−Cu)など、他の如何なる配線材料であってもよい。   In this example, the size and shape of the electrode 4 is a 100 μm square, but the shape of the electrode 4 is not limited to this, and may be any shape such as a circle, an ellipse, a triangle, and a rectangle. Any size may be used as long as the function as an electrode used for electrical wiring can be maintained. Furthermore, although the material of the electrode 4 and the wiring circuit 8 is also Al in this example, it is not limited to this, but copper (Cu), aluminum-silicon (Al-Si), aluminum-silicon-copper (Al-Si) Any other wiring material such as -Cu) may be used.

また、本例では、貫通孔3の直径を80μmの円形として形成しているが、これには限定されず、貫通孔3と電極4との接触面全体が、電極4の内部に位置するような大きさであれば如何なる大きさでもよく、その形状も円形のみならず楕円形、四角形、三角形、矩形など如何なる形状でもよい。   In this example, the diameter of the through hole 3 is formed as a circle of 80 μm. However, the present invention is not limited to this, and the entire contact surface between the through hole 3 and the electrode 4 is located inside the electrode 4. Any size may be used as long as it is a large size, and the shape may be not only a circle but also any shape such as an ellipse, a rectangle, a triangle, and a rectangle.

また、本実施形態の半導体装置の製造方法では、基板2の材質にシリコン(Si)等からなる半導体ウェハを用いた半導体基板を例として説明しているが、この場合には、上述したように半導体基板12に形成された貫通孔3内の側面3aに、例えばSiNやSiO等からなる絶縁部9を形成することができる(図4参照)。該絶縁部9の側面、及び電極4の露呈部4aを覆うようにして導電部16を形成することにより、半導体基板12と導電部16とを電気的に絶縁することができる。
半導体基板12への貫通孔3及び絶縁部9の形成については、従来から行われている方法を用いることができる。
なお、基板にガラス材等の非導電性材料を用いた場合には、絶縁部9を形成する必要は無い。
In the semiconductor device manufacturing method of the present embodiment, a semiconductor substrate using a semiconductor wafer made of silicon (Si) or the like as the material of the substrate 2 is described as an example. In this case, as described above, An insulating portion 9 made of, for example, SiN or SiO 2 can be formed on the side surface 3a in the through hole 3 formed in the semiconductor substrate 12 (see FIG. 4). By forming the conductive portion 16 so as to cover the side surface of the insulating portion 9 and the exposed portion 4a of the electrode 4, the semiconductor substrate 12 and the conductive portion 16 can be electrically insulated.
For forming the through hole 3 and the insulating portion 9 in the semiconductor substrate 12, a conventional method can be used.
In the case where a non-conductive material such as a glass material is used for the substrate, it is not necessary to form the insulating portion 9.

また、本例では、補強材17の材質として樹脂材料を用いているが、これには限定されず、補強材17の材質として、応力緩和作用を有する金属材料を用いても良い。   In this example, a resin material is used as the material of the reinforcing material 17, but the present invention is not limited to this, and a metal material having a stress relaxation action may be used as the material of the reinforcing material 17.

以上、説明したように、本実施形態の半導体装置10によれば、基板2の一方の面2aに配され、該面内にある機能素子5と電気的に接続された電極4と、基板2の他方の面2bから、一方の面2aに配された電極4が露呈するように、基板2内に開けられた貫通孔3と、該貫通孔3内の側面3a及び電極4の露呈部4aを覆うように配され、電極4と電気的に接続された導電部16と、該導電部16に接するように配された補強材17とを具備した構成としている。
また、本実施形態の半導体装置10の製造方法によれば、基板2の他方の面2bから、一方の面2aに配された電極4が露呈するようにして、基板2内に貫通孔3を形成する工程Aと、貫通孔3内の側面3a及び電極4の露呈部4aを覆うようにして、電極4と電気的に接続するように導電部16を形成する工程Bと、導電部16を覆うようにして補強材17を形成する工程Cと、を少なくとも具備してなる。
これにより、半導体装置10が熱サイクルや高温環境下において使用される場合であっても、基板2をなす材料と電極4及び導電部16をなす材料との間の熱膨張係数の差に起因して生じる熱ひずみに対して応力を緩和することができ、電極の破断等が生じることが無い。
また、補強材17によって導電部16が覆われることにより、該導電部16の酸化や変形、劣化を防止することができる。
また、貫通孔内におけるボイドやシーム等が生じることに伴うめっき液の残留や、該残留液が熱プロセスを含む工程において急激に気化し、電極や基板を破壊するのを防止することができる。
従って、導電部16と電極4との間の電気的な接続不良や、基板2の破壊等を生じることが無く、信頼性の高い半導体装置10を得ることができる。
As described above, according to the semiconductor device 10 of the present embodiment, the electrode 4 disposed on one surface 2a of the substrate 2 and electrically connected to the functional element 5 in the surface, and the substrate 2 A through-hole 3 opened in the substrate 2 such that the electrode 4 disposed on the one surface 2a is exposed from the other surface 2b of the substrate, and the side surface 3a in the through-hole 3 and the exposed portion 4a of the electrode 4 The conductive portion 16 is disposed so as to cover the conductive portion 16 and is electrically connected to the electrode 4, and the reinforcing member 17 is disposed so as to be in contact with the conductive portion 16.
Further, according to the method for manufacturing the semiconductor device 10 of the present embodiment, the through hole 3 is formed in the substrate 2 so that the electrode 4 disposed on the one surface 2a is exposed from the other surface 2b of the substrate 2. Step A for forming, Step B for forming the conductive portion 16 so as to be electrically connected to the electrode 4 so as to cover the side surface 3a in the through hole 3 and the exposed portion 4a of the electrode 4, and the conductive portion 16 And at least a step C of forming the reinforcing member 17 so as to cover it.
Thereby, even when the semiconductor device 10 is used in a thermal cycle or a high temperature environment, it is caused by a difference in thermal expansion coefficient between the material forming the substrate 2 and the material forming the electrode 4 and the conductive portion 16. The stress can be relaxed with respect to the thermal strain generated, and the electrode is not broken.
In addition, since the conductive portion 16 is covered with the reinforcing material 17, oxidation, deformation, and deterioration of the conductive portion 16 can be prevented.
Further, it is possible to prevent the plating solution from remaining due to the formation of voids, seams, and the like in the through-holes, and the residual solution from being rapidly vaporized in a process including a thermal process, thereby destroying the electrode and the substrate.
Therefore, a highly reliable semiconductor device 10 can be obtained without causing an electrical connection failure between the conductive portion 16 and the electrode 4 or destruction of the substrate 2.

なお、本実施形態の半導体装置では、図1に示すような、導電部16及び補強材17の全体が貫通孔3内に収容されている例を説明しているが、図2に示す例のように、導電部が、基板2の他方の面2b上まで延設されてなる半導体装置としても良い。図示例では、導電部26が、他方の面2b上に、延設部26a、26bとして延設されている。このような構成とすることにより、他方の面2b側の配線も一括して形成することができ、製造工程の削減が可能となる。
また、図5に示す例のように、補強材57を、導電部56の延設された少なくとも一部を覆うように配した構成としても良い。図示例では、導電部56が、他方の面2b上に、延設部56a、56bとして延設されているとともに、補強材57が、他方の面2b上に、被覆部57a、57bとして延設され、該被覆部57a、57bが、それぞれ前記延設部56a、56bを覆うようにして形成されている。このような構成とすることにより、補強材が、後述するバンプを形成するためのオーバーコート層を兼ねることができる。
In the semiconductor device of the present embodiment, the example in which the entire conductive portion 16 and the reinforcing material 17 are accommodated in the through hole 3 as illustrated in FIG. 1 is described. However, in the example illustrated in FIG. Thus, a semiconductor device in which the conductive portion extends to the other surface 2 b of the substrate 2 may be used. In the example of illustration, the electroconductive part 26 is extended as extended part 26a, 26b on the other surface 2b. By adopting such a configuration, the wiring on the other surface 2b side can also be formed in a lump, and the manufacturing process can be reduced.
Further, as in the example shown in FIG. 5, the reinforcing material 57 may be arranged so as to cover at least a part of the conductive portion 56 that is extended. In the illustrated example, the conductive portion 56 is extended as extended portions 56a and 56b on the other surface 2b, and the reinforcing member 57 is extended as covering portions 57a and 57b on the other surface 2b. The covering portions 57a and 57b are formed so as to cover the extending portions 56a and 56b, respectively. By setting it as such a structure, a reinforcing material can serve as the overcoat layer for forming the bump mentioned later.

図2及び図5に示すような、基板2の何れかの面上に導電部が延設された半導体装置を製造する場合には、導電部26(56)を形成する工程を、貫通孔3の側面3a及び電極4の露呈部4aとともに、他方の面2b上まで、導電部の延設部26a、26b(56a、56b)が覆うように設ける方法とすれば良い。   When manufacturing a semiconductor device in which a conductive portion is extended on any surface of the substrate 2 as shown in FIGS. 2 and 5, the step of forming the conductive portion 26 (56) is performed through the through hole 3. The side surface 3a of the electrode 4 and the exposed portion 4a of the electrode 4 may be provided so that the extended portions 26a and 26b (56a and 56b) of the conductive portion cover the other surface 2b.

また、本実施形態の半導体装置は、図5に示すように、基板2の表面に補強材57を延設することによって、導電部56や配線回路8を保護するためのオーバーコート層(被覆部57a、57b)を配する際、導電部56の内面を補強材57で覆いながら、該補強材57が延設された被覆部57a、57bをオーバーコート層として一体成形することができ、作業工程の削減が可能となる。
この際、被覆部の一部に、導電部56aが覗き込むことができるような開口部57cを設けることにより、この開口部57cに半田バンプ58を設けることもできる。つまり、補強材57と被覆部57a、57bとを一体として形成することにより、従来は別体として設ける必要があったオーバーコート層を一緒に成形するので、密着性が向上するともに、工程が削減されて低コスト化が実現できる。また、この場合には、導電部56を覆う材料と、基板2の表面をオーバーコートする材料が同一材料であり、且つ継ぎ目の無い連続体として形成されるため、密着性の点で優れ、例えば、吸湿、高温環境等において生じるオーバーコート層の剥がれ等を防止することができる。
また、補強材57とオーバーコート層となる被覆部57a、57bとを一体成形する場合、材料に感光性樹脂を用いれば、基板2表面の配線に合わせ、高精度のパターン形状を有した被覆部57a、57bを形成することができる。
Further, as shown in FIG. 5, the semiconductor device of this embodiment has an overcoat layer (covering portion) for protecting the conductive portion 56 and the wiring circuit 8 by extending a reinforcing material 57 on the surface of the substrate 2. 57a, 57b), the covering portions 57a, 57b provided with the reinforcing material 57 can be integrally formed as an overcoat layer while covering the inner surface of the conductive portion 56 with the reinforcing material 57, and the working process Can be reduced.
At this time, by providing an opening 57c through which the conductive portion 56a can be looked into in a part of the covering portion, the solder bump 58 can be provided in the opening 57c. In other words, by forming the reinforcing material 57 and the covering portions 57a and 57b as one body, an overcoat layer that conventionally had to be provided separately is formed together, so that adhesion is improved and processes are reduced. As a result, cost reduction can be realized. Further, in this case, the material covering the conductive portion 56 and the material overcoating the surface of the substrate 2 are the same material and are formed as a seamless continuous body. It is possible to prevent peeling of the overcoat layer that occurs in moisture absorption, high temperature environment, and the like.
Further, when the reinforcing member 57 and the covering portions 57a and 57b to be the overcoat layers are integrally formed, if a photosensitive resin is used as the material, the covering portion having a highly accurate pattern shape according to the wiring on the surface of the substrate 2 57a and 57b can be formed.

また、本実施形態の半導体装置は、基板上において電極が配されていない位置に貫通孔を設けた場合であっても、貫通孔の側面のみを覆うように導電部を配し、該導電部を覆って接するように補強材を配した構成とすることにより、上述の効果が得られる。   In addition, the semiconductor device according to the present embodiment includes a conductive portion so as to cover only the side surface of the through hole even when the through hole is provided at a position where no electrode is provided on the substrate. The above-described effects can be obtained by adopting a configuration in which the reinforcing material is arranged so as to cover and touch.

以下、本発明に係る半導体装置の実施例について、図7〜8を用いて説明する。   Examples of the semiconductor device according to the present invention will be described below with reference to FIGS.

[作製工程]
基板として、厚さが200μm、大きさが6インチ(直径150mmの円)のシリコン半導体基板を用い、基板の一方の面に電極、機能素子及び配線回路(図示略)を配した。電極として、Alパッドを用いた。
そして、基板の他方の面から一方の面に配した電極が露呈するようにして、基板内に孔径が80μmの貫通孔を、DRIE(エッチング処理)によって形成した。貫通孔内の側面には、図示略の絶縁部として、SiOの被膜を形成した。
そして、貫通孔内の側面及び電極の露呈部を覆うようにしてシード層(Cr)及び銅材料を配することにより導電部を形成した後、導電部の内面に熱硬化性エポキシ樹脂を充填するように埋設して補強材を形成し、本発明に係る半導体装置(実施例)を得た(図8(a)参照)。
[Production process]
A silicon semiconductor substrate having a thickness of 200 μm and a size of 6 inches (a circle having a diameter of 150 mm) was used as a substrate, and electrodes, functional elements, and wiring circuits (not shown) were arranged on one surface of the substrate. An Al pad was used as the electrode.
And the through-hole whose hole diameter is 80 micrometers was formed in the board | substrate by DRIE (etching process) so that the electrode distribute | arranged to one side might be exposed from the other side of a board | substrate. A SiO 2 film was formed on the side surface of the through hole as an insulating portion (not shown).
And after forming a conductive part by arranging a seed layer (Cr) and a copper material so as to cover the side surface in the through hole and the exposed part of the electrode, the inner surface of the conductive part is filled with a thermosetting epoxy resin. Thus, a reinforcing material was formed by embedding the semiconductor device according to the present invention (Example) (see FIG. 8A).

また、上述同様にして、貫通孔を基板内に形成した後、貫通孔内の側面及び電極の露呈部を覆うようにして、電極と電気的に接続するように導電部を形成して該導電部の内面側に空間を有した状態とし、従来の半導体装置(比較例)を得た(図7(a)参照)。   Further, in the same manner as described above, after the through hole is formed in the substrate, a conductive portion is formed so as to be electrically connected to the electrode so as to cover the side surface in the through hole and the exposed portion of the electrode. A conventional semiconductor device (comparative example) was obtained with a space on the inner surface side of the part (see FIG. 7A).

[評価試験]
上述の各サンプルを、実施例n=260、比較例n=100の数量で用い、−40℃:30分、125℃:30分の計1時間を1サイクルとして、熱サイクル試験を計100サイクル:100時間行った。
熱サイクル試験終了後、各サンプルの電極の破断の有無を、顕微鏡で観察、確認した。
[Evaluation test]
Each of the above samples was used in the quantity of Example n = 260 and Comparative Example n = 100, and the thermal cycle test was performed in total of 100 cycles with 1 hour as a total of −40 ° C .: 30 minutes and 125 ° C .: 30 minutes. : Performed for 100 hours.
After the thermal cycle test, the presence or absence of breakage of the electrode of each sample was observed and confirmed with a microscope.

[評価結果]
図8(c)に示すように、本発明に係る半導体装置は、上記条件の熱サイクル試験を行った場合であっても電極の破断等が発生せず、初期状態(図8(b)参照)に対して変化が見られなかった。実施例のサンプル260台中、電極の破断が生じたサンプルは無かった。
[Evaluation results]
As shown in FIG. 8C, the semiconductor device according to the present invention does not break the electrode even when the thermal cycle test under the above conditions is performed, and the initial state (see FIG. 8B). ) Did not change. Of the 260 samples in the example, no sample had electrode breakage.

一方、図7(c)に示すように、従来の半導体装置は、上記条件の熱サイクル試験を行った後、比較例のサンプル100台中、78台に電極の破断が生じた。
図7(b)に示す初期状態においては、電極面に破断は見られないが、熱サイクル試験後、図7(c)に示すように、電極面に、貫通孔及び導電部に沿った円形の破断痕が生じている。また、図7(d)の断面図に示すように、電極の導電部と接している部分と、基板に接触している部分とが完全に破断している。
On the other hand, as shown in FIG. 7C, in the conventional semiconductor device, after performing the thermal cycle test under the above conditions, breakage of electrodes occurred in 78 of 100 samples of the comparative example.
In the initial state shown in FIG. 7 (b), the electrode surface is not broken, but after the thermal cycle test, as shown in FIG. 7 (c), the electrode surface has a circular shape along the through hole and the conductive portion. The fracture mark is generated. Further, as shown in the sectional view of FIG. 7D, the portion of the electrode in contact with the conductive portion and the portion in contact with the substrate are completely broken.

以上の結果により、本発明に係る半導体装置が、熱サイクルや高温環境下において使用される場合であっても、基板材料と電極及び導電部材料との間の熱膨張係数の差に起因して生じる熱ひずみに対し、導電部の内面側の空間に、樹脂等の別材料による補強材を配することによって応力を緩和でき、電極の破断等が生じず、高い信頼性を有することが明らかとなった。   From the above results, even when the semiconductor device according to the present invention is used in a thermal cycle or a high temperature environment, it is caused by the difference in thermal expansion coefficient between the substrate material and the electrode and conductive part material. It is clear that the stress can be relieved by arranging a reinforcing material made of another material such as resin in the space on the inner surface side of the conductive part against the generated thermal strain, and the electrode is not broken and has high reliability. became.

本発明に係る半導体装置の一例を説明する断面図である。It is sectional drawing explaining an example of the semiconductor device which concerns on this invention. 本発明に係る半導体装置の他例を説明する断面図である。It is sectional drawing explaining the other example of the semiconductor device which concerns on this invention. 本発明に係る半導体装置の他例を説明する要部断面図である。It is principal part sectional drawing explaining the other example of the semiconductor device which concerns on this invention. 本発明に係る半導体装置の他例を説明する要部断面図である。It is principal part sectional drawing explaining the other example of the semiconductor device which concerns on this invention. 本発明に係る半導体装置の他例を説明する要部断面図である。It is principal part sectional drawing explaining the other example of the semiconductor device which concerns on this invention. 本発明に係る半導体装置の製造方法の一例を説明する工程図である。It is process drawing explaining an example of the manufacturing method of the semiconductor device which concerns on this invention. 従来の半導体装置を用いて熱サイクル試験を行った場合の状態を説明する概略図である。It is the schematic explaining the state at the time of performing a heat cycle test using the conventional semiconductor device. 本発明に係る半導体装置を用いて熱サイクル試験を行った場合の状態を説明する概略図である。It is the schematic explaining the state at the time of performing a thermal cycle test using the semiconductor device concerning the present invention. 従来の半導体装置を説明する断面図である。It is sectional drawing explaining the conventional semiconductor device.

符号の説明Explanation of symbols

2、12…基板、2a…一方の面、2b…他方の面、3…貫通孔、3a…側面、4…電極、4a…露呈部、5…機能素子、16、26、36、46、56…導電部、26a、26b、56a、56b…延設部、17、27、37、47、57…補強材、27a、27b、57a、57b…被覆部、8…配線回路、9…絶縁部、10、20…半導体装置
DESCRIPTION OF SYMBOLS 2,12 ... Board | substrate, 2a ... One side, 2b ... The other side, 3 ... Through-hole, 3a ... Side surface, 4 ... Electrode, 4a ... Exposed part, 5 ... Functional element, 16, 26, 36, 46, 56 ... conductive parts, 26a, 26b, 56a, 56b ... extension parts, 17, 27, 37, 47, 57 ... reinforcing materials, 27a, 27b, 57a, 57b ... covering parts, 8 ... wiring circuits, 9 ... insulating parts, 10, 20 ... Semiconductor device

Claims (7)

基板の一方の面に配され、該面内にある機能素子と電気的に接続された電極と、
前記基板の他方の面から一方の面に配した電極が露呈するように、基板内に開けられた貫通孔と、
前記貫通孔内の側面及び前記電極の露呈部を覆うように配され、前記電極と電気的に接続された導電部と、
前記導電部に接するように配された補強材と、
を具備したことを特徴とする半導体装置。
An electrode disposed on one surface of the substrate and electrically connected to a functional element in the surface;
A through hole opened in the substrate so that the electrode disposed on the one surface from the other surface of the substrate is exposed;
A conductive portion disposed so as to cover the side surface in the through hole and the exposed portion of the electrode, and electrically connected to the electrode;
A reinforcing material disposed so as to be in contact with the conductive portion;
A semiconductor device comprising:
前記補強材は、前記導電部によって覆われた貫通孔内部に埋設されていることを特徴とする請求項1に記載の半導体装置   The semiconductor device according to claim 1, wherein the reinforcing material is embedded in a through hole covered with the conductive portion. 前記導電部は、前記他方の面上まで延設されていることを特徴とする請求項1又は2に記載の半導体装置。   The semiconductor device according to claim 1, wherein the conductive portion extends to the other surface. 前記補強材は、前記導電部の延設された少なくとも一部を覆うように配されていることを特徴とする請求項3に記載の半導体装置。   The semiconductor device according to claim 3, wherein the reinforcing material is disposed so as to cover at least a part of the conductive portion that is extended. 前記貫通孔内の側面と前記導電部との間に絶縁部を配したことを特徴とする請求項1乃至4のいずれか1項に記載の半導体装置。   5. The semiconductor device according to claim 1, wherein an insulating portion is disposed between a side surface in the through-hole and the conductive portion. 基板の一方の面に配され、該面内にある機能素子と電気的に接続された電極と、前記基板の他方の面から一方の面に配した電極が露呈するように、基板内に開けられた貫通孔と、 前記貫通孔内の側面及び前記電極の露呈部を覆うように配され、前記電極と電気的に接続された導電部と、前記導電部に接するように配された補強材とを具備してなる半導体装置の製造方法であって、
前記基板の他方の面から一方の面に配した電極が露呈するように、基板内に貫通孔を形成する工程と、
前記貫通孔内の側面と及び前記電極の露呈部を覆うように、前記電極と電気的に接続するように導電部を形成する工程と、
前記導電部を覆うように補強材を形成する工程と、
を少なくとも具備してなることを特徴とする半導体装置の製造方法。
An electrode that is disposed on one surface of the substrate and is electrically connected to a functional element in the surface and an electrode disposed on the one surface from the other surface of the substrate are opened in the substrate. A through hole, a conductive part electrically connected to the electrode, and a reinforcing member arranged to be in contact with the conductive part, covering the side surface in the through hole and the exposed part of the electrode A method for manufacturing a semiconductor device comprising:
Forming a through hole in the substrate so that the electrode disposed on the one surface from the other surface of the substrate is exposed;
Forming a conductive portion so as to be electrically connected to the electrode so as to cover the side surface in the through hole and the exposed portion of the electrode;
Forming a reinforcing material to cover the conductive portion;
A method for manufacturing a semiconductor device, comprising:
前記導電部を形成する工程は、前記貫通孔内の側面及び前記電極の露呈部とともに、前記他方の面上まで前記導電部が覆うように設けることを特徴とする請求項6に記載の半導体装置の製造方法。
7. The semiconductor device according to claim 6, wherein the step of forming the conductive portion is provided so that the conductive portion covers the other surface together with the side surface in the through hole and the exposed portion of the electrode. Manufacturing method.
JP2005287075A 2005-09-30 2005-09-30 Semiconductor device and manufacturing method of semiconductor device Expired - Fee Related JP4593427B2 (en)

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