JP3126784B2 - Stacked multi-chip semiconductor device - Google Patents

Abstract

PURPOSE:To provide a space between a terminal and a lead and improve solder permeability by providing a spacer on the terminal of a connector frame. CONSTITUTION:A connector frame 2a is provided with a front plane terminal, a rear plane terminal 26a and a rear plane terminal 27a. A front plane spacer 30a and a rear plane spacer 31a are formed on the top plane of the frame 2a. The front plane terminal 26a and the rear plane terminal 27a are connected by an edge plane through hole 29a. A connector frame 2b has a same structure as the connector frame 2a. The outer lead 15a of a TCP 1a passes between the front plane terminal 26a and the rear plane terminal 27b being sandwiched between the front plane spacer frame 2a and a rear plane spacer 31b and reaches the edge of the connector frame. Solder 33a wets the through hole 29a, the front plane terminal 26a and the rear plane terminal 27b and fills the whole connecting part. Solder 5 can be filled in the space between a board 34, which faces a board spacer 35 and the rear plane spacer 31a of the connector frame 2a making contact and that holds a fixed space by the spacer, and the rear plane terminal of the connector frame 2a.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device used for information equipment and the like, and more particularly to a multilayer multi-chip semiconductor device having a large capacity and a high reliability of a connection portion.

[0002]

2. Description of the Related Art Semiconductor memories are used in large amounts in information devices such as large computers, workstations, personal computers, and word processors, and it is expected that these devices will have higher performance, more functions, and more products in the future. Therefore, it is considered that the demand for the semiconductor memory used here is also increasing at an accelerating rate. In this case, in a device that requires a large-capacity memory, the mounting area occupied by the semiconductor memory in the device tends to increase more and more, which is the biggest factor that hinders miniaturization and weight reduction of the device.

As a method of solving this problem, there has been a method of increasing the memory capacity per chip by increasing the integration of elements in the chip, which has been strongly promoted in the past, or
A method of mounting a packaged memory module on a printed wiring board at high density, or Japanese Patent Application Laid-Open No. 59-180386.
As described in Japanese Patent Application Laid-Open No. H06-101067 and Japanese Patent Application Laid-Open No. 61-101067, there is a method of stacking a plurality of semiconductor chips in a thickness direction to achieve high density.

[0004] Among these methods, the method of increasing the density of elements in a chip has come to a new stage which cannot be solved by extension of the conventional technology, and it is necessary to develop a new technology and a new production facility. Methods for high-density mounting on printed wiring boards include miniaturization of modules, double-sided mounting on printed wiring boards, and the use of ZIP (zigzag in-line-package) components. It is difficult to further increase the density as far as a module in which a single package is used is used.

On the other hand, a method of stacking a plurality of IC chips in the thickness direction is extremely advantageous, and various proposals have been made so far.

[0006]

However, the methods proposed so far, including the disclosure in the above-mentioned publication, have a structure in which the terminals of the respective layers are connected in close contact with each other, so that sufficient connection reliability cannot be ensured. There was a problem.

It is an object of the present invention to provide a large-capacity multi-chip semiconductor device which solves the above-mentioned problems of the prior art and ensures high reliability of a connection portion.

[0008]

SUMMARY OF THE INVENTION An object of the present invention is to provide a multi-layered multi-layer tape carrier package comprising a plurality of tape carrier packages in which semiconductor chips are electrically connected to a film carrier tape via a connector frame having connection terminals on at least one surface thereof. In the chip semiconductor device, a multi-chip semiconductor device in which an insulating film is formed thicker than the connection terminal thickness on at least one surface of the connector frame, or a projection is formed on a part of the terminal on at least one surface of the connector frame A multi-chip semiconductor device, or
In a laminated multi-chip semiconductor device in which a plurality of tape carrier packages in which semiconductor chips are electrically connected to a film carrier tape are laminated and connected via a connector frame having a wiring pattern on at least one surface thereof, one end of the connector frame is connected to an end of the connector frame. A multi-layer semiconductor device having a structure exposed to the outside, or a plurality of tape carrier packages in which semiconductor chips are electrically connected to a film carrier tape having a wiring pattern on at least one surface via a connector frame. In the connected laminated multi-chip semiconductor device, the laminated carrier is a laminated multi-chip semiconductor device having a tape carrier package in which the lead of the film carrier package is the same as or more than the end surface of the connector frame terminal. Especially It can be achieved me.

[0009]

According to the above configuration, the thickness of the joint solder between the layers can be secured to a certain thickness or more, and sufficient solder can be supplied to the connection portion, and the high reliability of the connection of the connection portion can be ensured. Can be secured.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The configuration of the multichip semiconductor device of the present invention will be specifically described below with reference to embodiments.

An embodiment of the multichip semiconductor device of the present invention will be described with reference to FIGS. In the drawings, the same reference numerals denote the same contents, and a tape carrier package.
(Hereinafter abbreviated as TCP) and in the figure where connector frames are stacked in multiple levels,
Classification is made by adding symbols such as a, b, c, and d.

First, FIG. 1 is a diagram showing a cross section of a module in which a TCP 1 and a connector frame 2 are stacked alternately and an electrically connected multichip semiconductor device 6 of the present invention is connected to a motherboard 4 by solder 5. is there. That is, the connector frame 2 and the TCP 1 are alternately stacked in four layers, the top layer is covered, and joined by solder to form a multi-chip semiconductor device 6, which is mounted on the mother board 4 by the solder 5. To be connected.

Next, FIG. 2 shows a plan view of the TCP 1, and FIG. 3 shows a cross section taken along the line AA of FIG. In these figures, a bump 11 is formed on the upper surface of a semiconductor chip 10 and the bump 11
The inner lead 13 formed on the film carrier tape 12 is connected to the
The support ring 14 composed of a part of the base material holds the lead and has a role of a wiring area for expanding a lead pitch from the inner lead 13 to the outer lead 15.

A protective coating resin 16 is applied to the surface of the semiconductor chip 10 and the support ring portion 14 including the inner lead bonding portion. The leads arranged in the short side direction include a chip selection lead 18 connected to the chip selection bump 17, a common lead 15 connected to the other bumps 11, and a dummy lead 19 not connected to the bump. A temporary fixing lead 20 is provided on the support ring 14 in the long side direction.
Is arranged.

Next, FIG. 4 is a plan view of the connector frame, FIG. 5 is an enlarged plan view of a part of the connector frame, FIG. 6 is a side view of FIG.
FIG. 7 is a cross-sectional view taken along the line AA of FIG. 4 to 7, front and back terminals 26 and back terminals 27 are formed on the front and back surfaces of the base material 25, and the terminals on the front and back surfaces are electrically connected by end through holes 29 having lands 28 on the front and back surfaces. ing. Front spacer 30 and back spacer on the inside of the terminal
31 are formed. A temporary fixing terminal 32 is arranged on the surface of the base material 25 in the longitudinal direction.

FIG. 8 is a partially enlarged sectional view of the connecting portion. In this figure, the first-stage connector frame 2a has surface terminals.
26a and a back surface terminal 27a are formed, and a top surface spacer 30a and a back surface spacer 31a are formed on the upper surface of the terminal. The front terminal 26a and the back terminal 27a are connected by an end face through hole 29a. The second-stage connector frame 2b is also a first-stage connector frame.
It has the same structure as the connector frame 2a of the tier. The outer lead 15a of the TCP 1a has a front spacer 30a and a rear spacer 31b.
It passes between the front terminal 26a and the back terminal 27b in a form sandwiched between them and reaches the end of the connector frame. Also, solder 33a
Wets the end face through-hole 29a, the front surface terminal 26a, and the back surface terminal 27b, and is filled in the entire connection portion.

A substrate terminal 34 is formed on the motherboard 4, and a substrate spacer 35 is formed on the substrate terminal 34. The board spacer 35 and the backside spacer 31a of the connector frame 2a are opposed to and in contact with each other, and the solder 5 is provided between the board terminal 34 and the backside terminal 27a of the connector frame 2a, which are kept at a fixed interval by these spacers. Is filled.

FIG. 9 is a circuit block diagram for explaining the operation of the multi-chip semiconductor device 6. In this figure, semiconductor chips 10a, 10b, 10c and 10d have address terminals 40, data input / output terminals 41, write enable terminals 42,
Out enable terminal 43, power supply terminal 44, ground terminal 4
5. The chip selection terminals 46a, 46b, 46c, 46d are electrically connected. Of these terminals, chip select terminals 46a-4
6d is independently connected to each of the semiconductor chips 10a to 10d, but other terminals are commonly connected to the semiconductor chips 10a to 10d. Note that in FIG.
And the data input terminal 41 is shown by one line,
The actual wiring is composed of a plurality of wires. In contrast,
Write enable terminal 42, out enable terminal 43, power supply terminal 44, ground terminal 45, and chip selection terminals 46a to 46d
Is often one in each case in actual wiring.

In this circuit, first, in writing data to the semiconductor chip 10, necessary information is given as electrical signals to address lines and data lines, and a write enable signal line is
By turning on the chip selection terminal of the chip for which information is to be stored while it is on, predetermined information is stored at a desired address of the selected chip. The other three chips have their chip selection terminals kept off, so that the information inside the chips does not change. Similarly,
To read information from the chip, a signal indicating an address from which information is to be extracted is given to an address line, a data input / output permission terminal is turned on, and a chip selection terminal from which information is to be extracted is turned on. Information from a desired address of the selected chip is output to the data input / output terminal.

FIG. 10 is a perspective view of the chip selection terminal portion.
In this figure, a chip select terminal is provided on the motherboard 4.
50a to 50d, and a chip selection terminal on connector frame 2
51a to 51d are formed. Also, on the TCP 1 side, chip select bumps 17a to 17d are formed at common positions of the semiconductor chips 10 of each stage, and these bumps 17a to 17d are formed.
And chip selection leads 18a to 18d having different pattern shapes depending on each stage are formed.
Are connected to the chip selection terminal 51 of FIG. Three dummy leads 19 that are not connected to the bumps on the chip are formed on the TCP 1 film, and the dummy leads 19 are connected to the terminals of the connector frame 2.

FIGS. 11 and 12 are enlarged cross-sectional views of the connection portion showing the connection state between the connector frame terminal and the TCP 1 lead and between the multi-chip semiconductor device 6 and the motherboard 4. FIG. 11 shows a common terminal portion (A-A in FIG. 9). FIG. 12 shows the fourth stage semiconductor 10d.
10 is an enlarged cross-sectional view of a connection portion at a chip selection position connected to a motherboard (a position BB in FIG. 9). In FIG. 11, a substrate terminal 34 is formed on the surface of the motherboard 4, and a substrate spacer 35 is formed on the substrate terminal 34. The connector frame 2a and the connector frame 2b are connected by solder with the outer lead 15a of the TCP 1a interposed therebetween.
Similarly, connector frame 2b and connector frame 2c, connector frame 2
c and connector frame 2d, connector frame 2d and lid 3
The outer leads 15 of TCP 1 are sandwiched and connected by solder 33. The connector frame 2 a and the motherboard 4 are connected by solder 5.

In FIG. 12, a chip selection bump 17d is connected to a chip selection lead 18d, and the connector frames are connected to each other by solders 33a to 33d with a dummy lead 19 interposed therebetween. Is electrically connected to the chip selection substrate terminal 50d arranged at the same time.
In contrast, the first to third chip select bumps 17a to 17a-1
7c is not connected to the lead at this cross-sectional position.

In such a configuration, the detailed structure of each part of the multichip semiconductor device according to the present invention will be described below.

First, in FIG. 1, a mother board 4 is a printed wiring board having single-layer and multi-layer wirings, and has a multi-chip semiconductor device 6 shown in FIG. With
(Wiring and other components are not shown), which is a part of an electronic device having functions such as input / output, calculation, storage, and display.

2 and 3, the semiconductor chip 10 is made of silicon and has a memory element formed therein.
It is a dynamic random access memory having a bit storage capacity. On the surface of the semiconductor chip 10, gold bumps 11 and 17 formed by plating as signal input / output terminals are arranged.

The film carrier tape 12 is formed by fixing a copper foil to a polyimide film and patterning the copper foil to form a lead. The lead surface after patterning is plated with gold using nickel as a base.

The inner leads 13 formed on the film carrier tape are aligned with the bumps 11 and 17 on the semiconductor chip 10, and a heating block is pressed from above the inner leads 13, and connected by a gold-gold thermocompression bonding method. I do.

Here, the bumps 11 on the semiconductor chip 10 and
The formation of 17 is not particularly limited to the formation by the plating method, but it is possible to fix a small piece of gold formed in a separate process in advance, or to attach gold wires to the bumps 11 and 17 using the principle of wire bonding. A method such as thermocompression bonding to a shape can also be applied. Further, the material is not limited to gold, but may be copper, nickel, or an alloy thereof.

The surface treatment of the leads on the film carrier tape is not limited to gold plating, and tin plating, solder plating and the like can be sufficiently applied. Further, the material of the lead is not limited to copper, and copper alloy, iron, iron alloy, and the like can be applied.

The protective coat protects the surface of the chip 10 and the inner lead 13 and is made of an epoxy resin in this embodiment. The arrangement of the bumps 11 and 17 on the chip is shown on the short side in FIG.
Naturally, those arranged on the long sides, those arranged on the four sides, and those arranged at the center of the chip are also included.

In FIG. 2, the temporary fixing leads formed on the long sides are used for temporary connection when the TCP 1 and the connector frame 2 are aligned and fixed. That is,
In the step of stacking and connecting the TCP1 and the connector frame 2 in a plurality of stages, first, a set of the TCP1 and the connector frame 2 are temporarily fixed to form a TCP with a connector frame (hereinafter abbreviated as a TCP with a frame). The alignment between the connector frame 2 and the TCP 1 is performed using an alignment mark (not shown) provided on each of them, and the temporary fixing lead of the TCP 1 is thermocompression-bonded to the temporary fixing terminal of the connector frame. I do.

The connector frame 2 shown in FIGS.
This is to connect the leads of each TCP1 when connecting multiple TCPs, and to keep the interval between TCP1s constant at the same time.

In FIGS. 4 to 8, the connector frame 2 is formed as a connection terminal by forming a pattern on the front and back using a double-sided copper-clad laminate of a glass epoxy base material 25, and a through-hole for connecting the front and back pattern. Is formed, a resin layer serving as a spacer is formed on a part of the connection terminal by a screen printing method, and then the outer shape is punched into a shape shown in FIG. The front and back patterns and through holes are subjected to solder plating on copper plating. In the above punching,
By designing the mold so as to cut along the center line of the through hole, an end face through hole 29 exposing a part of the inner wall of the through hole is formed. The temporary fixing terminal is used for temporary connection with TCP 1 as described above.

In this embodiment, a double-sided copper-clad laminate of a glass epoxy base material 25 is used for the connector frame 2, but the material of the connector frame 2 is not limited to this, and other materials such as organic resin or ceramic may be used. Can be used.

The spacers 30 and 31 ensure the thickness of the solder connection layer at the time of lamination connection, and the solder of the connection portion is TCP 1
Epoxy resin is used to prevent solder from penetrating inside through the leads.They are not limited to epoxy resin, but are not limited to epoxy resin. And other inorganic materials can be used. Further, when forming the front and back patterns, it is also possible to form a part of the pattern at the spacer position shown in the figure in a convex shape by plating or etching. The surface of the front and back patterns other than the portion covered by the spacer is a connection terminal contributing to the connection. Although the surface of the terminal on the connector frame is plated with solder, this is not limited to solder, and may be gold, tin, or copper when a through hole is formed.

In FIGS. 2 and 10, the chip selecting bumps 17 on the multi-chip semiconductor device 6 are arranged at fixed positions on the chip 10, so that the type of the chip is not affected by the stacked stages. One type is sufficient. Also, connector frame 2
May be at the same pattern position in each stage, and may be of one type. On the other hand, since the film carrier tape 12 has a different pattern shape for each stage, four types of film carrier tapes 12 are prepared according to the respective patterns.
As shown in FIG. 12, the dummy leads 19 on the TCP 1 are used to connect between the connector frames 2 at each stage of the chip selection terminal portion.

The lid shown in FIGS. 1 and 10 provides internal protection when the multichip semiconductor device 6 is mounted on the motherboard 4 by using a printed wiring board having no internal hollow, and also has terminals for terminals formed on the surface. By increasing the area, it is possible to easily perform the electrical characteristic inspection at the time of stacking four layers.

Here, a method of laminating the TCP 1 and the connector frame 2 will be described. The stacked connection between TCP 1 and connector frame 2 is performed by first aligning TCP 1 and connector frame 2 in each stage, temporarily fixing them to form TCP 1 with a frame, and then attaching the frame.
TCP 1 is aligned in four stages, and the lid is aligned with the uppermost layer, and stacked and connected. Here, for temporary fixing of the framed TCP 1, the temporary fixing terminal 32 of the connector frame 2 and the temporary fixing lead 20 of the TCP 1 are crimped by a heating and pressure bonding method of a pulse heating method. In this case, since solder plating is used for the terminals of the connector frame 2 and gold plating is used for the TCP 1 paste, solder reflow connection is possible without using flux, and cleaning after this process is unnecessary. There is an advantage that there is. In the present embodiment, the temporary fixing by thermocompression bonding has been described, but a method of fixing by an adhesive, fixing by mechanical clamping, or the like is also applicable.

In order to temporarily fix the four TCPs 1 with the frame and the lid on the uppermost layer, a method was adopted in which the steps were sequentially aligned one by one from the first position and temporarily fixed with an adhesive. In this case, the upper framed TCP 1 was pressed with a constant load when the adhesive was cured so that the thickness of each connection layer was constant. Align the four TCP1s with the frame and the lid on the uppermost layer, temporarily fix them, apply a soldering flux to the joints, and immerse 29 of the through holes in the end face in molten solder to solder the joints. Was attached.

The multi-chip semiconductor device 6 thus solder-connected is aligned and arranged on the mother board 4 on which solder printing has been performed, and solder connection is performed by vapor reflow soldering to obtain a multi-chip semiconductor module.

FIG. 11 is a view showing a cross section of a connection portion of the multi-chip semiconductor module. The mother board 4, the multi-chip semiconductor device 6, the terminals of the connector frame of each stage, and the TCP
This indicates that the lead 1 is completely connected by solder.

Next, an application example of this embodiment will be described with reference to FIG.
14 explains.

FIG. 13 is a sectional view of a connection portion between the terminal of the connector frame 2 and the outer lead of TCP 1. In this figure, the outer lead 15a of TCP 1 sandwiched between the front terminal 26a of the connector frame 2a and the rear terminal 27b of the connector frame 2b.
Has a structure in which only L extends from the end of the connector frame 2.

FIG. 14 is a plan view of the connecting portion shown in FIG. In this figure, the tip portion of the outer lead 15 is wider than the original portion, and has substantially the same size as the land 28. FIGS. 15 and 16 are enlarged views of the cross section of the connection portion after solder connection. FIG. 15 shows a connection portion with good solder wettability of the lead, and FIG. 16 shows a state of the connection portion with poor wettability. It is.

The present embodiment provides a structure capable of reliably performing an inspection of the solder wettability of the lead of the TCP 1 at the time of assembling the multichip semiconductor device and connecting the solder. That is, by protruding the outer lead from the end of the connector frame 2 as shown in FIGS.
By making the width of the tip of the outer lead 15 equal to the width of the end face through-hole 29, when the solder wettability is good, a good solder fillet 60 is formed as shown in FIG. 15 and when the wettability is poor. Since no solder fillet is formed as shown in FIG. 16, solder wettability can be easily inspected from the appearance.

[0046]

As described above, by using a multi-chip semiconductor device according to the present invention as a device according to the present invention, it is possible to solve the problems of the prior art and secure a high reliability of the connection portion. A multi-chip semiconductor device having a large capacity can be provided.

That is, by providing the spacers on the terminals of the connector frame, it is possible to provide a certain distance between the terminals and the leads. The occupying gold content could be greatly reduced, and the connection reliability could be greatly improved. In addition, by adopting a structure that exposes the connection part of the connector frame to the end face by using a through hole structure at the end face and also exposes the end part of the TCP lead at the same time, the appearance of the connection state can be inspected at a glance, and the quality can be improved. Improvements and productivity can be achieved. Furthermore, the connection process can be simplified by enabling the solder connection by the molten solder method, and the gold on the TCP lead surface diffuses into the molten solder, minimizing the gold content in the connection area. This greatly improved the connection reliability.

[Brief description of the drawings]

FIG. 1 is a sectional view of a connection portion of a multichip semiconductor device of the present invention.

FIG. 2 is a plan view of a TCP.

FIG. 3 is a sectional view taken along the line AA of FIG. 2;

FIG. 4 is a plan view of a connector frame.

FIG. 5 is a partially enlarged plan view of the connector frame.

FIG. 6 is a side view of the connector frame.

FIG. 7 is a sectional view of an AA portion of the connector frame.

FIG. 8 is a partially enlarged cross-sectional view of a multi-chip semiconductor device.

FIG. 9 is a circuit block diagram of a multichip semiconductor device.

FIG. 10 is a perspective view of a chip selection terminal unit.

FIG. 11 is an enlarged sectional view of a connection portion of the common terminal portion.

FIG. 12 is an enlarged sectional view of a connection portion of a chip selection terminal portion.

FIG. 13 is a sectional view of a connection portion between a connector frame terminal and a TCP outer lead.

FIG. 14 is a plan view of the connecting portion in FIG. 13;

FIG. 15 is an enlarged cross-sectional view of a connection portion of a lead with good solder wettability.

FIG. 16 is an enlarged cross-sectional view of a connection portion of a lead having poor solder wettability.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... TCP (tape carrier package), 2 ... Connector frame, 4 ... Motherboard, 5 and 33 ... Solder, 6 ... Multi-chip semiconductor device, 10 ... Semiconductor chip, 15 ... Outer lead, 18 ... Chip select lead, 19 ... Dummy Lead,
26 ... front terminal, 27 ... rear terminal, 29 ... end face through hole, 30 ... front spacer, 31 ... rear spacer, 50 ... chip selection board terminal, 51 ... chip selection terminal, 60 ... fillet.

──────────────────────────────────────────────────続 き Continuing from the front page (72) Inventor Hiroyuki Tanaka 292 Yoshidacho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Within the Hitachi, Ltd. Production Engineering Laboratory (72) Inventor Ichiro Miyano 292 Yoshidacho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Hitachi, Ltd., Production Technology Laboratory (72) Inventor Kazuo Yamazaki 5-2-1, Josuihonmachi, Kodaira-shi, Tokyo Hitachi, Ltd.Semiconductor Design and Development Center (72) Inventor Munehiro Yamada, Kodaira-shi, Tokyo 5-20-1, Mizumotocho Hitachi Semiconductor Co., Ltd. Semiconductor Design and Development Center (56) References JP-A-2-198148 (JP, A) JP-A-2-134859 (JP, A) (58) Field (Int.Cl. ⁷ , DB name) H01L 25/10 H01L 25/04

Claims (16)

(57) [Claims] 1. A laminated multi-chip semiconductor device in which a plurality of tape carrier packages in which semiconductor chips are electrically connected to a film carrier tape are laminated and connected via a connector frame having connection terminals on at least one surface thereof. A multi-chip semiconductor device, wherein an insulating film is formed on at least one surface of the insulating film so as to be thicker than the connection terminal. 2. The laminated multi-chip semiconductor device according to claim 1, wherein said insulating film is formed on a base material of said connector frame. 3. The stacked multi-chip semiconductor device according to claim 1, wherein said insulating film is formed on a terminal of said connector frame. 4. The laminated multi-chip semiconductor device according to claim 1, wherein an organic resin is used for said insulating film. 5. The stacked multi-chip semiconductor device according to claim 1, wherein an inorganic insulator is used for said insulating film. 6. The stacked multi-chip semiconductor device according to claim 1, wherein said insulating film is formed of a solder resist film. 7. The laminated multi-chip semiconductor device according to claim 1, wherein said insulating film is formed of a ceramic insulating film. 8. A laminated multi-chip semiconductor device in which a plurality of tape carrier packages each having a semiconductor chip electrically connected to a film carrier tape are laminated and connected via a connector frame having connection terminals on at least one surface thereof. 3. A stacked multi-chip semiconductor device, wherein a protrusion is formed on at least one surface of the terminal. 9. The stacked multi-chip semiconductor device according to claim 8, wherein said protrusions are formed of the same material as the terminals. 10. The stacked multi-chip semiconductor device according to claim 8, wherein said projection is formed of a material different from that of said terminal. 11. The stacked multi-chip semiconductor device according to claim 8, wherein said protrusions are formed by plating. 12. The stacked multi-chip semiconductor device according to claim 8, wherein said protrusions are formed by a printing method. 13. A laminated multi-chip semiconductor device in which a plurality of tape carrier packages each having a semiconductor chip electrically connected to a film carrier tape are laminated and connected via a connector frame having a wiring pattern on at least one surface thereof. A stacked multi-chip semiconductor device having a structure in which one end of an upper pattern is exposed to an end of a connector frame and an insulating film according to any one of claims 1 to 7 is added. 14. A laminated multi-chip semiconductor device in which a plurality of tape carrier packages each having a semiconductor chip electrically connected to a film carrier tape are laminated and connected via a connector frame having a wiring pattern on at least one surface thereof. 13. A stacked multi-chip semiconductor device having a structure in which one end of an upper pattern is exposed to an end of a connector frame, and the projections according to claims 8 to 12 are added. 15. At least one of the elements shown in claims 1 to 14
Using a connector frame having a different structure, a tape carrier package for electrically connecting the semiconductor chip to the film carrier tape having a wiring pattern on at least one surface, the laminated multi-chip semiconductor device in which a plurality of stacked connected through the connector frame A multilayer multi-chip semiconductor device having a tape carrier package in which leads of the film carrier package are extended from ends of the connector frame. 16. The multi-layer semiconductor chip according to claim 15, wherein the lead width of the film carrier package located near the end of the connector frame is equal to or larger than the terminal width of the connector frame. apparatus.