JP3033315B2 - Stacked multi-chip semiconductor device and manufacturing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of a semiconductor device and a method of manufacturing the same, and more particularly, to a structure of a large-capacity stacked multi-chip semiconductor device having a plurality of memory capacities for the same mounting area as a conventional IC package. It relates to a manufacturing method.

[0002]

2. Description of the Related Art Semiconductor memory is a large computer,
It is used in large quantities in information devices such as workstations, personal computers, and word processors, and the demand for semiconductor memory used in these devices is also accelerating as these devices become more sophisticated, multifunctional, and expand their products. It is expected that the number will increase. On the other hand, in a device requiring a large-capacity memory, the mounting area occupied by the semiconductor memory in the device tends to increase more and more, which is the biggest factor that hinders the reduction in size and weight of the device. One of the solutions to this problem is to increase the memory capacity per chip due to the high integration of elements in the chip, which has been strongly pushed in the past. Another one is a method of mounting a packaged memory module on a printed wiring board at high density, and another one is a method of Japanese Patent Laid-Open No. 59-194460.
As described in Japanese Patent Application Laid-Open No. 61-185958, a plurality of semiconductor chips are stacked in the thickness direction to achieve high density. Of these, the increase in the density of elements in a chip has come to a new stage which cannot be solved by extension of the conventional technology, and it is necessary to develop a new technology and a new production facility.

In addition, high-density mounting on a printed wiring board requires miniaturization of a module, double-sided mounting on a printed wiring board, ZI
Although P (zigzag in-line-package) components are employed, it is difficult to further increase the density in a range where a module in which one chip is packaged is used.

On the other hand, a method of stacking a plurality of IC chips in a thickness method is very advantageous, and various methods have been proposed.

[0005]

However, the conventional method of stacking a plurality of IC chips has a structure in which the terminals of each layer are connected in close contact with each other, so that the connection reliability cannot be sufficiently ensured. However, there is a problem that it is difficult to inspect the bonding state after the assembly because of the structure arranged inside.

An object of the present invention is to provide a structure and a manufacturing method of a stacked multi-chip semiconductor device in which the above-mentioned disadvantages of the prior art are eliminated, the appearance inspection can be easily performed, and the connection reliability is sufficiently ensured.

[0007]

SUMMARY OF THE INVENTION The object of the present invention is to fold a TCP lead along an end of a connector frame to dispose a connecting portion on an end face of a module and to make a thickness of a bonding solder between layers sufficiently large. This is achieved by:

[0008]

According to the present invention, there is provided a laminated multi-chip semiconductor device in which a plurality of tape carrier packages in which semiconductor chips are electrically connected to a film carrier tape having a wiring pattern on at least one surface are laminated and connected via a connector frame. A laminated multi-chip semiconductor device comprising a tape carrier package having an insulating film formed on at least one surface of a carrier tape so as to be thicker than the wiring pattern.

According to the structure of the present invention, a structure in which a protrusion is formed on the upper surface of the TCP or a recess deeper than the outer lead is formed on the upper surface of the connector frame, and the lower surface lead is structured to be wider than the recess, thereby providing a frame. An immersion soldering method that can keep the thickness of the solder layer connecting the leads sufficiently thick and constant at the time of TCP lamination can be adopted, and the connection reliability has been greatly improved. Further, since the outer leads are completely exposed at the end faces, the appearance inspection of the connection state can be performed at a glance, thereby improving the quality and productivity. Furthermore, since the outer leads of the TCP can be bent along the lower surface from the end of the connector frame to connect the upper and lower surfaces of the connector frame, a connector frame that does not require a wiring pattern can be used, and the cost of members can be greatly increased. The reduction was achieved.
In addition, since a certain spacing can be provided between the leads, the solder permeability at the time of solder fusion connection can be improved, and further, the content of gold in the solder at the connection portion can be significantly reduced, and the connection reliability can be reduced. Performance can be greatly improved.

[0010]

An embodiment of the present invention will be described below with reference to the drawings.

First, a first embodiment will be described with reference to FIGS. In the drawings, the same reference numerals indicate the same contents (the same applies to the following description). Also, TC
In the figure in which the P and the connector frame are stacked in a plurality of stages, it is assumed that the numbers are denoted by a, b, c, and d after the numerals from the lower stage to the upper stage.

FIG. 1 shows a tape carrier package (hereinafter referred to as T).
A cross section in which a multi-chip semiconductor device 4 according to the present invention, in which 1 and connector frames 2 are alternately stacked and electrically connected by attaching a cover 3 to the uppermost layer, is connected to a motherboard 5 by solder 6. FIG.

FIG. 2 is a plan view of the TCP 1 with a part cut away and broken, and FIG. 3 is a cross-sectional view taken along the line AA in FIG.

2 and 3, the semiconductor chip 1
A bump 11 is formed on the upper surface of the film carrier tape 0, and an inner lead 13 formed on the film carrier tape 12 is electrically connected to the bump 11.

A support ring 14 formed of a part of the base material of the film carrier tape 12 holds a lead and has a role of a wiring area for widening a lead pitch from the inner lead 13 to the outer lead 15. A lead holding tape 16 is provided at an end of the outer lead 15.

A protective coating resin 17 is applied to the surface of the semiconductor chip 10 and the support ring 14 including the inner lead bonding portion.

The leads arranged in the lateral direction include a chip selection lead 19 connected to the chip selection bump 18, a common lead 15 connected to the other bumps 11, and dummy leads 20, 21, 22 not connected to the bumps. Further, a protrusion 23 made of an organic insulating resin is formed at an intermediate position between the inner lead portion and the outer lead portion.

FIG. 4 is a plan view of the connector frame 2, FIG. 5 is an enlarged view of a part of the connector frame in an application example of the embodiment, (a) is a plan view, and (b) is a side view of (a). FIG.

In FIG. 4, the connector frame 2 is a short member 3
0 and the longitudinal member 31 are integrally formed in a frame shape with a hollow central portion, and are formed to be slightly thicker than the TCP1. 5A and 5B, the short member 30
A concave portion 32 is formed on the surface of the.

FIG. 6 is a perspective view of a framed TCP 35 in which the TCP 1 and the connector frame 2 are combined. FIG. 7 is an enlarged cross-sectional view of a part of the multi-chip semiconductor device 4 shown in FIG. It is a figure for explaining the details of lamination connection in a figure.

6 and 7, the support ring 14 of the TCP 1 is disposed on the upper surface of the short member 30 of the connector frame 2, the upper part of the support ring 14 of the outer lead 15 becomes the upper surface lead 36, The missing portion is bent along the end surface of the connector frame 2 to become an end surface lead 37, and the lead holding tape 16 is disposed on the lower surface of the connector frame 2 and the lead portion on the lead holding tape 16 forms a lower surface lead 38. . The upper surface of the connector frame 2 and the support ring 14 are bonded and fixed to an upper adhesive 39, and the lead holding tape 16 and the lower surface of the connector frame 2 are bonded and fixed by a lower adhesive 40. A protrusion 23 is formed on the support ring 14 and at a position on the chip side of the outer lead 15. A substrate terminal 41 is formed on the upper surface of the motherboard 4, and a substrate protrusion 42 is formed at a position on the chip side of the upper surface of the substrate terminal 41. The solder 43a connects the upper surface lead 36a of the TCP 35a with the first step frame and the lower surface lead 38b of the TCP 35b with the second step frame.
The solder 6 is composed of the substrate terminal 41 and the first step framed TCP 35a.
Are connected.

FIG. 8 is a circuit block diagram for explaining the operation of the multi-chip semiconductor device 4. In this figure, address terminals 50, data input / output terminals 51, write enable terminals 52, out enable terminals 53, power supply terminals 54, ground terminals 55, and chip selection terminals 56a, 56 are provided on semiconductor chips 10a, 10b, 10c, 10d.
b, 56c and 56d are electrically connected. Among these terminals, the chip selection terminals 56a to 56d are independently connected to the respective semiconductor chips 10a to 10d, but the other terminals are commonly connected to the semiconductor chips 10a to 10d. Although the address terminal 50 and the data input / output terminal 51 are shown by one line in FIG. 8, the actual wiring is composed of a plurality of lines. On the other hand, each of the write enable terminal 52, the out enable terminal 53, the power supply terminal 54, the ground terminal 55, and the chip selection terminals 56a to 56d is often one in actual wiring.

In this circuit, first, the semiconductor chip 10
For writing to the memory, necessary information is given as an electrical signal to the address terminal 50 and the data input / output terminal 51, the write enable terminal 52 is turned on, and the chip selection terminal 56 of the chip in which information is to be stored is turned on. As a result, information necessary for a desired address of the selected chip is stored. As for the other three chips, the chip selection terminals 56 are kept off, so that the information inside the chips does not change.

Similarly, the reading of information from the chip is performed by
A signal indicating an address from which information is to be extracted is given to the address terminal 50, the out enable terminal 53 is turned on, and the chip selection terminal 56 from which information is to be extracted is turned on. Is output to the data input / output terminal 51.

FIG. 9 is a perspective view showing a chip select terminal arrangement portion of the multi-chip semiconductor device 4 for each stage. In this figure, chip selection board terminals 60 a to 60 d and a common board terminal 41 are formed on a motherboard 5. On the TCP 1 side, respective chip selection bumps 18a to 18d and bumps 11 for common terminals are formed at the same position on the semiconductor chip 10 in each stage. Outer portions are connected to the chip selection bumps 18a to 18d and connected to the respective stages. Chip selection leads 19a to 19d having different lead arrangement positions are formed. On the TCP1 film, three dummy leads 20, 21, 22 that are not connected to the bumps on the chip are formed for each TCP.

FIGS. 10 and 11 are cross-sectional views of connection portions showing the connection between the TCPs and the connection between the multi-chip semiconductor device 4 and the motherboard 5. FIG. 10 shows a common terminal portion (A in FIG. 8).
FIG. 11 shows a fourth-stage semiconductor chip 10d.
FIG. 9 is an enlarged cross-sectional view of a connection portion at a chip selection position connected to the motherboard 5 (position BB in FIG. 8). FIG.
At 0, a substrate terminal is formed on the surface of the motherboard 5, and a substrate protrusion 42 is formed on the substrate terminal 41. TCP1a and TCP1b are connected by solder 43a. Similarly, TCP1b and TCP1c are connected by solder 43b, TCP1c and TCP1d are connected by solder 43c, and TCP1d and lid 3 are connected by solder 43d. The TCP 1 a and the motherboard 5 are connected by solder 6. Figure 2 shows the TCP1
As described with reference to FIG. 3, the outer leads 15, the inner leads 13, the bumps 11, and the semiconductor chip 10 are formed and are electrically connected.

In FIG. 11, a chip select bump 18d disposed on the fourth stage TCP 1d is connected to a chip select lead 19d, and the respective TCPs are sandwiched between dummy leads 22a to 22c. Solder 4
They are connected by 3a to 43c, and are further electrically connected to a chip selection board terminal 60d arranged on the motherboard 5. On the other hand, the first to third TCP
Chip selection bumps 18a-18 arranged on 1a-1c
c is not connected to the outer lead at this cross-sectional position.

In such a configuration, the detailed structure of each part of the multichip semiconductor device according to the present invention will be described.

First, in FIG. 1, a mother board 5 is a printed wiring board having single-layer and multi-layer wirings. On the surface thereof, other semiconductor parts and general electric parts are mounted together with the multi-chip semiconductor device 4 shown in FIG. (Wiring and other parts are not shown), input / output, operation,
It is a part of an electronic device having functions such as storage and display. The motherboard 5 and the multi-chip semiconductor device 4 are electrically connected by solder 6. The multi-chip semiconductor device 4 has a T
Connector frames 2 for keeping the interval between the CP 1 and each TCP constant are alternately stacked, and the leads between the TCPs are electrically connected by solder. The cover 3 protects the internal semiconductor chip and has a wiring pattern on the upper surface thereof that is electrically connected to the leads of the uppermost layer TCP, and has a structure capable of inspecting the electrical characteristics of the multi-chip semiconductor device.

2 and 3, the semiconductor chip 10 is made of silicon and has a memory element formed therein.
Dynamic random with M-bit storage capacity
Access memory. On the surface of the semiconductor chip 10, gold bumps 11 and 18 formed by plating as signal input / output terminals are arranged. The film carrier tape 12 is composed of a combination of a polyimide film and a copper foil fixed on the film, and the copper foil is patterned and used as a lead, and the lead surface after patterning is made of nickel as a base. Gold plated. The inner leads 1 formed on the film carrier tape 12 are formed on the bumps 11 on the semiconductor chip 10.
3, the heating block is pressed from above the inner leads 13, and the bumps 11 and the inner leads 13 are connected by a gold-gold thermocompression bonding method.

Here, the bumps 11 on the semiconductor chip 10
The method of forming the gold wire is not particularly limited to the plating method, but a method of fixing a small piece of gold formed in another step in advance, or forming a gold wire into the shape of the bump 11 by using the principle of wire bonding. A method such as pressure bonding can also be used. The material is not limited to gold, but copper,
Of course, nickel and alloys thereof may be used.

The surface treatment of the leads on the film carrier tape 12 is not limited to gold plating, and tin plating, solder plating and the like can be applied sufficiently. In addition, the material of the lead is not limited to copper, and it is needless to say that copper alloy, iron, iron alloy and the like can be applied.

The protective coating resin 17 protects the surface of the chip 10 and the bonding portion including the inner leads 13 and is coated with an organic resin by a potting method. Instead, they may be inorganic or a mixture of organic and inorganic. In addition, the method of applying the resin is not limited to the potting method, and a dipping or transfer molding method can be sufficiently applied.

The arrangement of the bumps 11 on the chip 10 is shown in FIG.
In the above, the one arranged on the short side of the chip 10 is shown, but the one arranged on the long side on the chip 10, the one arranged on four sides, and the one arranged at the center of the chip 10 Of course applicable.

The outer lead holding tape 16 is used to prevent the outer lead 15 from being deformed when the outer lead 15 is formed and cut from a long tape and during subsequent handling, and when the lead is bent and adhered and fixed to the back surface of the connector frame. In order to hold the outer lead and prevent disturbance.

The protrusions 23 are used to secure the thickness of the solder connection layer when the TCPs 1 are stacked and connected in multiple stages, and to prevent the solder at the connection portion from passing through the leads and entering the chip side. Although an epoxy-based resin that sufficiently withstands the application temperature was used, this is not limited to the epoxy-based resin, and other organic resins or inorganic materials can also be used. Further, when forming the outer leads, it is also possible to form a part of the leads at the protruding arrangement positions shown in the figure in a convex shape by plating or etching.

The connector frame 2 shown in FIG. 4 and FIG.
This is for keeping a constant interval between the TCPs 1 when a plurality of 1s are stacked and connected.

In FIGS. 4 and 5, the connector frame 2 uses a glass epoxy base material, but the material is not limited to this, and any other organic resin or inorganic material such as a ceramic substrate is used. Can also be used.

Although FIG. 4 shows a connector frame 2 having no pattern, concave portions, and convex portions, it is needless to say that a connector frame 2 having a pattern, concave portions, and convex portions can be sufficiently applied.

The concave portion 32 shown in FIG.
The role of the guide groove when arranging the outer lead 1;
By making the depth of the recess 32 larger than the thickness of the outer lead, a sufficient solder thickness at the time of laminating and bonding can be ensured without any protrusion on the TCP 1.

In FIGS. 6 and 7, the end face leads 37 are formed by eliminating a film portion to facilitate bending of the leads and to improve the dimensional accuracy after the bending. The protrusions 23 keep the distance between the upper surface lead 36 of one TCP and the lower surface lead 38 of the other TCP constant, thereby facilitating penetration of the solder into the connection portion at the time of soldering, and improving the solderability. Connection is enabled. In addition, the end surface lead 37 serves to connect the upper surface lead 36 and the lower surface lead 36 on the TCP.

The flow of the electric signal will be described with reference to FIGS. 9 and 10, the signal applied to the board terminal 41 of the motherboard 5 passes through the solder 6, passes through the outer lead 15a, the inner lead 13a, and the bump 11a of the TCP 1a. It is connected to the semiconductor chip 10a. At the same time,
Similarly, a signal is transmitted to TCP1b, TCP1c, and TCP1d, and the same signal is sent to each semiconductor chip. 9 and 11, the signal applied to the substrate terminal 60d passes through the solder 60d and passes through the dummy lead 2 of the TCP 1a.
2a, solder 43a, dummy lead 22b, solder 43
b, dummy lead 22c, solder 43c, and
1d chip select terminal 19d reaches chip select bump 1
Through 8d, it is connected to the semiconductor chip 10d. here,
Since the dummy leads 22a to 22c are not connected to any of the chips, this signal is not transmitted to the TCPs 1a to 1c, but is selectively transmitted only to the TCP 1d. As a result, signals can be selectively input / output to only one of the plurality of chips.

In FIG. 9, the multi-chip semiconductor device 4
Since the upper chip selection bumps 18 are arranged at fixed positions on the chip 10, the type of chip may be one without being affected by the layers to be stacked. Also, the same connector frame 2 can be used in each stage, and only one type may be used. On the other hand, since the lead pattern of the film carrier tape 12 is different for each stage, four types are prepared according to the respective patterns.

Dummy leads 20, 21, and 2 on TCP1
Numeral 2 is for connecting the connector frames 2 of each stage of the chip selection terminal portion as shown in FIG.

The lid shown in FIGS. 1 and 9 uses a printed wiring board having no internal hollow to protect the inside when the multi-chip semiconductor device 6 is mounted on the motherboard 4 and to provide terminals for terminals formed on the surface. By increasing the area, it is possible to easily perform an electrical characteristic test at the time of four-layer stacking.

Here, a method of laminating the TCP 1 and the connector frame 2 will be described. The stacked connection of the TCP1 and the connector frame 2 is performed by first fixing the TCP1 and the connector frame 2 at each stage to form a TCP35 with a frame, and then connecting the TCP1 with the frame 4
The step and the lid 3 are aligned and stacked and connected.

First, the method of assembling the framed TCP 35 will be described. The semi-cured thermosetting adhesives 39 and 40 are applied to the front and back surfaces of the short side portion 30 of the connector frame 2, and the outer shape is cut on the connector frame 2 to form individual pieces of TCP 1.
, The outer lead 15 is bent by a special jig, the lead holding tape 16 is placed on the back surface of the connector frame 2, the adhesive is cured by heat treatment, and
1 and the connector frame 2 are fixed, and the framed TCP 35 is assembled.

Next, the four TCPs 35 with the frame and the lid 3 of the uppermost layer are sequentially aligned one by one from the first stage, and temporarily with an adhesive applied in the long side direction of the connector frame 2 having no lead. Laminate while fixing. The alignment was performed by a method of optically reading and aligning the alignment pattern on the upper surface of the lower TCP and the alignment pattern on the lower surface of the upper TCP disposed thereon. In the laminating step, the upper framed TCP 35 is pressed with a constant load when the adhesive is cured so that the thickness of each connection layer becomes a constant thickness determined by the protrusions formed on the TCP1.

After positioning and temporarily fixing the four framed TCPs 1 and the top cover 3, a flux for soldering is applied to the connection portions, and the end surface leads 37 are immersed in molten solder to thereby form a connection portion. Was soldered.

The multichip semiconductor device 4 thus soldered is connected to a motherboard 5 on which solder printing is performed.
It was positioned above and soldered by vapor reflow soldering to form a multi-chip semiconductor module.

As described above, by forming the lead of the TCP 1 along the end of the connector frame 2 so that the outer lead 15 of the TCP 1 is
Since the connection terminals on the upper surface, the connection terminals on the lower surface, and the upper and lower terminals of P35 are all connected, it is not necessary to form a pattern on the connector frame 2. As a result, the manufacturing cost of the connector frame can be significantly reduced, and further, it is not necessary to consider the alignment accuracy between the TCP and the connector frame 2 in assembling the TCP with the frame.
Simplification of the member formation and simplification of the assembly process can be achieved. Also,
Due to the structure in which the outer leads are exposed at the end face of the TCP and the connection gap structure formed by protrusions on the TCP, a fusion soldering method in which the connection is immersed in molten solder can be adopted, simplifying the connection process. Was achieved.

Further, by combining the securing of the thickness of the connection solder layer by the protrusions formed on the TCP and the adoption of the molten solder method, it is possible to sufficiently diffuse the metal of the surface of the TCP lead into the molten solder. Since the gold content of the connection portion can be suppressed to a very low level, the deterioration of the strength of the connection portion due to the gold content can be prevented, and the reliability of the connection can be greatly improved. Further, by exposing the connection part, the appearance inspection of the connection state can be performed at a glance, thereby improving the quality and the productivity.

Further, by using a solder resist film for the protrusion, it is possible to prevent solder from penetrating into the vicinity of the chip.

Next, an application example of the first embodiment will be described with reference to FIGS.

FIG. 12 is a sectional view of a lead portion of a framed TCP 35 in which the TCP 1 and the connector frame 2 are combined according to an application example, and FIG. 13 is a perspective view of FIG.

This application example is characterized in that an end face concave portion 70 is formed at the end of the connector frame 2, and the other configuration is the same as that of the first embodiment.

12 and 13, when the end recess 70 provided on the end surface of the connector frame 2 is bent, the outer lead is bent when the outer lead portion of the TCP 1 is bent.
Since the connector frame 2 is bent so as to fit into the connector frame 2, there is no displacement between the connector frame 2 and the TCP 1. In addition, the upper and lower leads of the outer lead are bent precisely by the action of the end face concave portion, and when projected from the upper surface, they are arranged with good overlap, so that the positioning of the framed TCP at the time of lamination is easy. Will be able to do it.

Although the concave portion is provided only at the end of the connector frame 2 in this application example, the concave portion may be provided on the upper surface and the lower surface of the connector frame 2.

Further, a structure in which the outer lead and the concave portion are connected by soldering by applying a metallizing process to the bottom surface and the side surface of the concave portion is also effective.

Next, a second embodiment will be described with reference to FIGS.

FIG. 14 is a sectional view of the framed TCP of the second embodiment, FIG. 15 is a perspective view of the same, and FIG.
FIG. 6 is a cross-sectional view in a direction perpendicular to the outer leads in a state where the two layers are stacked.

In FIGS. 14 and 15, the connector frame 2 has an upper surface concave portion 72 and an end surface concave portion 70 formed on the upper surface and the end surface. Further, the support ring 14 has a structure that does not reach the upper surface of the connector frame 2, and the outer lead 15 fits into the upper surface concave portion 72 and the end surface concave portion 70 and is bent to the lower surface.

In FIG. 16, the depth of the upper surface concave portion 72 provided on the upper surface of the connector frame 2 is formed to be deeper than the thickness of the upper surface lead 36, and the lower surface lead 38 is formed wider than the upper surface concave portion 72. I have.

As a result, as shown in FIG.
When the CP is stacked in two or more layers, the lower framed TCP
A constant space can be provided between the upper surface lead 36a of the 2a and the lower surface lead 38b of the upper framed TCP 2b, and the solder connection thickness similar to the protrusion formed on the TCP shown in the first embodiment is kept constant. The effect can be obtained.

[0065]

As described above, according to the present invention,
There is an effect that a structure and a manufacturing method of a stacked multi-chip semiconductor device in which an appearance inspection can be easily performed and connection reliability is sufficiently secured can be obtained.

[Brief description of the drawings]

FIG. 1 is a sectional view of a connection portion between a multichip semiconductor device and a motherboard.

FIG. 2 is a plan view of TCP.

FIG. 3 is a sectional view taken along the line AA of FIG. 2;

FIG. 4 is a plan view of a connector frame.

FIG. 5 is a plan view and a side view in which a part of the connector frame is enlarged.

FIG. 6 is a perspective view of a TCP with a frame.

FIG. 7 is a sectional view of a connection portion between the multi-chip semiconductor device and the motherboard.

FIG. 8 is a circuit block diagram of a multichip semiconductor device.

FIG. 9 is a perspective view of a chip selection terminal unit.

FIG. 10 is a sectional view of a connection portion of a common terminal portion.

FIG. 11 is a sectional view of a connection portion of a chip selection terminal portion.

FIG. 12 is a sectional view of a lead portion of a framed TCP.

FIG. 13 is a perspective view of a lead portion of a framed TCP.

FIG. 14 is a sectional view of a lead portion of a framed TCP.

FIG. 15 is a perspective view of a lead portion of a framed TCP.

FIG. 16 is a cross-sectional view of a state where TCPs with frames are stacked in two stages.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... TCP (tape carrier package), 2 ... connector frame, 4 ... Multi-chip semiconductor device, 5 ... Motherboard, 6,43 ... Solder, 10 ... Semiconductor chip, 15 ... Outer lead, 19 ... Chip selection lead, 20,21 ,
22: dummy lead, 23: protrusion, 35: TC with frame
P, 36: Top lead, 37: End lead, 38: Lower lead, 60: Chip selection board terminal, 70: End recess
72 ... recess on the upper surface.

──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Ichiro Miyano 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Pref.Hitachi, Ltd.Production Technology Laboratory (72) Inventor Kazuo Yamazaki 5--20 Kamimizu Honcho, Kodaira-shi, Tokyo No. 1 Hitachi, Ltd. Semiconductor Design and Development Center (72) Inventor Munehiro Yamada 5-2-1 Kamimihoncho, Kodaira-shi, Tokyo Stock Company Hitachi, Ltd. Semiconductor Design and Development Center (56) References JP-A-2-134859 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 25/04 H01L 25/10

Claims (18)

(57) [Claims] 1. A laminated multi-chip semiconductor device in which a plurality of tape carrier packages each having a semiconductor chip electrically connected to a film carrier tape having a wiring pattern on at least one surface are connected and laminated via a connector frame. A multi-chip semiconductor device comprising: a tape carrier package having an insulating film formed on at least one surface thereof to be thicker than the wiring pattern. 2. The stacked multi-chip semiconductor device according to claim 1, wherein an organic resin is used for the insulating film. 3. The stacked multi-chip semiconductor device according to claim 1, wherein an inorganic insulating material is used for the insulating film. 4. A stacked multi-chip semiconductor device according to claim 1, wherein the insulating film is formed by a solder resist film. 5. The semiconductor device according to claim 1, further comprising a dummy lead that is not electrically connected to the semiconductor chip.
A stacked multi-chip semiconductor device using a CP. 6. The conductive pattern according to claim 1, wherein the outer lead portion of the tape carrier package is bent with one end of the connector frame sandwiched therebetween, and is disposed on the back surface of the connector frame. A laminated multi-chip semiconductor device comprising a tape carrier package with a frame as described above. 7. A stacked multi-chip semiconductor device according to claim 1, wherein a tape material of a lead portion located at an end face of the connector frame of the tape carrier package is removed. 8. The connector frame according to claim 1, wherein a concave portion is provided on at least one surface of the connector frame, an outer lead portion of the tape carrier package is disposed in the concave portion, and one end of the lead is connected to a side surface of the connector frame. A stacked multi-chip semiconductor device, wherein the semiconductor device is folded and disposed on a lower surface via a device. 9. The stacked multi-chip semiconductor device according to claim 1, wherein at least one surface of the recess formed in the connector frame is subjected to a metallizing process. 10. The stacked multi-chip semiconductor device according to claim 1, wherein a width of a lower surface lead of the lead is wider than a width of a concave portion formed on an upper surface of the connector frame. 11. A laminated multi-chip semiconductor device in which a plurality of tape carrier packages in which semiconductor chips are electrically connected to a film carrier tape having a wiring pattern on at least one surface are laminated and connected via a connector frame. At least an upper surface is provided with a concave portion deeper than the thickness of the lead of the film carrier tape, the lead is disposed in the concave portion, and one end of the lead is bent to the lower surface via a side surface of the connector frame, and the disposed tape carrier with a frame is disposed. A stacked multi-chip semiconductor device, comprising a package. 12. The multi-chip semiconductor device according to claim 11, wherein the width of the lower surface lead of the lead is wider than the width of the recess formed on the upper surface of the connector frame. 13. The laminated multi-chip semiconductor device according to claim 1, wherein the tape carrier packages with frames are fixed with an adhesive. 14. A laminated multi-chip semiconductor device according to claim 1, wherein the whole of the tape carrier package with frames is electrically connected and then molded entirely with an insulating resin. 15. A cover according to any one of claims 1 to 14, wherein a lid having a surface pattern electrically connected to each outer lead of said TCP with uppermost frame is attached to an uppermost layer in which a plurality of TCPs with frame are laminated. A stacked multi-chip semiconductor device characterized by the above-mentioned. 16. The connection between leads of the framed tape carrier package according to any one of claims 1 to 15, wherein
-A stacked multi-chip semiconductor device using Pb-based solder. 17. A method for manufacturing a laminated multi-chip semiconductor device, comprising connecting a plurality of tape carrier packages in which semiconductor chips are electrically connected to a film carrier tape having a wiring pattern on at least one surface via a connector frame. Adhesive is applied to both front and back sides of the side of the frame, TCP is cut into individual pieces on this connector frame, the outer leads are bent, the outer leads are bent, and the lead holding tape is placed on the back of the connector frame. And a method of manufacturing a framed TCP, wherein the adhesive is cured. 18. A method for manufacturing a laminated multi-chip semiconductor device in which a plurality of tape carrier packages each having a semiconductor chip electrically connected to a film carrier tape having a wiring pattern on at least one surface thereof are laminated and connected via a connector frame. One framed TCP on one side and another framed T
A method for manufacturing a laminated multi-chip semiconductor device, comprising: positioning, arranging and laminating CPs, applying a flux to an interlayer connection position of the laminated framed TCP, and immersing the connection portion in molten solder.