JPH10173125A - Multi-chip module - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a multichip module which has a memory capacity that is a plurality of times as large as the mounting area of the conventional package and can increase the operating speed of the package by forming a plurality of electrodes by piling a plurality of semiconductor modules upon another with spacers in between and electrically connecting the semiconductor modules to each other. SOLUTION: A plurality of electrodes are formed by piling semiconductor modules 28 electrically connected to a semiconductor chip 2 upon another with spacers 20 in between and electrically connecting the modules 28 to each other. A capacitor which electrically connects a multi-chip semiconductor device constituted in the above-mentioned way to the electrodes of the semiconductor device is provided. For example, four film carrier semiconductor modules 28a-28d are laminated upon another and electrically connected to each other. The spacers 20 are formed in frame-like shapes and provided with front-surface patterns 22, rear-surface patterns 24, and through holes 26 for connecting the modules 28a-28d to each other.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of a multi-chip module using a large-capacity multi-chip semiconductor device having a memory capacity several times as large as the mounting area of a conventional IC package.

[0002]

2. Description of the Related Art Semiconductor memories are widely used from OA equipment such as personal computers, word processors, workstations, and facsimile machines to video equipment such as digital VTRs and TVs. It is expected that the demand for the semiconductor memory used here will increase at an accelerating rate. In parallel with this, in the manufacture of semiconductor memories, efforts are being made to increase the memory capacity per chip by increasing the density of the memory, and the memory capacity in a chip is increasing four times every three years. Currently, 1Mbit DRAM is mass-produced, 4Mbit DRAM is sample shipped, 16MDRA
M is in the prototype stage. However, there are many problems in the basic technology and the manufacturing process for increasing the capacity of the chip. In particular, for the transition from the current 1 Mbit to 4 Mbit, development of new memory cells, submicron wiring technology, package Enormous costs are required for the development of technics.

Conventionally, as a package for memory, a plastic package formed by mounting a chip on a tab of a lead frame, wire-bonding a tip of an internal lead to a bonding pad of the chip by wire bonding, and resin molding is mainly used. .

The package has a memory capacity of 256 Kb.
Before this, DIP (Dual i
n line Package) was the mainstream, but the demand for high-density mounting became stronger thereafter, and SOJ (small outline J) with a mounting area smaller than that of DIP was adopted.
-Lead package), ZIP (zigzag)
in-line package).

Here, the DIP is a type in which leads are extended in two rows in two directions of a package long side, and these leads are bent downward under the package. The leads are inserted into through holes of a printed board and mounted. The ZIP is a type in which leads are protruded in one direction of the long side of the package and the leads are alternately bent, and is a through-hole insertion type in which the package is mounted vertically. The SOJ is a surface mount type in which the package is protruded in two long sides, but the lead pitch is reduced to half of the DIL, and the leads are bent downward into a "J" shape and mounted directly on the surface of the printed board. D
It aims at reducing the package length in the longitudinal direction and mounting on both sides of a printed circuit board as compared with the IL.

[0006] Regarding the conventional package, Nikkei Microdevices Supplement No. 1 pp. 73-80 and 87-89 are described with respect to the package form and mounting on a printed board. Since the lead wire is inserted into the connector, mounting on both sides is not possible and the mounting efficiency is not good. On the other hand, the ZIP can be mounted at a higher density than the DIP because of the vertical shape. That is, while the dimension between the lead rows of the DIP is three grid pitches of the printed board, that of the ZIP is one grid pitch, and the mounting density on the printed board is almost twice that of the DIP. Although SOJ is a horizontal mounting, it has features such as high-density mounting more than twice as large as DIP because the layout of the lead pins is not restricted by the lattice of the printed board and double-sided mounting is possible.

[0007]

As described above, three types of conventional packages are generally used. However, all three types incorporate one chip in one package, and each package has one chip unless the capacity on the chip side increases. However, there is a disadvantage that the memory capacity does not increase. Also, there is only a difference of about twice in the mounting density on the printed board due to the difference in the package form, and there has been a problem that it is difficult to mount a large capacity and high density with the conventional package.

In particular, when a package having a large capacity and a high density is used in an electronic device or the like, a module considering its high-speed operation is required.

An object of the present invention is to provide a multi-chip module having a memory capacity which is two or more times as large as the mounting area of a conventional package and enabling high-speed operation of the package.

[0010]

According to the present invention, in order to achieve the above object, a plurality of semiconductor modules electrically connected to a semiconductor chip are stacked via a spacer, and the semiconductor modules are electrically connected. A multi-chip semiconductor device having a plurality of electrodes formed thereon, and a capacitor electrically connected to the electrodes of the multi-chip semiconductor device.

In this case, the multi-chip semiconductor device forms the connection pattern for electrically connecting the semiconductor chip and the electrode with a different pattern shape for each of the semiconductor modules, and forms the connection pattern with the different pattern shape. It is preferable that an electrode electrically connected to the semiconductor chip is configured as a chip selector electrode of the semiconductor chip electrically connected to the connection pattern having the different pattern shape.

Alternatively, the multi-chip semiconductor device is formed such that a pattern shape formed on the semiconductor chip among connection patterns for electrically connecting the semiconductor chip and the electrodes is different for each semiconductor module,
An electrode electrically connected to a connection pattern having a different pattern shape formed on the semiconductor chip is configured as a chip selector electrode of the semiconductor chip electrically connected to a connection pattern having a different pattern shape formed on the semiconductor chip. Is preferred.

Alternatively, the multi-chip semiconductor device may include a common electrode for electrically connecting the semiconductor modules and electrically connecting each of the semiconductor chips of each of the semiconductor modules, and a semiconductor chip of each of the semiconductor modules. It is preferable that a chip selector electrode of each of the semiconductor modules is formed, and a shape of a connection pattern for electrically connecting the chip selector electrode and the semiconductor chip is different for each semiconductor module. .

Alternatively, the multi-chip semiconductor device may include a common electrode for electrically connecting the semiconductor modules and electrically connecting each of the semiconductor chips of each of the semiconductor modules, and a semiconductor chip of each of the semiconductor modules. A chip selector electrode of each of the semiconductor modules, and a connection pattern for electrically connecting the chip selector electrode and the semiconductor chip to a pattern shape formed on the semiconductor chip. It is preferable to form them differently.

Further, in these cases, it is preferable to form the chip selector electrode by electrically connecting the semiconductor modules to the position of the semiconductor module having the semiconductor chip to be selected.

[0016]

As a result, it is possible to provide a multi-chip module having a memory capacity which is several times larger than the mounting area of the conventional package and taking into consideration a connection target with an electronic device or the like.

Further, by providing a capacitor near the multi-chip semiconductor device, a multi-chip module corresponding to high-speed operation can be provided. That is, by shortening the wiring distance between the multi-chip semiconductor device and the capacitor compared to a conventional module having an externally mounted capacitor, it is possible to provide a multi-chip module compatible with high-speed operation.

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to FIGS.

Before describing the multi-chip module of the present invention as shown in FIGS. 20 to 22, an example of a multi-chip semiconductor device 120 which is one of the components will be described with reference to FIGS. 1 to 19. . Here, the multi-chip module is obtained by adding a structure serving as an external connection terminal to a multi-chip semiconductor device formed by stacking a plurality of semiconductor modules.

FIG. 1 is a sectional view of a multi-chip semiconductor device in which four film carrier semiconductor modules 28a to 28d are stacked and electrically connected.

FIG. 2 is an enlarged cross-sectional view of the connection portion of the first and second stages of the film carrier semiconductor module from below with the multi-chip semiconductor device shown in FIG. 1 mounted on a motherboard.

FIG. 3 is a plan view of the second lower film carrier semiconductor module 28b of the multichip semiconductor device shown in FIG.

FIGS. 4 to 6 are perspective views showing details of the chip selection terminal portion. FIG. 4 is the second stage from the bottom, and FIG. 5 is the first stage from the bottom.
The film carrier semiconductor module of the tier, FIG. 6 shows a motherboard.

FIG. 7 is a circuit block diagram showing an electrical connection state of each semiconductor chip of a multi-chip semiconductor device in which four semiconductor chips are stacked.

First, the configuration of the multichip semiconductor device according to the present invention will be described with reference to FIGS. In each drawing, the same reference numerals indicate the same contents.

In FIGS. 1 and 2, the semiconductor chip 2a
A bump 4a, the bump 4a and the film carrier tape 6a are electrically connected by an inner lead portion 10a which is a part of a lead portion, and an outer lead portion 12a which is a part of the lead portion is formed of a semiconductor. It protrudes outside the chip 2a and is connected to the spacer 20a.

The spacer 20a is formed in a frame shape (hereinafter, the frame-shaped spacer is referred to as a frame-shaped spacer). In order to electrically connect the film carrier semiconductor modules, the surface pattern 22a and the back surface are formed. Pattern 2
4a, a through hole 26a for electrically connecting the front surface pattern 22a and the back surface pattern 24a is formed.
The surface pattern 22a and the outer lead 1
2a is electrically connected by the first connection layer 16a. Thus, the semiconductor chip 2a is electrically connected to the back surface pattern 24a.

The upper surface of the semiconductor chip 2a and the side portions of the semiconductor chip 2a including the inner lead portions 10a are coated with a protective coating resin 14a.

The above structure is the basic structure of the film carrier semiconductor module 28a. In the above, the lowermost film carrier semiconductor module 28 of FIG.
Although the configuration of “a” has been described, the second, third, and fourth stages from the bottom have almost the same configuration. Hereinafter, in each figure, the lowermost film carrier semiconductor module is denoted by “a” after the reference sign as described above, and the second level is denoted by “b”.
Are displayed with “c” on the third row and “d” on the fourth row.

Between the film carrier semiconductor modules, the surface pattern 22a of the first-stage film carrier semiconductor module 28a and the back surface pattern 24b of the second-stage film carrier semiconductor module 28b
Are electrically connected through the second connection layer 18b. Other film carrier semiconductor modules are similarly connected. The wiring pattern 32 formed on the upper surface of the motherboard 30 is different from the back pattern 24 a of the lowermost film carrier semiconductor module 28 a in the third connection layer 34.
To make electrical connection.

In a multi-chip semiconductor device in which a plurality of film carrier semiconductor modules are stacked as described above, a signal is supplied from a motherboard.
The first connection layers 16a-d and the second connection layer 18 that connect the spacers 20a-d with the back patterns 24a-d, the through holes 26a-d, and the surface patterns 22a-d, and the spacers.
a to d and the like become electrodes of the multi-chip semiconductor device.

Further, for connecting the electrodes to the semiconductor chip, for example, bumps 4a to 4d, inner leads 10a to 10d,
The outer leads 12a to 12d, the surface patterns 22a to 22d, and the like serve as connection patterns for the film carrier semiconductor module constituting the multi-chip semiconductor device.

That is, what electrically connects the film carrier semiconductor modules and is electrically connected to the wiring pattern 32 such as the motherboard 30 becomes an electrode, and the wiring up to the semiconductor chip connected to this electrode becomes the connection pattern. .

Next, the details of the wiring and the like of the film carrier semiconductor module will be further described with reference to FIG. 3 and the like. In FIG. 3, a plurality of lead portions including the outer lead portion 12a and the inner lead portion 10a are described. The semiconductor chip 2a can be divided into a single chip selection lead wire 40b and a plurality of other common lead wires 42b, each of which connects the semiconductor chip 2a and the surface pattern formed on the frame-shaped spacer 20a. . This chip selection lead wire 4
Numeral 0 is for supplying a signal for permitting read / write operation sent from the motherboard to the semiconductor chip 2a. Therefore, the chip selection lead wire 40 is connected to a chip selector electrode which is unique to each film carrier semiconductor module among the above-mentioned electrodes.

Next, an example of a chip selector electrode and a connection pattern for connecting the chip selector electrode and the semiconductor chip, which are unique to each film carrier semiconductor module, will be described with reference to FIGS. explain.

As can be seen from FIG.
b is connected to a common terminal pattern 46b which is a surface pattern. In addition, the chip selection lead wire 40b includes a chip selection terminal pattern 44b, a chip selection dedicated pattern 5
0b, a pattern 48b connecting the chip selection terminal pattern 44b and the chip selection dedicated pattern 50b. In this case, the common terminal pattern 46b and the back surface pattern 52b are
8b. Similarly, the chip-selection-specific pattern 50b and the back surface pattern 56b are electrically connected to each other through the through-hole 60b. Further, no through hole is formed between the chip selection terminal pattern 44b and the back surface pattern 54b.

On the other hand, FIG. 5 shows that the chip selection terminal pattern 44a and the back surface pattern 54a
2a, the chip selection terminal 44
The other configuration is the same as that of FIG. 4 except that the a and the chip selection exclusive pattern 50a are electrically insulated.

FIG. 6 shows a wiring pattern of the motherboard. In the drawing, a chip selection terminal pattern 64, a chip selection exclusive pattern 66, and a common terminal pattern 68 are formed on the upper surface of the motherboard 30. Lines 70, 72, and 74 are connected to the terminal pattern.

In the multi-chip semiconductor device, a film carrier semiconductor module shown in FIG. 5 and a film carrier semiconductor module shown in FIG. 4 are sequentially laminated on a mother board shown in FIG. Therefore, the chip selection terminal pattern 64 on the motherboard, the back surface pattern 54a of the film carrier semiconductor module connected thereto, the through hole 62a, and the chip selection terminal pattern 44a are the chip selectors unique to the semiconductor chip 2a connected to the chip selection lead wire 40a. It becomes an electrode. In addition, the chip selection terminal pattern 44a and the chip selection lead wire 40a are connection patterns for electrically connecting the chip selector electrode and the semiconductor chip 2a.

Similarly, the chip selection terminal pattern 66 on the motherboard, the backside pattern 56a connected thereto, the through hole 60a, the chip selection dedicated pattern 50a, the backside pattern 56b connected therewith, the through hole 60b, the chip selection dedicated pattern 50b But the chip selection lead wire 4
It becomes a chip selector electrode unique to the semiconductor chip 2b connected to Ob. The chip selection terminal pattern 44b and the chip selection lead wire 40b are connection patterns for electrically connecting the chip selector electrode and the semiconductor chip 2b.

The common terminal pattern 66 on the motherboard, the back pattern 52a connected thereto, the through hole 58a, the common terminal pattern 46a, the back pattern 52b connected therewith, the through hole 58b, and the common terminal pattern 46b are respectively It is electrically connected to the semiconductor chips 2a, 2b via the common lead wires 42a, 42b, which are connection patterns, and serves as an electrode common to each film carrier semiconductor module.

As described above, by changing the shapes of the connection patterns connected to the respective chip selector electrodes, the chip selector electrodes connected to the connection patterns having the different shapes can be formed as unique to each semiconductor module. it can.

Further, since the electrodes are formed by laminating the film carrier semiconductor modules, the electrodes can be easily formed.

That is, by making the shapes of the connection patterns connected to the respective chip selector electrodes different, the electrodes can be easily formed, and the chip selector electrodes can be formed unique to each semiconductor module.

Further, when forming the chip selector electrode of each film carrier semiconductor module, the chip selector electrode is not electrically connected to the film carrier semiconductor module stacked above the corresponding film carrier semiconductor module. With such a configuration, the electrode for the chip selector can be formed unique to each semiconductor module.

When the multi-chip semiconductor device is configured as described above, a circuit block diagram showing the electrical connection state is as shown in FIG.

Here, a method of storing information (data input) and reading stored data (data output) to and from a semiconductor memory chip in a multi-chip semiconductor device will be described.

In the figure, semiconductor chips 2a, 2b, 2
c and 2d have an address terminal 80 and a data input / output terminal 8
2. The write enable terminal 84, the out enable terminal 86, the power supply terminal 88, the ground terminal 90, and the chip selection terminals 92a, 92b, 92c, 92d are electrically connected. Among these terminals, the chip selection terminals 92a to 92a
92d is independently connected to each of the semiconductor chips 2a to 2d, but other terminals are connected to the semiconductor chips 2a to 2d.
Commonly connected to 2d.

Input / output of information is performed in address units set in the chip. Writing information to a certain address requires an address signal that specifies the address, a write enable signal that permits writing, and a data signal that includes data to be stored. However, when the amount of information increases and one chip cannot store information, it becomes necessary to use a plurality of chips. FIG. 7 shows an example of four chips. For example, if 100 addresses can be set for one chip, addresses 0 to 99 are set for each chip. As described above, if an operation of writing data at address 99 of the semiconductor chip 2a is taken as an example, a signal indicating "address 99" is written to the address terminal 88, and a data signal for writing is written to the data input / output terminal 82. By applying a write enable signal to the write enable terminal 84 and simultaneously sending a chip selection signal to the chip select terminal 92a connected to the semiconductor chip 2a, the address signal, the data signal, and the write enable signal are changed to four semiconductor chips. Only the semiconductor chip 2a is effective among 2a to 2d, and does not act on the other semiconductor chips 2b to 2d. That is, necessary data is written to the address 99 of the semiconductor chip 2a, but the address 99 of the other three non-selected semiconductor chips remains unchanged.

Similarly, when reading data, an out enable signal for a read permission signal operates,
Otherwise, the data input / output terminal 8 is in the same connection state as the write.
2, the data stored at the address 99 of the semiconductor chip 2a is output.

In FIG. 7, the address terminal 80 and the data input / output terminal 82 are shown by one line, but the actual wiring is composed of a plurality of lines. On the other hand, the write enable terminal 84 and the out enable terminal 8
6, each of the power supply terminal 88, the ground terminal 90, and the chip selection terminals 92a to 92d is often one in actual wiring.

Next, the operation of the multichip semiconductor device described above will be described.

In FIG. 1 and FIG. 2, a semiconductor chip 2a is a semiconductor chip for a memory in which a storage element is integrated, and writes and reads data according to a signal supplied from a motherboard 30.

The flow of electric signals at the time of writing and reading data is as follows.
Is supplied from the outside to the third connection layer 34, the back pattern 24a of the spacer 20a, the through hole 26a, the surface pattern 22a, the first connection layer 16a, the outer lead portion 12a, the inner lead portion 10a of the film carrier 6a. First-stage semiconductor chip 2 through bump 4a
It is supplied to the elements in a. Similarly, the second stage semiconductor chip 2b and the third and fourth stage semiconductor chips 2c, 2c
A signal is also supplied to d at the same time.

Here, the chip selection lead wire 40b shown in FIG. 4 corresponds to the chip selection terminal 92a shown in FIG. 7, and is independently connected to each semiconductor chip. Is the address terminal 8 of FIG.
0, data input / output terminal 82, write enable terminal 8
4, correspond to an out enable terminal 86, a power supply terminal 88, and a ground terminal 90, and are commonly connected to each terminal.

That is, as shown in FIGS. 4 to 6, the signal supplied to the common terminal passes through the common terminal pattern 68 of the motherboard 30 and the back surface pattern 52 of the spacer 20a.
a, through-hole 58a, surface pattern 46a, and common lead 42a, are supplied to first-stage semiconductor chip 2a, and further supplied to common lead 42 from back surface pattern 52b of second-stage spacer 20b. As described above, it is supplied to each chip simultaneously.

On the other hand, the chip selection terminal pattern 64
Are supplied to the back surface pattern 54a of the spacer 20a, the through hole 62a, and the front surface pattern 4a.
4a, is supplied to the first-stage semiconductor chip 2a via the chip selection lead wire 40a, but since the back surface pattern 54b and the front surface pattern 44b of the spacer 20b are not electrically connected, the second-stage semiconductor chip Not supplied to 2b.

Similarly, the chip selection signal supplied to the chip selection terminal pattern 66 of the motherboard 30 is not supplied to the first-stage semiconductor chip 2a but is selectively supplied to only the second-stage semiconductor chip 2b. can do. Note that the same circuit pattern is provided on the spacers of the respective stages for the second and higher stages of chips, so that the chips can be independently selected.

As a result, a desired semiconductor chip can be operated using the chip selector electrode, and data can be written / read to / from the stacked film carrier semiconductor modules without malfunction.

Next, other spacer shapes used in the multi-chip semiconductor device will be described.

Although a spacer having a rectangular external shape as shown in FIG. 3 has been described above, a structure having spacers only on two surfaces of the film carrier lead wire arrangement as shown in FIG. 8 is also possible.

That is, the film carrier tape semiconductor module can also be laminated by the structure having the first and second spacers 20b1 and 20b2 arranged opposite to each other as shown in FIG.

In FIG. 1, the frame-shaped spacers of the first to fourth stages have the same shape without the spacer members at both the front and back surfaces of the semiconductor chip. As shown in FIG. 9, the eye spacer is a spacer 64a having a spacer member 96a interposed also on the lower surface of the semiconductor chip 2a, and a wiring pattern 98a of any shape is formed on any surface of the spacer member connected to the motherboard. It can also be. That is, it is a structure that can arbitrarily form a pattern arrangement that matches the standardized connection pattern of the motherboard.

In the above, the structure in which the front and back patterns are formed on the spacers and the front and back patterns are electrically connected by the through holes has been described. A structure in which the outer lead is bent to the back surface via the spacer surface and side surfaces, or a structure using bent front and back conductive leads may be used. FIG. 10 shows a connection pattern formed by bending the outer lead as an example. In this case, the conventional front surface pattern, back surface pattern, and through hole are unnecessary.

FIG. 10 is a cross-sectional view showing the joint between the spacer and the outer lead of the film carrier semiconductor module. The spacer 20a has a front surface pattern 100a and a back surface pattern 24a. The bent front end of the outer lead 12a and the back surface pattern 24a are fixed by the lower surface connection layer 104a.

In the above structure, the outer leads 12
a is passed through the upper surface of the spacer 20a, is extended to the side surface and further to the lower surface of the spacer 20a by bending, and is joined to the back surface pattern 24a to conduct the front and back of the spacer.

Next, FIGS. 11 to 13 show other chip selector electrodes used in the multi-chip semiconductor device.

FIGS. 11 to 13 show the same positions as FIGS. 4 to 6, and the same reference numerals indicate the same contents. However, the common terminal pattern is omitted.

This feature is that the connection patterns for connecting the chip selector electrode and the semiconductor chip are formed differently on the semiconductor chip, and the front and back patterns formed on the spacer 20b and the front and back patterns are connected. The through-hole conduction pattern is formed in the same structure as the spacer 20a.

As described above, by arranging the outer lead shapes of the film carrier to be different from each other as shown by 40a and 40b, it becomes possible to select a corresponding semiconductor chip independently via each chip selector electrode. I have. The outer lead wire bending method described with reference to FIG. 10 can easily achieve the purpose by applying this structure.

FIGS. 14 to 16 show other chip selector electrodes used in the multichip semiconductor device.

Also in this case, the shape of the connection pattern for connecting the chip selector electrode and the semiconductor chip is made different on the semiconductor chip, but the spacers 20a and 20b have the same structure, and the outer leads 4 of the film carrier are formed.
0a, 40a ', 40b, and 40b' are different in that they have the same structure.

That is, in FIG. 14 and FIG. 15, the chip selection pads 102b and 102a, the pad connection line 104
b, 104a and spare chip selection pads 106b, 10b
8b, 106a and 108a are formed. In the first-stage semiconductor chip 2a, the chip selection pad 102a and the chip selection spare pad 106a are connected by a pad connection line 104a, and the chip selection spare pad 108a is insulated from the chip selection pad 102a. ing. In the second stage semiconductor chip 2b, the chip selection pad 102b is connected to the chip selection spare pad 108b, and is insulated from the chip selection spare pad 106b.

With such a configuration, the motherboard 3
When a signal is applied to the 0 chip select terminal 64, the semiconductor chip 2a can be independently selected, and when a signal is applied to the chip select terminal 66, the semiconductor chip 2b can be independently selected.

Next, other spacer shapes used for the multi-chip semiconductor device are shown in FIG.

FIG. 17 shows that the leads connected to the semiconductor chip 2 via the bumps 4 extend so as to electrically connect through holes formed in the spacer 110. That is, this is an example in which no surface pattern is formed.

In forming the leaded spacer 110, a hole into which the semiconductor chip 2 is fitted is punched into a substrate having only one surface of the base material to which the conductive material for pattern is fixed, and then a conductive material for forming a lead pattern is formed on the other surface. Is pasted including the hole portion, and thereafter, using the manufacturing process of the printed wiring board, FIG.
As shown in FIG. 7, a leaded spacer 110 having a lead pattern protruding from one end of a base material is formed.

Leader spacer 110 and semiconductor chip 2
Is used by a known inner lead bonding method such as gold-gold or gold-tin. In stacking the film carrier semiconductor modules using the present leaded spacer, the first connecting portion 16a shown in FIG. 2 is unnecessary, which is very advantageous in the assembling process.

By using a material of the same quality as the motherboard for the spacer, the connection reliability after mounting on the motherboard can be greatly improved.

Next, a method of manufacturing a multi-chip semiconductor device will be described.

FIG. 18 shows an outline of the manufacturing process. In FIGS. 1, 2 and 18, first, the inner leads 10a of the patterned film carrier tape are aligned with the bumps 4a formed on the surface of the semiconductor chip 2a, and the inner leads are bonded. This bonding method is based on TAB (Tape Automated Bonn).
(ding) inner lead bonding. Next, a protective coat is applied to the bonding surface and the chip select terminal surface and side surface. At this time, the semiconductor chip 2a and the bonding portion are inspected and the quality is classified.

Next, the film carrier module 6a is cut out from the film carrier tape. In parallel with this, from the printed wiring board on which a plurality of
The individual spacers are cut out and taken out, aligned with the film carrier module 6a, made a first connection, and a first connection layer 16 is formed. Thus, a single unit of the film carrier semiconductor module shown in FIG. 1 is obtained.

Next, after the four film carrier semiconductor modules are set on the positioning jig, the back surface pattern 24 of each film carrier semiconductor module is brought into contact with the outer lead 12, and only the terminal portion is immersed in the molten solder bath. Make the second connection. Thereafter, resin coating is performed while leaving the connection to the motherboard.

In this process chart, a method of cutting the film carrier tape after first connecting the outer shape-cut spacer to the film carrier tape before the outer shape cut, and the method of cutting the outer shape of the film carrier tape to the spacer printed wiring board before the outer shape cut A first connection of the modules is also possible.

The first connection in this embodiment is performed by a solder reflow method in which a solder using Sn—Pb-based solder previously attached to the terminal portion of the through hole is heated and melted by a thermocompression bonding head to perform bonding. Adopted, Au-
Au thermocompression bonding Au-Sn bonding, a connection method using a conductive paste, and the like can of course be applied.

Another example of a method for manufacturing a multi-chip semiconductor device will be described with reference to FIG.

FIG. 19 shows an outline of the manufacturing process, and particularly shows a method of manufacturing a multi-chip semiconductor device using the spacer with leads shown in FIG.

First, the inner leads of the patterned spacers with leads are connected to the bumps of the semiconductor chip. This state is the structure shown in FIG. Next, the entire chip including the protective coat on the chip surface and the bonding portion is inspected to determine whether the chip is good or not. Thereafter, stacking, alignment, second connection, performance inspection, and resin coating are performed by the same method as described with reference to FIG. 18 to complete a multi-chip semiconductor device.

Next, an example of the multi-chip module of the present invention in which external connection terminals are added to the multi-chip semiconductor device described above will be described.

FIG. 21 shows a conventional dual in-line IC.
A multi-chip semiconductor device 1 is mounted on a package substrate 138 having lead pins 136 arranged in the same manner as the package.
20 and a multi-chip module 140 electrically connected to a capacitor which has conventionally been externally mounted, has a structure which can be easily mounted on a motherboard wired by a conventional pattern design.

FIG. 22 shows still another multi-chip module, in which lead pins 144 are electrically connected to a multi-chip semiconductor device 120 and a capacitor 142 on a substrate arranged on the lower surface of a package substrate 146.

FIG. 23 shows still another multi-chip module 154 in which a multi-chip semiconductor device 120 according to the present invention and a plurality of capacitors 142 are electrically connected to a wiring board 152 having connector terminals 150.

That is, FIGS. 21 to 23 show a multi-layer structure in which a plurality of semiconductor modules electrically connected to a semiconductor chip are stacked via a spacer, and a plurality of electrodes are formed by electrically connecting the semiconductor modules. The multi-chip semiconductor device includes a chip semiconductor device and a capacitor electrically connected to an electrode of the multi-chip semiconductor device.

The multi-chip modules shown in FIGS. 21 to 23 are not shown in the drawings, but are mechanically protected by applying a protective coat and a cover to the substrate surface.

As described above, in the present multi-chip module, the multi-chip semiconductor device to be mounted is formed by a plurality of semiconductor chips, so that the storage capacity is several times larger than the mounting area of the conventional module. And is very effective for portable electronic devices requiring a small and large-capacity memory.

[0096]

As described above, according to the present invention, it is possible to obtain a multi-chip module having a memory capacity that is two or more times as large as the mounting area of the conventional package.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a multi-chip semiconductor device applied to a multi-chip module of the present invention.

FIG. 2 is a cross-sectional view of a multi-chip semiconductor device applied to the multi-chip module of the present invention.

FIG. 3 is a plan view of a multichip semiconductor device applied to the multichip module of the present invention.

FIG. 4 is a perspective view of a chip selection terminal structure of a multichip semiconductor device applied to the multichip module of the present invention.

FIG. 5 is a perspective view of a chip selection terminal structure of a multichip semiconductor device applied to the multichip module of the present invention.

FIG. 6 is a perspective view of a chip selection terminal structure of a multichip semiconductor device applied to the multichip module of the present invention.

FIG. 7 is a circuit block diagram of a multichip semiconductor device applied to the multichip module of the present invention.

FIG. 8 is a plan view and a cross-sectional view of a spacer structure of a multi-chip semiconductor device applied to the multi-chip module of the present invention.

FIG. 9 is a plan view and a cross-sectional view of a spacer structure of a multi-chip semiconductor device applied to the multi-chip module of the present invention.

FIG. 10 is a plan view and a cross-sectional view of a spacer structure of a multi-chip semiconductor device applied to the multi-chip module of the present invention.

FIG. 11 is a perspective view of another example of the chip selection terminal structure of the multichip semiconductor device applied to the multichip module of the present invention.

FIG. 12 is a perspective view of another example of the chip selection terminal structure of the multichip semiconductor device applied to the multichip module of the present invention.

FIG. 13 is a perspective view of another example of the chip selection terminal structure of the multichip semiconductor device applied to the multichip module of the present invention.

FIG. 14 is a perspective view of another example of the chip selection terminal structure of the multichip semiconductor device applied to the multichip module of the present invention.

FIG. 15 is a perspective view of another example of the chip selection terminal structure of the multichip semiconductor device applied to the multichip module of the present invention.

FIG. 16 is a perspective view of another example of the chip selection terminal structure of the multi-chip semiconductor device applied to the multi-chip module of the present invention.

FIG. 17 is a sectional view of a leaded spacer of a multichip semiconductor device applied to the multichip module of the present invention.

FIG. 18 is a manufacturing process diagram of the multi-chip semiconductor device of the multi-chip semiconductor device applied to the multi-chip module of the present invention.

FIG. 19 is a manufacturing process diagram of the multi-chip semiconductor device applied to the multi-chip module of the present invention.

FIG. 20 is a perspective view showing a multichip module of the present invention.

FIG. 21 is a perspective view showing a multichip module of the present invention.

FIG. 22 is a perspective view showing a multichip module of the present invention.

[Explanation of symbols]

 2 Semiconductor chip, 6 Film carrier, 10 Inner lead, 12 Outer lead, 16 First connection layer, 18 Second connection layer, 20 Spacer, 28 Film semiconductor module, 30 Motherboard, 44 Chip selection terminal pattern, 110 ... Leaded spacer

 ──────────────────────────────────────────────────続 き Continued on front page (72) Koji Serizawa, Inventor 292, Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Inside the Hitachi, Ltd. Production Technology Laboratory (72) Inventor Michiharu Honda 292, Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Address: Hitachi, Ltd., Production Technology Laboratory (72) Inventor Toru Yoshida 292, Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture, Ltd.- Hitachi, Ltd. Production Technology Laboratory (72) Michio Tanimoto: Michio Tanimoto, Kamizuhoncho, Kodaira, Tokyo 1450 Inside Musashi Factory, Hitachi, Ltd.

Claims (6)

[Claims] 1. A multi-chip semiconductor device in which a plurality of semiconductor modules electrically connected to a semiconductor chip are stacked via a spacer, and a plurality of electrodes are formed by electrically connecting the semiconductor modules. A multi-chip module, comprising: a capacitor electrically connected to an electrode of the chip semiconductor device. 2. The multi-chip semiconductor device according to claim 1, wherein a connection pattern for electrically connecting the semiconductor chip and the electrode is formed to have a different pattern shape for each semiconductor module. 2. The multi-chip module according to claim 1, wherein an electrode to be electrically connected is configured as a chip selector electrode of the semiconductor chip to be electrically connected to the connection pattern having the different pattern shape. 3. The multi-chip semiconductor device, wherein a pattern shape formed on the semiconductor chip among connection patterns for electrically connecting the semiconductor chip and the electrodes is formed differently for each semiconductor module, An electrode electrically connected to a connection pattern having a different pattern shape formed on the semiconductor chip is configured as a chip selector electrode of the semiconductor chip electrically connected to a connection pattern having a different pattern shape formed on the semiconductor chip. 2. The multi-chip module according to claim 1, wherein: 4. The semiconductor chip included in each of the semiconductor modules, wherein the multi-chip semiconductor device electrically connects the semiconductor modules and electrically connects each of the semiconductor chips included in each of the semiconductor modules. A chip selector electrode of each of the semiconductor modules, and a shape of a connection pattern for electrically connecting the chip selector electrode to the semiconductor chip is formed for each of the semiconductor modules. The multi-chip module according to claim 1, wherein 5. The semiconductor chip included in each of the semiconductor modules, wherein the multi-chip semiconductor device electrically connects the semiconductor modules and electrically connects each of the semiconductor chips included in each of the semiconductor modules. A chip selector electrode of each of the semiconductor modules, and a connection pattern for electrically connecting the chip selector electrode and the semiconductor chip to a pattern shape formed on the semiconductor chip. 2. The multi-chip module according to claim 1, wherein the multi-chip module is formed differently. 6. The chip selector electrode according to claim 2, wherein said chip selector electrode is formed by electrically connecting said semiconductor modules to a position of a semiconductor module having a semiconductor chip to be selected. A multichip module according to any one of the above.