JP2765571B2 - Multi-chip module - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of a multi-chip module using a large-capacity multi-chip semiconductor device having a memory capacity several times as large as the mounting area of a conventional IC package.

2. Description of the Related Art Semiconductor memories are widely used from OA equipment such as personal computers, word processors, workstations, and facsimile machines to video equipment such as digital VTRs and TVs. It is expected that the demand for the semiconductor memory used here will increase at an accelerating rate. In parallel with this, in the manufacture of semiconductor memories, efforts are being made to increase the memory capacity per chip by increasing the density of the memory, and the memory capacity in a chip is increasing four times every three years. Currently, 1Mbit DRAM is mass-produced, 4Mbit DRAM is sample shipped, 16MDRA
M is in the prototype stage. However, there are many problems in the basic technology and the manufacturing process for increasing the capacity of the chip. In particular, for the transition from the current 1 Mbit to 4 Mbit, development of new memory cells, submicron wiring technology, package Enormous costs are required for the development of technics. 2. Description of the Related Art Conventionally, as a package for a memory, a plastic package formed by mounting a chip on a tab of a lead frame, wire-bonding a tip of an internal lead to a bonding pad of the chip by wire bonding, and resin molding is mainly used. The package type has a memory capacity of 256.
Before Kbit, DIP (Dual
in line package), but the demand for high-density mounting has increased since then, and
SOJ (small outlin) smaller than IP
e J-lead package), ZIP (zig
zag in-line package). Here, the DIP is a type in which leads are extended in two rows in two directions of the long side of the package, and these leads are bent downward under the package. The leads are inserted into through holes of a printed board and mounted. The ZIP is a type in which leads are protruded in one direction of the long side of the package and the leads are alternately bent, and is a through-hole insertion type in which the package is mounted vertically. The SOJ is a surface mount type in which the package is protruded in two long sides, but the lead pitch is reduced to half of the DIL, and the leads are bent downward into a "J" shape and mounted directly on the surface of the printed board. DIL
The purpose of this is to reduce the length of the package in the longitudinal direction and to mount both sides on a printed board. Regarding conventional packages, Nikkei Microdevices Supplement No. 1 pp. 73-80 and 87-
No. 89 is mentioned here, and since the DIP mounts the package horizontally and inserts the lead wire into the through-hole, it cannot be mounted on both sides and the mounting efficiency is not good. On the other hand, the ZIP can be mounted at a higher density than the DIP because of the vertical shape. That is, while the dimension between the lead rows of the DIP is three grid pitches of the printed board, that of the ZIP is one grid pitch, and the mounting density on the printed board is almost twice that of the DIP. Although SOJ is a horizontal mounting, it has features such as high-density mounting more than twice as large as DIP because the layout of the lead pins is not restricted by the lattice of the printed board and double-sided mounting is possible.

As described above, three types of conventional packages are generally used. However, all three types incorporate one chip in one package, and each package has one chip unless the capacity on the chip side increases. However, there is a disadvantage that the memory capacity does not increase. Also, there is only a difference of about twice in the mounting density on the printed board due to the difference in the package form, and there has been a problem that it is difficult to mount a large capacity and high density with the conventional package. Especially,
When a package having a large capacity and a high density is used in an electronic device or the like, a module is required in consideration of the electrical connection structure. SUMMARY OF THE INVENTION An object of the present invention is to provide a multi-chip module which has the above-mentioned problems, has a memory capacity that is twice as large as the mounting area of a conventional package, and takes into account electrical connection with electronic devices and the like. is there.

According to the present invention, in order to achieve the above object, a plurality of semiconductor modules electrically connected to a semiconductor chip are stacked via a spacer, and the semiconductor modules are electrically connected. A multi-chip module formed by resin sealing a multi-chip semiconductor device having a plurality of electrodes formed thereon, wherein the multi-chip module faces the lowermost or uppermost semiconductor module of the multi-chip semiconductor device. An external lead terminal electrically connected to an electrode of the multi-chip semiconductor device is formed on one surface so as to be exposed. A multi-chip semiconductor device in which a plurality of semiconductor modules electrically connected to a semiconductor chip are stacked via a spacer, and a plurality of electrodes are formed by electrically connecting the semiconductor modules; And a wiring board electrically connected to an electrode of the multi-chip semiconductor device, and an external lead terminal electrically connected to the electrode of the multi-chip semiconductor device via the wiring board. A chip module, wherein the external lead-out terminal is formed on one side of the wiring board, and the external lead-out terminal is formed so as to be exposed from the multi-chip module. In addition, a plurality of semiconductor modules electrically connected to a semiconductor chip are stacked via a spacer, and a multichip semiconductor device in which a plurality of electrodes are formed by electrically connecting the semiconductor modules is formed by resin sealing. A multi-chip module, the multi-chip semiconductor device having a lowermost layer or an uppermost layer of the multi-chip module, which extends from the end of one surface of the multi-chip module facing the semiconductor module in a direction in which the semiconductor modules are stacked. It is formed by exposing an external lead terminal electrically connected to an electrode of the multi-chip semiconductor device. In these cases, the multi-chip semiconductor device forms the connection pattern for electrically connecting the semiconductor chip and the electrode with a different pattern shape for each of the semiconductor modules. Preferably, the electrode to be electrically connected is configured as a chip selector electrode of the semiconductor chip to be electrically connected to the connection pattern having the different pattern shape. Alternatively, the multi-chip semiconductor device is formed such that a pattern shape formed on the semiconductor chip among connection patterns for electrically connecting the semiconductor chip and the electrodes is different for each semiconductor module, and the semiconductor chip An electrode electrically connected to a connection pattern having a different pattern shape formed thereon may be configured as a chip selector electrode of the semiconductor chip electrically connected to a connection pattern having a different pattern shape formed on the semiconductor chip. preferable. Alternatively, the multi-chip semiconductor device selects a common electrode electrically connected between the semiconductor modules and electrically connected to each of the semiconductor chips included in each of the semiconductor modules, and a semiconductor chip included in each of the semiconductor modules. It is preferable that a chip selector electrode of each of the semiconductor modules is formed, and a shape of a connection pattern for electrically connecting the chip selector electrode and the semiconductor chip is different for each of the semiconductor modules. Alternatively, the multi-chip semiconductor device selects a common electrode electrically connected between the semiconductor modules and electrically connected to each of the semiconductor chips included in each of the semiconductor modules, and a semiconductor chip included in each of the semiconductor modules. Forming a chip selector electrode of each of the semiconductor modules, and changing a pattern shape formed on the semiconductor chip among connection patterns for electrically connecting the chip selector electrode and the semiconductor chip to each of the semiconductor modules. It is preferable to form it. Further, in these cases, it is preferable to form the chip selector electrode by electrically connecting the semiconductor modules to the position of the semiconductor module having the semiconductor chip to be selected.

As a result, it is possible to provide a multi-chip module having a memory capacity which is several times larger than the mounting area of the conventional package and taking into consideration a connection target with an electronic device or the like.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will now be described with reference to FIGS.
Will be described. First, as shown in FIGS.
Before explaining the Ming multi-chip module,
FIG. 1 illustrates an example of a multi-chip semiconductor device 120 as a component.
This will be described with reference to FIGS. Where the multi-chip
Modules are formed by stacking multiple semiconductor modules.
External connection to the formed multi-chip semiconductor device
The structure which becomes a terminal is added. Figure 1 shows four
Stacking film carrier semiconductor modules 28a to 28d
Cross-sectional view of a multi-chip semiconductor device electrically connected
It is. FIG. 2 shows the multi-chip semiconductor device shown in FIG.
1st stage and 1st stage from below with mounted on motherboard
The connection part of the second stage film carrier semiconductor module
It is the expanded sectional view. FIG. 3 shows the multi-chip shown in FIG.
The second stage film carrier semiconductor from the bottom of the semiconductor device
It is a top view of module 28b. 4 to 6 show chips.
FIG. 4 is a perspective view showing details of the selection terminal portion, and FIG.
FIG. 5 shows the first stage film carrier semiconductor module from the bottom.
Joule, FIG. 6 is a motherboard. FIG. 7 shows a semiconductor
Each half of a multi-chip semiconductor device with four stacked chips
FIG. 3 is a circuit block diagram showing an electrical connection state of a conductor chip.
You. First, in FIG. 1 to FIG.
The configuration of the top semiconductor device will be described. In each figure,
The same reference numerals indicate the same contents. 1 and 2
Therefore, bumps 4a are formed on the semiconductor chip 2a.
And the bump 4a and the film carrier tape 6a are
Electrical connection at the inner lead part 10a which is a part of the part
Outer lead portion 12 which is a part of the lead portion.
a protrudes outside the semiconductor chip 2a and
Connected to a. The spacer 20a is formed in a frame shape.
(Hereinafter, frame-shaped spacers are
Called sa. ), Between film carrier semiconductor modules
The front surface pattern 22a and the back surface pattern
24a, front surface pattern 22a and back surface pattern 24a
Through hole 26a is formed to electrically connect
I have. Also, the surface pattern 22a and the outer
The node 12a is electrically connected by the first connection layer 16a.
Have been. As a result, the back surface of the semiconductor chip 2a is
Until the turn 24a, they are electrically connected.
The upper surface of the semiconductor chip 2a and the inner lead portion 10
a protective coating resin 1 on the side of the semiconductor chip 2a containing
4a is coated. The above configuration is the film
This is the basic structure of the carrier semiconductor module 28a. Up
In FIG. 1, the lowermost film carrier semiconductor module of FIG.
The configuration of the module 28a has been described.
The eyes, third and fourth stages have substantially the same configuration. Or later
In each figure, the bottom film carrier semiconductor module
The letter "a" is added after the sign as described above, and
For "b", for the third row "c", for the fourth row
Display with "d" appended. This film carrier semiconductor
Between modules, the first stage film carrier
Surface pattern 22a of semiconductor module 28a and second stage
Back of the film carrier semiconductor module 28b
The turn 24b is electrically connected to the turn 24b via the second connection layer 18b.
Continue. Between other film carrier semiconductor modules
Are connected in the same way. In addition, the shape is
The formed wiring pattern 32 is the lower film carrier.
The back pattern 24a of the semiconductor module 28a
Electrical connection is made via the three connection layers 34. Like this
Number of film carrier semiconductor modules
In chip chips, the signal from the motherboard
Receiving the signal, for example, having the spacers 20a to 20d
Back patterns 24a-d, through holes 26a-d,
First connection layer for connecting turns 22a-d and spacers
16a-d, the second connection layers 18a-d, etc.
It becomes the electrode of the conductor device. Also, this electrode and the semiconductor chip
For example, bumps 4a to 4d, inner leads
10a-d, outer leads 12a-d, surface pattern 22
a to d etc. constitute a multi-chip semiconductor device
It becomes the connection pattern of the carrier semiconductor module. Sand
That is, the film carrier semiconductor modules are electrically connected.
Then, it is electrically connected to the wiring pattern 32 of the motherboard 30 and the like.
Is connected to the electrode, and the semiconductor connected to this electrode
The wiring to the body chip becomes the connection pattern. Next,
Details on the wiring etc. of the Lum carrier semiconductor module
This will be further described with reference to FIG. 3 and the like.
Including the outer lead portion 12a and the inner lead portion 10a
The plurality of lead portions are one chip selection lead wire 40.
b and a plurality of other common lead wires 42b
And the semiconductor chip 2a and the frame-shaped
Connected to the surface pattern formed on the pacer 20a.
You. This chip select lead 40 is
Semi-conducted signal to allow read / write operation to be sent
It is supplied to the body chip 2a. Therefore chip selection
The selection lead wire 40 is connected to each film capacitor among the aforementioned electrodes.
Chip selector power unique to the rear semiconductor module
Connected to poles. Next, each film carrier semiconductor model
Chip selector electrode that is unique to Joule
And connecting the chip selector electrode to the semiconductor chip.
An example of the connection pattern will be described with reference to FIGS.
You. As can be seen from FIG. 4, the common lead 42b is
Connected to the common terminal pattern 46b which is a surface pattern.
You. The chip selection lead wire 40b is connected to the chip selection end.
Child pattern 44b, chip selection dedicated pattern 50b,
Chip selection terminal pattern 44b and chip selection dedicated pattern
Surface pattern consisting of a pattern 48b connecting to the surface pattern 50b
Connected to the In this case, the common terminal pattern 46
b and the back surface pattern 52b are interposed through the through hole 58b.
Is electrically connected to the
Pattern 50b and the back pattern 56b form a through hole 60b.
Are electrically connected via Also, chip select terminal
There is a through hole between the pattern 44b and the back pattern 54b.
No rule is formed. On the other hand, FIG.
The terminal pattern 44a and the back pattern 54a
Point electrically connected by through hole 62a, chip
The selection terminal 44a and the chip selection dedicated pattern 50a
Except for gas insulation, the other configuration is the same as that of FIG.
ing. Figure 6 shows the wiring pattern of the motherboard
In the figure, on the upper surface of the motherboard 30
Chip selection terminal pattern 64, chip selection dedicated pattern
66, a common terminal pattern 68 is formed.
Lines 70, 72 and 74 are connected to these terminal patterns.
ing. In the multi-chip semiconductor device, the mask shown in FIG.
The film carrier semiconductor module shown in FIG.
Joule, film carrier semiconductor module shown in FIG.
Are laminated in order. Therefore, on the motherboard
Chip selection terminal pattern 64, film connected to this
Back pattern 54a of carrier semiconductor module, through
Hole 62a and chip select terminal pattern 44a
Unique to the semiconductor chip 2a connected to the selection lead wire 40a.
It becomes a chip selector electrode. Also, the chip select terminal pattern
44a and the chip selection lead wire 40a
Connection electrode for electrically connecting the data electrode and the semiconductor chip 2a.
Turns. Similarly, the chip select end on the motherboard
A child pattern 66, a back pattern 56a connected thereto,
Through hole 60a, chip selection pattern 50a,
Back surface pattern 56b, through hole 60b,
The chip selection dedicated pattern 50b is a chip selection lead wire.
Chip selector unique to semiconductor chip 2b connected to 40b
It becomes an electrode. In addition, the chip selection terminal pattern 44b,
The lead wire 40b is connected to the chip selector electrode and the semiconductor
The connection pattern electrically connects the body chip 2b.
You. Also, the common terminal pattern 66 on the motherboard,
Back surface pattern 52a, through hole 58a,
Common terminal pattern 46a, back side pattern connected to this
52b, through hole 58b, common terminal pattern 46b
Are the common lead wires 42 that are the respective connection patterns.
electrically connected to the semiconductor chips 2a and 2b through a and b, respectively.
Common electrode for film carrier semiconductor module
You. Thus, each chip selector electrode is connected
By changing the shape of the connection pattern
Chip selectors connected to connection patterns of different shapes
Make the poles unique to each semiconductor module.
Can be. Also, film carrier semiconductor module
The electrodes are formed by stacking
Can be formed. That is, each chip
Change the shape of the connection pattern connected to the selector electrode
This makes it easy to form the electrodes,
Form electrodes as unique to each semiconductor module
be able to. In addition, each film carrier semiconductor module
When forming the chip selector electrode,
If the selector electrode is
Film carrier semiconductor module laminated above
Configure not to be electrically connected to the module
This allows the chip selector electrode to be connected to each semiconductor module.
Can be formed unique to the device. like this
If a multi-chip semiconductor device is configured in
FIG. 7 is a circuit block diagram showing the connection state. here
Semiconductor memory chip in a multichip semiconductor device.
Storage of information (data input) and stored information
A method of reading out (data output) will be described. In the figure
Addressing the semiconductor chips 2a, 2b, 2c and 2d.
Terminal 80, data input / output terminal 82, write enable
Terminal 84, out enable terminal 86, power supply terminal 88,
Ground terminal 90, chip selection terminals 92a, 92b, 9
2c and 92d are electrically connected. These terminals
Of the chip selection terminals 92a to 92d
Although independently connected to the conductor chips 2a to 2d,
The other terminals are commonly connected to the semiconductor chips 2a to 2d.
ing. The input and output of information is performed by the address unit set in the chip.
It is performed in the place. To write information to a certain address,
Address signal to specify, write rice to enable writing
Cable signal and data signal containing data to be stored are required.
is there. However, the amount of information has increased and one chip has no information.
Need to use multiple chips when it can't accommodate information
Occurs. FIG. 7 shows an example of four chips.
Suppose, for example, that 100 addresses can be set in one chip.
In this case, addresses 0 to 99 are set for each chip. This
Now the data at address 99 of the semiconductor chip 2a
As an example, the operation of writing
A signal indicating “address 99” is supplied to the data input / output terminal 82.
A data signal for writing is supplied to a write enable terminal 8.
4 to the semiconductor chip 2 at the same time.
A chip selection terminal 92a connected to a
Address signal, data signal, and line signal.
The enable signal is applied to the four semiconductor chips 2a to 2d.
Only the semiconductor chip 2a is valid, and other semiconductor chips
It does not act on 2b-2d. That is, the semiconductor chip 2
The necessary data is written to address 99 of a,
Address 99 of the three unselected semiconductor chips remains unchanged
Become. Similarly, for reading data,
The out enable signal for the enable signal operates,
Is connected to the data input / output terminal 82 in the same connection state as writing.
The data stored at address 99 of the conductor chip 2a is output.
Will be empowered. Note that, in FIG.
The child 80 and the data input / output terminal 82 are shown by one line.
However, the actual wiring is composed of a plurality of wires. This
In response, the write enable terminal 84, out enable
Terminal 86, power terminal 88, ground terminal 90, and chip
The selection terminals 92a to 92d are each 1 in actual wiring.
Often books. Next, the multichip explained so far
The operation of the semiconductor device will be described. 1 and 2
Body chip 2a is a memory half in which storage elements are integrated.
A conductive chip, and a signal supplied from the motherboard 30
Write and read data according to the
is there. Electric signal flow when writing and reading data
First, the external pattern is attached to the wiring pattern 32 of the motherboard 30.
From the third connection layer 34, the spacer 20a
Back surface pattern 24a, through hole 26a, front surface pattern
Through the first connection layer 16a and the film carrier
6a outer lead portion 12a, inner lead portion 10
a, inside the first-stage semiconductor chip 2a through the bumps 4a
Are supplied to the elements. Similarly, the second stage semiconductor chip 2
b and the third and fourth stage semiconductor chips 2c and 2d
Are also supplied with signals at the same time. Here, the chip shown in FIG.
The chip selection lead wire 40b is connected to the chip selection terminal 92 shown in FIG.
a, and is independently connected to each semiconductor chip.
Other common lead wires 42b are also the same as those shown in FIG.
Dress terminal 80, data input / output terminal 82, write enable
Cable terminal 84, out enable terminal 86, power supply terminal 8
8, corresponding to the ground terminal 90, common to each terminal
Connected. That is, as shown in FIGS.
The signal supplied to the common terminal is
The back surface pattern of the spacer 20a via the through terminal pattern 68
52a, through hole 58a, surface pattern 46a,
First-stage semiconductor chip 2a via common lead wire 42a
To the back surface of the second-stage spacer 20b.
Supplied from the turn 52b to the common lead wire 42,
As described above, they are simultaneously supplied to each chip. On the contrary
Chip selection signal supplied to the chip selection terminal pattern 64
The symbols are the back pattern 54a of the spacer 20a and the through hole
62a, surface pattern 44a, chip selection lead wire
Supplied to the first-stage semiconductor chip 2a via the first semiconductor chip 2a
Are the back pattern 54b of the spacer 20b and the front pattern.
44b is not electrically connected, so the second stage
It is not supplied to the semiconductor chip 2b. Motherboard as well
Chip 30 supplied to the chip selection terminal pattern 66 of the
The selection signal is supplied to the first-stage semiconductor chip 2a.
Not selectively supplied to only the second stage semiconductor chip 2b
can do. Note that the second and higher chips
Even if the same circuit pattern is provided on the spacer at each stage
This allows independent chip selection. This allows
Move the desired semiconductor chip using the chip selector electrode.
Can be made into laminated film carrier semiconductor
Write / read data to / from module without malfunction
Delivery can be realized. Next, multi-chip semiconductor
Other spacer shapes used for the device will be described.
You. Until now, a space with a rectangular shape as shown in FIG.
Although the description has been made with respect to the film cap, as shown in FIG.
Structure with spacers only on two sides of rear lead wire arrangement
Is also possible. That is, as shown in FIG.
Having first and second spacers 20b1 and 20b2
Depending on the structure, film carrier tape semiconductor module
Can be stacked. Also, the first stage in FIG.
Frame-shaped spacers from the front to the back of the semiconductor chip
Same structure without spacer members on both sides
The first stage spacer is shown in FIG.
The spacer member 96a is also provided on the lower surface of the semiconductor chip 2a.
And a spacer 64a interposed therebetween.
Arbitrary shape wiring pattern on any surface connected to motherboard
Structure 98a may be formed. Sand
That match the standardized connection pattern of the motherboard
This is a structure that allows arbitrary pattern arrangement to be formed. Also,
Until now, front and back patterns have been formed on spacers,
Holes connect the front and back patterns electrically.
Has been explained, but the connection to conduct the front and back pattern
Pattern for film carrier outerwear
Is folded to the back via the spacer front and side surfaces.
Structured or constructed using bent front and back conductive leads
It may be. Fig. 10 shows an example of this
4 shows a connection pattern formed by bending a gate. This place
If the previous surface pattern, back pattern, through-hole
Rules are not required. FIG. 10 shows a film carrier semiconductor.
Shows the joint between the module spacer and the outer lead
In the cross-sectional view, the spacer 20a has a surface pattern 100a,
A back pattern 24a is formed. Folded
The tip of the outer lead 12a and the back surface pattern 24a are below.
It is fixed by the surface connection layer 104a. With the above structure
And the outer lead 12a is attached to the upper surface of the spacer 20a.
Street, the side of the spacer 20a
It extends to the lower surface and is joined to the back pattern 24a.
The continuity of the front and back of the sa is done. Next, multi-chip semiconductor
Figure shows other chip selector electrodes used in body devices
11 to FIG. 11 to 13 correspond to FIGS. 4 to 6.
The same position is indicated, and the same sign indicates the same content.
I have. However, the common terminal pattern is omitted.
You. This feature consists of the chip selector electrode and the semiconductor chip.
Pattern on the semiconductor chip to connect to
Formed on the spacer 20b.
Front and back patterns and through hoes connecting front and back patterns
The conductive pattern was formed with the same structure as the spacer 20a.
Is a point. Thus, the outer carrier of the film carrier
To different arrangements as shown at 40a and 40b
In this way, each chip selector electrode
And the semiconductor chip can be selected independently.
ing. Outer lead wire bending explained in FIG.
The application of this structure makes it easy to
Can be achieved. In addition, multi-chip semiconductor devices
FIG. 14 shows another chip selector electrode used for
To FIG. This is also a chip selector electrode and semiconductor
The shape of the connection pattern that connects the chip to the semiconductor chip
Although formed differently above, the spacers 20a and 20a
b) has the same structure as the film carrier
40a, 40a ', 40b, 40b' have the same structure.
Is different. That is, in FIGS. 14 and 15,
Chip select pads 102b, 102a, pad connection lines
104b, 104a and spare chip selection pad 106
b, 108b, 106a and 108a are formed, and the first stage
In the semiconductor chip 2a of FIG.
Pad selection pad 106a and pad connection line 10
4a, the connection word and the chip selection spare pad 108a are
It is insulated from the top selection pad 102a. Also, the second stage
In the second semiconductor chip 2b, the chip selection pad 102b
Connect the chip selection spare pad 108b to select the chip
It is insulated from the spare pad 106b. Such a configuration
To the chip select terminal 64 of the motherboard 30
When the signal is applied, the semiconductor chip 2a can be selected independently.
When a signal is applied to the chip select terminal 66, a semiconductor
Chip 2b can be selected independently. Next, multi-chip semiconductor
FIG. 17 shows other spacer shapes used for the body device.
You. FIG. 17 shows connection between the semiconductor chip 2 and the bump 4
Through the through hole formed on the spacer 110
Are extended to electrically connect the rails. You
That is, this is an example in which a surface pattern is not formed. This Lee
For the formation of the spacer 110 with a dough, only one side of the substrate
Semiconductor chip 2 fits on the substrate to which the conductive material for
After punching out the hole to be
Paste the conductive material including the holes, and then print
Using the wire plate manufacturing process, the base material as shown in FIG.
Leaded spacer with lead pattern protruding at one end
Form 110. Leaded spacer 110 and semiconductor chip
The bonding of the tip 2 is already known such as gold-gold, gold-tin, etc.
An inner lead bonding method is used. With this lead
Of film carrier semiconductor module using spacer
In stacking, the first connecting portion 16a shown in FIG.
It is important and very advantageous in the assembling process. In addition, before
To use the same material as the motherboard for the spacer
Therefore, the connection reliability after mounting on the motherboard is greatly increased.
Can be improved. Next, multi-chip semiconductor devices
A method of manufacturing the device will be described. FIG. 18 shows an outline of the manufacturing process.
Shown in In FIG. 1, FIG. 2 and FIG.
Inner lead 10 of thinned film carrier tape
a and the bump 4a formed on the surface of the semiconductor chip 2a.
Then, the inner lead portion is bonded.
This bonding method uses TAB (Tape Automated).
attached Bonding) Inner lead bondin
This is a method generally known as "logging". Then Bon
Protective coating on the mounting surface and chip selection terminal surface and side
Is applied. At this time, the semiconductor chip 2a and the bonding
Inspection of the parts and classification of quality. Then film key
Cut the film carrier module 6a from the carrier tape
Start. In parallel with this, a plurality of spacers are simultaneously formed.
One spacer from the printed wiring board
And aligned with the film carrier module 6a.
To make a first connection to form a first connection layer 16
I do. Thus, the film carrier semiconductor module shown in FIG.
A single unit of the tool is created. Then film carrier semiconductor
After installing four modules on the alignment jig,
Lum carrier semiconductor module back surface pattern 24
Only the terminals are melted by contacting the outer leads 12
A second connection is made by immersion in the bath. After this, the motherboard
Resin coating is performed, leaving the connection to the. In this process diagram
Before cutting the film carrier tape
After the first connection of the spacers, the film carrier table
To cut the tape, and the spacer pudding before cutting the outer shape
Film carrier module
A first connection method is also possible. In this embodiment,
The first connection is pre-attached to the terminal of the through hole.
The solder using the Sn-Pb-based solder
Solder reflow method for bonding by heating and melting
Adopted, Au-Au thermocompression bonding Au-Sn bondin
Of course, connection methods using conductive paste are also applicable.
You. For other examples of multi-chip semiconductor device manufacturing methods
This will be described with reference to FIG. FIG. 19 shows the outline of the manufacturing process.
In particular, use the spacer with leads shown in FIG.
Shows how to manufacture a multi-chip semiconductor device.
You. First, the inner of the patterned spacer with leads
Connect the leads to the bumps on the semiconductor chip. This state
Is the structure shown in FIG. Next, protect the chip
Inspection of the whole chip including the
The quality is classified and the outer shape is cut only for good products. This
After that, they are stacked by the same method as described in FIG.
Perform alignment, second connection, performance inspection, resin coating
A multi-chip semiconductor device is completed. Next, the theory so far
The external connection terminal is added to the multichip semiconductor device
Example of multi-chip module of the present invention added
explain. FIG. 20 shows a multi-chip semiconductor device 12 inside.
0 is a multi-chip module 122 including
A child 124 (external lead terminal) is arranged on one side of the module.
Is placed. Module is connected to terminal 124 (external drawer)
Module) by applying resin coat 126
The outer shape is formed. Terminal 124 (external drawer end
(A) has an Au plating treatment on the surface. This configuration
Connect the multichip module to the terminal (124
To the motherboard that has terminals facing the
The storage device of the electronic device
You. That is, in FIG. 20, the semiconductor chip is electrically connected.
Stacked multiple semiconductor modules via spacers
Overlapping, electrically connecting the semiconductor modules to each other
The multi-chip semiconductor device on which the electrodes are formed is sealed with resin.
A multi-chip module formed by
Of the lowermost or uppermost layer of the semiconductor device
One of the multi-chip modules facing the body module
Electrically connected to the electrodes of the multi-chip semiconductor device
The external lead terminals to be connected are formed by exposing them.
FIG. 21 shows another multi-chip module.
Multi-chip including multi-chip semiconductor device 120 in section
Multi-chip semiconductor device
120 is electrically connected to the wiring board 130 inside the module.
Each signal terminal is connected to one end of the wiring board 130.
Terminal 132 (external pull-out terminal)
ing. That is, in FIG.
Multiple semiconductor modules connected via a spacer
Stacking and electrically connecting the semiconductor modules to each other.
A multi-chip semiconductor device in which several electrodes are formed;
A multi-chip semiconductor device mounted with a multi-chip semiconductor device;
A wiring board electrically connected to the electrodes of the device;
Via the electrode of the multichip semiconductor device and the wiring substrate
With external draw-out terminals for electrical connection
A chip module, wherein one side of the wiring board has the external lead.
A lead terminal is formed, and the external lead terminal is
It is formed so as to be exposed from the top module. FIG.
Indicates yet another multi-chip module. this
Connects the connector terminal 132 (external lead-out terminal)
The lower two parts of the
Stacked multi-chip semiconductor devices, or
This structure is advantageous for semiconductor chips with multiple terminals.
You. That is, FIG. 22 shows an electrical connection with the semiconductor chip.
Stacked semiconductor modules via spacers
By electrically connecting the semiconductor modules,
Multi-chip semiconductor device with electrodes formed is sealed with resin
A multi-chip module,
The lowermost or uppermost semiconductor module of the semiconductor device;
End of one side of the multi-chip module facing the module
From the part in the direction in which the semiconductor modules are stacked.
As described above, the electrodes of the multi-chip semiconductor device
The external lead terminals to be connected are formed by exposing them.
As described above, this multi-chip module
Multi-chip semiconductor device
It is almost the same as the conventional module
With a structure that has multiple times the storage capacity for the same mounting area
Yes, portable electronic equipment that requires a small, large-capacity memory
Very effective for vessels.

As described above, according to the present invention, it is possible to obtain a multi-chip module having a memory capacity that is two or more times as large as the mounting area of the conventional package.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a multi-chip semiconductor device applied to a multi-chip module of the present invention.

FIG. 2 is a cross-sectional view of a multi-chip semiconductor device applied to the multi-chip module of the present invention.

FIG. 3 is a plan view of a multichip semiconductor device applied to the multichip module of the present invention.

FIG. 4 is a perspective view of a chip selection terminal structure of a multichip semiconductor device applied to the multichip module of the present invention.

FIG. 5 is a perspective view of a chip selection terminal structure of a multichip semiconductor device applied to the multichip module of the present invention.

FIG. 6 is a perspective view of a chip selection terminal structure of a multichip semiconductor device applied to the multichip module of the present invention.

FIG. 7 is a circuit block diagram of a multichip semiconductor device applied to the multichip module of the present invention.

FIG. 8 is a plan view and a cross-sectional view of a spacer structure of a multi-chip semiconductor device applied to the multi-chip module of the present invention.

FIG. 9 is a plan view and a cross-sectional view of a spacer structure of a multi-chip semiconductor device applied to the multi-chip module of the present invention.

FIG. 10 is a plan view and a cross-sectional view of a spacer structure of a multi-chip semiconductor device applied to the multi-chip module of the present invention.

FIG. 11 is a perspective view of another example of the chip selection terminal structure of the multichip semiconductor device applied to the multichip module of the present invention.

FIG. 12 is a perspective view of another example of the chip selection terminal structure of the multichip semiconductor device applied to the multichip module of the present invention.

FIG. 13 is a perspective view of another example of the chip selection terminal structure of the multichip semiconductor device applied to the multichip module of the present invention.

FIG. 14 is a perspective view of another example of the chip selection terminal structure of the multichip semiconductor device applied to the multichip module of the present invention.

FIG. 15 is a perspective view of another example of the chip selection terminal structure of the multichip semiconductor device applied to the multichip module of the present invention.

FIG. 16 is a perspective view of another example of the chip selection terminal structure of the multi-chip semiconductor device applied to the multi-chip module of the present invention.

FIG. 17 is a sectional view of a leaded spacer of a multichip semiconductor device applied to the multichip module of the present invention.

FIG. 18 is a manufacturing process diagram of the multi-chip semiconductor device of the multi-chip semiconductor device applied to the multi-chip module of the present invention.

FIG. 19 is a manufacturing process diagram of the multi-chip semiconductor device applied to the multi-chip module of the present invention.

FIG. 20 is a perspective view showing a multichip module of the present invention.

FIG. 21 is a perspective view showing a multichip module of the present invention.

FIG. 22 is a perspective view showing a multichip module of the present invention.

[Explanation of symbols]

 2 Semiconductor chip, 6 Film carrier, 10 Inner lead, 12 Outer lead, 16 First connection layer, 18 Second connection layer, 20 Spacer, 28 Film semiconductor module, 30 Motherboard, 44 Chip selection terminal pattern, 110 ... Leaded spacer

──────────────────────────────────────────────────続 き Continuing on the front page (72) Koji Serizawa, Inventor 292, Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Hitachi, Ltd.Production Technology Laboratory (72) Michiharu Honda, 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Address Co., Ltd., Hitachi, Ltd., Production Technology Laboratory (72) Inventor Toru Yoshida 292, Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture, Ltd. 1450 No. in Musashi Plant, Hitachi, Ltd. (56) References Patent 2728432 (JP, B2) (58) Fields investigated (Int. Cl. ⁶ , DB name) H01L 25/00-25/18 H01L 21/60

Claims (8)

(57) [Claims] 1. A multi-chip semiconductor device in which a plurality of semiconductor modules electrically connected to a semiconductor chip are stacked via a spacer , and a plurality of electrodes are formed by electrically connecting the semiconductor modules to each other. A multi-chip module comprising: a multi-chip semiconductor device electrically connected to an electrode of the multi-chip semiconductor device on one surface of the multi-chip module opposed to the lowermost or uppermost semiconductor module of the multi-chip semiconductor device; A multi-chip module formed by exposing external lead-out terminals. 2. A multi-chip semiconductor device in which a plurality of semiconductor modules electrically connected to a semiconductor chip are stacked via a spacer , and a plurality of electrodes are formed by electrically connecting the semiconductor modules. A wiring board mounted with the chip semiconductor device and electrically connected to an electrode of the multi-chip semiconductor device; and an external lead-out terminal electrically connected to the electrode of the multi-chip semiconductor device via the wiring board. A multi-chip module, comprising: the external lead-out terminal formed on one side of the wiring board; and the external lead-out terminal being exposed from the multi-chip module. 3. A multi-chip semiconductor device in which a plurality of semiconductor modules electrically connected to a semiconductor chip are stacked via a spacer , and a plurality of electrodes are formed by electrically connecting the semiconductor modules to each other. A multi-chip module, wherein the multi-chip semiconductor device extends from an end of one surface of the multi-chip module facing the lowermost or uppermost semiconductor module of the multi-chip semiconductor device in a direction in which the semiconductor modules are stacked. The multi-chip module is formed by exposing the external lead-out terminals electrically connected to the electrodes of the multi-chip semiconductor device. Wherein said multi-chip semiconductor device, wherein the pattern shape of the connection pattern for electrically connecting the semiconductor chip and the electrode formed different for each of the semi-conductor modules, the connection pattern of said different pattern multi-chip according to any one of claims 1 to 3, characterized by being configured as an electrode chip selector of said semiconductor chip to electrically connect the electrodes of the electrically to the connection pattern of said different pattern shape to be connected with module. 5. The semiconductor device according to claim 5, wherein said multi-chip semiconductor device is
Among the connection patterns for electrically connecting the conductor chip and the electrodes, the pattern shape formed on the semiconductor chip is
Different was formed on each semi-conductor module, the semiconductor switch
Connection patterns with different pattern shapes formed on the
An electrode for electrical connection is formed on the semiconductor chip.
The electrical connection with connection patterns having different turn shapes
Configured as chip selector electrode for semiconductor chip
The multi-chip module according to claim 1, wherein: 6. The multi-chip semiconductor device according to claim 5 , wherein
Each of the semiconductor modules is electrically connected by electrically connecting the conductor modules.
Electrically connected to each of the semiconductor chips of the module
Common electrode and semiconductor of each semiconductor module
The chip selector of each of the semiconductor modules for selecting a chip
Electrode for the chip selector and the electrode for the chip selector
The shape of the connection pattern for electrical connection with the body chip
It is characterized by being formed differently for each semiconductor module
The multi-chip module according to claim 1, wherein 7. Wherein the multi-chip semiconductor device is
Each of the semiconductor modules is electrically connected by electrically connecting the conductor modules.
Electrically connected to each of the semiconductor chips of the module
Common electrode and semiconductor of each semiconductor module
The chip selector of each of the semiconductor modules for selecting a chip
Electrode for the chip selector and the electrode for the chip selector
Of the connection patterns for electrically connecting with the body chip
The pattern shape formed on the semiconductor chip is
Claims characterized by being formed differently for each joule
Item 4. The multichip module according to any one of Items 1 to 3. 8. A half having a semiconductor chip to be selected
Half of the way up to the conductor module position Electricity between conductor modules
The chip selector electrode is connected by pneumatic connection.
8. The method according to claim 4, wherein
Onboard multi-chip module.