KR102029484B1 - Printed circuit board and chip package comprising the same - Google Patents

Printed circuit board and chip package comprising the same Download PDF

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Publication number
KR102029484B1
KR102029484B1 KR1020130147314A KR20130147314A KR102029484B1 KR 102029484 B1 KR102029484 B1 KR 102029484B1 KR 1020130147314 A KR1020130147314 A KR 1020130147314A KR 20130147314 A KR20130147314 A KR 20130147314A KR 102029484 B1 KR102029484 B1 KR 102029484B1
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KR
South Korea
Prior art keywords
pad
center
circuit board
printed circuit
chip
Prior art date
Application number
KR1020130147314A
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Korean (ko)
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KR20150062544A (en
Inventor
박성열
Original Assignee
삼성전기주식회사
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Priority to KR1020130147314A priority Critical patent/KR102029484B1/en
Publication of KR20150062544A publication Critical patent/KR20150062544A/en
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Publication of KR102029484B1 publication Critical patent/KR102029484B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/142—Metallic substrates having insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Abstract

The present invention relates to a printed circuit board.
The printed circuit board according to the present invention is a printed circuit board in which an insulating layer and a wiring layer are alternately stacked,
A plurality of conductive electrode pads are formed on the surface of the insulating layer, and the conductive electrode pads are formed to be inclined laterally than the central portion, thereby preventing slipping when the chip is mounted.

Description

Printed circuit board and chip package comprising the same}

The present invention relates to a printed circuit board having a solder pad for preventing slip of the chip.

Recently, with the development of the electronics industry, high performance, high functionalization, and miniaturization of electronic components are required. Accordingly, high integration, thinning, and fine circuit patterning are required in substrates for surface mount components such as SIP (system in package) and 3D packages. It is emerging.

In particular, a wire bonding method and a flip chip bonding method are used to electrically connect a semiconductor chip and a printed circuit board in a surface mounting technology of an electronic component on a substrate.

Here, the wire bonding method bonds a semiconductor chip printed on a printed circuit board to a printed circuit board using an adhesive, and transmits and receives information between a lead frame of the printed circuit board and a metal terminal (ie, a solder pad) of the semiconductor chip. For this purpose, the electronic device and the wire are molded with a thermosetting resin, a thermoplastic resin, or the like after being connected with a metal wire.

In addition, the flip chip bonding method forms external connection terminals (i.e. solder balls) of several tens of micrometers in size to several hundreds of micrometers of gold, solder, or other metal on a semiconductor chip, and is opposite to the conventional mounting method by wire bonding. In this case, the semiconductor chip on which the bump is formed is flipped and mounted so that the surface thereof faces the substrate.

However, although the wire bonding method is more productive than other packaging methods, there is a disadvantage in that the size of the module is increased and an additional process is required because it must be connected to the printed circuit board using a wire, and the flip chip bonding method is widely used. .

The flip chip bonding method has a structure in which solder balls are interposed between an electrode layer formed in an open region of a solder resist layer of a printed circuit board and a connection terminal of a semiconductor chip, and are electrically connected to each other.

At this time, in the process of placing the semiconductor chip on the printed circuit board and combining through the reflow process, the position of the solder pad and the solder ball is changed, which may cause alignment mismatch that is not connected to a predesigned wiring pattern.

That is, the semiconductor package has a problem in that the reliability of the product is degraded, such as a wiring to be connected or a short to be connected.

Republic of Korea Patent Publication No. 2012-0085673

Accordingly, the present invention was devised to solve the above-mentioned disadvantages and problems in the conventional printed circuit board, and the side pads formed at both sides are formed higher than the center pad formed at the center of the printed circuit board to form a recess, thereby soldering. SUMMARY OF THE INVENTION An object of the present invention is to provide a printed circuit board in which slip of a semiconductor chip is prevented.

The object of the present invention is to provide a printed circuit board in which an insulating layer and a wiring layer are alternately stacked.

A plurality of conductive electrode pads are formed on the surface of the insulating layer, and the conductive electrode pads are achieved by providing a printed circuit board formed to be inclined laterally than a central portion.

In this case, the conductive electrode pad may include a center pad positioned at the center of the insulating layer and side pads inclined at both sides of the center pad.

In addition, the side pad may be configured as an inclined pad that is inclined upward at both ends of the center pad.

In addition, the side pads may be formed in pairs, and may be formed stepped to form a step.

Meanwhile, another object of the present invention is to provide a chip package including a printed circuit board in which an insulating layer and a wiring layer are alternately stacked.

A printed circuit board having a plurality of conductive electrode pads formed on a surface of the insulating layer, wherein the conductive electrode pads are inclined laterally than a central portion; And a solder ball coupled to the conductive electrode pad. It is achieved by providing a chip package comprising a.

In this case, the solder ball may be smaller in diameter from the center portion to the side portion.

In addition, the side pads may be configured in pairs to prevent separation of the solder balls.

As described above, the printed circuit board according to the present invention has the advantage that the chip can be accurately coupled with the printed circuit board to reduce the defect of the chip package.

In addition, the present invention can be automatically aligned and bonded when the chip is mounted on the printed circuit board, there is no need for a separate fixing jig has the advantage of reducing the product manufacturing time.

1 is a perspective view of an embodiment of a printed circuit board according to the present invention;
2 is a perspective view of another embodiment of a printed circuit board according to the present invention;
3 is an exploded cross-sectional view of an embodiment of a chip package in which a chip is mounted on a printed circuit board.
4 is an exploded cross-sectional view of another embodiment of a chip package in which a chip is mounted on a printed circuit board.
5 is a cross-sectional view of the chip package of Figure 4 combined.

Advantages and features of the present invention, techniques for achieving them, and the like will become apparent with reference to the embodiments described below in detail with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various forms. This embodiment may be provided to make the disclosure of the present invention complete, and to fully inform the scope of the invention to those skilled in the art.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. In this specification, the singular also includes the plural unless specifically stated otherwise in the phrase. As used herein, 'comprise' and / or 'comprising' refers to a component, step, operation and / or element that is mentioned in the presence of one or more other components, steps, operations and / or elements. Or does not exclude additions.

1 is a perspective view of an embodiment of a printed circuit board according to the present invention, FIG. 2 is a perspective view of another embodiment of a printed circuit board according to the present invention, and FIG. 3 is an embodiment of a chip package in which a chip is mounted on a printed circuit board. 4 is an exploded cross-sectional view of a chip package in which a chip is mounted on a printed circuit board.

As shown, the present invention may be composed of a conductive electrode pad 120 for electrically connecting the chip 130 on the build-up layer 110 and the upper surface of the build-up layer.

The build-up layer 110 may have a conductive pattern formed on a specific layer while the insulating layer and the wiring layer are alternately repeatedly formed to form the multilayer printed circuit board 100, and the conductive patterns are formed by vias connecting upper and lower interlayer wiring layers. Can be electrically connected.

Both sides of the build-up layer may be formed of an insulating layer that molds and electrically insulates the wiring layer. The insulating layer may be opened so that a portion of the wiring layer may be connected to the chip 130, and the via may be exposed to the outside. And, except the exposed vias are applied with a solder resist to prevent short circuit of the wiring, and serves to protect the substrate by preventing corrosion from foreign matter.

The via may further include a conductive electrode pad 120 on an upper surface thereof so as to be connected to the chip 130. The conductive electrode pad 120 may protrude from the solder resist layer to form lands on which the chip 130 may be mounted.

The chip 130 may include a grid-shaped solder ball 140 formed in a ball grid array (BGA) so that a circuit pattern formed therein is electrically connected to the printed circuit board 100. When the 140 is coupled to the conductive electrode pad 120 formed on the printed circuit board may be electrically connected.

In this case, a solder paste for connecting to the chip 130 may be coated on the upper surface of the conductive electrode pad. Since the solder paste is the same material as the solder ball formed on the chip 130 to be mounted, the solder paste may be easily fused in a reflow process, and thus the contact force with the printed circuit board 100 may be improved.

That is, when the solder ball is in contact with the upper surface of the solder paste, a high temperature is applied in a short time to form a solder molten state. When the solder paste and the solder ball become viscous liquid, they are hardened when the chips are joined to each other by surface tension. It may be fixed to the printed circuit board 100.

Since the solder ball 140 formed on the chip 130 and the conductive electrode pad 120 formed on the printed circuit board should be connected to correspond to each other, mutual alignment is very important. In particular, electronic devices tend to be miniaturized, and integration is required to deliver a large number of input / output signals, so accuracy is required for fine pattern connection.

However, when the solder balls formed on the chip 130 and the solder paste coated on the upper surface of the conductive electrode pad are combined during the reflow process, the chips 130 slip and are not aligned with each other due to the imbalanced placement of the solder balls. You may not.

The present invention may include a conductive electrode pad 120 having a thickness difference for each pad disposed on an upper surface of a via exposed to the outside to solve the above problem. As illustrated in FIGS. 2 and 4, the conductive electrode pad 120 may be configured to be higher in the outward direction from the center of the printed circuit board, and may be disposed symmetrically with respect to the center of the printed circuit board.

If the solder ball 140 is disposed to correspond to the upper surface of a specific conductive pad designed in advance, the chip 130 may be fixed to the conductive pad and fixed at the same time without a separate fixing jig, and the chip 130 may be correctly aligned as it is reflowed. have.

That is, in the reflow process, the chip 130 slips and misalignment is prevented, thereby preventing package defects such as an electrical opening formed in a predesigned wiring or a shorting of wiring to be opened.

The conductive electrode pad 120 may be formed of a central pad 121 having a constant central thickness and a side pad 122 that is thicker than the central pad 121 and formed on both sides of the flat pad. The side pads 122 may be formed higher than the center pads by giving more plating progress time than the center pads.

The center pad 121 is a portion in which the body of the chip 130 is placed, and pads having the same thickness may be aligned at the center of the printed circuit board. The side pad 122 may be coupled to the ends of the chip 130 and may be higher than the center pad. When the formed solder balls are in contact with each other, the solder balls 140 positioned on the center pad 121 may not contact the center pads.

At this time, when the chip 130 is placed on the upper surface of the conductive electrode pad and the reflow process is performed, the solder ball 140 and the solder paste applied to the upper surface of the pad are reduced in thickness while melting, and the solder balls that are not contacted are spaced apart from the upper surface of the center pad. The 140 may contact the center pad 121 and may be electrically connected to each other while the solder is melted.

The side pads 122 may be configured in pairs, and may be formed with steps so that the outside thereof is formed higher. In this case, a plurality of side pads 122 may be formed to form a step, and may be formed to be inclined in the direction from the side to the center portion, and may be formed higher than the center pad center portion.

That is, since the conductive electrode pad 120 may be configured in a concave shape in which the side pad 122 having a high outer side and a center portion is low, the solder ball 140 is positioned at a side pad having a high outer side at one side, and a reflow process As the solder ball 140 flows from the side pad toward the center pad, slippage of the chip 130 may be formed.

However, the solder ball 140 positioned on the conductive electrode pad having the outer side formed high on the other side of the printed circuit board may induce slippage of the chip 130 in the opposite direction, and both forces act in opposite directions to balance the force. Can be fixed.

Therefore, the solder ball 140 may be positioned to correspond to a predetermined conductive electrode pad, and when the reflow process is performed, the chip 130 may be automatically aligned with the flowability of the solder. In addition, since the printed circuit board 100 and the chip 130 may be fixed by the balance of the force to move inside, the chip 130 may be prevented from slipping.

In the solder ball 140, a small solder ball 140 is disposed in a thick conductive electrode pad part, and a large solder ball 140 is disposed in a low conductive electrode pad part to place the chip 130 on the upper surface of the conductive electrode pad. The solder ball 140 may be interposed between the recesses to prevent movement.

As shown in FIG. 4, the solder ball 140 in contact with the center pad has a large diameter, and the solder ball 140 in contact with the side pad has a small diameter to make the sum of the solder pad thickness and the diameter of the solder ball 140 similar. Can be.

At this time, the solder in contact with the center pad has a structure that is inserted into the recessed portion can be prevented from moving the chip 130, it is possible to prevent the slip of the chip 130 even if the reflow process.

In addition, there is no need for a separate jig for fixing the chip 130 during the reflow process, thereby reducing the manufacturing time by shortening the process.

On the other hand, although the electrode pad and the solder ball 140 form a uniform pattern and presented a symmetrical embodiment, the solder ball 140 arrangement may not be constant, so the electrode pad and the solder ball 140 depending on whether the arrangement of the dispersion Symmetrical and asymmetrical structures can be formed.

The side pads 122 may be symmetrical diagonally or symmetrically on the x-axis or y-axis to form symmetry for at least one direction.

When the side pads 122 are symmetrical in all directions, the alignment of the chip 130 may be secured even when the reflow process is performed on the entire printed circuit board 100. However, when the side pad 122 is symmetrical about one of the diagonal, x, or y axes, the symmetry is not balanced in all directions of the chip 130. Slips can be formed.

Accordingly, the alignment of the chip 130 may be formed through partial melting by performing a reflow process on one end of the symmetry, and forming a solder joint on the other end of the symmetry.

That is, when the entire reflow proceeds, the balance may be broken and a slip of the chip 130 may be formed in a specific direction. However, in one direction, the side pads 122 may be kept in balance so that one side may be partially melted and the other side may be combined. After bonding, the remaining regions may be partially melted to prevent slippage of the chip 130.

In addition, the conductive electrode pad 120 may have a concave portion such as a wave shape or a saw tooth, and the solder ball 140 may have a large diameter in the groove portion to be inserted into the groove.

As illustrated in FIGS. 2 and 4, the conductive electrode pad 120 may include a central pad 121 having a constant central thickness and an inclined pad 123 having a thicker side surface. Since the inclination pad 123 has an inclination in which the thickness is uniformly increased in the outward direction from the horizontal pad, the gravity of the solder ball placed at both ends of the inclination pad 123 to lower the inclination surface toward the center pad forms the equilibrium chip 130. ) Can be fixed without moving during solder bonding.

5 is a cross-sectional view of the chip package 200 formed as the printed circuit board and the chip of FIG. 4 undergo a reflow process.

As shown, the printed circuit board includes a build-up layer 110 in which conductor layers and insulating layers are alternately stacked, and conductive electrode pads 120 protrudingly formed on the surface of the insulating layer to form external electrodes. The pad 120 may include a side pad 122 and a center pad 121 having different thicknesses.

In addition, a solder ball 240 electrically connecting the chip 230 and the printed circuit board may be interposed in the conductive electrode pad 220, and the solder ball 240 may have a larger diameter toward the center portion.

Therefore, even when the chip 230 is placed on the conductive electrode pad 220 and undergoes the reflow process, the chip 230 is not shaken, thereby enabling accurate electrical connection to a predesigned pattern.

In addition, the solder bonded portion may further include a molding layer 250 to prevent the inflow of foreign matter.

The foregoing detailed description illustrates the present invention. In addition, the foregoing description merely shows and describes preferred embodiments of the present invention, and the present invention can be used in various other combinations, modifications, and environments. That is, changes or modifications may be made within the scope of the concept of the invention disclosed in this specification, the scope equivalent to the disclosed contents, and / or the skill or knowledge in the art. The above-described embodiments are for explaining the best state in carrying out the present invention, the use of other inventions such as the present invention in other state known in the art, and the specific fields of application and uses of the present invention. Various changes are also possible. Accordingly, the detailed description of the invention is not intended to limit the invention to the disclosed embodiments. Also, the appended claims should be construed to include other embodiments.

100. Printed Circuit Board
110, 210. Buildup Floor
120, 220. Conductive electrode pads
121, 221.Center Pad
122. Side Pads
123, 223. Inclined Pads
130, 230 chips
140, 240. Solder Balls
200. Chip Package
250. Molding layer

Claims (7)

In a printed circuit board in which an insulating layer and a wiring layer are alternately stacked,
A plurality of conductive electrode pads are formed on the surface of the insulating layer,
The plurality of conductive electrode pads may include a center pad positioned at the center of the insulating layer and a plurality of side pads formed at both sides of the center pad.
The heights of the plurality of side pads are greater than the heights of the center pads as they are relatively far from the center pads.
Each of the plurality of side pads includes a first unit pad and a second unit pad coupled to one external terminal and spaced apart from each other.
The height of the first unit pad disposed relatively close to the center pad is smaller than the height of the second unit pad disposed relatively far from the center pad.
Printed circuit board.
delete delete delete In a chip package including a printed circuit board in which an insulating layer and a wiring layer are laminated alternately,
A printed circuit board including a plurality of conductive electrode pads formed on a surface of the insulating layer, wherein the plurality of conductive electrode pads include a center pad positioned at the center of the insulating layer and a plurality of side pads inclined on both sides of the center pad; And
A chip having a solder ball coupled to each of the plurality of conductive electrode pads;
Including;
The heights of the plurality of side pads are greater than the heights of the center pads as they are relatively far from the center pads.
Each of the plurality of side pads includes a first unit pad and a second unit pad coupled to one of the plurality of solder balls and spaced apart from each other.
The height of the first unit pad disposed relatively close to the center pad is less than the height of the second unit pad disposed relatively far from the center pad.
Chip package.
The method of claim 5,
The plurality of solder ball is a chip package diameter decreases toward the side from the center portion of the chip.
delete
KR1020130147314A 2013-11-29 2013-11-29 Printed circuit board and chip package comprising the same KR102029484B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020130147314A KR102029484B1 (en) 2013-11-29 2013-11-29 Printed circuit board and chip package comprising the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020130147314A KR102029484B1 (en) 2013-11-29 2013-11-29 Printed circuit board and chip package comprising the same

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KR20150062544A KR20150062544A (en) 2015-06-08
KR102029484B1 true KR102029484B1 (en) 2019-10-07

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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005217173A (en) * 2004-01-29 2005-08-11 Sharp Corp Printed wiring board, connecting method thereof and manufacturing method thereof
JP2009099637A (en) * 2007-10-15 2009-05-07 Fujitsu Ltd Circuit board, semiconductor device, and manufacturing method of semiconductor device

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH087655Y2 (en) * 1990-04-26 1996-03-04 株式会社ケンウッド Mounting structure for surface mount components
JPH10209207A (en) * 1997-01-28 1998-08-07 Matsushita Electric Ind Co Ltd Method for mounting chip
JP2012169591A (en) 2011-01-24 2012-09-06 Ngk Spark Plug Co Ltd Multilayer wiring board

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005217173A (en) * 2004-01-29 2005-08-11 Sharp Corp Printed wiring board, connecting method thereof and manufacturing method thereof
JP2009099637A (en) * 2007-10-15 2009-05-07 Fujitsu Ltd Circuit board, semiconductor device, and manufacturing method of semiconductor device

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