JP2008311508A - Electronic component package and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a thin electronic component package whose electronic component can be electrically connected absolutely, and a manufacturing method thereof. <P>SOLUTION: An electronic component package 10 of this invention is equipped with a core layer 11 formed by laminating three layers of a core upper layer 11a, a core intermediate layer 11b and a core lower layer 11c, each of which is formed by impregnating resin in a base material and is electrically insulating; core wiring layers 12a and 12b disposed between the insulating layers forming the core layer 11; and an electronic component 30 disposed in a cavity portion 14 formed in the core layer 11. A bonding wire 13 electrically connects the electronic component 30 and the core wiring layer 12a. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to an electronic component package and a manufacturing method thereof, and more particularly, to an electronic component package having a small thickness and in which electronic components are reliably electrically connected and a manufacturing method thereof.

  Conventionally, electronic component packages in which electronic components such as semiconductor chips are mounted are widely used. In this type of electronic component package, in order to mount electronic components and circuit components at a high density, wiring boards are formed in multiple layers.

For example, the electronic component package 100 shown in FIG. 5 includes a core layer 200 having mechanical strength as a skeleton of the electronic component package 100, and insulating layers 201, 202, and 203 are stacked on the upper side of the core layer 200. In addition, an insulating layer 204 is laminated below the core layer 200, and has a multilayer wiring board structure in which a wiring layer is formed between the core layer 200 and the insulating layer and between the insulating layers. In addition, the electronic component 300 is disposed in the cavity 240 formed in the insulating layer 202 laminated on the upper side of the core layer 200. A sealing material 230 is filled in a gap portion of the cavity 240 where the electronic component 300 is disposed.
In addition, a solder resist layer 205 is formed as an insulating layer on the upper side of the insulating layer 203 and the lower side of the insulating layer 204 to protect the multilayer wiring board. Further, a through hole 260 is formed in the core layer 200 so as to penetrate therethrough.

  The electronic component 300 has solder bumps 301. In the electronic component 300, the solder bump 301 is electrically connected to the electrode pad 220 formed on the wiring layer 250. Thus, the electronic component 300 is electrically connected to the wiring layer by so-called flip chip connection.

  This flip-chip connection is a connection technique often used in an electronic component package, for example, as in the examples shown in Patent Documents 1 and 2.

JP 2002-290051 A JP 2002-246505 A

In the electronic component package manufacturing method described above, a procedure for performing flip chip connection between the electronic component 300 and the wiring layer 250 will be described below with reference to FIGS.
First, as shown in FIG. 6A, a multilayer wiring board 400 on which a core layer 200, an insulating layer, and a wiring layer are formed is formed according to a conventional method.

Next, as shown in FIG. 6B, electrode pads 220 are formed on the wiring layer 250 on the upper side of the multilayer wiring board 400.
Next, as shown in FIG. 6C, after the electronic component 300 is placed on the multilayer wiring board 400 so that the solder bumps 301 are in contact with the electrode pads 220 formed on the wiring layer 250, The solder bump 301 is melted to electrically connect the electronic component 300 and the electrode pad 220.

  Here, when the electronic component 300 is placed on the multilayer wiring board 400, extremely high positional accuracy is required. Since the dimensions of both the solder bump 301 and the electrode pad 220 are extremely small, the electronic component 300 is not electrically connected to the multilayer wiring board 400 when the position where the electronic component 300 is placed is shifted. The package will be defective. In the example of flip chip connection shown in FIG. 6, the electronic component 300 is mounted on the multilayer wiring board 400 with the solder bump 301 facing downward, so that the solder bump 301 melts and the electrode pad 220 is correctly connected. It is also very difficult to check whether it has been made during the manufacturing process.

  Further, in the conventional electronic component package shown in FIG. 5, the electronic component 300 is disposed on the upper side of the core layer 200 having a predetermined thickness, and the electronic component 300 is disposed in addition to the thickness of the core layer 200. The thickness of the insulating layer 202 to be added is added, and the thickness of the electronic component package is increased. For example, the insulating layer 202 on which the electronic component 300 is disposed may be at least 150 μm thick.

In addition, there is a limit to reducing the thickness of the core layer 200 having mechanical strength as a skeleton of the electronic component package 100. Depending on the material for forming the core layer 200, for example, when the core layer 200 is formed by impregnating a glass cloth with an epoxy resin, the thickness of the core layer 200 is at least 200 μm. There is a case.
As a result, only the thickness of the core layer 200 and the thickness of the insulating layer 202 on which the electronic component 300 is disposed may be at least 350 μm, which causes a problem that the electronic component package becomes thick.

  Furthermore, in the electronic component package shown in FIG. 5, as described above, since the thickness of the insulating layer 202 is at least 150 μm, the aspect ratio of the via 210 formed through the insulating layer 202 becomes large, and the via 210 Has an elongated shape.

  When a via having a large aspect ratio is formed using, for example, a plating process, the plating solution may not spread throughout the via hole, and the via may break.

  Accordingly, an object of the present invention is to provide an electronic component package and a method for manufacturing the same, which can eliminate the above-described drawbacks of the prior art. In particular, it is an object of the present invention to provide an electronic component package having a small thickness and in which an electronic component is reliably electrically connected, and a method for manufacturing the same.

  In order to solve the above-described problems, an electronic component package according to the present invention includes a core layer formed by laminating a plurality of insulating layers formed by impregnating a base material with a resin, and the insulating layer that forms the core layer. A core wiring layer disposed between each of the layers, and an electronic component disposed in a cavity formed in the core layer. The electronic component and the core wiring layer are electrically connected by a bonding wire. Connected.

  In addition, the present invention provides an insulating core intermediate layer in which the core layer has an intermediate through hole that forms the cavity, and an insulating core that is disposed below the core intermediate layer and to which the electronic component is fixed. A lower layer and an insulating core upper layer that is disposed on the upper side of the core middle layer and has the upper layer through-hole that forms the cavity together with the middle layer through-hole are laminated to form the core upper layer and the core The upper core wiring layer disposed between the core middle layer is formed with a through hole having the same position and size as the middle layer through hole, and the upper layer through hole is formed larger than the middle layer through hole. A portion of the core middle layer around the middle layer through hole extends inward in the layer direction of the upper layer through hole together with the upper core wiring layer, and extends the upper core wiring layer. The protruding part and the electronic component are Which is preferably electrically connected by loading wire.

  In the present invention, a via penetrating the core intermediate layer is formed, and the upper core wiring layer and the lower core wiring layer are electrically connected by the via, and the aspect ratio of the via Is preferably 1 or less.

  In the present invention, it is preferable that a sealing resin is filled in a gap portion of the cavity where the electronic component is disposed.

  In the present invention, it is preferable that one or a plurality of wiring boards are laminated on the upper side or the lower side of the core layer.

  In the present invention, the core substrate is preferably formed by impregnating a base material made of glass cloth with an epoxy resin.

  In addition, the method for manufacturing an electronic component package according to the present invention includes forming a through hole in an insulating core middle layer formed by impregnating a base material with resin and laminating a conductive layer on both surfaces, and the conductive layer A wiring pattern is formed on each of the above, and an insulating core upper layer formed by impregnating a base material with a resin and having a through hole larger than the through hole of the core middle layer is formed on the upper side of the core middle layer. The two through holes are made to coincide with each other so that the wiring pattern around the through hole in the middle layer extends inward in the layer direction of the through hole in the upper layer of the core and is laminated. Then, an insulating core lower layer formed by impregnating a base material with resin is laminated on the lower side of the core middle layer, and the core upper layer, the core middle layer, and the core lower layer are heated and pressurized. And electronic components are placed in the cavity After fixed to the core layer, and the electronic component, and a portion of the wiring pattern extends inward of the core layer of the through-holes, and be electrically connected by a bonding wire.

As described above, according to the electronic component package of the present invention, the thickness is small, and the electronic components are reliably electrically connected.
In addition, according to the method for manufacturing an electronic component package of the present invention, it is possible to form an electronic component package that is thin and can reliably connect electronic components.

  Hereinafter, an electronic component package of the present invention will be described based on a preferred embodiment thereof with reference to the drawings.

  As shown in FIG. 1, the electronic component package 10 of this embodiment is formed by laminating three electrically insulating core upper layers 11a, core intermediate layers 11b, and core lower layers 11c formed by impregnating a base material with resin. The core layer 11, the core wiring layers 12a and 12b disposed between the insulating layers forming the core layer 11, and the electronic component 30 disposed in the cavity 14 formed in the core layer 11, The electronic component 30 and the core wiring layer 12 a are electrically connected by the bonding wire 13. FIG. 1 shows a cross-sectional view of an electronic component package 10.

  In the electronic component package 10 of the present embodiment, as shown in FIG. 1, the core layer 11 is disposed on the lower side of the core middle layer 11b, and the core middle layer 11b having the middle layer through-holes 15b that form the cavity 14. A core lower layer 11c to which the electronic component 30 is fixed and a core upper layer 11a having an upper layer through hole 15a that is disposed on the upper side of the core middle layer 11b and forms the cavity portion 14 together with the middle layer through hole 15b are laminated. Yes.

  In this specification, the direction of the core layer 11 on the core upper layer 11a side is referred to as the upper side of the core layer 11, and the opposite side is referred to as the lower side of the core layer 11. Further, the upper direction of the core layer 11 is referred to as the upper side of the electronic component package 10, and the opposite side is referred to as the lower side of the electronic component package 10.

  The core layer 11 has high rigidity and mechanical strength as a skeleton of the electronic component package 10. Each of the core upper layer 11a, the core middle layer 11b, and the core lower layer 11c has electrical insulation (hereinafter also simply referred to as insulation), and insulates the wiring layers.

  Each of the insulating core upper layer 11a, core intermediate layer 11b, and core lower layer 11c is preferably formed of a material having high rigidity and excellent workability. In the present embodiment, the core upper layer 11a, the core middle layer 11b, and the core lower layer 11c are each formed by impregnating a base material made of glass cloth with a thermosetting epoxy resin.

  In the present embodiment, an upper core wiring layer 12a having a predetermined wiring pattern is disposed between the core upper layer 11a and the core middle layer 11b. Similarly, a lower core wiring layer 12b having a predetermined wiring pattern is disposed between the core lower layer 11c and the core middle layer 11b. Each of the upper core wiring layer 12a and the lower core wiring layer 12b can be formed by a known method such as copper plating.

  Thus, in the present embodiment, the core layer 11 is formed by stacking the core upper layer 11a, the core middle layer 11b, the core lower layer 11c, the upper core wiring layer 12a, and the lower core wiring layer 12b.

  In the core upper layer 11a, an upper layer through hole 15a penetrating the core upper layer 11a is formed in a direction perpendicular to the surface direction. The core middle layer 11b is also formed with a middle layer through hole 15b penetrating through the core middle layer 11b in a direction perpendicular to the surface direction.

  In the present embodiment, the shape of the upper layer through hole 15a in plan view is formed larger than the middle layer through hole 15b, and the center of the upper layer through hole 15a in plan view and the center of the middle layer through hole 15b in plan view are formed. The core upper layer 11a and the core middle layer 11b are laminated so as to substantially coincide with each other.

  Further, as shown in FIG. 1, the upper core wiring layer 12a is formed with through-holes whose positions and dimensions are substantially the same as those of the middle-layer through-hole 15b.

The cavity 14 is formed by connecting the upper layer through hole 15a and the middle layer through hole 15b.
The cavity 14 is a recess having an opening on the core upper layer 11 a side in the core layer 11. As shown in FIG. 1, the cavity 14 has a stepped cross-sectional shape in which the size of the core upper layer 11a is larger than that of the core middle layer 11b.

  The shape of the middle layer through-hole 15b forming the lower portion of the cavity portion 14 is set to a shape that can accommodate the electronic component 30 in consideration of the shape and size of the electronic component 30 embedded therein. . Since the planar view shape of the electronic component 30 mounted on the electronic component package 10 is generally rectangular, the planar view shape of the middle layer through-hole 15b is preferably rectangular according to this, but it is limited to this. Alternatively, a circular shape or a polygonal shape other than a rectangle may be used.

  In this embodiment, the planar view shape of the electronic component 30 is a rectangle, and the middle layer through hole 15b and the upper layer through hole 15a are also formed in a rectangle.

  The electronic component 30 is inserted into the middle layer through hole 15b with the upper surface on which the terminal portion 31 is formed facing the opening side of the cavity portion 14, and the lower surface is the core lower layer The upper surface of 11c and the adhesive layer 22 are bonded and fixed.

The upper end portion where the terminal portion 31 of the electronic component 30 is formed extends upward from the upper surface of the core middle layer 11b and is located inside the upper layer through hole 15a.
It is preferable that the upper surface of the electronic component 30 does not protrude from the upper surface of the core upper layer 11 a in order to accommodate the electronic component 30 in the core layer 11.

The electronic component 30 is, for example, a semiconductor chip, a capacitor, a resistor, an inductor, or the like.
The adhesive layer 22 can be formed by using an adhesive sheet or by applying an adhesive. For example, a die attach film can be used as the adhesive sheet.

  In the electronic component package 10 of the present embodiment, as shown in FIG. 1, the core middle layer 11b around the middle layer through hole 15b has the upper layer through hole 15a together with the upper core wiring layer 12a from the left and right of the upper layer through hole 15a. The extending portion of the upper core wiring layer 12 a and the electronic component 30 are electrically connected by the bonding wire 13.

  More specifically, an electrode pad 20 is formed on the extended portion of the upper core wiring layer 12a, and the bonding wire 13 is electrically connected to the upper core wiring layer 12a with the electrode pad 20 interposed therebetween. Connected. The bonding wire 13 is electrically connected to the terminal portion 31 of the electronic component 30. The electrode pad 20 can be formed by, for example, NiAu plating.

  The wire diameter of the bonding wire 13 is normally about 15 to 25 μm, and the electrode pad 20 and the terminal portion 31 to which the bonding wire 13 is connected have dimensions that allow the bonding wire 13 to be connected. It is a small one. The portion of the upper core wiring layer 12a where the electrode pad 20 is formed has the same size as the electrode pad 20 and is formed in a wiring pattern with a narrow line width.

  Further, in this embodiment, the gap portion of the cavity 14 where the electronic component 30 is disposed is filled with a sealing resin 23 as a sealing material, and the electronic component 30 is fixed to the core layer 11. Yes. As a material for forming the sealing resin, a known material can be used. For example, a resin material used for potting an electronic component package can be used.

  The core layer 11 of the electronic component package 10 is formed with a via 16b penetrating the core middle layer 11b, and the upper core wiring layer 12a and the lower core wiring layer 12b are electrically connected by the via. ing. The via 16b preferably has an aspect ratio of 1 or less. When the aspect ratio of the via 16b is larger than 1 and has an elongated shape, a discontinuous portion of the conductive material is formed when the via is filled with the conductive material, for example, by plating, and the via is disconnected. May occur.

  In the present embodiment, the via hole is formed by laser processing. As for the shape of the via hole, the diameter of the via hole on one side where the laser beam is incident is larger than the diameter of the via hole on the other side. The aspect ratio of the via 16b having such an asymmetric shape is obtained from the average diameter of the via 16b and the length of the via 16b. The same applies to other vias of the electronic component package 10.

  The core upper layer 11a is formed with a via 16a penetrating through the core upper layer 11a. By the via, a wiring layer 19a and an upper core wiring layer 12a arranged adjacent to the upper side of the core upper layer 11a are formed. Electrically connected. The core lower layer 11c is formed with a via 16c penetrating through the core lower layer 11c, and the via layer 19b and the lower core wiring layer 12b disposed adjacent to the lower side of the core lower layer 11c by the via. And are electrically connected.

  In the electronic component package 10 of this embodiment, a plurality of wiring boards are stacked on the upper side and the lower side of the core layer 11. Specifically, on the upper side of the core layer 11, a multilayer wiring board in which a wiring layer 19a, an insulating layer 17a, and a wiring layer 19c are laminated in order from the lower side is laminated. A multilayer wiring board in which a wiring layer 19d, an insulating layer 17b, and a wiring layer 19b are sequentially stacked from the lower side is stacked below the core layer 11.

  In the insulating layer 17a, a via 16d penetrating the insulating layer 17a is formed, and the wiring layer 19c and the wiring layer 19a are electrically connected by the via. Similarly, a via 16e penetrating the insulating layer 17b is formed in the insulating layer 17b, and the wiring layer 19b and the wiring layer 19d are electrically connected by the via.

  The insulating layers 17a and 17b are formed of an insulating material, and can be formed of, for example, an epoxy resin. Further, each of the wiring layers 19a, 19b, 19c, and 19d can be formed by a known method such as copper plating.

  On the upper side of the insulating layer 17a and the wiring layer 19c, a solder resist layer 18a is formed so that only a predetermined portion of the wiring layer 19c to be the external connection terminal 21 is exposed. Similarly, a solder resist layer 18b is formed below the insulating layer 17b and the wiring layer 19d so that only a predetermined portion of the wiring layer 19d to be the external connection terminal 21 is exposed.

The external connection terminal 21 is formed on the above-described portion of the wiring layer 19c exposed from the solder resist layers 18a and 18b by a plating process such as a NiAu plating process.
A semiconductor device or other electronic component package can be electrically connected to the external connection terminal 21. The external connection terminal 21 is connected to an external voltage terminal or ground terminal.

Next, the dimension of each part of the electronic component package 10 described above will be described below.
The total thickness of the core upper layer 11a, the core middle layer 11b, and the core lower layer 11c is preferably at least 100 μm or more in order to ensure the rigidity of the electronic component package 10 and prevent deformation such as warpage.
The thickness of the core upper layer 11a, the core middle layer 11b, or the core lower layer 11c is preferably such that the aspect ratio of vias formed in each layer is 1 or less. For example, when a via hole is formed by laser processing, it is preferably equal to or smaller than the diameter of the laser beam. Specifically, if the diameter of the laser is about 80 μm, the thickness of each of the core upper layer 11a, the core middle layer 11b, and the core lower layer 11c is preferably 80 μm or less.
The lower limit of the thickness of each layer is preferably determined by the rigidity required for the electronic component package 10. In addition, the thicknesses of the core upper layer 11a and the core middle layer 11b are preferably determined as described later depending on the relationship with the dimensions of the electronic component 30.

The length L (see FIG. 1) from the upper surface of the electronic component 30 to the upper surface of the core upper layer 11a is preferably 60 μm or more, and particularly preferably 80 μm or more, so that the loop of the bonding wire 13 is located. It is preferable for securing the space. Therefore, it is preferable to set the thicknesses of the core upper layer 11a and the core middle layer 11b so that the length L falls within the above range.
As shown in FIG. 1, a part of the bonding wire 13 may extend to the insulating layer 17a adjacent to the upper side of the core upper layer 11a.

  Since the thickness of each of the upper core wiring layer 12a and the lower core wiring layer 12b laminated on the core layer 11 is normally 15 to 20 μm, the core upper layer 11a, the core middle layer 11b, and the core lower layer satisfying the above-described dimensions. The thickness of the laminated 11c, the upper core wiring layer 12a and the lower core wiring layer 12b can be at most 200 μm if the thickness of the electronic component 30 is 80 μm or less.

  In the bonding wire 13, it is preferable that the size of the loop formed by the wire is small from the viewpoint of reducing the thickness of the cavity portion 14 and thus reducing the thickness of the electronic component package 10. As a method for reducing the loop of the bonding wire 13, for example, a low loop type wire bonding technique can be used. By using the low-loop type wire bonding technique, the height of the wire loop can be reduced to 100 μm or less.

  According to the electronic component package 10 of this embodiment described above, the electronic component 30 is disposed in the core layer 11, and the upper core wiring layer 12 a and the lower core wiring layer 12 b are disposed in the core layer 11. Therefore, the thickness of the electronic component package 10 can be reduced. In addition, the electronic component 30 disposed inside the core layer 11 having high rigidity and hardly deformed is protected by the core layer 11.

  Further, since the upper core wiring layer 12a and the lower core wiring layer 12b are sandwiched between the core middle layer 11b having high rigidity and the core upper layer 11a or the core lower layer 11c, the upper core wiring layer 12a and the lower core wiring layer 12b The deformation of the core wiring layer 12b is prevented. Therefore, even if a wiring pattern having a thin line width such that the electrode pad 20 is formed is formed on the upper core wiring layer 12a or the lower core wiring layer 12b, the wiring pattern portion is prevented from being disconnected due to deformation. The Further, since the portion of the upper core wiring layer 12a where the electrode pad 20 is formed is also laminated on the core middle layer 11b, disconnection is similarly prevented.

  Since the electronic component 30 is electrically connected to the upper core wiring layer 12a, which is difficult to deform, by the bonding wire 13, the reliability of the electrical connection between the electronic component 30 and the wiring layer 12a is high.

  In addition, the vias 16a and 16b formed through the core upper layer 11a and the core middle layer 11b in which the electronic component 24 is disposed have a high aspect ratio, and are not easily disconnected.

  Next, an example of a method for manufacturing the electronic component package of the present invention described above will be described below with reference to FIGS.

  First, as shown in FIG. 2A, a core composite 50 in which conductive layers 40a and 40b are formed on both surfaces of an electrically insulating plate-like core middle layer 11b is prepared. The core complex 50 can be formed by a known method. The core middle layer 11b can be formed into a plate shape by, for example, impregnating a base material made of glass cloth with a thermosetting epoxy resin and thermosetting it. In addition, the conductive layers 40a and 40b can be formed by forming a film on the core middle layer 11b by sputtering or copper plating. Alternatively, copper foil may be attached to the core middle layer 11b.

Next, via holes are formed in the core intermediate layer 11b, the conductive layer 40a located on the upper side of the core intermediate layer 11b, and the conductive layer 40b located on the lower side by laser processing so as to penetrate the via 16b. In the example shown in FIG. 2B, since the laser beam is incident from the conductive layer 40a side, the via hole has an asymmetric shape with a large diameter on the conductive layer 40a side.
Further, as a method for forming a via hole, drilling may be used in addition to laser processing.

  Next, the via hole formed as described above is wired by a plating process such as a copper plating process to form the via 16b. The via 16b is formed so as to penetrate the core middle layer 11b and the conductive layers 40a and 40b.

  Next, as shown in FIG. 2C, the electrode pad 20 is formed on the upper side of the conductive layer 40a by a plating process at a position where the electrode pad 20 is to be formed. As the plating treatment, for example, NiAu plating treatment can be used.

  Next, as shown in FIG. 2D, the middle layer through-hole 15b is formed in the core middle layer 11b. The middle layer through hole 15b can be formed at a predetermined position by using a device such as a router. The shape of the middle layer through hole 15b is preferably set so that the electronic component 30 can be accommodated in consideration of the shape and size of the electronic component 30 embedded therein. In this embodiment, the planar view shape of the electronic component 30 is a rectangle, and the planar view shape of the middle layer through hole 15b is also formed in a rectangle.

  Next, as shown in FIG. 2E, a predetermined wiring pattern is formed on the conductive layer 40a to produce the upper core wiring layer 12a. Specifically, a photosensitive resist is applied to the surface of the conductive layer 40a, the photosensitive resist is exposed and developed to form a resist pattern, and the exposed portion of the conductive layer 40a that is not covered with the resist pattern is removed. Thus, the upper core wiring layer 12a having a predetermined wiring pattern can be formed. At this time, the electrode pad 20 is left. Similarly, a predetermined wiring pattern is formed on the conductive layer 40b to produce the lower core wiring layer 12b.

  Next, as shown in FIG. 3 (f), an electrically insulating core upper layer 11a having a conductive layer 40c laminated on one surface and having an upper layer through hole 15a is formed on the upper side of the core middle layer 11b. The layer 40c is laminated facing upward. The core upper layer 11a is formed by impregnating a glass cloth as a base material with a thermosetting epoxy resin and has a rigidity sufficient to maintain a plate-like form, but is still completely thermoset. It is in a non-existent state, has flexibility, and has a sticky surface. The conductive layer 40c can be formed in the same manner as the conductive layers 40a and 40b.

  Further, the core upper layer 11a has an upper layer through hole 15a having a larger dimension in plan view than the middle layer through hole 15b of the core middle layer 11b. The plan view shape of the upper layer through-hole 15a is formed in the same rectangle as the middle layer through-hole 15b. The upper layer through hole 15a can be formed by the same method as the middle layer through hole 15b.

  More specifically, as shown in FIG. 3 (f), the core upper layer 11a is arranged on the upper side of the core middle layer 11b, and the wiring pattern portion of the upper core wiring layer 12a around the middle layer through hole 15b of the core middle layer 11b is The two through holes 15a and 15b are made to coincide with each other so as to extend inward in the layer direction of the upper layer through hole 15a of the upper layer 15a, and the cavity portion 14 is formed and laminated. In the present embodiment, the core upper layer 11a and the core middle layer 11b are stacked such that the centers of the upper layer through hole 15a and the middle layer through hole 15b coincide with each other. As a result, as shown in FIG. 3F, the wiring pattern portion of the upper core wiring layer 12a extends inward from the left and right sides of the upper layer through hole 15a.

  Next, an electrically insulating core lower layer 11c having a conductive layer 40d laminated on one surface is laminated below the core middle layer 11b with the conductive layer 40d facing downward. The core lower layer 11c is formed by impregnating a glass cloth, which is a base material, with a thermosetting epoxy resin, and has a rigidity sufficient to maintain a plate-like form, but has not been completely thermoset yet. It is a state, has flexibility, and has a sticky surface. The conductive layer 40d can be formed in the same manner as the conductive layers 40a and 40b.

  Next, the core upper layer 11a, the upper core wiring layer 12a, the core middle layer 11b, the lower core wiring layer 12b, and the core lower layer 11c are integrated by heating and pressing to form the core layer 11. By this heat treatment, the thermosetting epoxy resin forming the core upper layer 11a and the core lower layer 11c is completely cured. Thus, it is preferable to form the core layer 11 by using the epoxy resin in an incompletely cured state so that the core upper layer 11a and the core lower layer 11c themselves function as an adhesive layer.

  Next, as shown in FIG. 3G, the adhesive layer 22 is formed on the core lower layer 11c exposed at the bottom of the middle layer through-hole 15b, and the electronic component 30 and the terminal portion 31 thereof are formed. The surface is inserted into the middle layer through-hole 15 b toward the opening side of the cavity portion 14, disposed in the cavity portion 14, and bonded and fixed to the core lower layer 11 c through the adhesive layer 22.

  Next, the electronic component 30 and the wiring pattern portion of the upper core wiring layer 12 a extending inward of the upper layer through hole 15 a of the core upper layer 11 a are electrically connected by the bonding wires 13. Specifically, the bonding wire 13 is electrically connected to the wiring pattern portion of the upper core wiring layer 12 a via the electrode portion 20. Further, the bonding wire 13 is electrically connected to the terminal portion 31 of the electronic component 30. The bonding wire 13 is preferably formed using a low loop type wire bonding technique.

  There may be a deviation in the position where the electronic component 30 is disposed in the cavity portion 14, but if a wire bonding technique is used, the position of the electronic component 30 disposed in the cavity portion 14 is considered and the electrode pad 20 is disposed. And the terminal portion 31 can be electrically connected by the bonding wire 13.

  Next, it is preferable to inspect the electrical connection between the bonding wire 13 and the electrode pad 20 and the terminal portion 31 of the electronic component 30. Since the electronic component 30 is arranged with the terminal portion 31 facing upward and the terminal portion 31 is exposed, it is easy to inspect the terminal portion 31. Similarly, since the electrode pad 20 is formed on the portion of the upper core wiring layer 12a extending inward of the upper layer through-hole 15a, the electrode pad 20 is in an exposed state. It is also easy to inspect. Then, the defective connection is removed from the process.

  Next, as shown in FIG. 3 (h), the liquid sealing resin 23 is filled in the gap portion of the cavity 14 where the electronic component 30 is disposed, and then the sealing resin 23 is solidified. Since the sealing resin 23 is a liquid having a low viscosity at the time of filling, the cavity 14 can be filled without deforming the loop shape of the bonding wire 13.

  Next, as shown in FIG. 4 (i), a via 16a that penetrates the core upper layer 11a and electrically connects the conductive layer 40c and the wiring layer 12a is formed. Similarly, a via 16c that penetrates the core lower layer 11c and electrically connects the conductive layer 40d and the wiring layer 12b is formed. The via 16a and the via 16c can be formed in the same manner as the via 16b.

  Next, as shown in FIG. 4J, a predetermined wiring pattern is formed on each of the conductive layer 40c and the conductive layer 40d, and the wiring layer 19a and the wiring layer 19b are manufactured. The wiring layer 19a and the wiring layer 19b can be formed in the same manner as the wiring layers 40a and 40b.

Next, the insulating layer 17a is formed above the cavity 14, the core upper layer 11a, and the wiring layer 19a filled with the sealing resin 23. The insulating layer 17a can be formed by laminating a thermosetting resin sheet or applying a thermosetting resin solution and then solidifying by heating. When a thermosetting resin solution is applied, the bonding wire 13 can be embedded in the insulating layer 17a as shown in FIG. Further, the use of a method of applying a thermosetting resin solution absorbs unevenness of the wiring layer 19a, the sealing resin 23, or the core upper layer 11a, and can form a flat surface above the insulating layer 17a. To preferred.
As the thermosetting resin sheet or resin solution, a thermosetting epoxy resin can be used.
Similarly, an insulating layer 17b is formed below the core lower layer 11c and the wiring layer 19b.

  Next, a conductive layer is formed on the upper side of the insulating layer 17a, and a wiring pattern is formed on the conductive layer, whereby the wiring layer 19c is manufactured. This conductive layer can be formed in the same manner as the conductive layers 40a and 40b. Similarly, a wiring layer 19d is formed below the insulating layer 17b.

  Next, a via 16d that penetrates the insulating layer 17a and electrically connects the wiring layer 19c and the wiring layer 19a is formed. Similarly, a via 16e that penetrates the insulating layer 17b and electrically connects the wiring layer 19b and the wiring layer 19d is formed. The via 16d and the via 16e can be formed in the same manner as the via 16b.

  Thereafter, a solder resist layer 18a is formed on the insulating layer 17a and the wiring layer 19c so as to expose only the portion where the external connection terminal 21 is located. A connection terminal 21 is formed. For example, NiAu plating can be used for this plating process. Similarly, the solder resist layer 18b and the external connection terminal 21 are formed below the insulating layer 17b and the wiring layer 19d, and the electronic component package 10 shown in FIG. 1 is obtained.

According to this embodiment described above, the electrode pad 20 and the terminal portion 31 can be reliably electrically connected by the bonding wire 13 in consideration of the position of the electronic component 30 disposed in the cavity portion 14. . In addition, when the electronic component 30 is arranged in the cavity portion 14, high arrangement accuracy is not required, so that the electronic component package 10 can be easily manufactured.
Further, by inspecting the electrical connection between the bonding wire 13 and the electrode pad 20 and the terminal part 31 of the electronic component 30, defective products can be removed during the process, so that the electronic component 40 can be reliably Connected electronic component package 10 can be manufactured.

The electronic component package and the manufacturing method thereof according to the present invention are not limited to the above-described embodiments or embodiments, and can be appropriately changed without departing from the spirit of the present invention.
For example, in the above-described embodiment, only one electronic component 30 is mounted. However, two or more cavities may be formed, and the electronic components may be arranged and fixed in the respective cavities.

  Further, in the above-described embodiment, the wiring board is laminated on each of the upper side and the lower side of the core layer 11, but the wiring board may be laminated only on the upper side or the lower side of the core layer 11. Further, only one wiring board may be stacked on the upper side or the lower side of the core layer 11.

  In the above-described embodiment, the multilayer wiring board including the wiring layer 19a, the insulating layer 17a, and the wiring layer 19c is laminated on the upper side of the core layer 11, but further on the upper side of the core layer 11, A multilayer wiring board composed of a large number of insulating layers and wiring layers may be laminated. The same applies to the multilayer wiring board laminated below the core layer 11.

  Moreover, although thermosetting resin was used in embodiment and the embodiment mentioned above, you may use photocurable resin.

FIG. 1 is a cross-sectional view showing an embodiment of an electronic component package of the present invention. FIG. 2 is a diagram for explaining an embodiment of a method for manufacturing the electronic component package of FIG. FIG. 3 is a diagram for explaining an embodiment of a method for manufacturing the electronic component package of FIG. FIG. 4 is a diagram for explaining an embodiment of the method for manufacturing the electronic component package of FIG. FIG. 5 is a cross-sectional view of a conventional electronic component package. FIG. 6 is a diagram for explaining a main part of the method of manufacturing the electronic component package of FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Electronic component package 11 Core layer 11a Core upper layer 11b Core middle layer 11c Core lower layer 12a Upper core wiring layer 12b Lower core wiring layer 13 Bonding wire 14 Cavity 15a Upper layer through-hole 15b Middle layer through-hole 16a, 16b, 16c, 16d, 16e Via 17a, 17b Insulating layer 18a, 18b Solder resist layer 19a, 19b, 19c, 19d Wiring layer 20 Electrode pad 21 External connection terminal 22 Adhesive layer 23 Sealant 30 Electronic component 40a, 40b, 40c, 40d Conductive layer 50 Core composite body

Claims (7)

A core layer formed by laminating a plurality of insulating layers formed by impregnating a base material with a resin;
A core wiring layer disposed between each of the insulating layers forming the core layer;
An electronic component disposed in a cavity formed in the core layer,
The electronic component package, wherein the electronic component and the core wiring layer are electrically connected by a bonding wire. An insulating core intermediate layer having an intermediate through hole forming the cavity, an insulating core lower layer disposed below the core intermediate layer to which the electronic component is fixed, and the core intermediate layer; And an insulating core upper layer having an upper layer through hole that forms the hollow portion together with the middle layer through hole.
In the upper core wiring layer disposed between the core upper layer and the core middle layer, a through hole is formed that has the same position and dimensions as the middle layer through hole,
The upper layer through hole is formed to be larger than the middle layer through hole, and the portion of the core middle layer around the middle layer through hole is inward in the layer direction of the upper layer through hole together with the upper core wiring layer. 2. The electronic component package according to claim 1, wherein the electronic component package is extended toward the upper core wiring layer and the electronic component is electrically connected by a bonding wire.   Vias penetrating the core middle layer are formed, and the upper core wiring layer and the lower core wiring layer are electrically connected by the vias, and an aspect ratio of the via is 1 or less The electronic component package according to claim 2.   4. The electronic component package according to claim 1, wherein a sealing material is filled in a gap portion of the cavity where the electronic component is disposed. 5.   5. The electronic component package according to claim 1, wherein one or a plurality of wiring boards are stacked on the upper side or the lower side of the core layer. 6.   The electronic component package according to any one of claims 1 to 5, wherein the core substrate is formed by impregnating a base material made of glass cloth with an epoxy resin. A through-hole is formed in an insulating core middle layer formed by impregnating a base material with a resin and a conductive layer laminated on both sides,
Forming a wiring pattern on each of the conductive layers;
On the upper side of the core middle layer, an insulating core upper layer formed by impregnating a base material with a resin and having a through hole larger than the through hole of the core middle layer is formed around the through hole of the core middle layer. Two wiring holes are aligned with each other so that the wiring pattern extends inward in the layer direction of the through hole in the upper layer of the core, and a cavity is formed and laminated,
Under the core middle layer, an insulating core lower layer formed by impregnating a base material with resin is laminated,
The core upper layer, the core middle layer, and the core lower layer are integrated by heating and pressing,
After the electronic component is disposed in the cavity and fixed to the core lower layer,
A method of manufacturing an electronic component package, comprising: electrically connecting the electronic component and a portion of the wiring pattern extending inward of a through hole in the core upper layer by a bonding wire.

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