JP4228926B2 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
JP4228926B2
JP4228926B2 JP2004022222A JP2004022222A JP4228926B2 JP 4228926 B2 JP4228926 B2 JP 4228926B2 JP 2004022222 A JP2004022222 A JP 2004022222A JP 2004022222 A JP2004022222 A JP 2004022222A JP 4228926 B2 JP4228926 B2 JP 4228926B2
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JP
Japan
Prior art keywords
solder
lead frame
semiconductor chip
semiconductor device
thickness
Prior art date
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Expired - Fee Related
Application number
JP2004022222A
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Japanese (ja)
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JP2005129886A (en
Inventor
良成 池田
克彦 吉原
祐二 飯塚
英司 望月
岳志 藤井
満男 山下
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Fuji Electric Co Ltd
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Fuji Electric Device Technology Co Ltd
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Publication date
Application filed by Fuji Electric Device Technology Co Ltd filed Critical Fuji Electric Device Technology Co Ltd
Priority to JP2004022222A priority Critical patent/JP4228926B2/en
Publication of JP2005129886A publication Critical patent/JP2005129886A/en
Application granted granted Critical
Publication of JP4228926B2 publication Critical patent/JP4228926B2/en
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Description

この発明は、半導体チップと他の構成部材とを半田により接合した半導体装置に関する。 This invention relates to a semiconductor chip and other components in the semiconductor equipment joined by soldering.

従来、ＩＧＢＴモジュールなどのパワー半導体装置では、ケース構造と呼ばれるパッケージ構造が主流である。このケース構造について、図１７および図１８を参照しながら説明する。図１７は、ケース構造の半導体装置のオープンサンプル状態を示す平面図であり、図１８は、図１７の切断線Ａ−Ａにおける断面図である。なお、図１７では、ケースおよび外部電極用端子は省略されている。   Conventionally, in a power semiconductor device such as an IGBT module, a package structure called a case structure has been mainstream. The case structure will be described with reference to FIGS. 17 and 18. 17 is a plan view showing an open sample state of a semiconductor device having a case structure, and FIG. 18 is a cross-sectional view taken along a cutting line AA in FIG. In FIG. 17, the case and the external electrode terminal are omitted.

図１７および図１８に示すように、ＩＧＢＴなどの半導体素子を有する半導体チップ１の裏面は、半田接合層２を介して絶縁基板３の表面の回路パターン部４に接合されている。絶縁基板３の裏面は、半田接合層５を介してヒートシンク６の表面に接合されている。ヒートシンク６の周縁には、ケース７が接着されている。ケース７の内側には、外部電極用端子８が設けられている。外部電極用端子８と絶縁基板表面の回路パターン部４とは、アルミニウム（Ａｌ）製のワイヤ９により電気的に接続されている。また、半導体チップ１の表面に設けられた図示しない電極（以下、表面電極とする）と回路パターン部４とは、アルミニウム製のワイヤ１０により電気的に接続されている。ケース７とヒートシンク６との間には、ゲル１１が封入されている。   As shown in FIGS. 17 and 18, the back surface of the semiconductor chip 1 having a semiconductor element such as IGBT is bonded to the circuit pattern portion 4 on the surface of the insulating substrate 3 via the solder bonding layer 2. The back surface of the insulating substrate 3 is bonded to the surface of the heat sink 6 via the solder bonding layer 5. A case 7 is bonded to the periphery of the heat sink 6. An external electrode terminal 8 is provided inside the case 7. The external electrode terminal 8 and the circuit pattern portion 4 on the surface of the insulating substrate are electrically connected by an aluminum (Al) wire 9. In addition, an electrode (not shown) (hereinafter referred to as a surface electrode) provided on the surface of the semiconductor chip 1 and the circuit pattern portion 4 are electrically connected by an aluminum wire 10. A gel 11 is sealed between the case 7 and the heat sink 6.

近時、上述したケース構造の半導体装置では、電流密度を低減させて信頼性の向上を図るために、半導体チップの表面電極と絶縁基板表面の回路パターン部とをリードフレームにより電気的に接続する構造が提案されている。この構造では、半導体チップの表面電極にニッケル（Ｎｉ）および金（Ａｕ）が成膜される。そして、リードフレームの一端と回路パターン部との接合、およびリードフレームの他端と半導体チップの表面電極との接合には、半田が用いられる（たとえば、特許文献１参照。）。   Recently, in the semiconductor device having the above-described case structure, in order to reduce the current density and improve the reliability, the surface electrode of the semiconductor chip and the circuit pattern portion on the surface of the insulating substrate are electrically connected by the lead frame. A structure has been proposed. In this structure, nickel (Ni) and gold (Au) are deposited on the surface electrode of the semiconductor chip. Solder is used for joining one end of the lead frame to the circuit pattern portion and joining the other end of the lead frame to the surface electrode of the semiconductor chip (see, for example, Patent Document 1).

ところで、金属板の表面に絶縁基板の裏面を半田により接合する際に、金属板と絶縁基板との間の半田接合層の厚さを一定にするため、金属板と絶縁基板との間にワイヤを挟んだ状態で半田を溶かして固まらせる方法が公知である（たとえば、特許文献２参照。）。   By the way, when the back surface of the insulating substrate is bonded to the surface of the metal plate by soldering, a wire is provided between the metal plate and the insulating substrate in order to make the thickness of the solder bonding layer between the metal plate and the insulating substrate constant. A method is known in which solder is melted and solidified in a state of sandwiching (see, for example, Patent Document 2).

特開２００１−３３２６６４号公報JP 2001-332664 A 特開平１１−１８６３３１号公報JP-A-11-186331

しかしながら、一旦溶けた半田が固まったときに、半田接合層の厚さが所定の厚さよりも薄くなったり、半田接合層の上の部材が傾いて半田接合層の厚さが均一でなくなることがある。そうなると、半田による接合部に要求される電気的な性能や熱的な性能を確保することが困難になる。また、半導体装置を実際に使用したときの温度負荷の繰り返しによって半田接合層に生じる剪断応力が過大となり、早期にクラックが発生してしまうため、半田による接合部の長期信頼性を確保することが困難である。   However, once the melted solder is solidified, the thickness of the solder joint layer may be thinner than a predetermined thickness, or the member on the solder joint layer may be inclined and the thickness of the solder joint layer may not be uniform. is there. If it becomes so, it will become difficult to ensure the electrical performance and thermal performance which are requested | required of the junction part by solder. In addition, since the shear stress generated in the solder joint layer due to repeated temperature load when the semiconductor device is actually used becomes excessive and cracks occur early, it is possible to ensure long-term reliability of the solder joint. Have difficulty.

そこで、上記特許文献２ではワイヤをスペーサとして用いることによって、半田接合層の厚さが均一で所望の厚さとなるようにしている。しかし、特許文献２に開示されているように半田接合後に金属板と絶縁基板との間のワイヤの断面形状を楕円形状で安定させることは困難である。そのため、実際にはワイヤの部分からクラックが発生する可能性が高い。   Therefore, in Patent Document 2, a wire is used as a spacer so that the thickness of the solder bonding layer is uniform and a desired thickness. However, as disclosed in Patent Document 2, it is difficult to stabilize the cross-sectional shape of the wire between the metal plate and the insulating substrate in an elliptical shape after soldering. Therefore, there is a high possibility that a crack will actually occur from the wire portion.

この発明は、上述した従来技術による問題点を解消するため、半導体チップと他の構成部材との半田による接合の信頼性を高めること、または半導体チップ以外の構成部材同士の半田による接合の信頼性を高めることによって、長期信頼性の高い半導体装置を提供することを目的とする。 In order to solve the above-described problems caused by the prior art, the present invention increases the reliability of bonding between the semiconductor chip and other components by soldering, or the reliability of bonding between components other than the semiconductor chip by soldering. by increasing, it shall be the object to provide a semiconductor device having high long-term reliability.

上述した課題を解決し、目的を達成するため、請求項１の発明にかかる半導体装置は、半導体チップの表面に設けられた電極と、該電極の上まで延びるリードフレームとが、１００μｍ以上の厚さの半田接合層を介して接合されており、前記リードフレームのビッカース硬さは４０以下であることを特徴とする。 In order to solve the above-described problems and achieve the object, a semiconductor device according to the invention of claim 1 has an electrode provided on the surface of a semiconductor chip and a lead frame extending above the electrode having a thickness of 100 μm or more. The lead frame has a Vickers hardness of 40 or less .

この請求項１の発明によれば、半導体チップとリードフレームとの線膨張係数差に起因して半田接合層に発生する熱応力と歪みが低減されるので、半導体チップとリードフレームとの接合の信頼性を高めることができる。また、半導体チップとリードフレームとの線膨張係数差に起因して半田接合層に発生する熱応力と歪みがより一層低減されるので、半導体チップとリードフレームとの接合の信頼性をさらに高めることができる。リードフレームのビッカース硬さを４０以下にするには、リードフレームの焼き鈍しをおこなえばよい。たとえば、リードフレームの材料に銅を選択した場合、８００℃以下で焼き鈍しをおこなって、ビッカース硬さを４０以下とすればよく、同じくアルミニウムを選択した場合は４００℃程度で焼き鈍しをおこなって、ビッカース硬さを４０以下とすればよい。リードフレームには他の金属（たとえばインジウム、金など）も適用可能であり、所望のビッカース硬さを得るべく所定の温度で焼き鈍しをおこなうようにするとよい。 According to the first aspect of the present invention, since the thermal stress and strain generated in the solder bonding layer due to the difference in linear expansion coefficient between the semiconductor chip and the lead frame are reduced, the bonding between the semiconductor chip and the lead frame is reduced. Reliability can be increased. In addition, since the thermal stress and strain generated in the solder bonding layer due to the difference in linear expansion coefficient between the semiconductor chip and the lead frame are further reduced, the reliability of the bonding between the semiconductor chip and the lead frame is further enhanced. Can do. In order to reduce the Vickers hardness of the lead frame to 40 or less, the lead frame may be annealed. For example, if copper is selected as the lead frame material, annealing should be performed at 800 ° C. or lower and the Vickers hardness should be 40 or lower. Similarly, if aluminum is selected, annealing is performed at about 400 ° C. The hardness may be 40 or less. Other metals (for example, indium, gold, etc.) can also be applied to the lead frame, and it is preferable to perform annealing at a predetermined temperature in order to obtain a desired Vickers hardness.

また、請求項２の発明にかかる半導体装置は、請求項１に記載の発明において、少なくとも前記リードフレームの表面はニッケルでできていることを特徴とする。 According to a second aspect of the present invention, in the semiconductor device according to the first aspect , at least the surface of the lead frame is made of nickel.

この請求項２の発明によれば、リードフレームを構成する銅（Ｃｕ）と半田との合金層が成長するのが抑制されるので、半導体チップとリードフレームとの接合の信頼性をさらに高めることができる。リードフレームの表面をニッケルにするには、リードフレームの表面にニッケルめっきを施せばよい。 According to the second aspect of the present invention, since the growth of the alloy layer of copper (Cu) and solder constituting the lead frame is suppressed, the reliability of the bonding between the semiconductor chip and the lead frame is further enhanced. Can do. In order to make the surface of the lead frame nickel, the surface of the lead frame may be plated with nickel.

また、請求項３の発明にかかる半導体装置は、裏面にヒートシンクが接合されていない支持基板の表面に半導体チップが固定されており、該半導体チップの表面電極にリードフレームが半田により接合された半導体装置であって、半導体チップの表面に設けられた電極と、該電極の上まで延びるリードフレームとが、５０μｍ以上の厚さの半田接合層を介して接合されており、前記リードフレームのビッカース硬さは４０以下であることを特徴とする。 Moreover, such a semiconductor device in the invention of claim 3, the semiconductor chip on the surface of the supporting substrate heatsink on the back surface is not bonded and is fixed to the front electrode of the semiconductor chip lead frame are joined by soldering a semiconductor In the apparatus, an electrode provided on a surface of a semiconductor chip and a lead frame extending above the electrode are bonded via a solder bonding layer having a thickness of 50 μm or more, and the Vickers hardness of the lead frame is The length is 40 or less .

また、請求項４の発明にかかる半導体装置は、請求項３に記載の発明において、前記半導体チップの表面電極には、ニッケルおよび金よりなる膜が成膜されており、前記半田は、Ｓｎ−Ａｇ系の半田であることを特徴とする。 According to a fourth aspect of the present invention, there is provided the semiconductor device according to the third aspect , wherein a film made of nickel and gold is formed on the surface electrode of the semiconductor chip, and the solder is Sn- It is an Ag-based solder.

この請求項３または４の発明によれば、半導体チップとリードフレームとの線膨張係数差に起因して半田接合層に発生する熱応力と歪みが低減されるので、半導体チップとリードフレームとの接合の信頼性を高めることができる。 According to the third or fourth aspect of the present invention, the thermal stress and strain generated in the solder joint layer due to the difference in linear expansion coefficient between the semiconductor chip and the lead frame are reduced. The reliability of joining can be improved.

本発明にかかる半導体装置によれば、半導体チップとリードフレームとの線膨張係数差に起因して半田接合層に発生する熱応力と歪みが低減されるので、半導体チップとリードフレームとの接合の信頼性（疲労寿命）を高めることができる。したがって、半導体装置の長期信頼性を高めることができるという効果を奏する。   According to the semiconductor device of the present invention, since the thermal stress and strain generated in the solder bonding layer due to the difference in linear expansion coefficient between the semiconductor chip and the lead frame are reduced, the bonding between the semiconductor chip and the lead frame is reduced. Reliability (fatigue life) can be improved. Therefore, there is an effect that the long-term reliability of the semiconductor device can be improved.

以下に添付図面を参照して、この発明の好適な実施の形態を詳細に説明する。   Exemplary embodiments of the present invention will be described below in detail with reference to the accompanying drawings.

（実施の形態１）
図２は、本発明の実施の形態１にかかる半導体装置の、図１７の切断線Ａ−Ａに相当する断面における構成を示す断面図である。図２に示すように、半導体チップ１の裏面は、半田接合層２を介して、支持基板である絶縁基板３の表面に設けられた回路パターン部４に接合されている。半導体チップ１の表面には、図示しない表面電極が設けられている。この表面電極には、たとえば無電解めっき法によりニッケルおよび金が成膜されている。これは、後述するように表面電極とリードフレーム２１との半田接合を容易にするためである。 (Embodiment 1)
FIG. 2 is a cross-sectional view showing a configuration of the semiconductor device according to the first embodiment of the present invention in a cross section corresponding to the cutting line AA of FIG. As shown in FIG. 2, the back surface of the semiconductor chip 1 is bonded to a circuit pattern portion 4 provided on the surface of an insulating substrate 3 as a support substrate via a solder bonding layer 2. A surface electrode (not shown) is provided on the surface of the semiconductor chip 1. The surface electrode is formed with nickel and gold, for example, by electroless plating. This is to facilitate solder bonding between the surface electrode and the lead frame 21 as will be described later.

リードフレーム２１の一端は、半田接合層２２を介して回路パターン部４に接合されている。リードフレーム２１の他端は、半田接合層２３を介して半導体チップ１の表面電極に接合されている。絶縁基板表面の回路パターン部４と半導体チップ１の表面電極とは、リードフレーム２１により電気的に接続されている。リードフレーム２１は、電気配線に使用されるため、電気抵抗が低く、かつ高熱伝導性を有する銅やアルミニウムなどの金属でできているのが好ましい。   One end of the lead frame 21 is bonded to the circuit pattern portion 4 via the solder bonding layer 22. The other end of the lead frame 21 is bonded to the surface electrode of the semiconductor chip 1 via the solder bonding layer 23. The circuit pattern portion 4 on the surface of the insulating substrate and the surface electrode of the semiconductor chip 1 are electrically connected by a lead frame 21. Since the lead frame 21 is used for electrical wiring, the lead frame 21 is preferably made of a metal such as copper or aluminum having low electrical resistance and high thermal conductivity.

絶縁基板３の裏面は、半田接合層５を介してヒートシンク６の表面に接合されている。ヒートシンク６の周縁には、樹脂成型されたケース７が接着されている。ケース７の内側には、外部電極用端子８が設けられている。外部電極用端子８と絶縁基板表面の回路パターン部４とは、アルミニウム製のワイヤ９により電気的に接続されている。半導体チップ１、絶縁基板３およびワイヤ９を水分や湿気や塵から保護するために、ケース７とヒートシンク６との間には、ゲル１１が封入されている。   The back surface of the insulating substrate 3 is bonded to the surface of the heat sink 6 via the solder bonding layer 5. A resin molded case 7 is bonded to the periphery of the heat sink 6. An external electrode terminal 8 is provided inside the case 7. The external electrode terminal 8 and the circuit pattern portion 4 on the surface of the insulating substrate are electrically connected by an aluminum wire 9. A gel 11 is enclosed between the case 7 and the heat sink 6 in order to protect the semiconductor chip 1, the insulating substrate 3, and the wire 9 from moisture, moisture, and dust.

図１は、図２に示す構成の半導体装置の半導体チップ１とリードフレーム２１との接合部を拡大して示す断面図である。図１に示すように、半導体チップ１とリードフレーム２１との接合部である半田接合層２３の厚さは、１００μｍ以上であるのが適当である。その理由について図３〜図５を用いて説明する。   FIG. 1 is an enlarged cross-sectional view showing a joint portion between the semiconductor chip 1 and the lead frame 21 of the semiconductor device having the configuration shown in FIG. As shown in FIG. 1, it is appropriate that the thickness of the solder bonding layer 23 which is a bonding portion between the semiconductor chip 1 and the lead frame 21 is 100 μm or more. The reason will be described with reference to FIGS.

図３は、半導体チップ１とリードフレーム２１とを接合する半田接合層２３の歪み（相当塑性歪み）と、その半田接合層２３の厚さとの関係を示す特性図である。なお、この図３に示す特性図は、半田接合層２３としてＳｎ（錫）−３．５Ａｇ（銀）半田を用い、リードフレーム２１のビッカース硬さ（Ｈｖ）を６０として、−４０〜１２５℃の温度範囲での温度サイクル試験を模擬したＦＥＭ（有限要素法）解析により得られた結果である。図３より、半田接合層２３が厚いほど、半田接合層２３の発生歪みが低減することがわかる。   FIG. 3 is a characteristic diagram showing the relationship between the strain (equivalent plastic strain) of the solder joint layer 23 that joins the semiconductor chip 1 and the lead frame 21 and the thickness of the solder joint layer 23. In the characteristic diagram shown in FIG. 3, Sn (tin) -3.5Ag (silver) solder is used as the solder bonding layer 23, and the Vickers hardness (Hv) of the lead frame 21 is 60. It is the result obtained by FEM (finite element method) analysis which simulated the temperature cycle test in the temperature range. From FIG. 3, it can be seen that the thicker the solder bonding layer 23, the less the distortion generated in the solder bonding layer 23.

図４は、−４０〜１２５℃の温度範囲での温度サイクル試験を実施したときの半導体チップ１とリードフレーム２１とを接合する半田接合層２３に発生したクラックの長さと、その半田接合層２３の厚さとの関係を示す特性図である。なお、ビッカース硬さが６０と４０のリードフレーム２１を用いた。図４より、半田接合層２３の厚さが１００μｍ以上になると、半田接合層２３でのクラック発生が大幅に低減することがわかる。   FIG. 4 shows the length of cracks generated in the solder joint layer 23 that joins the semiconductor chip 1 and the lead frame 21 when the temperature cycle test in the temperature range of −40 to 125 ° C. is performed, and the solder joint layer 23. It is a characteristic view which shows the relationship with the thickness of this. A lead frame 21 having a Vickers hardness of 60 and 40 was used. As can be seen from FIG. 4, when the thickness of the solder joint layer 23 is 100 μm or more, the occurrence of cracks in the solder joint layer 23 is significantly reduced.

図５は、Ｓｎ−Ａｇ系半田の相当塑性歪みと寿命サイクル数との関係を実験により調べた結果を示す特性図である。一般に、温度サイクル寿命の要求値は、産業用で３００サイクルであり、自動車用で３０００サイクルである。図５より、相当塑性歪み量が０．４％であるときに、３００００サイクルの寿命があることがわかる。つまり、相当塑性歪み量が０．４％であれば、自動車用としての要求寿命をさらに１桁上げることができる。図３を参照すると、半導体チップ１とリードフレーム２１とを接合する半田接合層２３の厚さが１００μｍのときに相当塑性歪み量が０．４％であることがわかる。したがって、半田接合層２３の厚さを１００μｍ以上に設定することによって、半田接合層２３の信頼性を大幅に向上させることができる。   FIG. 5 is a characteristic diagram showing the results of experiments examining the relationship between the equivalent plastic strain and the number of life cycles of Sn—Ag solder. In general, the required temperature cycle life is 300 cycles for industrial use and 3000 cycles for automobile use. FIG. 5 shows that when the equivalent plastic strain amount is 0.4%, there is a life of 30000 cycles. That is, if the equivalent plastic strain amount is 0.4%, the required life for automobiles can be further increased by one digit. Referring to FIG. 3, it can be seen that the equivalent plastic strain amount is 0.4% when the thickness of the solder joint layer 23 for joining the semiconductor chip 1 and the lead frame 21 is 100 μm. Therefore, the reliability of the solder bonding layer 23 can be significantly improved by setting the thickness of the solder bonding layer 23 to 100 μm or more.

また、リードフレーム２１のビッカース硬さは、好ましくは４０以下であるのがよい。その理由について図６を用いて説明する。図６は、半導体チップ１とリードフレーム２１とを接合する半田接合層２３の歪み（相当塑性歪み）と、その半田接合層２３の厚さとの関係を示す特性図である。なお、この図６に示す特性図は、リードフレーム２１を焼き鈍してビッカース硬さを４０とし、−４０〜１２５℃の温度範囲での温度サイクル試験を模擬したＦＥＭ解析により得られた結果である。図６より、リードフレーム２１を焼き鈍して、ビッカース硬さを通常の６０〜７０程度から４０まで下げることによって、半田接合層２３の発生歪みが大幅に低減することがわかる。   Further, the Vickers hardness of the lead frame 21 is preferably 40 or less. The reason will be described with reference to FIG. FIG. 6 is a characteristic diagram showing the relationship between the strain (equivalent plastic strain) of the solder joint layer 23 that joins the semiconductor chip 1 and the lead frame 21 and the thickness of the solder joint layer 23. The characteristic diagram shown in FIG. 6 is a result obtained by FEM analysis simulating a temperature cycle test in the temperature range of −40 to 125 ° C. by annealing the lead frame 21 and setting the Vickers hardness to 40. 6 that annealing of the lead frame 21 and lowering the Vickers hardness from about 60 to 70 to 40 will greatly reduce the distortion generated in the solder joint layer 23. FIG.

また、少なくともリードフレーム２１の表面はニッケルでできているとよい。たとえば、リードフレーム２１の表面にニッケルめっきが施されているとよい。そうすれば、リードフレーム２１を構成する銅材と半田との合金層の成長が抑制されるので、より一層、半田接合層２３の信頼性が向上する。   Further, at least the surface of the lead frame 21 is preferably made of nickel. For example, the surface of the lead frame 21 may be nickel plated. By doing so, the growth of the alloy layer of the copper material and the solder constituting the lead frame 21 is suppressed, so that the reliability of the solder joint layer 23 is further improved.

（参考の形態）
図７は、本発明の参考の形態にかかる半導体装置の製造方法により製造された半導体装置の構成を示す断面図である。図７に示すように、参考の形態では、ヒートシンク６と絶縁基板３とを接合する半田接合層５、絶縁基板３と半導体チップ１とを接合する半田接合層２、絶縁基板３とリードフレーム２１とを接合する半田接合層２２、および半導体チップ１とリードフレーム２１とを接合する半田接合層２３のそれぞれの半田厚さを所定の厚さにするために、各半田接合層２，５，２２，２３にスペーサとしてフィラー３１を設けている。なお、実施の形態１と同様の構成については同一の符号を付して、説明を省略する。 (Reference of the form)
FIG. 7 is a cross-sectional view showing a configuration of a semiconductor device manufactured by the method for manufacturing a semiconductor device according to a reference embodiment of the present invention. As shown in FIG. 7, in the reference embodiment , a solder bonding layer 5 for bonding the heat sink 6 and the insulating substrate 3, a solder bonding layer 2 for bonding the insulating substrate 3 and the semiconductor chip 1, the insulating substrate 3 and the lead frame 21. In order to make each solder thickness of the solder bonding layer 22 for bonding the semiconductor chip 1 and the solder bonding layer 23 for bonding the semiconductor chip 1 and the lead frame 21 to a predetermined thickness, the solder bonding layers 2, 5, 22 , 23 is provided with a filler 31 as a spacer. In addition, the same code | symbol is attached | subjected about the structure similar to Embodiment 1, and description is abbreviate | omitted.

参考の形態の製造方法について説明する。図８〜図１０は、本発明の参考の形態にかかる半導体装置の製造方法を説明するために製造途中の半導体装置の一部の構成を示す断面図である。まず、ヒートシンク６、絶縁基板３および半導体チップ１のそれぞれの表面にクリーム半田２５を、それぞれに応じたパターンで印刷する。その際、ヒートシンク６に印刷されるクリーム半田２５の印刷領域が、ヒートシンク６に接合される被接合部材である絶縁基板３との接合領域よりも小さくなるようにする（図９参照）。また、ヒートシンク６に印刷されるクリーム半田２５の厚さは、ヒートシンク６と絶縁基板３とを接合する半田接合層５の最終厚さ、すなわち一旦溶けた後に固まったときの厚さよりも厚くなるようにする（図９と図１０を比較参照）。 The manufacturing method of the reference form will be described. 8 to 10 are cross-sectional views showing a partial configuration of a semiconductor device being manufactured in order to describe a method of manufacturing the semiconductor device according to a reference embodiment of the present invention. First, cream solder 25 is printed on each surface of the heat sink 6, the insulating substrate 3, and the semiconductor chip 1 in a pattern corresponding to each. At that time, the printing area of the cream solder 25 printed on the heat sink 6 is made smaller than the bonding area with the insulating substrate 3 which is a member to be bonded to the heat sink 6 (see FIG. 9). The thickness of the cream solder 25 printed on the heat sink 6 is larger than the final thickness of the solder bonding layer 5 for bonding the heat sink 6 and the insulating substrate 3, that is, the thickness when the solder bonding layer is solidified after being melted. (Refer to FIG. 9 and FIG. 10 for comparison).

特に図示しないが、絶縁基板３についても同様にして、絶縁基板３の上にクリーム半田を印刷する。その際、絶縁基板３に印刷されるクリーム半田の印刷領域が、半導体チップ１が接合される箇所では半導体チップ１との接合領域よりも小さくなり、リードフレーム２１の基端が接合される箇所ではリードフレーム２１の基端との接合領域よりも小さくなるようにする。また、絶縁基板３に印刷されるクリーム半田の厚さは、一旦溶けて固まったあとの厚さよりも厚くなるようにする。   Although not specifically shown, cream solder is printed on the insulating substrate 3 in the same manner. At that time, the printing area of the cream solder printed on the insulating substrate 3 is smaller than the bonding area with the semiconductor chip 1 at the position where the semiconductor chip 1 is bonded, and at the position where the base end of the lead frame 21 is bonded. It is made smaller than the joining region with the base end of the lead frame 21. Further, the thickness of the cream solder printed on the insulating substrate 3 is set to be thicker than the thickness after melting and hardening once.

また、特に図示しないが、半導体チップ１についても同様である。すなわち、半導体チップ１の上にクリーム半田を、その印刷領域がリードフレーム２１との接合領域よりも小さくなり、かつその厚さが半田接合層２３の最終的な厚さよりも厚くなるように、印刷する。ついで、図８に示すように、ヒートシンク６上のクリーム半田２５の上にディスペンサー等で複数個のフィラー３１を置く。そして、図９に示すように、ヒートシンク６上にクリーム半田２５とフィラー３１をのせたものの上に、絶縁基板３上にクリーム半田（図９では省略）を印刷したものを置く。   Further, although not particularly illustrated, the same applies to the semiconductor chip 1. That is, the cream solder is printed on the semiconductor chip 1 so that the printing area is smaller than the bonding area with the lead frame 21 and the thickness is larger than the final thickness of the solder bonding layer 23. To do. Next, as shown in FIG. 8, a plurality of fillers 31 are placed on the cream solder 25 on the heat sink 6 by a dispenser or the like. Then, as shown in FIG. 9, a piece of cream solder (not shown in FIG. 9) printed on the insulating substrate 3 is placed on the heat sink 6 on which the cream solder 25 and the filler 31 are placed.

ついで、図示しないが、絶縁基板３上のクリーム半田の上にディスペンサー等で複数個のフィラーを置く。さらにその上に、半導体チップ１上にクリーム半田を印刷したものを置く。そして、半導体チップ１上のクリーム半田の上にディスペンサー等で複数個のフィラーを置いた後、絶縁基板３と半導体チップ１に跨がるようにリードフレーム２１を置く。   Next, although not shown, a plurality of fillers are placed on the cream solder on the insulating substrate 3 with a dispenser or the like. Furthermore, the thing which printed the solder paste on the semiconductor chip 1 is put on it. Then, after a plurality of fillers are placed on the cream solder on the semiconductor chip 1 with a dispenser or the like, the lead frame 21 is placed so as to straddle the insulating substrate 3 and the semiconductor chip 1.

ここで、フィラーの融点は、半田の融点よりも高温である。換言すれば、フィラーは、半田の融点では溶融したり昇華したりしない材料でできている。フィラーの形状は、必ずしも限定しないが、球形であるのが望ましい。その理由は、球形のフィラーであれば、半田が一旦溶けて固まる際にフィラーが回転したり移動しても、フィラーの突出量は常に直径になる、すなわち一定になるからである。各半田接合層２，５，２２，２３に設けるフィラーの径は、それぞれの半田接合層の最終的な厚さと同じである。また、各半田接合層２，５，２２，２３に対するフィラーの配置は、その上に積層される被接合部材が傾かないようにするため、被接合部材との接合領域に対して均一な配置とする。たとえば、被接合部材との接合領域の四隅近傍に１つずつフィラーを配置する。   Here, the melting point of the filler is higher than the melting point of the solder. In other words, the filler is made of a material that does not melt or sublime at the melting point of the solder. The shape of the filler is not necessarily limited, but is preferably spherical. The reason is that if the filler is spherical, even if the solder is once melted and hardened, the amount of protrusion of the filler always becomes a diameter, that is, constant even if the filler rotates or moves. The diameter of the filler provided in each solder joint layer 2, 5, 22 and 23 is the same as the final thickness of each solder joint layer. In addition, the fillers are arranged on the solder bonding layers 2, 5, 22, and 23 in a uniform arrangement with respect to the bonding region with the members to be bonded so that the members to be stacked thereon are not inclined. To do. For example, the fillers are arranged one by one near the four corners of the joining region with the member to be joined.

最後に、上述したようにしてヒートシンク６、絶縁基板３、半導体チップ１およびリードフレーム２１を一体化したものをリフロー炉等に入れ、加熱してクリーム半田２５を溶かす。クリーム半田２５が溶けると、フィラー３１が溶けた半田層に落ち込む。それによって、ヒートシンク６と絶縁基板３との間、絶縁基板３と半導体チップ１との間、絶縁基板３とリードフレーム２１の基端との間、および半導体チップ１とリードフレーム２１の先端との間に、それぞれフィラー３１により規定される寸法の隙間ができる。そして、溶けた半田が広がり、その隙間を埋める。   Finally, the heat sink 6, the insulating substrate 3, the semiconductor chip 1 and the lead frame 21 integrated as described above are put into a reflow furnace or the like and heated to melt the cream solder 25. When the cream solder 25 melts, it falls into the solder layer in which the filler 31 is melted. Thereby, between the heat sink 6 and the insulating substrate 3, between the insulating substrate 3 and the semiconductor chip 1, between the insulating substrate 3 and the base end of the lead frame 21, and between the semiconductor chip 1 and the tip of the lead frame 21. A gap having a dimension defined by the filler 31 is formed between them. And the melted solder spreads and fills the gap.

この状態で冷却し、溶けた半田を固まらせると、図１０に示すように、フィラー３１により規定される所定の厚さの半田接合層５を介して、絶縁基板３を傾くことなくヒートシンク６に接合することができる。また、半田接合層５の端部の形状はフィレット形状となる。なお、図１０では、絶縁基板３よりも上の半田接合層、フィラー、半導体チップ１およびリードフレーム２１を省略している。   When the molten solder is solidified in this state, as shown in FIG. 10, the insulating substrate 3 is not tilted to the heat sink 6 via the solder bonding layer 5 having a predetermined thickness defined by the filler 31. Can be joined. Further, the shape of the end portion of the solder bonding layer 5 is a fillet shape. In FIG. 10, the solder bonding layer, filler, semiconductor chip 1 and lead frame 21 above the insulating substrate 3 are omitted.

図１１は、図７に示す構成のリードフレーム構造ＩＧＢＴモジュールにおいて、半田接合層にフィラーを用いて半田接合層の厚さを約１００μｍとしたものと、フィラーを用いていないためにリードフレームの重さにより半田接合層の厚さが５０μｍ以下になったものについて、−４０〜１２５℃の温度範囲での温度サイクル試験を実施したときの半田接合層のクラック進展の推移を示す特性図である。図１１より、フィラーを用いて半田接合層の厚さを所定の１００μｍとしたモジュールでは、３００サイクルを超えても半田接合面積が８０％以上であることがわかる。   FIG. 11 shows a lead frame structure IGBT module having the structure shown in FIG. It is a characteristic view which shows transition of the crack progress of a solder joint layer when the temperature cycle test in the temperature range of -40 to 125 degreeC is implemented about what the thickness of the solder joint layer became 50 micrometers or less by this. As can be seen from FIG. 11, in the module in which the thickness of the solder joint layer is set to a predetermined 100 μm using the filler, the solder joint area is 80% or more even when 300 cycles are exceeded.

それに対して、フィラーを用いていないモジュールでは、１００サイクルで接合面積は４０％よりも低くなり、３００サイクルでは接合面積は３０％より低くなっている。この結果から、フィラーを用いて半田接合層の厚さを所定の厚さ、たとえば１００μｍ以上にしたモジュールでは、半田接合層の剪断歪みが軽減され、クラックの進展が抑制されることがわかる。このことは、モジュールの半田による接合部における信頼性（機械的な特性）が向上することを示している。   On the other hand, in the module using no filler, the bonding area is lower than 40% at 100 cycles, and the bonding area is lower than 30% at 300 cycles. From this result, it can be seen that in a module in which the thickness of the solder joint layer is set to a predetermined thickness using a filler, for example, 100 μm or more, the shear strain of the solder joint layer is reduced and the progress of cracks is suppressed. This indicates that the reliability (mechanical characteristics) at the joint portion by the solder of the module is improved.

ところで、フィラーとして、図１２に示すように、表面に低融点金属３２を成膜したフィラー３３を用いてもよい。低融点金属３２としてつぎのものが挙げられる。単体金属の場合、錫、インジウム（Ｉｎ）、鉛（Ｐｂ）など、融点が半田リフロー温度（３５０℃以下）よりも低い金属である。また、２種類以上の金属の場合には、ＳｎもしくはＰｂベースの材料、たとえばＳｎ−Ｐｂ系、Ｓｎ−Ｉｎ系、Ｓｎ−Ａｇ系、Ｓｎ−Ａｇ−Ｃｕ系、Ｓｎ−Ｚｎ（亜鉛）系、Ｓｎ−Ｂｉ（ビスマス）系、Ｓｎ−Ｓｂ(アンチモン)系、Ｓｎ−Ｃｕ系など、半田リフロー時に溶融する金属である。これらの低融点金属３２は、無電解めっき法、蒸着法またはスパッタ法などによりフィラー３３の表面に成膜される。   By the way, as shown in FIG. 12, a filler 33 having a low melting point metal 32 formed on the surface may be used as the filler. Examples of the low melting point metal 32 include the following. In the case of a single metal, it is a metal whose melting point is lower than the solder reflow temperature (350 ° C. or lower), such as tin, indium (In), lead (Pb). In the case of two or more kinds of metals, Sn or Pb-based materials such as Sn—Pb, Sn—In, Sn—Ag, Sn—Ag—Cu, Sn—Zn (zinc), Sn-Bi (bismuth) -based, Sn-Sb (antimony) -based, Sn-Cu-based metals that melt at the time of solder reflow. These low melting point metals 32 are formed on the surface of the filler 33 by an electroless plating method, a vapor deposition method or a sputtering method.

このように、低融点金属３２が成膜されたフィラー３３を用いると、半田がフィラー３３の表面に十分に濡れ広がる。また、クリーム半田２５と同じ組成の低融点金属３２が成膜されたフィラー３３を使用する場合には、フィラー３３の周囲が完全に半田に濡れるため、信頼性の高い半田接合が可能となる。さらに、図１３に示すフィラー３４のように、フィラー３４のコア（中心部）３５を剛性の低い材料、たとえば樹脂で形成してもよい。あるいは、フィラー３４のコア３５を空洞としてもよい。いずれにしても、フィラー３４が変形しやすくなり、応力が緩和されるので、より一層、半田接合層の信頼性が高くなる。   Thus, when the filler 33 on which the low melting point metal 32 is formed is used, the solder is sufficiently spread on the surface of the filler 33. Further, when the filler 33 on which the low melting point metal 32 having the same composition as that of the cream solder 25 is used, the periphery of the filler 33 is completely wetted with the solder, so that highly reliable solder bonding is possible. Furthermore, like the filler 34 shown in FIG. 13, the core (center part) 35 of the filler 34 may be formed of a material having low rigidity, for example, a resin. Alternatively, the core 35 of the filler 34 may be hollow. In any case, since the filler 34 is easily deformed and the stress is relieved, the reliability of the solder joint layer is further increased.

なお、図７に示すように、全ての半田接合層２，５，２２，２３にフィラー３１を設けてもよいし、いずれか一つ、二つまたは三つの半田接合層にフィラー３１を設けてもよい。また、予めクリーム半田内にフィラーを混入させておいてもよい。また、クリーム半田の代わりに板半田を用いてもよい。その場合には、フィラーを先に置き、その上に板半田をのせ、さらにその上に被接合部材を置いてもよい。   In addition, as shown in FIG. 7, the filler 31 may be provided in all the solder bonding layers 2, 5, 22, and 23, or the filler 31 may be provided in any one, two, or three solder bonding layers. Also good. Moreover, you may mix a filler in cream solder beforehand. Moreover, you may use plate solder instead of cream solder. In that case, a filler may be placed first, plate solder may be placed thereon, and a member to be joined may be placed thereon.

（実施の形態２）
図１５は、本発明の実施の形態２にかかる半導体装置の、図１７（ただし、ヒートシンク６はない）の切断線Ａ−Ａに相当する断面における構成を示す断面図である。図１４は、図１５に示す構成の半導体装置の半導体チップ１とリードフレーム２１との接合部を拡大して示す断面図である。図１５に示すように、実施の形態２が実施の形態１と異なるのは、支持基板である絶縁基板３の裏面にヒートシンクが接合されていないことである。すなわち、実施の形態２の半導体装置は、ヒートシンクを有していない構成の装置であって、例えば小中容量クラスのパワーモジュールに適した構成のものである。 (Embodiment 2 )
15 is a cross-sectional view showing a configuration of the semiconductor device according to the second embodiment of the present invention in a cross section corresponding to a cutting line AA in FIG. 17 (however, there is no heat sink 6). FIG. 14 is an enlarged cross-sectional view showing a joint portion between the semiconductor chip 1 and the lead frame 21 of the semiconductor device having the configuration shown in FIG. As shown in FIG. 15, the second embodiment is different from the first embodiment in that a heat sink is not bonded to the back surface of the insulating substrate 3 that is a support substrate. That is, the semiconductor device of the second embodiment, an apparatus configuration that does not have a heat sink, such as those of the configuration suitable for the power module of the small, medium capacity class.

絶縁基板３の周縁には、樹脂成型されたケース４７が接着されている。ケース４７の内側には、外部電極用端子４８ａ，４８ｂが設けられている。外部電極用端子４８ａと半導体チップ１の一部の表面電極とは、アルミニウム製のワイヤ９により電気的に接続されている。半導体チップ１の残りの表面電極は、リードフレーム２１を介して、絶縁基板表面の回路パターン部４に電気的に接続されている。半導体チップ１の、少なくともリードフレーム２１が接合される表面電極には、半田による接合を可能とするため、たとえば無電解めっき法によりニッケルおよび金が成膜されている。   A resin-molded case 47 is bonded to the periphery of the insulating substrate 3. External electrode terminals 48 a and 48 b are provided inside the case 47. The external electrode terminal 48 a and a part of the surface electrode of the semiconductor chip 1 are electrically connected by an aluminum wire 9. The remaining surface electrode of the semiconductor chip 1 is electrically connected to the circuit pattern portion 4 on the surface of the insulating substrate via the lead frame 21. At least the surface electrode of the semiconductor chip 1 to which the lead frame 21 is bonded is formed with nickel and gold, for example, by electroless plating in order to enable bonding by solder.

外部電極用端子４８ｂは、絶縁基板表面の回路パターン部４に接続されている。半導体チップ１、リードフレーム２１およびワイヤ９を水分や湿気や塵から保護するために、ケース４７と絶縁基板３との間には、ゲル１１が封入されている。そして、図１４に示すように、実施の形態２では、半導体チップ１とリードフレーム２１との接合部である半田接合層２３の厚さは、５０μｍ以上であるのが適当である。その他の構成は、実施の形態１と同様である。したがって、実施の形態１と同様の構成については、同一の符号を付して説明を省略する。なお、絶縁基板３は単一構成のものであってもよいし、複数枚で構成されていてもよい。 The external electrode terminal 48b is connected to the circuit pattern portion 4 on the surface of the insulating substrate. Gel 11 is enclosed between the case 47 and the insulating substrate 3 in order to protect the semiconductor chip 1, the lead frame 21, and the wire 9 from moisture, moisture, and dust. Then, as shown in FIG. 14, in the second embodiment, the thickness of the semiconductor chip 1 and the lead frame 21 and the joining portion is a solder bonding layer 23 may suitably be at 50μm or more. Other configurations are the same as those in the first embodiment. Therefore, the same components as those of the first embodiment are denoted by the same reference numerals and description thereof is omitted. The insulating substrate 3 may have a single structure or a plurality of insulating substrates.

半田接合層２３の適当な厚さの理由について、図１６を用いて説明する。半田接合層２３の適当な厚さを調べるため、本発明者らは、半導体チップ１の表面電極に、無電解めっき法によりニッケルおよび金を成膜し、その表面電極に、Ｓｎ−Ａｇ系半田を用いてＣｕ製のリードフレーム２１を接合したサンプルを用意し、−４０〜１２５℃の温度範囲で３００サイクルの温度サイクル試験を実施した。その結果を図１６に示す。図１６は、半導体チップ１とリードフレーム２１との接合界面に発生したクラックの進展長さと、半田接合層２３の厚さとの関係を示す特性図である。図１６より、半田接合層２３の厚さが５０μｍ以上になると、半田接合層２３でのクラック進展長さが大幅に低減することがわかる。したがって、半田接合層２３の厚さは５０μｍ以上であるのが適当である。   The reason for the appropriate thickness of the solder bonding layer 23 will be described with reference to FIG. In order to investigate an appropriate thickness of the solder bonding layer 23, the present inventors formed a film of nickel and gold on the surface electrode of the semiconductor chip 1 by an electroless plating method, and formed Sn—Ag solder on the surface electrode. The sample which joined the lead frame 21 made from Cu was prepared, and the temperature cycle test of 300 cycles was implemented in the temperature range of -40 to 125 degreeC. The result is shown in FIG. FIG. 16 is a characteristic diagram showing the relationship between the length of a crack generated at the bonding interface between the semiconductor chip 1 and the lead frame 21 and the thickness of the solder bonding layer 23. FIG. 16 shows that when the thickness of the solder joint layer 23 is 50 μm or more, the crack propagation length in the solder joint layer 23 is significantly reduced. Therefore, it is appropriate that the thickness of the solder bonding layer 23 is 50 μm or more.

なお、実施の形態２にかかる半導体装置を製造する際に、半田接合層の厚さを所望の厚さとするために、参考の形態のようにフィラーを用いて製造してもよい。以上において本発明は、上述した実施の形態に限らず、半導体チップの電気的、熱的および機械的な接続を半田による接合で確保するパワーデバイスに共通したものである。 When the semiconductor device according to the second embodiment is manufactured, it may be manufactured using a filler as in the reference embodiment in order to set the thickness of the solder bonding layer to a desired thickness. As described above, the present invention is not limited to the above-described embodiment, but is common to power devices that ensure electrical, thermal, and mechanical connection of semiconductor chips by soldering.

以上のように、本発明は、半導体チップと他の構成部材とを半田により接合した構成を有する半導体装置に有用であり、特に、ＩＧＢＴモジュールなどのように発熱の大きいパワー半導体装置に適している。   As described above, the present invention is useful for a semiconductor device having a configuration in which a semiconductor chip and other components are joined by soldering, and is particularly suitable for a power semiconductor device that generates a large amount of heat, such as an IGBT module. .

本発明の実施の形態１にかかる半導体装置の半田による接合部を拡大して示す断面図である。It is sectional drawing which expands and shows the junction part by the solder of the semiconductor device concerning Embodiment 1 of this invention. 本発明の実施の形態１にかかる半導体装置の全体構成を示す断面図である。1 is a cross-sectional view showing an overall configuration of a semiconductor device according to a first embodiment of the present invention. 半導体チップとリードフレームとを接合する半田接合層の歪み（相当塑性歪み）と厚さとの関係を示す特性図である。FIG. 6 is a characteristic diagram showing a relationship between a strain (equivalent plastic strain) and a thickness of a solder joint layer that joins a semiconductor chip and a lead frame. 温度サイクル試験により半導体チップとリードフレームとを接合する半田接合層に発生したクラックの長さと半田接合層の厚さとの関係を示す特性図である。FIG. 6 is a characteristic diagram showing a relationship between the length of a crack generated in a solder joint layer joining a semiconductor chip and a lead frame by a temperature cycle test and the thickness of the solder joint layer. Ｓｎ−Ａｇ系半田の相当塑性歪みと寿命サイクル数との関係を示す特性図である。It is a characteristic view which shows the relationship between the equivalent plastic strain of Sn-Ag system solder, and the number of life cycles. 半導体チップとリードフレームとを接合する半田接合層の歪み（相当塑性歪み）と厚さとの関係を示す特性図である。FIG. 6 is a characteristic diagram showing a relationship between a strain (equivalent plastic strain) and a thickness of a solder joint layer that joins a semiconductor chip and a lead frame. 本発明の参考の形態にかかる半導体装置の製造方法により製造された半導体装置の構成を示す断面図である。It is sectional drawing which shows the structure of the semiconductor device manufactured by the manufacturing method of the semiconductor device concerning the reference form of this invention. 本発明の参考の形態にかかる半導体装置の製造方法を説明するために製造途中の半導体装置の一部の構成を示す断面図である。It is sectional drawing which shows the structure of a part of semiconductor device in the middle of manufacture in order to demonstrate the manufacturing method of the semiconductor device concerning the reference form of this invention. 本発明の参考の形態にかかる半導体装置の製造方法を説明するために製造途中の半導体装置の一部の構成を示す断面図である。It is sectional drawing which shows the structure of a part of semiconductor device in the middle of manufacture in order to demonstrate the manufacturing method of the semiconductor device concerning the reference form of this invention. 本発明の参考の形態にかかる半導体装置の製造方法を説明するために製造途中の半導体装置の一部の構成を示す断面図である。It is sectional drawing which shows the structure of a part of semiconductor device in the middle of manufacture in order to demonstrate the manufacturing method of the semiconductor device concerning the reference form of this invention. 温度サイクル試験による半田接合面積と繰返し数との関係を示す特性図である。It is a characteristic view which shows the relationship between the solder joint area by a temperature cycle test, and the number of repetitions. 本発明の参考の形態にかかる半導体装置の製造方法において用いられるフィラーの一例を示す断面図である。It is sectional drawing which shows an example of the filler used in the manufacturing method of the semiconductor device concerning the reference form of this invention. 本発明の参考の形態にかかる半導体装置の製造方法において用いられるフィラーの別の例を示す断面図である。It is sectional drawing which shows another example of the filler used in the manufacturing method of the semiconductor device concerning the reference form of this invention. 本発明の実施の形態２にかかる半導体装置の半田による接合部を拡大して示す断面図である。It is sectional drawing which expands and shows the junction part by the solder of the semiconductor device concerning Embodiment 2 of this invention. 本発明の実施の形態２にかかる半導体装置の全体構成を示す断面図である。It is sectional drawing which shows the whole structure of the semiconductor device concerning Embodiment 2 of this invention. 温度サイクル試験により半導体チップとリードフレームとの界面に発生したクラックの進展長さと半田接合層の厚さとの関係を示す特性図である。FIG. 6 is a characteristic diagram showing the relationship between the progress of cracks generated at the interface between a semiconductor chip and a lead frame and the thickness of a solder bonding layer in a temperature cycle test. 従来の半導体装置のオープンサンプル状態を示す平面図である。It is a top view which shows the open sample state of the conventional semiconductor device. 図１７の切断線Ａ−Ａにおける断面図である。It is sectional drawing in the cutting line AA of FIG.

符号の説明Explanation of symbols

１ 半導体チップ
２，５，２２，２３ 半田接合層
３ 支持基板（絶縁基板）
６ ヒートシンク
２１ リードフレーム
３１，３３，３４ フィラー
３２ 低融点金属
３５ フィラーの中心部（コア）
1 Semiconductor chip 2, 5, 22, 23 Solder bonding layer 3 Support substrate (insulating substrate)
6 Heat sink 21 Lead frame 31, 33, 34 Filler 32 Low melting point metal 35 Filler center (core)

Claims (4)

半導体チップの表面に設けられた電極と、該電極の上まで延びるリードフレームとが、１００μｍ以上の厚さの半田接合層を介して接合されており、
前記リードフレームのビッカース硬さは４０以下であることを特徴とする半導体装置。 An electrode provided on a surface of the semiconductor chip, a lead frame extending to the top of the electrodes are bonded via the solder bonding layer above 100μm thick,
The semiconductor device according to claim 1, wherein the lead frame has a Vickers hardness of 40 or less . 少なくとも前記リードフレームの表面はニッケルでできていることを特徴とする請求項１に記載の半導体装置。The semiconductor device according to claim 1, wherein at least a surface of the lead frame is made of nickel. 裏面にヒートシンクが接合されていない支持基板の表面に半導体チップが固定されており、該半導体チップの表面電極にリードフレームが半田により接合された半導体装置であって、A semiconductor device in which a semiconductor chip is fixed to the surface of a support substrate to which a heat sink is not bonded to the back surface, and a lead frame is bonded to the surface electrode of the semiconductor chip by solder,
半導体チップの表面に設けられた電極と、該電極の上まで延びるリードフレームとが、５０μｍ以上の厚さの半田接合層を介して接合されており、An electrode provided on the surface of the semiconductor chip and a lead frame extending to the top of the electrode are bonded via a solder bonding layer having a thickness of 50 μm or more,
前記リードフレームのビッカース硬さは４０以下であることを特徴とする半導体装置。The semiconductor device according to claim 1, wherein the lead frame has a Vickers hardness of 40 or less. 前記半導体チップの表面電極には、ニッケルおよび金よりなる膜が成膜されており、前記半田は、Ｓｎ−Ａｇ系の半田であることを特徴とする請求項３に記載の半導体装置。4. The semiconductor device according to claim 3, wherein a film made of nickel and gold is formed on the surface electrode of the semiconductor chip, and the solder is Sn-Ag solder.
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