JP4765098B2 - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof Download PDF

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JP4765098B2
JP4765098B2 JP2005298293A JP2005298293A JP4765098B2 JP 4765098 B2 JP4765098 B2 JP 4765098B2 JP 2005298293 A JP2005298293 A JP 2005298293A JP 2005298293 A JP2005298293 A JP 2005298293A JP 4765098 B2 JP4765098 B2 JP 4765098B2
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solder
lead
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semiconductor device
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JP2007109834A (en
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良成 池田
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Fuji Electric Co Ltd
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    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
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    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
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    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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    • H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
    • H01L2224/83101—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus as prepeg comprising a layer connector, e.g. provided in an insulating plate member
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    • H01L2224/83909—Post-treatment of the layer connector or bonding area
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    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
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    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]

Description

本発明は、パワー用ＩＧＢＴモジュールなどを対象とする半導体装置、およびその製造方法に関する。   The present invention relates to a semiconductor device intended for a power IGBT module and the like, and a manufacturing method thereof.

頭記したＩＧＢＴモジュールを例に、その従来構造を図２に示す。図において、１は放熱用銅ベース、２はセラミック板２ａの上面，下面に銅回路パターン２ｂ，銅箔２ｃを成層して銅ベース１に搭載した絶縁基板、３，４はＩＧＢＴ，ＦＷＤの半導体チップ、５は銅ベース１／絶縁基板２の銅箔２ｃ，および絶縁基板２の銅回路パターン２ｂ／半導体チップ３，４を接合した半田接合層、６は銅ベース１の下面にサーマルコンパウンド７で伝熱的に接合し冷却体（ヒートシンク）である。なお、図２では配線リード、モジュールの外囲ケースなどは省略して描かれてない。ここで、銅ベース１／絶縁基板２の銅箔２ｃ，および絶縁基板２の銅回路パターン２ｂ／半導体チップ３，４を接合する半田材には板半田あるいはクリーム半田を使用し、リフロー工程を経て半田接合層５を形成するようにしている。     The conventional structure of the IGBT module described above is shown in FIG. In the figure, 1 is a heat-dissipating copper base, 2 is an insulating substrate mounted on the copper base 1 with a copper circuit pattern 2b and a copper foil 2c formed on the upper and lower surfaces of the ceramic plate 2a, and 3 and 4 are semiconductors of IGBT and FWD. The chip 5 is a copper base 1 / a copper foil 2c of the insulating substrate 2, and the copper circuit pattern 2b of the insulating substrate 2 / the solder bonding layer joining the semiconductor chips 3 and 4, and 6 is a thermal compound 7 on the lower surface of the copper base 1. It is a cooling body (heat sink) that is joined in a heat transfer manner. In FIG. 2, the wiring leads, the module enclosing case, etc. are not shown. Here, plate solder or cream solder is used as the solder material for joining the copper base 1 / the copper foil 2c of the insulating substrate 2 and the copper circuit pattern 2b / semiconductor chips 3 and 4 of the insulating substrate 2, and after a reflow process. A solder bonding layer 5 is formed.

一方、最近では環境問題からＳｎ−Ｐｂ系半田の代替として鉛成分を含まない鉛フリー半田が採用されるようになっており、前記のＩＧＢＴモジュール（パワーモジュール）に適用する半田材としては、現在知られている各種組成の鉛フリー半田の中でも、取りわけ接合性（半田濡れ性），機械的特性，伝熱抵抗などの面で比較的バランスがよく、かつ製品への実績もあるＳｎ−Ａｇ系の鉛フリー半田が多く使われている（例えば、非特許文献１参照）。
また、ヒートシンクの上に絶縁基板，さらにその上に半導体チップを半田接合した階層接続構造において、下位の接合部には高温系の鉛フリー半田としてＳｎ−Ｓｂ系半田を使用し、上位接合部にはＳｎ−Ｓｂ系半田よりも融点が低いＳｎ−Ａｇ系半田にＣｕなどの元素を添加した組成の鉛フリー半田を使用する半田接合構造も知られている。（例えば特許文献１参照）。
両角，他２名，「パワー半導体モジュールにおける信頼性設計技術」，冨士時報，富士電機株式会社，平成１３年２月１０日，第７４巻，第２号，p１４５〜１４８ 特開２００１−３５９７８号公報 On the other hand, recently, lead-free solder containing no lead component has been adopted as an alternative to Sn-Pb solder due to environmental problems. As a solder material applied to the IGBT module (power module), Among lead-free solders of various known compositions, Sn-Ag has a relatively good balance in terms of jointability (solder wettability), mechanical properties, heat transfer resistance, etc., and has a track record in products. Many lead-free solders are used (see, for example, Non-Patent Document 1).
Further, in a hierarchical connection structure in which an insulating substrate is soldered on a heat sink and a semiconductor chip is soldered thereon, Sn—Sb solder is used as a high-temperature lead-free solder at the lower joint, and the upper joint is used. Also known is a solder joint structure using lead-free solder having a composition in which an element such as Cu is added to Sn—Ag solder having a melting point lower than that of Sn—Sb solder. (For example, refer to Patent Document 1).
Both corners, 2 others, “Reliability design technology in power semiconductor modules”, Fuji time signal, Fuji Electric Co., Ltd., February 10, 2001, Vol. 74, No. 2, p145-148 JP 2001-35978 A

ところで、先記のように半導体チップ／絶縁基板の接合にＳｎ−Ａｇ系の鉛フリー半田を適用した半導体モジュールについて、パワーサイクル試験（モジュールの実動作を模擬した断続通電試験）により半田接合部に発生した亀裂（欠陥）の進展形態を観察したところによれば、降伏強度が大きいＳｎ−Ａｇ系の鉛フリー半田は、図３で表すように発熱密度が高い半導体チップ３の中央部下付近を起点としてほぼ同心円状に亀裂（符号Ｐで表す）が進展することが明らかになった。また、この亀裂の特徴は、半田層の厚さ方向に対して平行な縦割れ，または網目状を呈してＳｎの結晶粒界を選択的に進展しており、このことからＳｎ−Ａｇ系の鉛フリー半田では熱劣化（組織変化）によって亀裂が進行するものと想定される（非特許文献１のｐ１４７参照）。
このように、半導体チップ／絶縁基板の接合にＳｎ−Ａｇ系の鉛フリー半田を適用した半導体装置の半田接合部について、従来構造のままでは半導体チップの中央部下付近の半田接合層に熱劣化（組織変化）が発生して亀裂が生じるために、長期に亘り高い信頼性を確保することが難しい。 By the way, as described above, for a semiconductor module in which Sn-Ag lead-free solder is applied to the semiconductor chip / insulating substrate joint, a power cycle test (intermittent current test simulating the actual operation of the module) is performed on the solder joint. According to the observation of the progress of cracks (defects), Sn-Ag lead-free solder with a high yield strength starts near the center of the semiconductor chip 3 where the heat generation density is high as shown in FIG. As a result, it became clear that cracks (represented by the symbol P) progress almost concentrically. In addition, the characteristics of this crack are vertical cracks parallel to the thickness direction of the solder layer, or a network, and the Sn crystal grain boundaries are selectively propagated. In lead-free solder, it is assumed that cracks progress due to thermal degradation (structural change) (see p147 of Non-Patent Document 1).
As described above, with respect to the solder joint portion of the semiconductor device in which Sn-Ag lead-free solder is applied to the semiconductor chip / insulating substrate joint, the solder joint layer near the lower center of the semiconductor chip is thermally deteriorated with the conventional structure ( It is difficult to ensure high reliability over a long period of time because of the occurrence of cracks due to structural changes.

また、先記の特許文献１に開示されている接合構造で使用するＳｎ−Ｓｂ系半田は、Ｓｎ−Ａｇ系半田に比べて耐熱性が高いが濡れ性に劣り、単独で使用する場合には良好な半田フィレットが形成されないで溶融半田が接合面域から外方に流出するといった問題がある。
本発明は上記の点に鑑みなされたものであり、その目的は半導体チップ／絶縁基板間の半田接合部について、半導体チップの中央部下付近の半田接合層に発生する熱劣化を巧みに抑制して高いパワーサイクル耐性と長期信頼性の向上が図れるように改良した半導体装置、およびその製造方法を提供することにある。 In addition, the Sn—Sb solder used in the joint structure disclosed in Patent Document 1 is higher in heat resistance than Sn—Ag solder, but poor in wettability. There is a problem that molten solder flows out from the joint area without forming a good solder fillet.
The present invention has been made in view of the above points, and the purpose of the present invention is to skillfully suppress thermal degradation that occurs in the solder joint layer near the center of the semiconductor chip at the solder joint between the semiconductor chip and the insulating substrate. An object of the present invention is to provide an improved semiconductor device and a method for manufacturing the same so that high power cycle resistance and long-term reliability can be improved.

上記目的を達成するために、本発明によれば、絶縁基板の回路パターン上に半導体チップを半田マウントした半導体装置において、
半導体チップと回路パターンとの間の半田接合面域を半導体チップの中央部下に対応する中央面部と、該中央面部を取り囲む外周面部とに二分した上で、その中央面部にはＳｎをベースとする半田組成にＳｂを添加したＳｎ−Ｓｂ系の第１の鉛フリー半田を適用して接合し、外周面部にはＳｎをベースとする半田組成に、前記第１の鉛フリー半田よりも融点を低くしかつ半田濡れ性をよくする元素を添加した第２の鉛フリー半田を適用して接合するものする（請求項１記載）。
ここで、前記前記第２の鉛フリー半田は、Ｓｎをベースとする半田組成にＡｇ，Ｃｕ，Ｎｉ，Ｂｉ，Ｉｎからなる群のうち少なくとも１種を添加した鉛フリー半田（請求項２）、あるいは前記組成にＧｅ，Ｓｂからなる群のうち少なくとも１種をさらに添加した鉛フリー半田を使用するものとする（請求項３）。 In order to achieve the above object, according to the present invention, in a semiconductor device in which a semiconductor chip is solder mounted on a circuit pattern of an insulating substrate,
The solder joint surface area between the semiconductor chip and the circuit pattern is divided into a central surface portion corresponding to the lower central portion of the semiconductor chip and an outer peripheral surface portion surrounding the central surface portion, and the central surface portion is based on Sn. A Sn—Sb-based first lead-free solder with Sb added to the solder composition is applied and joined, and the outer peripheral surface portion has a Sn-based solder composition with a lower melting point than the first lead-free solder. In addition, the second lead-free solder to which an element for improving solder wettability is added is applied and bonded (claim 1).
Here, the second lead-free solder is a lead-free solder in which at least one selected from the group consisting of Ag, Cu, Ni, Bi, and In is added to a Sn-based solder composition (claim 2), Or the lead-free solder which added at least 1 sort (s) further in the composition which consists of Ge and Sb to the said composition shall be used (Claim 3).

また、前記第１，第２の鉛フリー半田は、半田接合面域の中央面部，外周面部のパターン形状に合わせて裁断した板半田，もしくは印刷するクリーム半田を使用する（請求項４）。
一方、前記半導体装置を製造する本発明による半田接合方法では、絶縁基板の回路パターン上に指定した半田接合面域の中央面部，外周面部にそれぞれ前記第１，第２の鉛フリー半田を配し、その上に半導体チップを重ね合わせた状態で前記第１の鉛フリー半田の融点以上に加熱して半田接合するようにする（請求項５）。 In addition, the first and second lead-free solders use plate solder cut according to the pattern shape of the central surface portion and outer peripheral surface portion of the solder joint surface area or cream solder to be printed (Claim 4).
On the other hand, in the solder bonding method according to the present invention for manufacturing the semiconductor device, the first and second lead-free solders are arranged on the central surface portion and the outer peripheral surface portion of the solder bonding surface area designated on the circuit pattern of the insulating substrate. Then, in a state where the semiconductor chip is superposed thereon, it is heated to the melting point of the first lead-free solder or higher so as to be soldered (Claim 5).

上記のように半導体チップ／回路パターン間の半田接合について、チップの外周部に比べて高温となる半導体チップの中央部下の面域には第１の鉛フリー半田（Ｓｎ−Ｓｂ系の鉛フリー半田）を適用することで、その半田組成のＳｂがＳｎに固溶して金属間化合物の析出を抑え、接合面全域をＳｎ−Ａｇ系の鉛フリー半田で接合したものと比べて高い耐熱性の確保と、半田接合層の熱劣化を低減できる。
一方、接合面域の外周面部には、Ｓｎをベースとして前記第１の鉛フリー半田より融点を低くし、半田濡れ性を良好にする金属を添加した第２の鉛フリー半田を適用したことにより、高い半田濡れ性を確保して半田接合部に良好な半田フィレットを形成できる。また、この第２の鉛フリー半田に添加する金属として熱伝導率の高いＣｕ，Ａｇなどを添加することにより半田接合層の伝熱熱抵抗が低減し、これにより従来構造で問題となっていた半田接合部の熱劣化を効果的に抑えて半導体装置のパワーサイクル耐性，長期信頼性を大幅に向上できる。 As described above, the first lead-free solder (Sn—Sb-based lead-free solder) is formed in the surface area under the center of the semiconductor chip, which is higher in temperature than the outer periphery of the chip. ), Sb of the solder composition is dissolved in Sn to suppress the precipitation of intermetallic compounds, and the entire bonding surface has higher heat resistance than those bonded with Sn-Ag lead-free solder. Ensuring and thermal degradation of the solder joint layer can be reduced.
On the other hand, the second lead-free solder to which the melting point is lower than that of the first lead-free solder and the metal that improves solder wettability is added based on Sn is applied to the outer peripheral surface portion of the joint surface area. It is possible to ensure high solder wettability and to form a good solder fillet at the solder joint. Further, by adding Cu, Ag or the like having a high thermal conductivity as a metal to be added to the second lead-free solder, the heat transfer heat resistance of the solder joint layer is reduced, thereby causing a problem in the conventional structure. The thermal degradation of the solder joint can be effectively suppressed, and the power cycle resistance and long-term reliability of the semiconductor device can be greatly improved.

また、その半田接合工程では、前記の中央面部と外周面部のパターン形状に合わせて打ち抜き形成した第１および第２鉛フリー半田の板半田，あるいはクリーム半田を絶縁基板の銅回路パターン上に配した上でこの上に半導体チップを重ね合わせ、ここでＣｕ，Ａｇなどを添加した第２の鉛フリー半田の融点（Ｓｎ−Ｃｕ系（２２７℃共晶），Ｓｎ−Ａｇ系（２２１℃共晶）など）よりも高融点なＳｎ−Ｓｂ系の第１の鉛フリー半田（融点：２３５℃共晶）に合わせて、半田リフローを第１の鉛フリー半田の融点以上に加熱して行うことにより、接合面域の全域を同時に半田接合できる。しかも、この半田接合工程では濡れ性のよい外周面部の第２の鉛フリー半田（Ｓｎ−Ｃｕ系，Ｓｎ−Ａｇ系など）が先に溶融して半導体チップ／回路パターンの間の周域に良好な半田フィレットを形成して、その内周側にＳｎ−Ｓｂ系の第１の鉛フリー半田を封じ込めるので、濡れ性の低いＳｎ−Ｓｂ系の半田が接合面域の外側に漏出することなしに所定の中央面部に適正に半田接合層を形成する。 In the solder joining process, the first and second lead-free solder plate solder or cream solder formed by punching in accordance with the pattern shape of the central surface portion and the outer peripheral surface portion is disposed on the copper circuit pattern of the insulating substrate. On top of this, a semiconductor chip is overlaid, and the melting point of the second lead-free solder to which Cu, Ag, etc. are added (Sn—Cu system (227 ° C. eutectic), Sn—Ag system (221 ° C. eutectic)) In accordance with Sn-Sb-based first lead-free solder (melting point: 235 ° C. eutectic) having a melting point higher than that of the first lead-free solder , the solder reflow is performed by heating above the melting point of the first lead-free solder , The entire bonding area can be soldered simultaneously. In addition, in this solder joining process, the second lead-free solder (Sn—Cu type, Sn—Ag type, etc.) on the outer peripheral surface portion having good wettability is melted first, and is excellent in the peripheral area between the semiconductor chips / circuit patterns. And a Sn-Sb-based first lead-free solder is contained on the inner peripheral side of the solder fillet, so that Sn-Sb-based solder having low wettability does not leak to the outside of the joint surface area. A solder joint layer is appropriately formed on a predetermined central surface portion.

つまり、上記のような組合せ条件で半田組成の異なる鉛フリー半田を適用して、半導体チップ／絶縁基板の回路パターン間を接合することにより、個々の鉛フリー半田がもつ特性の欠点を二種類の半田が互いにカバーし合って信頼性の高い半田接合部を確保することができる。   In other words, by applying lead-free solder with different solder composition under the above combination conditions and joining between the circuit patterns of the semiconductor chip / insulating substrate, there are two types of defects in the characteristics of each lead-free solder. Solder covers each other to ensure a highly reliable solder joint.

以下、本発明の実施の形態を図１（ａ）〜（ｂ）に示す実施例に基づいて説明する。なお、図示実施例の図は半導体チップ３と絶縁基板２の銅回路パターン２ｂとの半田接合部を模式的に表している。
すなわち、銅回路パターン２ｂと半導体チップ３との半田接合について、図示実施例では接合面域Ａをチップ中心部下に対応する中央面部Ｂ（円形）と、該中央面部Ｂを取り囲む外周面部Ｃとに二分した上で、中央面部ＢにはＳｎ−Ｓｂ系の鉛フリー半田（第１の鉛フリー半田）８（融点：２３５℃共晶）を適用し、外周面部ＣにはＳｎ−Ａｇ系の鉛フリー半田（第２の鉛フリー半田）９（融点：２２１℃共晶）を適用して半田接合している。
ここで、前記半田８，９に板半田を使用する場合には、図１（ｃ）のように前記中央面部Ｂに対応したパターン形状（円形）に裁断したＳｎ−Ａｇ系の鉛フリー半田８と、外周輪郭を半導体チップ３の外形（方形状）に合わせ、板面中央に前記中央面部Ｂの形状に対応した穴９ａを打ち抜いて裁断したＳｎ−Ａｇ系の鉛フリー半田９とを用意して両者を図示のように組合せ、これを銅回路パターン２ｂ上の所定位置に載せる。 DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below based on the examples shown in FIGS. The diagram of the illustrated embodiment schematically shows a solder joint between the semiconductor chip 3 and the copper circuit pattern 2b of the insulating substrate 2. FIG.
That is, with respect to the solder bonding between the copper circuit pattern 2b and the semiconductor chip 3, in the illustrated embodiment, the bonding surface area A is divided into a central surface portion B (circular) corresponding to the lower portion of the chip center and an outer peripheral surface portion C surrounding the central surface portion B. After being divided in half, Sn-Sb-based lead-free solder (first lead-free solder) 8 (melting point: 235 ° C. eutectic) is applied to the central surface portion B, and Sn-Ag-based lead is applied to the outer peripheral surface portion C. Free solder (second lead-free solder) 9 (melting point: 221 ° C. eutectic) is applied for solder bonding.
Here, in the case where plate solder is used for the solders 8 and 9, Sn-Ag lead-free solder 8 cut into a pattern shape (circular shape) corresponding to the central surface portion B as shown in FIG. And Sn-Ag lead-free solder 9 having an outer peripheral contour matched to the outer shape (rectangular shape) of the semiconductor chip 3 and punching a hole 9a corresponding to the shape of the central surface portion B at the center of the plate surface. The two are combined as shown in the figure and placed on a predetermined position on the copper circuit pattern 2b.

一方、クリーム半田を使用する場合には、中央面部Ｂ，外周面部Ｃのパターン形状に対応したマスクを使ってクリーム半田を銅回路パターン２ｂに印刷する。なお、図示例では中央面部Ｂの形状を円形としたが、これに限定されるものではなく、方形状あるいは多角形状としてもよい。
次に、鉛フリー半田８，９の上に半導体チップ３を重ね合わせて保持した上で、この絶縁基板，半導体チップの仮組立体をリフロー炉に搬入し、炉内温度をＳｎ−Ｓｂ系の鉛フリー半田９の融点より若干高い温度（例えば２６０℃）に上げて半田接合を行う。これにより、同じ接合工程で中央面部Ｂに配したＳｎ−Ｓｂ系の鉛フリー半田８と外周面部Ｃに配したＳｎ−Ａｇ系の鉛フリー半田９とで半導体チップ３／銅回路パターン２ｂ間の接合面域Ａが同時に接合される。 On the other hand, when using cream solder, the cream solder is printed on the copper circuit pattern 2b using a mask corresponding to the pattern shape of the central surface portion B and the outer peripheral surface portion C. In the illustrated example, the shape of the central surface portion B is circular. However, the shape is not limited to this, and may be rectangular or polygonal.
Next, after holding the semiconductor chip 3 overlaid on the lead-free solders 8 and 9, the temporary assembly of the insulating substrate and the semiconductor chip is carried into a reflow furnace, and the furnace temperature is set to Sn-Sb system. Solder bonding is performed by raising the temperature slightly higher than the melting point of the lead-free solder 9 (for example, 260 ° C.). As a result, between the semiconductor chip 3 and the copper circuit pattern 2b, the Sn—Sb-based lead-free solder 8 disposed on the central surface portion B and the Sn-Ag-based lead-free solder 9 disposed on the outer peripheral surface portion C in the same bonding process. Bonding surface area A is bonded simultaneously.

なお、図示例では外周面部ＣにＳｎ−Ａｇ系の鉛フリー半田を適用したが、そのほかにＳｎをベースにＣｕ，Ｎｉ，Ｂｉ，Ｉｎのうち少なくとも１種を添加した２元素，３元素系鉛フリー半田、この鉛フリー半田にＧｅあるいはＳｂをさらに添加した多元系鉛フリー半田を使用してもよい。   In the illustrated example, Sn-Ag-based lead-free solder is applied to the outer peripheral surface portion C. In addition to this, two-element or three-element lead in which at least one of Cu, Ni, Bi, and In is added based on Sn. Free solder or multi-component lead-free solder obtained by further adding Ge or Sb to the lead-free solder may be used.

本発明の実施例による半導体チップ／絶縁基板の回路パターン間半田接合部の模式図で、（ａ）は断面側視図、（ｂ）は（ａ）の矢視Ｘ−Ｘ断面図、（ｃ）は板半田を使用した場合の組合せ説明図BRIEF DESCRIPTION OF THE DRAWINGS It is a schematic diagram of the solder joint part between the circuit patterns of the semiconductor chip / insulation board | substrate by the Example of this invention, (a) is a sectional side view, (b) is XX sectional drawing of (a) arrow XX, ) Is a combination explanatory diagram when using plate solder 本発明の実施対象となるＩＧＢＴモジュールの組立構造図Assembly structure diagram of IGBT module which is an object of the present invention 図２の半導体チップ／絶縁基板間をＳｎ−Ａｇ系鉛フリー半田で接合した場合に発生する半田接合層の亀裂進展状況を模式的に表した説明図Explanatory drawing which represented typically the crack progress condition of the solder joint layer which generate | occur | produces when joining between the semiconductor chip / insulation board | substrate of FIG. 2 with Sn-Ag system lead free solder

符号の説明Explanation of symbols

１ 銅ベース
２ 絶縁基板
２ｂ 銅回路パターン
３，４ 半導体チップ
５ 半田接合層
８ Ｓｎ−Ｓｂ系の鉛フリー半田
９ Ｓｎ−Ａｇ系の鉛フリー半田 DESCRIPTION OF SYMBOLS 1 Copper base 2 Insulation board 2b Copper circuit pattern 3, 4 Semiconductor chip 5 Solder joint layer 8 Sn-Sb system lead free solder 9 Sn-Ag system lead free solder

Claims (5)

絶縁基板の回路パターン上に半導体チップを半田マウントした半導体装置において、
半導体チップと回路パターンとの間の半田接合面域を半導体チップの中央部下に対応する中央面部と、該中央面部を取り囲む外周面部とに二分した上で、その中央面部にはＳｎをベースとする半田組成にＳｂを添加したＳｎ−Ｓｂ系の第１の鉛フリー半田を適用して接合し、外周面部にはＳｎをベースとする半田組成に、前記第１の鉛フリー半田よりも融点を低くしかつ半田濡れ性をよくする元素を添加した第２の鉛フリー半田を適用して接合したことを特徴とする半導体装置。 In a semiconductor device in which a semiconductor chip is solder mounted on a circuit pattern of an insulating substrate,
The solder joint surface area between the semiconductor chip and the circuit pattern is divided into a central surface portion corresponding to the lower central portion of the semiconductor chip and an outer peripheral surface portion surrounding the central surface portion, and the central surface portion is based on Sn. A Sn—Sb-based first lead-free solder with Sb added to the solder composition is applied and joined, and the outer peripheral surface portion has a Sn-based solder composition with a lower melting point than the first lead-free solder. And a second lead-free solder to which an element for improving solder wettability is added and bonded. 請求項１に記載の半導体装置において、前記第２の鉛フリー半田は、Ｓｎをベースとする半田組成にＡｇ，Ｃｕ，Ｎｉ，Ｂｉ，Ｉｎからなる群のうち少なくとも１種を添加した鉛フリー半田であることを特徴とする半導体装置。 2. The semiconductor device according to claim 1, wherein the second lead-free solder is a Sn-based solder composition in which at least one selected from the group consisting of Ag, Cu, Ni, Bi, and In is added to a Sn-based solder composition. A semiconductor device characterized by the above. 請求項２に記載の半導体装置において、前記第２の鉛フリー半田は、Ｇｅ，Ｓｂからなる群のうち少なくとも１種をさらに添加した鉛フリー半田であることを特徴とする半導体装置。 3. The semiconductor device according to claim 2, wherein the second lead-free solder is a lead-free solder to which at least one of a group consisting of Ge and Sb is further added. 請求項１乃至３に記載の半導体装置において、前記第１，第２の鉛フリー半田が、半田接合面域の中央面部，外周面部のパターン形状に合わせて裁断した板半田，もしくは印刷するクリーム半田であることを特徴とする半導体装置。 4. The semiconductor device according to claim 1, wherein the first and second lead-free solders are plate solders cut according to a pattern shape of a central surface portion and an outer peripheral surface portion of a solder joint surface area, or cream solder to be printed. A semiconductor device characterized by the above. 請求項１乃至４に記載の半導体装置の製造方法であって、絶縁基板の回路パターン上に指定した半田接合面域の中央面部，外周面部にそれぞれ前記第１，第２の鉛フリー半田を配し、その上に半導体チップを重ね合わせた状態で前記第１の鉛フリー半田の融点以上に加熱して半田接合することを特徴とする半導体装置の製造方法。 5. The method of manufacturing a semiconductor device according to claim 1, wherein the first and second lead-free solders are respectively disposed on a central surface portion and an outer peripheral surface portion of a solder joint surface area designated on a circuit pattern of an insulating substrate. A method for manufacturing a semiconductor device, comprising: heating the semiconductor chip over the melting point of the first lead-free solder in a state where a semiconductor chip is overlaid thereon.
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