JPH0347673A - Solder surface joining method and semiconductor integrated circuit device using its method - Google Patents

Solder surface joining method and semiconductor integrated circuit device using its method

Info

Publication number
JPH0347673A
JPH0347673A JP18436889A JP18436889A JPH0347673A JP H0347673 A JPH0347673 A JP H0347673A JP 18436889 A JP18436889 A JP 18436889A JP 18436889 A JP18436889 A JP 18436889A JP H0347673 A JPH0347673 A JP H0347673A
Authority
JP
Japan
Prior art keywords
solder
melting point
preform
joined
objects
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18436889A
Other languages
Japanese (ja)
Inventor
Hiroshi Akasaki
赤崎 博
Kanji Otsuka
寛治 大塚
Takeo Yamada
健雄 山田
Kazuhisa Kubo
和寿 久保
Hiroshi Tate
宏 舘
Norishige Kikuchi
菊地 哲慈
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi ULSI Engineering Corp
Hitachi Ltd
Original Assignee
Hitachi ULSI Engineering Corp
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi ULSI Engineering Corp, Hitachi Ltd filed Critical Hitachi ULSI Engineering Corp
Priority to JP18436889A priority Critical patent/JPH0347673A/en
Publication of JPH0347673A publication Critical patent/JPH0347673A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/831Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
    • H01L2224/83101Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus as prepeg comprising a layer connector, e.g. provided in an insulating plate member
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319Arrangement of the layer connectors prior to mounting
    • H01L2224/83194Lateral distribution of the layer connectors

Abstract

PURPOSE:To prevent the generation of a void caused by a fact that bubbles remain behind on the joint surface by using a solder perform which consists of solder of plural different compositions, and melted and diffused, and becomes a desired composition in an equalized state. CONSTITUTION:Plural joining objects 1, 2 are joined through solder. Therefore, they are joined by inserting a solder preform 5 between the joining objects 1, 2. The solder preform 5 is constituted of solder of plural different compositions, that is, low melting point solder 5a and high melting point solder 5b, and by melting and diffusing it, a desired composition is obtained in an equalized state. Subsequently, on each joint surface of the joining objects 1, 2, metallized layers 3, 4 are formed and joined through the solder preform 5. In such a way, the generation of a leak path in a sealing part can be prevented.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、半田面接合技術およびそれを用いた半導体集
積回路装置に関し、特に、半田面接合部における伝熱抵
抗の低減および気密性の向上などに有効な技術に関する
[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a solder surface bonding technique and a semiconductor integrated circuit device using the same, and in particular, to a method for reducing heat transfer resistance and improving airtightness in a solder surface joint. Regarding effective techniques such as

〔従来の技術〕[Conventional technology]

たとえば、汎用の電子計算機ンステムを構成する大規模
論理集積回路装置の製造工程では、所望の機能の半導体
集積回路が形成された個々の半導体ペレットを、たとえ
ば気密封止型のマイクロチップキャリヤなどのパッケー
ジに封入し、このパッケージをさらに大型のモジュール
ベースおよびモジュールキャンプなどからなる封止構造
の内部に封入した実装形態とすることで、実装密度の向
上および動作中に発熱する半導体ペレットの冷却機構の
簡素化・高効率化などを実現することが知られている。
For example, in the manufacturing process of large-scale logic integrated circuit devices that constitute general-purpose computer systems, individual semiconductor pellets on which semiconductor integrated circuits with desired functions have been formed are packaged, for example, in hermetically sealed microchip carriers. By enclosing this package inside a sealing structure consisting of a larger module base and module camp, etc., it is possible to improve packaging density and simplify the cooling mechanism for semiconductor pellets that generate heat during operation. It is known to achieve improvements in efficiency and efficiency.

ところで、半導体ペレットのマイクロチップキャリヤに
対する封止形態の一例としては、次のようなものが考え
られる。
By the way, as an example of the sealing form of the semiconductor pellet with respect to the microchip carrier, the following can be considered.

すなわち、第11図に示されるように、パッケージベー
ス100に対してあらかじめ半田バンブ200を介して
半導体ペレ7)300を固定しておくとともに、当該パ
ッケージベース100とキャップ400との封着面、さ
らには半導体ペレット300の背面に臨むキャップ40
0の内面に所定の−様な組成の予備半田を被着させてお
き、パンケージベース100とキャップ400の封着面
および半導体ペレット300の背面とキャンプ400の
内面とを密着させた状態で加熱することにより予備半田
を溶融・融合させて、パッケージベース100とキャッ
プ400との封着部の気密性の確保、および半導体ベレ
7)300の背面とキャップ400の内面との間に形成
された半田層による放熱路の確保などを達成するもので
ある。
That is, as shown in FIG. 11, the semiconductor pellet 7) 300 is fixed in advance to the package base 100 via the solder bump 200, and the sealing surface between the package base 100 and the cap 400, and is the cap 40 facing the back side of the semiconductor pellet 300
Preliminary solder with a predetermined --like composition is applied to the inner surface of the cap 400, and heated while the sealing surfaces of the pan cage base 100 and the cap 400, the back surface of the semiconductor pellet 300, and the inner surface of the camp 400 are in close contact with each other. By doing so, the preliminary solder is melted and fused to ensure the airtightness of the sealed portion between the package base 100 and the cap 400, and the solder formed between the back surface of the semiconductor bezel 7) 300 and the inner surface of the cap 400 is This layer ensures a heat dissipation path.

また、パッケージベース100の外面には、半田バンブ
500が形成されており、当該パフケージベース100
の内部に形成されている図示しない多層配線構造および
半田バンブ200を介して、内部に封入された半導体ペ
レyh300と外部との電気信号の授受を行うとともに
、モジュールベースなどの基板への実装が行われる。
Further, a solder bump 500 is formed on the outer surface of the package base 100, and the puff cage base 100
Electric signals are exchanged between the internally sealed semiconductor layer yh300 and the outside through a multilayer wiring structure (not shown) formed inside the board and solder bumps 200, and mounting on a board such as a module base is performed. be exposed.

また、特開昭61−125025号公報に開示される他
の技術では、共晶金属材を介した半導体チップ搭載基板
に対する半導体チップのボンディングに際して、共晶金
属材の厚さ方向に複数の穴を穿設するとともに、当該共
晶金属材を介して半導体チップと半導体チップ搭載基板
とを積み重ねた状態で、雰囲気を真空状態にして複数の
穴の内部に真空空洞を形成する。そして、共晶金属の融
点程度に加熱した後に不活性ガスを導入して雰囲気の真
空状態を破壊することにより、真空空洞と外部の不活性
ガス雲囲気との圧力差によって、半導体チップを半導体
チップ搭載基板に密着させると同時に溶融した共晶金属
によって真空空洞を圧し潰し、半導体チップに工具など
による外力を加えることなく、残留気泡(ボイド)など
のない共晶金属層による半導体チップと半導体チップ搭
載基板とのボンディングを達成しようとするものである
Furthermore, in another technique disclosed in Japanese Patent Application Laid-Open No. 61-125025, a plurality of holes are formed in the thickness direction of the eutectic metal material when bonding a semiconductor chip to a semiconductor chip mounting substrate via the eutectic metal material. At the same time, with the semiconductor chip and the semiconductor chip mounting substrate stacked together via the eutectic metal material, the atmosphere is made into a vacuum state to form vacuum cavities inside the plurality of holes. After heating to about the melting point of the eutectic metal, an inert gas is introduced to break the vacuum state of the atmosphere, and the pressure difference between the vacuum cavity and the outside inert gas cloud surrounds the semiconductor chip. Semiconductor chips and semiconductor chips are mounted using a eutectic metal layer with no residual air bubbles (voids) by crushing the vacuum cavity with melted eutectic metal at the same time as it is brought into close contact with the mounting substrate, without applying external force from tools etc. to the semiconductor chip. The aim is to achieve bonding with the substrate.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

ところが、前者の従来技術の場合には、予備半田の組成
が封着部および接合部の全域にわたって−11であるた
め、加熱に際しての溶融が各部において同時に起こり、
接合面の中央部に生じた気泡が逃げ場を失って閉じ込め
られた状態となりボイドが形成されやすくなる。
However, in the case of the former prior art, since the composition of the preliminary solder is -11 over the entire area of the sealing part and the joint part, melting occurs simultaneously in each part during heating.
Air bubbles generated in the center of the joint surface have no place to escape and become trapped, making it easy to form voids.

この結果、半導体ペレットの背面とキャップの内面との
間に介在して熱伝導路となる半田層においては、このボ
イドによって伝熱抵抗が増大し、半導体ペレットからキ
ャップ側への放熱効率を低下させるという問題を生じ、
また、パッケージベースとキャップとの封着部に介在す
る半田層においては、ボイドを通じて漏洩経路(リーク
パス)が形成されやすくなり、半導体ペレットが封入さ
れるマイクロチップキャリヤの気密保持性能を劣化させ
るという問題を生じる。
As a result, in the solder layer that is interposed between the back surface of the semiconductor pellet and the inner surface of the cap and serves as a heat conduction path, the voids increase the heat transfer resistance and reduce the efficiency of heat dissipation from the semiconductor pellet to the cap side. This gave rise to the problem of
In addition, in the solder layer interposed in the sealing area between the package base and the cap, a leak path is likely to be formed through voids, which deteriorates the airtightness of the microchip carrier in which the semiconductor pellet is encapsulated. occurs.

一方、後者の従来技術の場合には、接合部が外部雰囲気
に露出した状態にある場合には有効であるが、第11図
に示されるマイクロチップキャリヤの様に、封着部と、
この封着部に取り囲まれた内部の熱伝導接合部とを同時
に形成する封止形態では、内外の気圧差によって封着部
に介在する溶融半田層が破壊されることが懸念され、当
該マイクロチップキャリヤの組立工程への適用は困難で
ある。
On the other hand, in the case of the latter conventional technique, it is effective when the bonded portion is exposed to the external atmosphere, but as in the case of the microchip carrier shown in FIG.
In a sealing form in which an internal thermally conductive joint surrounded by this sealing part is formed at the same time, there is a concern that the molten solder layer interposed in the sealing part will be destroyed due to the pressure difference between the inside and outside. Application to carrier assembly processes is difficult.

そこで、本発明の目的は、被接合物の半田面接合部にお
けるボイドの発生を確実に防止することが可能な半田面
接合方法を提供することにある。
SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a solder surface joining method that can reliably prevent the generation of voids in the solder surface joints of objects to be joined.

本発明の他の目的は、封着部の融合不良などに起因する
リークパスの発生を低減させることが可能な半田面接合
方法を提供することにある。
Another object of the present invention is to provide a solder surface bonding method that can reduce the occurrence of leak paths due to poor fusion of the sealing portions.

本発明のさらに他の目的は、外囲器の封着部および放熱
用接着部などにおけるボイドの発生を防止して、動作の
信頼性を向上させた半導体集積回路装置を提供すること
にある。
Still another object of the present invention is to provide a semiconductor integrated circuit device in which the occurrence of voids in the sealed portion of the envelope, the heat dissipation adhesive portion, etc. is prevented, and the reliability of operation is improved.

本発明の前記ならびにその他の目的と新規な特徴は、本
明細書の記述および添付図面から明らかになるであろう
The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

3課題を解決するための手段〕 本願において開示される発明のうち、代表的なものの概
要を簡単に説明すれば、下記のとおりである。
Means for Solving the Three Problems] Among the inventions disclosed in this application, a brief overview of typical inventions is as follows.

すなわち、本発明になる半田面接合方法は、複数の被接
合物を半田を介して接合、する半田面接合方法であって
、複数の異なる組成の半田からなり、溶融拡散して均一
化した状態にて所望の組成となる半田プリフォームを用
いるようにしたものである。
That is, the solder surface bonding method according to the present invention is a solder surface bonding method in which a plurality of objects to be bonded are bonded via solder, and is made of a plurality of solders having different compositions, which are melted and diffused into a uniform state. A solder preform having a desired composition is used.

また、本発明になる半田面接合方法は、複数の被接合物
を半田を介して接合する半田面接合方法であって、被接
合物の接合面に、半田の高融点成分からなる第1の層を
半田の低融点成分からなる第2の層によって挟んだ三層
構造を呈する予備半田を被着させ、当該予備半田を融合
させて被接合物の接合を行うようにしたものである。
Further, the solder surface joining method according to the present invention is a solder surface joining method in which a plurality of objects to be joined are joined via solder, in which a first material made of a high melting point component of solder is applied to the bonding surfaces of the objects to be joined. Preliminary solder having a three-layer structure in which a layer is sandwiched between a second layer made of a low melting point component of solder is applied, and the objects to be bonded are bonded by fusing the preliminary solder.

また、本発明になる半導体集積回路装置は、半導体集積
回路素子が封入される外囲器の封着部および放熱用接着
部の少なくとも一方に、請求項1゜2.3,4,5.6
または7記載の半田面接合方法を用いたものである。
Further, the semiconductor integrated circuit device according to the present invention has a structure in which at least one of the sealing part and the heat dissipation bonding part of the envelope in which the semiconductor integrated circuit element is encapsulated has the following features.
Alternatively, the solder surface bonding method described in 7 is used.

〔作用〕[Effect]

上記した本発明の半田面接合方法によれば、たとえば、
被接合物に対向する主面の中央部が低融点半田、周辺部
が高融点半田からなる半田プリフォームを被接合物の間
に介在させることにより、接合時の加熱に際して、まず
低融点半田からなる接合面の中央部に溶融領域が形成さ
れ、当該溶融領域が順次外側へと拡大してゆく状態とな
るので、接合部の隙間などに存在する気体は、中央部か
ら外周部へ溶は拡がる低融点半田の波によって確実に接
合面の外部に排除され、接合面における気泡などの残留
によるボイドの発生を確実に防止することができる。
According to the solder surface joining method of the present invention described above, for example,
By interposing a solder preform between the objects to be welded, the central part of the main surface facing the object to be joined is made of low melting point solder and the peripheral area is made of high melting point solder, so that when heating during bonding, the low melting point solder is first A molten region is formed in the center of the joint surface, and the molten region gradually expands outward, so that the gas present in the gap between the joints spreads from the center to the outer periphery. The waves of the low melting point solder are reliably expelled to the outside of the bonding surface, and the generation of voids due to residual air bubbles on the bonding surface can be reliably prevented.

また、上記した本発明の半田面接合方法によれば、加熱
処理に際して、低融点の第2の層が相互に接する予備半
田の境界部および第2の層が接する予備半田と被接合物
との境界部から溶融が始まるので、予備半田の境界部お
よび予備半田と被接合物との境界部の融合が確実性われ
、融合不良に起因した封着部におけるリークパスの発生
を確実に防止することができる。
Further, according to the above-described solder surface joining method of the present invention, during the heat treatment, the boundary portion of the preliminary solder where the low melting point second layers are in contact with each other, and the boundary portion between the preliminary solder and the object to be joined where the second layer is in contact with each other. Since melting starts from the boundary, it is possible to ensure the fusion of the preliminary solder boundary and the boundary between the preliminary solder and the object to be joined, and to reliably prevent the occurrence of leak paths in the sealed portion due to poor fusion. can.

また、上記した本発明になる半導体集積回路装置によれ
ば、半導体集積回路素子が封入される外囲器の封着部お
よび放熱用接着部などにおけるボイドの発生が確実に回
避されるので、放熱用接着部における伝熱抵抗の増大に
起因する半導体集積回路素子の過熱や、外囲器の封着部
に形成されるリークパスによる気密性能の劣化が回避さ
れ、動作の信頼性が向上する。
Further, according to the semiconductor integrated circuit device of the present invention described above, the generation of voids in the sealing part of the envelope in which the semiconductor integrated circuit element is encapsulated, the adhesive part for heat dissipation, etc. is reliably avoided, so that the heat dissipation is prevented. Overheating of the semiconductor integrated circuit element due to an increase in heat transfer resistance at the adhesive part and deterioration of airtightness due to a leak path formed in the sealed part of the envelope are avoided, and operational reliability is improved.

〔実施例1〕 以下、図面を参照しながら、本発明の一実施例である半
田面接合方法の一例を詳細に説明する。
[Example 1] Hereinafter, an example of a solder surface bonding method which is an embodiment of the present invention will be described in detail with reference to the drawings.

第1図は、本発明の一実施例である半田面接合方法の一
例を模式的に示す接合部の略断面図であり、第2図は、
その要部を取り出して示す斜視図である。
FIG. 1 is a schematic cross-sectional view of a joint portion schematically showing an example of a solder surface joining method according to an embodiment of the present invention, and FIG.
FIG. 3 is a perspective view showing the main parts thereof.

被接合物1および被接合物2の互いに対向する接合面の
各々には、たとえば、Cr−Cu−AuまたはT i 
−N 1−Au、 W−N 1−Auなどの3層構造を
呈するメタライズ層3およびメタライズ層4が形成され
ており、後述の半田に対する濡れ性を向上させている。
For example, Cr-Cu-Au or Ti
A metallized layer 3 and a metallized layer 4 having a three-layer structure such as -N1-Au and W-N1-Au are formed to improve wettability with solder, which will be described later.

そして、被接合物1と2との間には、接合時に板状の半
田プリフォーム5が挟持される。
A plate-shaped solder preform 5 is held between the objects 1 and 2 during bonding.

この場合、前記被接合物1と被接合物2との間に介在す
る半田プリフォーム5は、第1図および第2図などに示
されるように、当該被接合物1および2のメタライズ@
3および4が形成されすこ接合面に臨む主面の中央部が
低融点半田5aで構成され、この低融点半田5aを取り
囲む周辺部が高融点半田5bで構成されている。
In this case, as shown in FIGS. 1 and 2, the solder preform 5 interposed between the objects 1 and 2 is metallized by the objects 1 and 2.
3 and 4 are formed and the central part of the main surface facing the joint surface is made of low melting point solder 5a, and the peripheral part surrounding this low melting point solder 5a is made of high melting point solder 5b.

すなわち、半田プリフォーム5が、たとえばPb / 
S n系の半田の場合には、中央部の低融点半田5aと
して、PbとSnの組成比がたとえ+f 7;3または
4:6などの半田を用い、周辺部の高融点半田5bとし
ては、たとえば95:5また(より:1などの半田を用
いる。
That is, the solder preform 5 is made of, for example, Pb/
In the case of Sn-based solder, a solder with a composition ratio of Pb and Sn of +f7;3 or 4:6 is used as the low melting point solder 5a in the center, and as the high melting point solder 5b in the periphery. For example, 95:5 or (more than:1) solder is used.

そして、両者が均一に融合した状態において、Pb、:
!:Snの組成比が、目的の半田面接合の用途に適した
、たとえば9:1となるように、半田プリフォーム5を
構成する低融点半田5aと高融つ。
Then, in a state where both are uniformly fused, Pb:
! :Sn is highly melted with the low melting point solder 5a constituting the solder preform 5 so that the composition ratio of Sn is 9:1, for example, suitable for the intended use of solder surface bonding.

半田5bの量を設定する。Set the amount of solder 5b.

以下、本実施例の作用の一例を説明する。An example of the operation of this embodiment will be described below.

まず、被接合物1と被接合物2との間に、前述のような
構造の半田プリフォーム5を挟持させ、所定の押圧荷重
を作用させて密着させながら目的の温度まで昇温する。
First, the solder preform 5 having the structure described above is sandwiched between the objects 1 and 2 to be bonded, and the temperature is raised to a target temperature while applying a predetermined pressing load to bring them into close contact.

この時、従来のように−様な組成の半田プリフォームを
用いる場合には、接合部の全域においてほぼ同時に溶は
始めるため、内部側の間隙に滞留していた気体が接合部
に閉じ込められた状態となって有害なボイドを形成する
ことが懸念される。
At this time, when using a solder preform with a similar composition as in the past, melting begins almost simultaneously in the entire area of the joint, so the gas that had accumulated in the internal gap becomes trapped in the joint. There is concern that this could lead to the formation of harmful voids.

これに対して、本冥施例の場合には、昇温過程では、半
田プリフォーム5において、まず融点のより低い中央部
の低融声半田5aから溶融が始まり、メタライズ層3お
よび4との接合に寄与するとともに、溶融して低融点半
田5aと高融点半田5bとの濃度差により成分の熱拡販
が生じ、低融点半田5aに接する周辺部の高融点半田5
bの融点が順次低下するため、溶融領域は半田プリフォ
ーム5の中央部、すなわち接合部の中心部から外周部に
向かって徐々に拡大する。
On the other hand, in the case of this embodiment, in the temperature rising process, melting starts from the low melting sound solder 5a in the central part, which has a lower melting point, in the solder preform 5, and the melting starts from the low melting sound solder 5a in the central part, which has a lower melting point. In addition to contributing to bonding, heat sales of the components occur due to the concentration difference between the low melting point solder 5a and the high melting point solder 5b by melting, and the high melting point solder 5 in the peripheral area in contact with the low melting point solder 5a.
Since the melting point of b gradually decreases, the melted region gradually expands from the center of the solder preform 5, that is, the center of the joint, toward the outer periphery.

これにより、被接合物1および2と半田プリフォーム5
との間隙に滞留していた気体は、中央部から外周部へと
溶は拡がる半田の彼によって外部に押し出され、接合部
から確実に排除されるので、接合部におけるボイドの発
生が確実に防止される。
As a result, objects to be joined 1 and 2 and solder preform 5
The gas remaining in the gap between the solder and the solder is pushed out by the solder, which spreads from the center to the outer periphery, and is reliably removed from the joint, thereby reliably preventing voids from forming at the joint. be done.

そして、溶融状態では、低融点半田5aと高融点半田5
bとが均一に溶は合って目的の組成の半田となるので、
被接合物1と2との接合部を目的の強度などの物性とす
ることができる。
In the molten state, the low melting point solder 5a and the high melting point solder 5
b and melt together uniformly to form solder with the desired composition,
The bonded portion between the objects 1 and 2 to be bonded can have desired physical properties such as strength.

この結果、たとえば、被接合物1および2が、それぞれ
第11図に示される半導体ベレ・ソト300およびキャ
ンプ400の場合には、熱伝導接合部を構成する半田層
にボイドが存在しないため、所期の設計値からの伝熱抵
抗の増大がなく、半導体ベレ7)300からキャンプ4
00の側への放熱が確実に行われ、動作中に半導体ベレ
7)300が過熱することが防止される。
As a result, for example, when the objects 1 and 2 to be bonded are semiconductor bere-soto 300 and camp 400 shown in FIG. There is no increase in heat transfer resistance from the design value of the semiconductor beam 7) from 300 to camp 4.
Heat dissipation to the 00 side is ensured, and the semiconductor plate 7) 300 is prevented from overheating during operation.

また、被接合物lおよび2が、それぞれ第11図に示さ
れるパッケージベース100およびキャンプ400の場
合には、封着部に発生したボイドに起因するリークパス
の形成が確実に防止され、マイクロチップキャリヤなど
の外囲器の気密保持性能が良好となり、外部から湿気の
侵入による半導体ペレ7)300などの腐食などが確実
に防止される。
Further, when the objects 1 and 2 to be bonded are the package base 100 and the camp 400 shown in FIG. The airtightness of the envelope is improved, and corrosion of the semiconductor pellet 7) 300 due to moisture intrusion from the outside is reliably prevented.

これにより、マイクロチップキャリヤなどの外囲器に半
導体ベレット300を封入して構成される半導体集積回
路装置の動作の信頼性が向上する。
This improves the operational reliability of a semiconductor integrated circuit device configured by enclosing the semiconductor pellet 300 in an envelope such as a microchip carrier.

〔実施例2〕 第3図および第4図は、本発明の他の実施例である半田
面接合方法を模式適に示す断面図および斜視図である。
[Embodiment 2] FIGS. 3 and 4 are a sectional view and a perspective view schematically showing a solder surface bonding method according to another embodiment of the present invention.

すなわち、本実施例2の場合には、半田プリフォーム6
として、中心部の融点M6aの低融点半田6aと最外周
部の融点M6dの高融点半田6dとの間に、融点を多段
階に変化させた半田領域6b、半田領域6Cを設け、各
々の融点M6bおよび融点M6cが、M6cl>M6 
c>M6 b>M6aとなるようにしたものである。
That is, in the case of the second embodiment, the solder preform 6
As such, a solder region 6b and a solder region 6C whose melting points are changed in multiple stages are provided between a low melting point solder 6a having a melting point M6a in the center and a high melting point solder 6d having a melting point M6d in the outermost periphery. M6b and melting point M6c are M6cl>M6
c>M6 b>M6a.

これにより、本実施例2の場合にも、昇温操作において
、半田プリフォーム6の中心部から外周部へと溶融領域
が拡大する状態となるので、前記実施例1の場合と同様
の効果を得ることができる。
As a result, in the case of the second embodiment, the melting region expands from the center to the outer periphery of the solder preform 6 during the temperature raising operation, so that the same effect as in the first embodiment can be obtained. Obtainable.

〔実施例3〕 第5図および第6図は、本発明のさらに他の実施例であ
る半田面接合方法の一例を模式的に示す略断面図および
斜視図である。
[Embodiment 3] FIGS. 5 and 6 are a schematic sectional view and a perspective view schematically showing an example of a solder surface bonding method according to yet another embodiment of the present invention.

本実施例3の場合には、半田プリフォーム7を構成する
中心部の低融点半田7aの厚さを周辺部の高融点半田7
bの厚さよりも大きくしたものである。
In the case of the third embodiment, the thickness of the low melting point solder 7a in the center part of the solder preform 7 is set to the thickness of the high melting point solder 7a in the peripheral part.
The thickness is larger than that of b.

これにより、中心部の低融点半田7aが周囲の高融点半
田7bより突出した状態となり、半田プリフォーム7を
介して被接合物1と2とを重ね合わせた時に、当該被接
合物1および2のメタライズ層3および4に接した状態
となるため、半田プリフォーム7の中心部を構成する低
融点半田7aからの溶融および溶融領域の拡大がより確
実に行われ、前記実施例1の場合と同様の効果を得るこ
とができる。
As a result, the low melting point solder 7a in the center protrudes from the surrounding high melting point solder 7b, and when the objects 1 and 2 are overlapped via the solder preform 7, the objects 1 and 2 Since the solder preform 7 is in contact with the metallized layers 3 and 4, the melting from the low melting point solder 7a constituting the center part of the solder preform 7 and the expansion of the melted area are performed more reliably, which is different from the case of the first embodiment. A similar effect can be obtained.

〔実施例4〕 第7図は、本発明のさらに他の実施例である半田面接合
方法の一例を模式的に示す断面図である。
[Embodiment 4] FIG. 7 is a sectional view schematically showing an example of a solder surface bonding method according to yet another embodiment of the present invention.

本実施例4の場合には、半田プリフォーム8として、板
状の高融点半田8bの表裏両面の中央部に、低融点半田
8aを張り合わせた、いわゆるクランド材を用いるよう
にしたものである。
In the case of the fourth embodiment, a so-called crand material is used as the solder preform 8, which is a plate-shaped high melting point solder 8b and a low melting point solder 8a bonded to the center of both the front and back surfaces.

これにより、昇温時に中央部の低融点半田8aから溶は
始めるので前記実施例1の場合と同様の効果が得られる
とともに、半田プリフォーム8としてクラッド材を用い
ることにより、当該半田プリフォーム8の製造原価を削
減することができるという利点がある。
As a result, melting starts from the low melting point solder 8a in the center when the temperature rises, so the same effect as in the first embodiment can be obtained, and by using a clad material as the solder preform 8, the solder preform 8 It has the advantage of reducing manufacturing costs.

なお、クラッド材としては、第7図に示した3層構造の
ものに限らず、第8図に示されるように、4層以上の構
造としてもよい。すなわち、同図の場合には、半田プリ
フォーム9として、板状の高融点半田9dの両主面の中
央部に、順次融点および面積が小さくなる低融点半田9
c、9b、9aを重ねて貼り合わせたクラッド材を用い
たものである。
Note that the clad material is not limited to the three-layer structure shown in FIG. 7, but may have a four-layer or more structure as shown in FIG. 8. That is, in the case of the figure, as the solder preform 9, low melting point solder 9 whose melting point and area gradually decrease is placed in the center of both main surfaces of the plate-shaped high melting point solder 9d.
It uses a clad material made by stacking and bonding layers c, 9b, and 9a.

〔実施例5〕 第9図は、本発明のさらに他の実施例である半田面接合
方法の一例を示す一部破断斜視図である。
[Embodiment 5] FIG. 9 is a partially cutaway perspective view showing an example of a solder surface bonding method according to still another embodiment of the present invention.

本実施例5の場合は、被接合物lおよび2が、それぞれ
、たとえば第11図に示されるパンケーンベース100
およびキャップ400である場合を示している。
In the case of the fifth embodiment, the objects 1 and 2 to be bonded are, for example, the Pancaen base 100 shown in FIG.
and a cap 400 are shown.

すなわち、この場合には、半田プリフォーム10は、封
着部の形状に合わせて額縁状を呈することになるが、本
実施例5では、半田プリフォームIOとして、額縁状の
幅の広い高融点半田tabの両主面の中央部に沿って、
同じく額縁状の幅の狭い低融点半田10aを張り合わせ
たものを用し)るようにしたものである。
That is, in this case, the solder preform 10 takes on a frame shape in accordance with the shape of the sealing part, but in the present embodiment 5, the solder preform IO has a frame shape with a wide width and a high melting point. Along the center of both main surfaces of the solder tab,
Similarly, a narrow frame-shaped low melting point solder 10a is pasted together.

これにより、被接合物1および2であるパッケージベー
ス100およびキャップ400の封着部の全長において
、当該封着部の中央部に位置する低融点半田10aがパ
ッケージの内外両方向に溶は拡がる状態となり、封着部
における残留気泡などによるボイドの発生を防止できる
As a result, over the entire length of the sealed parts of the package base 100 and the cap 400, which are the objects 1 and 2, the low melting point solder 10a located at the center of the sealed parts spreads in both directions inside and outside the package. , it is possible to prevent the generation of voids due to residual air bubbles in the sealed portion.

この結果、複数のボイドなどを連通して形成されるτ↓
−クバスが無くなり、マイクロチップキャリヤなどの外
囲器の気密保持性能が良好となり、外部から湿気の侵入
による半導体ペレット300などの腐食などが確実に防
止される。
As a result, τ↓ is formed by connecting multiple voids, etc.
- The airtightness of the envelope such as the microchip carrier is improved, and corrosion of the semiconductor pellet 300 due to the intrusion of moisture from the outside is reliably prevented.

〔実施例6〕 第10図は、本発明のさらに他の実施例である半田面接
合方法の一例を示す断面図である。
[Embodiment 6] FIG. 10 is a sectional view showing an example of a solder surface bonding method according to still another embodiment of the present invention.

本実施例6の場合には、パッケージベース100および
キャップ400の各々の新着面に形成されているメタラ
イズ層3a(4a)の上に、たとえば、P b/S r
+系の半田の場合には、高融点成分であるPbまたはp
bにSnを含む合金からなる中央の第1の層11aを挟
むように、低融点成分であるSnからなる第2の層11
bおよび11Cを形成して予備半田11としたものであ
る。
In the case of the sixth embodiment, for example, P b /S r
In the case of + type solder, the high melting point component Pb or p
A second layer 11 made of Sn, which is a low melting point component, is sandwiched between the central first layer 11a made of an alloy containing Sn in b.
b and 11C are formed to serve as preliminary solder 11.

なお、この予備半田11の形成方法としては、たとえば
、パンケージベース100およびキヤ。
The preliminary solder 11 can be formed using, for example, the pan cage base 100 and the carrier.

プ400のメタライズ層3a(4a)の上にSnおよび
Pbを交互に蒸着させるか、または、Pbを芯材としS
nを被覆材とするクラッド材を被着させるなどの方法が
ある。
Sn and Pb are alternately vapor-deposited on the metallized layer 3a (4a) of the metallized layer 3a (4a) of the metallized layer 400, or S
There are methods such as applying a cladding material using n as a covering material.

これにより、低融点のSnからなる第2の層llbが被
接合物であるパッケージベース100 (キャンプ40
0)のメタライズ層3a(4a)に接するとともに、組
立を行うべくパッケージベース100とキャンプ400
とを重ねた場合には、相互の予備半田11の最上層であ
る第2の層11C同士が接する状態となる。
As a result, the package base 100 (camp 40
The package base 100 and the camp 400 are in contact with the metallized layer 3a (4a) of 0) and for assembly.
When these are overlapped, the second layers 11C, which are the uppermost layers of the preliminary solder 11, are in contact with each other.

そして、その状態で封着のための加熱を行うと、パッケ
ージベース100およびキャップ400の各々の予備半
田11の境界となっている低融点の第2の層11Cおよ
びメタライズ層3a(4a)と接している第2の層11
bの部分から溶融が開始される。
When heating is performed for sealing in this state, the second layer 11C with a low melting point and the metallized layer 3a (4a) forming the boundary between the preliminary solder 11 of the package base 100 and the cap 400 come into contact with each other. second layer 11
Melting starts from part b.

この結果、たとえば予備半田11を均一な組成の半田で
構成する場合のように、当該予備半田の境界部などにお
ける融合不良の発生が確実に防止され、パッケージベー
ス100とキャップ400との封着部に気密性を損なう
リークバスが形成されることが回避される。
As a result, for example, when the preliminary solder 11 is composed of solder with a uniform composition, the occurrence of poor fusion at the boundary between the preliminary solder and the like is reliably prevented, and the sealing area between the package base 100 and the cap 400 is reliably prevented. This prevents the formation of leakage baths that impair the airtightness.

これにより、パッケージベース100およびキャンプ4
00を相互に封着して構成されるマイクロチップキャリ
ヤなどの外囲器における気密性の維持性能が向上し、当
該マイクロチップキャリヤ内に半導体ペレット300を
封入して構成される半導体集積回路装置の動作の信頼性
が向上する。
As a result, Package Base 100 and Camp 4
The performance of maintaining airtightness in an envelope such as a microchip carrier that is formed by sealing 00 to each other is improved, and the semiconductor integrated circuit device that is formed by encapsulating a semiconductor pellet 300 in the microchip carrier is improved. Operational reliability is improved.

以上本発明者によってなされた発明を実施例に基づき具
体的に説明したが、本発明は前記実施例に限定されるも
のではなく、その要旨を逸脱しない範囲で種々変更可能
であることはいうまでもない。
Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the Examples and can be modified in various ways without departing from the gist thereof. Nor.

たとえば、被接合物を相互に接続する半田としては、P
 b / S n系やAu/″Sn系などに限らず、他
の低融点□金属を用いたものであってもよい。
For example, as solder for interconnecting objects to be bonded, P
It is not limited to b/Sn type or Au/''Sn type, but may be one using other low melting point □ metals.

また、半田としては、P b / S n系やA u 
/ Sn系などの2元系合金に限らず3元以上の合金系
であってもよい。
In addition, as solder, P b /S n type and A u
/ It is not limited to binary alloys such as Sn-based alloys, but may be ternary or higher alloys.

〔発明の効果〕〔Effect of the invention〕

本願において開示される発明のうち、代表的なものによ
って得られる効果を簡単に説明すれば、以下のとおりで
ある。
Among the inventions disclosed in this application, the effects obtained by typical inventions are briefly described below.

すなわち、本発明になる半田面接合方法によれば、複数
の被接合物を半田を介して接合する半田面接合方法であ
って、複数の異なる組成の半田からなり、溶融拡散して
均一化した状態にて所望の組成となる半田プリフォーム
を用いるので、たとえば、被接合物に対向する主面の中
央部が低融点半田、周辺部が高融点半田からなる半田プ
リフォームを被接合物の間に介在させることにより、接
合時の加熱に際して、まず低融点半田からなる接合面の
中央部に溶融領域が形成され、当該溶融領域が順次外側
へと拡大してゆく状態となり、接合部の隙間などに存在
する気体は、中央部から外1胃部へ溶は拡がる低融点半
田の波によって確実に接合面の外部に排除され、接合面
における気泡などの残留によるボイドの発生を確実に防
止することができる。
That is, according to the solder surface bonding method of the present invention, a plurality of objects to be bonded are bonded via solder. Since we use a solder preform that has a desired composition depending on the condition, for example, a solder preform whose main surface facing the objects to be welded has a low melting point solder in the central part and a high melting point solder in the peripheral part is placed between the objects to be welded. By intervening the solder, during heating during bonding, a molten region is first formed in the center of the joint surface made of low melting point solder, and the molten region gradually expands outward, causing gaps in the joint, etc. The gas present in the bonding surface is reliably expelled from the bonding surface by the waves of low melting point solder that spread from the center to the outside, thereby reliably preventing the generation of voids due to residual air bubbles, etc. on the bonding surface. I can do it.

また、本発明になる半田面接合方法によれば、複数の被
接合物を半田を介して接合する半田面接合方法であって
、前記被接合物の接合面に、前記半田の高融点成分から
なる第1の層を前記半田の低融点成分からなる第2の層
によって挟んだ三1構造を呈する予備半田を被着させ、
当該予備半田を融合させて前記被接合物の接合を行うの
で、加熱処理に際して、低融点の第2の層が相互に接す
る予備半田の境界部および第2の層が接する予備半田と
被接合物との境界部から溶融が始まり、予備半田の境界
部および予備半田と被接合物との境界部の融合が確実に
行われ、融合不良に起因した封着部におけるリークバス
の発生を確実に防止することができる。
Further, according to the solder surface joining method of the present invention, a plurality of objects to be bonded are bonded via solder, wherein the bonding surface of the objects to be bonded is coated with a high melting point component of the solder. depositing a preliminary solder exhibiting a 31 structure in which a first layer consisting of the above solder is sandwiched between a second layer consisting of a low melting point component of the solder;
Since the objects to be joined are bonded by fusing the preliminary solder, during the heat treatment, the boundary portion of the preliminary solder where the second layer with a low melting point is in contact with each other, and the preliminary solder and the object to be joined where the second layer is in contact are Melting begins at the boundary between the pre-solder and the object to be welded, ensuring that the pre-solder and the pre-solder interface with the object to be welded are fused, reliably preventing the occurrence of a leak bath at the sealing part due to poor fusion. be able to.

また、本発明になる半導体集積回路装置によれば、半導
体集積回路素子が封入される外囲器の封着部および放熱
用接着部の少なくとも一方に、請求項1,2,3,4,
5.6または7記載の半田面接合方法を用いるので、半
導体集積回路素子が封入される外囲器の封着部および放
熱用接着部などにおけるボイドの発生が確実に回避され
、放熱用接着部における伝熱抵抗の増大に起因する半導
体集積回路素子の過熱や、外囲器の封着部に形成される
リークパスによる気密性能の劣化が回避され、動作の信
頼性が向上する。
Further, according to the semiconductor integrated circuit device of the present invention, at least one of the sealing part and the heat dissipation adhesive part of the envelope in which the semiconductor integrated circuit element is sealed includes the following claims 1, 2, 3, 4,
Since the solder surface bonding method described in 5.6 or 7 is used, the generation of voids in the sealing part of the envelope in which the semiconductor integrated circuit element is sealed, the heat dissipation adhesive part, etc. is reliably avoided, and the heat dissipation adhesive part Overheating of the semiconductor integrated circuit element due to an increase in heat transfer resistance in the semiconductor integrated circuit element and deterioration of airtightness due to a leak path formed in the sealed portion of the envelope are avoided, and operational reliability is improved.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例である半田面接合方法の一例
を模式的に示す接合部の略断面図、第2図はその要部を
取り出して示す斜視図、第3図は本発明の実施例2であ
る半田面接合方法の一例を模式的に示す接合部の略断面
図、第4図はその要部を取り出して示す斜視図、第5図
は本発明の実施例3である半田面接合方法の一例を模式
的に示す接合部の略断面図、第6図はその要部を取り出
して示す斜視図、第7図は、本発明の実施例4である半
田面接合方法を説明する断面図、 第8図はその変形例を示す略断面図、 第9図は、本発明の実施例5である半田面接合方法の一
例を示す斜視図、 第10図は、本発明の実施例6である半田面接合方法の
一例を示す断面図、 第11図は、半導体集積回路装置の封止構造の一例を示
す図である。 1.2・・・被接合物、3,4.3a、4a・・メタラ
イズ層、5・・・半田ブリフ・オーム、5a・・・低融
点半田、5b・・・高融点半田、6・・・半田プリフォ
ーム、6a・・・低融点半田、6b、6c・・・半田領
域、6d・・・高融点半田、7・・・半田プリフォーム
、7a・・・低融点半田、7b・・・高融点半田、8・
・・半田プリフォーム、8a・・・低融点半田、8b・
・・高融点半田、9・・・半田プリフォーム、9a・・
・低融点半田、9d・・・高融点半田、10・・・半田
プリフォーム、10a・・・低融点半田、10b・・・
高融点半田、11・・・予備半田、11a・・・第1の
層、ltb、IIC・・・第2の層、100・・・パッ
ケージベース、200・・・半田バンブ、300・・・
半導体ベレット、400・・・キャンプ、500・・・
半田バンブ。 第5図
Fig. 1 is a schematic cross-sectional view of a joint portion schematically showing an example of a solder surface joining method according to an embodiment of the present invention, Fig. 2 is a perspective view showing the main parts taken out, and Fig. 3 is a diagram of the present invention. Embodiment 2 A schematic cross-sectional view of a joint portion schematically showing an example of a solder surface bonding method according to Embodiment 2, FIG. 4 is a perspective view showing the main parts taken out, and FIG. FIG. 6 is a schematic cross-sectional view of a joint portion schematically showing an example of a solder surface bonding method, FIG. 6 is a perspective view showing the main parts thereof, and FIG. 8 is a schematic sectional view showing a modified example thereof; FIG. 9 is a perspective view showing an example of a solder surface bonding method according to Embodiment 5 of the present invention; FIG. 10 is a schematic sectional view showing a modification thereof; FIG. 11 is a cross-sectional view showing an example of the solder surface bonding method according to the sixth embodiment. FIG. 11 is a diagram showing an example of the sealing structure of a semiconductor integrated circuit device. 1.2... object to be joined, 3, 4.3a, 4a... metallized layer, 5... solder brief ohm, 5a... low melting point solder, 5b... high melting point solder, 6...・Solder preform, 6a...Low melting point solder, 6b, 6c...Solder area, 6d...High melting point solder, 7...Solder preform, 7a...Low melting point solder, 7b... High melting point solder, 8.
...Solder preform, 8a...Low melting point solder, 8b.
...High melting point solder, 9...Solder preform, 9a...
・Low melting point solder, 9d...High melting point solder, 10...Solder preform, 10a...Low melting point solder, 10b...
High melting point solder, 11... Preliminary solder, 11a... First layer, ltb, IIC... Second layer, 100... Package base, 200... Solder bump, 300...
Semiconductor pellet, 400...Camp, 500...
Handa bang. Figure 5

Claims (1)

【特許請求の範囲】 1、複数の被接合物を半田を介して接合する半田面接合
方法であって、複数の異なる組成の半田からなり、溶融
拡散して均一化した状態にて所望の組成となる半田プリ
フォームを用いる半田面接合方法。 2、前記半田プリフォームの前記被接合物に対向する主
面の中央部が低融点半田、周辺部が高融点半田からなる
ことを特徴とする請求項1記載の半田面接合方法。 3、前記半田プリフォームの前記被接合物に対向する主
面の中央部の前記低融点半田の厚さを周辺部の前記高融
点半田よりも厚くしたことを特徴とする請求項2記載の
半田面接合方法。 4、前記半田プリフォームが、板状の高融点半田の前記
被接合物に対向する主面の中央部に板状の低融点半田を
被着させてなることを特徴とする請求項1記載の半田面
接合方法。 5、複数の被接合物を半田を介して接合する半田面接合
方法であって、前記被接合物の接合面に、前記半田の高
融点成分からなる第1の層を前記半田の低融点成分から
なる第2の層によって挟んだ三層構造を呈する予備半田
を被着させ、当該予備半田を融合させて前記被接合物の
接合を行うことを特徴とする半田面接合方法。 6、前記三層構造を呈する前記予備半田が、蒸着または
メッキによって形成されることを特徴とする請求項5記
載の半田面接合方法。 7、三層構造を呈する前記予備半田が、前記半田の高融
点成分からなる第1の層を前記半田の低融点成分からな
る第2の層で挟んだ三層構造を呈するクラッド材からな
ることを特徴とする請求項5記載の半田面接合方法。 8、半導体集積回路素子が封入される外囲器の封着部お
よび放熱用接着部の少なくとも一方に、請求項1、2、
3、4、5、6または7記載の半田面接合方法を用いて
なる半導体集積回路装置。
[Scope of Claims] 1. A solder surface joining method for joining a plurality of objects to be joined through solder, which comprises a plurality of solders of different compositions, which are melted and diffused to be uniform in a desired composition. A solder surface joining method using a solder preform. 2. The solder surface joining method according to claim 1, wherein the center portion of the main surface of the solder preform facing the object to be joined is made of low melting point solder, and the peripheral portion is made of high melting point solder. 3. The solder according to claim 2, wherein the low melting point solder is thicker in the central part of the main surface of the solder preform facing the object to be joined than the high melting point solder in the peripheral part. Face-to-face meeting method. 4. The solder preform according to claim 1, wherein the solder preform is formed by attaching a plate-shaped low-melting-point solder to the center of the main surface of the plate-shaped high-melting-point solder facing the object to be joined. Solder surface joining method. 5. A solder surface bonding method for joining a plurality of objects to be bonded via solder, wherein a first layer made of a high melting point component of the solder is applied to a bonding surface of the objects to be bonded using a low melting point component of the solder. 1. A method for joining solder surfaces, comprising: depositing preliminary solder having a three-layer structure sandwiched between second layers consisting of second layers, and fusing the preliminary solder to join the objects to be joined. 6. The solder surface joining method according to claim 5, wherein the preliminary solder exhibiting the three-layer structure is formed by vapor deposition or plating. 7. The preliminary solder exhibiting a three-layer structure is made of a cladding material exhibiting a three-layer structure in which a first layer consisting of a high melting point component of the solder is sandwiched between a second layer consisting of a low melting point component of the solder. The solder surface joining method according to claim 5, characterized in that: 8. At least one of the sealing part and the heat radiation adhesive part of the envelope in which the semiconductor integrated circuit element is sealed,
8. A semiconductor integrated circuit device using the solder surface bonding method according to 3, 4, 5, 6 or 7.
JP18436889A 1989-07-17 1989-07-17 Solder surface joining method and semiconductor integrated circuit device using its method Pending JPH0347673A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18436889A JPH0347673A (en) 1989-07-17 1989-07-17 Solder surface joining method and semiconductor integrated circuit device using its method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18436889A JPH0347673A (en) 1989-07-17 1989-07-17 Solder surface joining method and semiconductor integrated circuit device using its method

Publications (1)

Publication Number Publication Date
JPH0347673A true JPH0347673A (en) 1991-02-28

Family

ID=16152003

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18436889A Pending JPH0347673A (en) 1989-07-17 1989-07-17 Solder surface joining method and semiconductor integrated circuit device using its method

Country Status (1)

Country Link
JP (1) JPH0347673A (en)

Cited By (9)

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Publication number Priority date Publication date Assignee Title
JPH0596395A (en) * 1991-10-04 1993-04-20 Mitsubishi Electric Corp Joining material, joining method and semiconductor equipment
JP2007109834A (en) * 2005-10-13 2007-04-26 Fuji Electric Holdings Co Ltd Semiconductor device and method of manufacturing same
JP2007243118A (en) * 2006-03-13 2007-09-20 Fuji Electric Holdings Co Ltd Semiconductor device
JP2008181940A (en) * 2007-01-23 2008-08-07 Mitsubishi Materials Corp Production process of substrate for power module and substrate for power module and power module
JP2008277335A (en) * 2007-04-25 2008-11-13 Fuji Electric Device Technology Co Ltd Semiconductor device and its manufacturing process
JP2009164016A (en) * 2008-01-08 2009-07-23 Fujitsu Ltd Terminal sheet, manufacturing method of terminal sheet, and semiconductor device
WO2012023899A1 (en) * 2010-08-16 2012-02-23 Agency For Science, Technology And Research Hermetic seal and method of manufacture thereof
JP2015088683A (en) * 2013-11-01 2015-05-07 富士通株式会社 Thermal interface sheet and processor
JP2015110235A (en) * 2013-12-06 2015-06-18 株式会社豊田中央研究所 Brazing structure

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0596395A (en) * 1991-10-04 1993-04-20 Mitsubishi Electric Corp Joining material, joining method and semiconductor equipment
JP2007109834A (en) * 2005-10-13 2007-04-26 Fuji Electric Holdings Co Ltd Semiconductor device and method of manufacturing same
JP2007243118A (en) * 2006-03-13 2007-09-20 Fuji Electric Holdings Co Ltd Semiconductor device
JP2008181940A (en) * 2007-01-23 2008-08-07 Mitsubishi Materials Corp Production process of substrate for power module and substrate for power module and power module
JP4702294B2 (en) * 2007-01-23 2011-06-15 三菱マテリアル株式会社 Power module substrate manufacturing method, power module substrate, and power module
JP2008277335A (en) * 2007-04-25 2008-11-13 Fuji Electric Device Technology Co Ltd Semiconductor device and its manufacturing process
JP2009164016A (en) * 2008-01-08 2009-07-23 Fujitsu Ltd Terminal sheet, manufacturing method of terminal sheet, and semiconductor device
WO2012023899A1 (en) * 2010-08-16 2012-02-23 Agency For Science, Technology And Research Hermetic seal and method of manufacture thereof
JP2015088683A (en) * 2013-11-01 2015-05-07 富士通株式会社 Thermal interface sheet and processor
US9704775B2 (en) 2013-11-01 2017-07-11 Fujitsu Limited Method for manufacturing thermal interface sheet
JP2015110235A (en) * 2013-12-06 2015-06-18 株式会社豊田中央研究所 Brazing structure

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