JPH04103149A - Package sealing method and semiconductor device - Google Patents

Package sealing method and semiconductor device

Info

Publication number
JPH04103149A
JPH04103149A JP22191590A JP22191590A JPH04103149A JP H04103149 A JPH04103149 A JP H04103149A JP 22191590 A JP22191590 A JP 22191590A JP 22191590 A JP22191590 A JP 22191590A JP H04103149 A JPH04103149 A JP H04103149A
Authority
JP
Grant status
Application
Patent type
Prior art keywords
brazing material
layer
formed
cap
preform
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP22191590A
Inventor
Hiroshi Akasaki
Kanji Otsuka
Original Assignee
Hitachi Ltd
Hitachi Vlsi Eng Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date

Links

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73253Bump and layer connectors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161Cap
    • H01L2924/1615Shape
    • H01L2924/16152Cap comprising a cavity for hosting the device, e.g. U-shaped cap

Abstract

PURPOSE: To improve a package sealed part in airtightness by a method wherein a preform brazing material provided with second brazing material layers formed on the front and the rear of an inner first brazing material layer is used, where the first brazing material layer is different from tire second brazing material layer in composition.
CONSTITUTION: A brazing material 5b excellent in wettability formed on both the front and the rear of a preform brazing material 5 is made to come into close contact with a metallization layer 9 formed on the inner face of a cap 4 and another metallization layer 8 formed on the back of a semiconductor element 3 to form a thermal conductive filling layer 11 which joins the back of the semiconductor element 3 and the inner layer of the cap 4 together. A part of a brazing material 5a which serves as the center layer of the preform material 5 and is excellent in airtightness and strength is squeezed out from a gap between the back of the semiconductor element 3 and the cap 4 by a load 10 is made to move along a route shown by an arrow. In result, the brazing material 5a is supplied to a gap between a metallization layer 6 formed on a base 1 and a metallization layer 7 on the cap 4. By this setup, a sealing bonding layer 12 is formed to hermetically seal up the base 1 and the cap 4.
COPYRIGHT: (C)1992,JPO&Japio
JP22191590A 1990-08-23 1990-08-23 Package sealing method and semiconductor device Pending JPH04103149A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP22191590A JPH04103149A (en) 1990-08-23 1990-08-23 Package sealing method and semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP22191590A JPH04103149A (en) 1990-08-23 1990-08-23 Package sealing method and semiconductor device

Publications (1)

Publication Number Publication Date
JPH04103149A true true JPH04103149A (en) 1992-04-06

Family

ID=16774156

Family Applications (1)

Application Number Title Priority Date Filing Date
JP22191590A Pending JPH04103149A (en) 1990-08-23 1990-08-23 Package sealing method and semiconductor device

Country Status (1)

Country Link
JP (1) JPH04103149A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0997938A2 (en) * 1998-07-08 2000-05-03 Hitachi, Ltd. Multi-chip module
US6075289A (en) * 1996-10-24 2000-06-13 Tessera, Inc. Thermally enhanced packaged semiconductor assemblies
EP1998370A3 (en) * 2000-08-31 2011-02-02 Intel Corporation Electronic assembly comprising solderable thermal interface and methods of manufacture

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6075289A (en) * 1996-10-24 2000-06-13 Tessera, Inc. Thermally enhanced packaged semiconductor assemblies
US6354485B1 (en) 1996-10-24 2002-03-12 Tessera, Inc. Thermally enhanced packaged semiconductor assemblies
EP0997938A2 (en) * 1998-07-08 2000-05-03 Hitachi, Ltd. Multi-chip module
EP0997938A3 (en) * 1998-07-08 2002-08-14 Hitachi, Ltd. Multi-chip module
EP1998370A3 (en) * 2000-08-31 2011-02-02 Intel Corporation Electronic assembly comprising solderable thermal interface and methods of manufacture

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