JPH0823002A - Semiconductor device and manufacturing method - Google Patents
Semiconductor device and manufacturing methodInfo
- Publication number
- JPH0823002A JPH0823002A JP6153487A JP15348794A JPH0823002A JP H0823002 A JPH0823002 A JP H0823002A JP 6153487 A JP6153487 A JP 6153487A JP 15348794 A JP15348794 A JP 15348794A JP H0823002 A JPH0823002 A JP H0823002A
- Authority
- JP
- Japan
- Prior art keywords
- solder
- semiconductor device
- plate
- surface treatment
- semiconductor element
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
- H01L2224/26152—Auxiliary members for layer connectors, e.g. spacers being formed on an item to be connected not being a semiconductor or solid-state body
- H01L2224/26175—Flow barriers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体素子と板状部材
とのはんだ接合に係り、特に温度変化に対する信頼性の
高い半導体装置及びその製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solder joint between a semiconductor element and a plate member, and more particularly to a semiconductor device having high reliability against temperature change and a manufacturing method thereof.
【０００２】[0002]
【従来の技術】従来の半導体装置、特に電力制御用の半
導体装置においては、基本的に半導体素子を基板等の板
状部材に積層し、はんだで接合した構造になっている。
ところが一般に半導体素子と板状部材との線膨張係数が
互いに異なっているため、繰返しの温度変化が加わる
と、はんだに繰返しのひずみが発生し、熱疲労破壊する
場合がある。2. Description of the Related Art A conventional semiconductor device, particularly a semiconductor device for power control, basically has a structure in which semiconductor elements are laminated on a plate-like member such as a substrate and joined by soldering.
However, since the linear expansion coefficient of the semiconductor element is generally different from that of the plate-shaped member, repeated strains may cause repeated strains in the solder to cause thermal fatigue failure.
【０００３】一般に、はんだは板状部材に比べて軟らか
いため、温度変化により発生するせん断ひずみの変化量
Δγは（１）式で表される。In general, since solder is softer than a plate-shaped member, the change amount Δγ of shear strain caused by temperature change is expressed by equation (1).
【０００４】 Δγ＝Δα×ΔＴ×Ｌ／２／Ｈ…………………（１） ここで、Δαは２枚の板状部材の線膨張係数の差、ΔＴ
は温度変化、Ｌははんだの接合長さ、Ｈははんだの厚さ
である。この（１）式において、ΔαとＬとは半導体装
置の機能によって決まり、ΔＴは使用条件で決まる。従
って、これらに影響を与えないようにはんだ接合部のひ
ずみを低減するには、はんだ接合部の厚さＨを大きくし
なければならない。Δγ = Δα × ΔT × L / 2 / H (1) where Δα is the difference between the linear expansion coefficients of the two plate members, and ΔT
Is the temperature change, L is the solder joint length, and H is the solder thickness. In this equation (1), Δα and L are determined by the function of the semiconductor device, and ΔT is determined by the usage conditions. Therefore, in order to reduce the strain of the solder joint so as not to affect them, the thickness H of the solder joint must be increased.
【０００５】このように、はんだ接合部のひずみを低減
し、熱疲労破壊を防止する上で最も効果があるのは、は
んだ接合部を厚くすることである。しかし、実際にはは
んだ接合部を厚くするためはんだの量を増やすと、接合
時に融解して周囲に流れ出し、厚さの確保が行われない
ばかりでなく、接合不良となる恐れがある。このため、
従来よりはんだ接合部の厚さを確保するための様々な工
夫がなされてきた。As described above, the thickest solder joint is most effective in reducing the strain of the solder joint and preventing thermal fatigue damage. However, in reality, if the amount of solder is increased in order to increase the thickness of the solder joint, the solder melts at the time of joining and flows out to the surroundings, and not only the thickness is not secured, but also there is a risk of poor joint. For this reason,
Conventionally, various measures have been taken to secure the thickness of solder joints.
【０００６】第１の方法は、互いに接合する２枚の板状
部材の間にスペーサを挿入することであり、特開昭５１
−６８１７８号公報、特開昭５３−５９３６５号公報、
特開昭５３−６１９７３号公報、特開昭５３−１３６４
８０号公報及び特開昭５４−１９３６４号公報等に開示
されている。The first method is to insert a spacer between two plate-like members which are joined to each other.
-68178, JP-A-53-59365,
JP-A-53-61973, JP-A-53-1364
No. 80, JP-A-54-19364, and the like.
【０００７】第２の方法は、互いに接合する板状部材の
一方に突起を設けることであり、特開昭４９−１２３２
７０号公報、特開昭５０−６７５６９号公報、特開昭５
３−５９３６６号公報、特開昭５３−１３９９７４号公
報、特開昭５４−１９６５８号公報及び特開昭５４−６
６０７３号公報等に開示されている。The second method is to provide a protrusion on one of the plate-like members to be joined to each other.
70, JP-A-50-67569, JP-A-5
3-59366, JP-A-53-139974, JP-A-54-19658 and JP-A-54-6.
No. 6073 is disclosed.
【０００８】第３の方法は、はんだの流れ止めを設ける
ことであり、特開昭５４−３７５７４号公報、特開昭５
４−８３７６６号公報及び特開昭６３−２０２９４８号
公報等に開示されている。The third method is to provide a solder flow stopper, which is disclosed in Japanese Patent Laid-Open Nos. 54-37574 and 5 Sho.
It is disclosed in JP-A-4-83766 and JP-A-63-202948.
【０００９】[0009]
【発明が解決しようとする課題】従来の半導体装置にあ
っては、スペーサを挿入する第１の方法は、はんだ接合
部の内部にボイド等の接合欠陥が生じやすく、また、部
品点数の増加を招き製造工程が増加するという問題があ
った。In the conventional semiconductor device, the first method of inserting the spacer is that a joint defect such as a void is likely to occur inside the solder joint, and the number of parts is increased. There is a problem that the number of manufacturing processes increases.
【００１０】突起を設ける第２の方法は、突起の形状を
制御することが困難であり、また金属板にしか適用でき
ないという問題があった。The second method of providing the protrusions has a problem that it is difficult to control the shape of the protrusions and can be applied only to a metal plate.
【００１１】流れ止めを設ける第３の方法は、第１の方
法と同様に部品点数の増加を招き、また製造工程を増加
させるという問題があった。特にこの方法は流れ止め自
体の接合に手間がかかり、これも一般には実用化されて
いない。The third method of providing the flow stop has a problem that the number of parts is increased as in the first method and the number of manufacturing steps is increased. In particular, this method requires much labor to join the flow stop itself, and this method has not been put into practical use in general.
【００１２】本発明の目的は、部品点数を増加すること
なく、はんだ接合部の厚さを確保することができ熱疲労
破壊に対する信頼性の高い半導体装置及びその製造方法
を提供することにある。An object of the present invention is to provide a semiconductor device which can secure the thickness of a solder joint portion without increasing the number of parts and has high reliability against thermal fatigue damage, and a manufacturing method thereof.
【００１３】[0013]
【課題を解決するための手段】前記の目的を達成するた
め、本発明に係る半導体装置は、線膨張係数が異なりか
つ互いにはんだ接合部を介して接合される少なくとも二
つの板状部材を備えた半導体装置において、いずれか一
方の板状部材のはんだ接合面の周囲に表面処理部を形成
し、表面処理部は、接合時にはんだの流出を阻止しては
んだ接合部を所定厚さに保持するものである構成とす
る。In order to achieve the above-mentioned object, a semiconductor device according to the present invention comprises at least two plate-shaped members having different linear expansion coefficients and joined to each other via solder joints. In a semiconductor device, a surface treatment portion is formed around the solder joint surface of one of the plate-like members, and the surface treatment portion prevents the solder from flowing out at the time of joining and holds the solder joint portion at a predetermined thickness. The configuration is
【００１４】そして少なくとも一つの半導体素子と、そ
れぞれの半導体素子を搭載しかつはんだ接合する少なく
とも一つの板状部材と、それぞれの半導体素子をリード
に接続したのち封止する封止材とよりなる半導体装置に
おいて、それぞれの板状部材のそれぞれの半導体素子と
のはんだ接合面の周囲に、接合時のはんだの流出を阻止
する表面処理部を形成した構成でもよい。A semiconductor comprising at least one semiconductor element, at least one plate-shaped member on which each semiconductor element is mounted and solder-bonded, and an encapsulant for connecting each semiconductor element to a lead and then sealing the leads. In the device, a surface treatment portion may be formed around the solder joint surface of each plate member with each semiconductor element to prevent the outflow of solder during joining.
【００１５】またそれぞれの板状部材は積層され、それ
ぞれの板状部材のうちの少なくとも一組の板状部材がは
んだ接合されている構成でもよい。Further, each plate member may be laminated, and at least one set of plate members among the plate members may be soldered.
【００１６】さらに少なくとも一組のそれぞれの板状部
材の平面寸法が異なり、大きい平面を有する板状部材の
はんだ接合面の周囲に、接合時のはんだの流出を防止す
る表面処理部を形成した構成でもよい。Further, at least one set of plate-shaped members having different plane dimensions, and a surface treatment portion for preventing the outflow of solder at the time of bonding is formed around the solder bonding surface of the plate-shaped member having a large flat surface. But it's okay.
【００１７】そして表面処理部は、不動態皮膜を形成す
る金属の膜で形成されている構成でもよい。The surface-treated portion may be formed of a metal film forming a passivation film.
【００１８】また表面処理部は、耐熱性樹脂の膜で形成
されている構成でもよい。The surface treatment section may be formed of a film of heat resistant resin.
【００１９】さらにそれぞれの板状部材のはんだ接合面
及び表面処理部の下面の少なくともいずれか一方の面
に、はんだの濡れ性を向上する第２の表面処理部を形成
した構成でもよい。Further, a second surface treatment portion for improving the wettability of solder may be formed on at least one of the solder joint surface of each plate member and the lower surface of the surface treatment portion.
【００２０】そして少なくとも一つの半導体素子と、そ
れぞれの半導体素子を搭載しかつはんだ接合する少なく
とも一つの板状部材と、それぞれの半導体素子をリード
に接続したのち封止する封止材とよりなる半導体装置に
おいて、それぞれの板状部材のそれぞれの半導体素子と
のはんだ接合面と、はんだ接合面の周囲以外の面とには
んだの濡れ性を向上する第２の表面処理部を形成した構
成でもよい。A semiconductor comprising at least one semiconductor element, at least one plate-shaped member on which each semiconductor element is mounted and solder-bonded, and an encapsulant for connecting each semiconductor element to leads and then sealing the semiconductor element. In the device, the second surface treatment section for improving the wettability of the solder may be formed on the solder joint surface of each plate member with each semiconductor element and the surface other than the periphery of the solder joint surface.
【００２１】また半導体装置の製造方法においては、前
記いずれか一つの半導体装置を製造する半導体装置の製
造方法において、いずれか一方の板状部材のはんだ接合
面にはんだを盛り上げ、それぞれのはんだ接合面の周囲
に表面処理を施し、それぞれのはんだの上に他方の板状
部材を搭載してはんだ溶融温度に加熱し、冷却後のはん
だ接合部を所定厚さに保持する構成とする。Further, in the method for manufacturing a semiconductor device, in the method for manufacturing a semiconductor device for manufacturing any one of the above semiconductor devices, solder is swelled on the solder bonding surface of one of the plate-shaped members, and each solder bonding surface is A surface treatment is applied to the periphery of the solder, the other plate-shaped member is mounted on each solder, the solder is heated to the solder melting temperature, and the solder joint after cooling is held to a predetermined thickness.
【００２２】[0022]
【作用】本発明によれば、一方の板状部材である基板の
はんだ接合面の周囲に、溶融はんだの流出が阻止する表
面処理部を形成したため、製造時にはんだの溶融温度で
加熱した際、溶融はんだは表面処理部の範囲に濡れ広が
ることがなく、大きな表面張力により溶融はんだが半球
状になろうとし、他方の板状部材である半導体素子を押
し上げる。この時の溶融はんだの形状は、はんだが凝固
した後も保持されるため、はんだ接合部の厚さが所定厚
さに保持され、かつ、溶融時のはんだ接合部の表面張力
に起因するセルフアライメント効果により、半導体素子
が基板とほぼ平行に接合される。そして、流れ止め部材
等が不要になるとともに熱疲労破壊に対する信頼性が向
上される。According to the present invention, since the surface treatment portion for preventing the outflow of the molten solder is formed around the solder joint surface of the board which is one plate-shaped member, when the solder is heated at the melting temperature of the solder during manufacturing, The molten solder does not wet and spread in the area of the surface-treated portion, and the large surface tension causes the molten solder to become hemispherical, pushing up the semiconductor element which is the other plate-shaped member. Since the shape of the molten solder at this time is retained even after the solder is solidified, the thickness of the solder joint is maintained at a predetermined thickness, and the self-alignment caused by the surface tension of the solder joint at the time of melting Due to the effect, the semiconductor element is bonded substantially parallel to the substrate. Further, the flow stop member and the like are not needed, and the reliability against thermal fatigue fracture is improved.
【００２３】[0023]
【実施例】本発明の第１の実施例を図１を参照しながら
説明する。図１に第１の実施例である半導体装置の断面
図を示す。図１に示すように、線膨張係数がそれぞれ異
なりかつ互いにはんだ接合される少なくとも二つの板状
部材、つまり半導体素子１及び基板２と、それぞれの半
導体素子１をリード７に接続する金属ワイヤ６と、金属
ワイヤ６を接続したのち封止する封止材（樹脂）５とよ
りなる半導体装置であって、いずれか一方の板状部材２
のはんだ接合面の周囲に表面処理部３を形成し、表面処
理部３は、接合時のはんだの流出を阻止してはんだ接合
部４を所定厚さに保持するものである構成とする。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described with reference to FIG. FIG. 1 is a sectional view of a semiconductor device according to the first embodiment. As shown in FIG. 1, at least two plate-shaped members having different linear expansion coefficients and solder-bonded to each other, that is, a semiconductor element 1 and a substrate 2, and a metal wire 6 connecting each semiconductor element 1 to a lead 7. , A semiconductor device comprising a sealing material (resin) 5 for connecting the metal wire 6 and then sealing the metal wire 6.
The surface treatment section 3 is formed around the solder joint surface of (1), and the surface treatment section 3 prevents the solder from flowing out at the time of joining and holds the solder joint section 4 at a predetermined thickness.
【００２４】すなわち半導体素子１はその下面がはんだ
接合部４によって基板２の上面に接合され、両端に固着
した金属ワイヤ６によりリード７と電気的に接続されて
いる。半導体素子１、基板２、金属ワイヤ６及びリード
７の一端等は樹脂５により封止されている。基板２の表
面のはんだ接合部４の周囲には、はんだの流出を阻止す
るはんだの濡れ性の悪い表面処理部３が形成されてい
る。表面処理の具体的な処理方法としては、不動態皮膜
（酸化化合物層）を形成するアルミニウム等の金属を、
メッキ、蒸着又はスパッタリング等の方法で基板２の表
面に膜状に形成する、又は図９に示す耐熱性樹脂の膜を
形成する方法等が挙げられる。That is, the lower surface of the semiconductor element 1 is bonded to the upper surface of the substrate 2 by the solder bonding portions 4, and the leads 7 are electrically connected by the metal wires 6 fixed to both ends. The semiconductor element 1, the substrate 2, the metal wires 6 and one ends of the leads 7 are sealed with a resin 5. Around the solder joint portion 4 on the surface of the substrate 2, a surface treatment portion 3 having poor solder wettability is formed to prevent the solder from flowing out. As a specific surface treatment method, a metal such as aluminum forming a passivation film (oxide compound layer) is used.
Examples thereof include a method of forming a film on the surface of the substrate 2 by a method such as plating, vapor deposition or sputtering, or a method of forming a film of heat resistant resin shown in FIG.
【００２５】図２〜図５に第１の実施例の半導体装置の
素子接合方法を示す。まず、図２に示すように、周囲に
表面処理部３を形成した基板２の素子搭載部に十分な量
のはんだ４ａを供給する。はんだ４ａは、ペースト状、
ブロック状又はシート状のいずれでもよい。表面処理部
３の平面形状は、図３に示すように、はんだ接合部を取
り囲む額縁状になっている。図２に示す状態の基板２を
はんだ４ａの融点以上に加熱すると、図４に示すよう
に、はんだが融解しはんだ４ｂのようになる。このと
き、はんだ４ｂの周辺部先端は、表面処理部３に接触す
るが、表面処理部３ははんだ接合を阻止する、いわゆる
濡れ性の悪い材料で形成されているため、溶融したはん
だ４ｂの周辺部先端がはんだ４ｂの表面張力により盛り
上がる。次に、図５に示すように、はんだ４ｃ上に半導
体素子１を搭載すると、はんだ４ｃは半導体素子１を押
し上げるとともに、半導体素子１の自重とはんだ４ｃの
表面張力とによるセルフアライメント効果により、半導
体素子１が傾くことなく基板２に対してほぼ平行にな
る。この後、冷却を行い、はんだを凝固させてもこの形
状が保たれるため、はんだ接合部の厚さを０．１〜０．
２ｍｍの所定厚さに確保することができる。2 to 5 show an element bonding method for the semiconductor device of the first embodiment. First, as shown in FIG. 2, a sufficient amount of solder 4a is supplied to the element mounting portion of the substrate 2 around which the surface treatment portion 3 is formed. The solder 4a is in paste form,
It may be either block-shaped or sheet-shaped. As shown in FIG. 3, the planar shape of the surface treatment section 3 is a frame shape surrounding the solder joint. When the substrate 2 in the state shown in FIG. 2 is heated above the melting point of the solder 4a, the solder melts and becomes the solder 4b, as shown in FIG. At this time, the tip of the peripheral portion of the solder 4b comes into contact with the surface treatment portion 3. However, since the surface treatment portion 3 is formed of a so-called poor wettability material that prevents solder joining, the periphery of the melted solder 4b. The tip of the part rises due to the surface tension of the solder 4b. Next, as shown in FIG. 5, when the semiconductor element 1 is mounted on the solder 4c, the solder 4c pushes up the semiconductor element 1, and the self-alignment effect by the self-weight of the semiconductor element 1 and the surface tension of the solder 4c causes the semiconductor The element 1 becomes substantially parallel to the substrate 2 without tilting. After that, this shape is maintained even if the solder is cooled and the solder is solidified. Therefore, the thickness of the solder joint is 0.1 to 0.
It is possible to ensure a predetermined thickness of 2 mm.
【００２６】以上の説明では、はんだを融解させた後に
半導体素子を搭載したが、図２に示す状態で予め半導体
素子を載置した後に加熱を行ってもよい。またはんだの
融解は、アルゴンガス等の不活性雰囲気又は水素ガス等
の還元性雰囲気中で行うことにより、はんだ接合をより
完全に行うことができる。In the above description, the semiconductor element is mounted after melting the solder, but heating may be performed after the semiconductor element is mounted in advance in the state shown in FIG. Further, melting of the solder is performed in an inert atmosphere such as argon gas or in a reducing atmosphere such as hydrogen gas, so that the solder joining can be performed more completely.
【００２７】本実施例では、表面処理部の平面形状を額
縁形状としたが、表面処理部の一部が切れていてもはん
だの表面張力により溶融はんだの流出を防ぐことができ
るため、必ずしもはんだ接合面の周囲を完全に取り囲む
必要はない。また、本実施例では表面処理部にある幅を
持たせているが、表面処理部は、溶融はんだに表面張力
を発生させるために設けているので、図３に示す平面方
向から見て線状であってもよい。In the present embodiment, the planar shape of the surface-treated portion is a frame shape. However, even if a part of the surface-treated portion is cut off, the molten solder can be prevented from flowing out due to the surface tension of the solder. It is not necessary to completely surround the joint surface. Further, although the surface treatment portion has a certain width in the present embodiment, since the surface treatment portion is provided to generate surface tension in the molten solder, the surface treatment portion is linear when viewed from the plane direction shown in FIG. May be
【００２８】図６に本発明の第２の実施例である半導体
装置の断面図を示す。本実施例では、絶縁基板（板状部
材）８の表面に配線板（板状部材）１０が３個所にメタ
ライズされており、それぞれの配線板１０の上に半導体
素子１がはんだ４ｄにより接合されている。そして、そ
れぞれの半導体素子１にリード７が直接接続されてい
る。絶縁基板８は、はんだ４ｅにより金属製の放熱板
（板状部材）９の上面に接合され、これらは樹脂５によ
り封止されている。放熱板９と絶縁基板８と、又は絶縁
基板８と配線板１０とが少なくとも１組の互いに平面寸
法の異なる板状部材を形成し、大きい平面を有する配線
板１０又は放熱板９のはんだ接合面の周囲に、はんだ流
出防止用の表面処理部３ａ，３ｂが形成されている。表
面処理部３ａ，３ｂにより、第１の実施例と同様に本実
施例でもはんだ接合部の厚さが所定厚さに確保されるた
め、高い信頼性を有する半導体装置を得ることができ
る。FIG. 6 is a sectional view of a semiconductor device according to the second embodiment of the present invention. In this embodiment, the wiring board (plate-shaped member) 10 is metallized at three places on the surface of the insulating substrate (plate-shaped member) 8, and the semiconductor element 1 is bonded onto each wiring board 10 by the solder 4d. ing. The leads 7 are directly connected to each semiconductor element 1. The insulating substrate 8 is bonded to the upper surface of a metal heat dissipation plate (plate member) 9 with solder 4e, and these are sealed with a resin 5. The heat dissipation plate 9 and the insulating substrate 8 or the insulation substrate 8 and the wiring board 10 form at least one set of plate-shaped members having different plane dimensions, and the solder joint surface of the wiring board 10 or the heat dissipation plate 9 having a large flat surface Surface treatment parts 3a and 3b for preventing solder outflow are formed around the. Since the surface treatment portions 3a and 3b assure the thickness of the solder joint portion to a predetermined thickness in this embodiment as well as the first embodiment, a semiconductor device having high reliability can be obtained.
【００２９】図７に本発明の第３の実施例である半導体
装置の断面図を示す。本実施例の半導体装置の構造は、
第１の実施例の半導体装置とほとんど同じであるが、本
実施例では、基板２のはんだ接合面に、はんだの濡れ性
を向上する第２の表面処理部１１を形成し、かつ基板２
のはんだ接合面の周囲に、はんだの濡れ性の悪い表面処
理部３を形成した。第２の表面処理部１１により、はん
だ接合部の接合欠陥が防げるため、さらに高い信頼性を
得ることができる。第２の表面処理部１１は、はんだ、
錫、ニッケル、金又は銀等をメッキ等により膜状に形成
することにより得られる。FIG. 7 is a sectional view of a semiconductor device according to the third embodiment of the present invention. The structure of the semiconductor device of this embodiment is
Although it is almost the same as the semiconductor device of the first embodiment, in this embodiment, the second surface treatment portion 11 for improving the wettability of solder is formed on the solder joint surface of the substrate 2 and the substrate 2
A surface-treated portion 3 having poor solder wettability was formed around the solder joint surface. Since the second surface treatment portion 11 can prevent a joint defect in the solder joint portion, higher reliability can be obtained. The second surface treatment section 11 is made of solder,
It is obtained by forming tin, nickel, gold, silver or the like into a film shape by plating or the like.
【００３０】図８に本発明の第４の実施例である半導体
装置の断面図を示す。本実施例の半導体装置の構造は、
第３の実施例の半導体装置とほとんど同じであるが、本
実施例では、基板２のはんだ接合側の表面全域に渡っ
て、はんだの濡れ性が向上する第２の表面処理部１１を
形成した後、はんだ接合面の周囲の第２の表面処理部１
１の上面に、はんだ流出防止用の表面処理部３を形成し
た。本実施例は、第３の実施例と同様の効果があり、し
かも表面処理部の形成が容易であるという利点がある。FIG. 8 is a sectional view of a semiconductor device according to the fourth embodiment of the present invention. The structure of the semiconductor device of this embodiment is
Although it is almost the same as the semiconductor device of the third embodiment, in this embodiment, the second surface treatment portion 11 for improving the solder wettability is formed over the entire surface of the substrate 2 on the solder bonding side. After that, the second surface treatment portion 1 around the solder joint surface
A surface treatment portion 3 for preventing solder outflow was formed on the upper surface of 1. This embodiment has the same effects as the third embodiment, and has the advantage that the surface-treated portion can be easily formed.
【００３１】図９に本発明の第５の実施例である半導体
装置の断面図を示す。本実施例の半導体装置の構造は、
第１の実施例の半導体装置とほとんど同じであるが、本
実施例では、はんだの接合を阻止する表面処理として、
耐熱性樹脂で形成した表面処理部１２を用いた。はんだ
は樹脂には接合しないため、第１の実施例と同様の効果
を奏する。樹脂の材質としては、ソルダーレジスト材が
好適であるが、ポリイミド又はポリテトラフルオロエチ
レン等の耐熱性樹脂フィルムを接着して用いてもよい。FIG. 9 is a sectional view of a semiconductor device according to the fifth embodiment of the present invention. The structure of the semiconductor device of this embodiment is
Although it is almost the same as the semiconductor device of the first embodiment, in this embodiment, as the surface treatment for preventing the solder joining,
The surface treatment part 12 formed of a heat resistant resin was used. Since the solder does not bond to the resin, it has the same effect as the first embodiment. A solder resist material is preferable as the material of the resin, but a heat resistant resin film such as polyimide or polytetrafluoroethylene may be adhered and used.
【００３２】図１０に本発明の第６の実施例である半導
体装置の断面図を示す。本実施例の半導体装置の構造
は、基板２のはんだ接合面にはんだの濡れ性が向上する
第２の表面処理部１１がはんだ接合面と、はんだ接合面
の周囲以外の面とに形成されている。すなわち、第２の
表面処理部１１と第２の表面処理部１１ａとに分割さ
れ、第２の表面処理部１１と第２の表面処理部１１ａと
の間のはんだ接合面の周囲に基板２の表面２ａが露出し
ている、つまり第２の表面処理部１１，１１ａよりはん
だの濡れ性が悪い表面処理部がはんだ接合面の周囲に形
成されていることになり、第１の実施例と同様の効果が
発生する。なお、表面２ａの上面に、積極的に第１の実
施例と同様の表面処理部を形成してもよい。FIG. 10 shows a sectional view of a semiconductor device according to a sixth embodiment of the present invention. In the structure of the semiconductor device according to the present embodiment, the second surface treatment portion 11 for improving the wettability of solder is formed on the solder joint surface of the substrate 2 on the solder joint surface and the surface other than the periphery of the solder joint surface. There is. That is, it is divided into the second surface treatment section 11 and the second surface treatment section 11a, and the substrate 2 is surrounded by the solder joint surface between the second surface treatment section 11 and the second surface treatment section 11a. That is, the surface 2a is exposed, that is, the surface treatment portion having a solder wettability lower than that of the second surface treatment portions 11 and 11a is formed around the solder joint surface, which is the same as the first embodiment. The effect of occurs. A surface treatment section similar to that of the first embodiment may be positively formed on the upper surface of the surface 2a.
【００３３】以上の実施例では、樹脂封止型半導体装置
について説明したが、本発明をセラミック半導体装置あ
るいはキャン封止型半導体装置に適用しても全く同様の
効果があることは言うまでもない。Although the resin-encapsulated semiconductor device has been described in the above embodiments, it goes without saying that the same effect can be obtained by applying the present invention to a ceramic semiconductor device or a can-encapsulated semiconductor device.
【００３４】[0034]
【発明の効果】本発明によれば、板状部材のはんだ接合
面の周囲に、接合時のはんだの流出を阻止する表面処理
部を形成したため、所定厚さのはんだ接合部が保持さ
れ、はんだ接合部に発生するひずみが低減して熱疲労破
壊を防止することができ、信頼性を高める効果がある。According to the present invention, since the surface treatment portion for preventing the outflow of the solder at the time of joining is formed around the solder joining surface of the plate-like member, the solder joining portion having a predetermined thickness is held, The strain generated in the joint can be reduced to prevent thermal fatigue fracture, and the reliability can be improved.
【図１】本発明の第１の実施例を示す断面図である。FIG. 1 is a sectional view showing a first embodiment of the present invention.
【図２】図１の半導体装置の製造方法を示す断面図であ
る。FIG. 2 is a cross-sectional view showing the method of manufacturing the semiconductor device of FIG.
【図３】図１の半導体装置の製造方法を示す断面図であ
る。FIG. 3 is a cross-sectional view showing the method of manufacturing the semiconductor device of FIG.
【図４】図１の半導体装置の製造方法を示す断面図であ
る。FIG. 4 is a cross-sectional view showing the method of manufacturing the semiconductor device of FIG.
【図５】図１の半導体装置の製造方法を示す断面図であ
る。FIG. 5 is a cross-sectional view showing the method of manufacturing the semiconductor device of FIG.
【図６】本発明の第２の実施例の半導体装置を示す断面
図である。FIG. 6 is a sectional view showing a semiconductor device according to a second embodiment of the present invention.
【図７】本発明の第３の実施例の半導体装置を示す断面
図である。FIG. 7 is a sectional view showing a semiconductor device according to a third embodiment of the present invention.
【図８】本発明の第４の実施例の半導体装置を示す断面
図である。FIG. 8 is a sectional view showing a semiconductor device according to a fourth embodiment of the present invention.
【図９】本発明の第５の実施例の半導体装置を示す断面
図である。FIG. 9 is a sectional view showing a semiconductor device according to a fifth embodiment of the present invention.
【図１０】本発明の第６の実施例の半導体装置を示す断
面図である。FIG. 10 is a sectional view showing a semiconductor device according to a sixth embodiment of the present invention.
１ 半導体素子 ２ 基板（板状部材） ３ 表面処理部 ３ａ，３ｂ 表面処理部 ４ はんだ接合部 ４ａ〜４ｅ はんだ接合部 ５ 樹脂（封止材） ７ リード ８ 絶縁基板（板状部材） ９ 放熱板（板状部材） １０ 配線板（板状部材） １１，１１ａ 第２の表面処理部 DESCRIPTION OF SYMBOLS 1 Semiconductor element 2 Board | substrate (plate-shaped member) 3 Surface treatment part 3a, 3b Surface treatment part 4 Solder joint part 4a-4e Solder joint part 5 Resin (sealing material) 7 Lead 8 Insulation board (plate-like member) 9 Heat sink (Plate-like member) 10 Wiring board (plate-like member) 11, 11a Second surface treatment part
Claims (9)
合部を介して接合される少なくとも二つの板状部材を備
えた半導体装置において、いずれか一方の板状部材のは
んだ接合面の周囲に表面処理部を形成し、該表面処理部
は、接合時にはんだの流出を阻止して前記はんだ接合部
を所定厚さに保持するものであることを特徴とする半導
体装置。1. A semiconductor device comprising at least two plate-shaped members which have different linear expansion coefficients and are bonded to each other via solder-bonded portions, and a surface treatment is applied to the periphery of the solder-bonded surface of one of the plate-shaped members. The semiconductor device is characterized in that a portion is formed and the surface treatment portion prevents the solder from flowing out at the time of joining and holds the solder joined portion at a predetermined thickness.
れの半導体素子を搭載しかつはんだ接合する少なくとも
一つの板状部材と、それぞれの半導体素子をリードに接
続したのち封止する封止材とよりなる半導体装置におい
て、それぞれの板状部材のそれぞれの半導体素子とのは
んだ接合面の周囲に、接合時のはんだの流出を阻止する
表面処理部を形成したことを特徴とする半導体装置。2. At least one semiconductor element, at least one plate-shaped member on which each semiconductor element is mounted and solder-bonded, and an encapsulant that connects each semiconductor element to leads and then seals the leads. In the semiconductor device, a surface treatment portion for preventing the outflow of solder at the time of bonding is formed around the solder bonding surface of each plate-shaped member with each semiconductor element.
て、それぞれの板状部材は積層され、それぞれの板状部
材のうちの少なくとも一組の板状部材がはんだ接合され
ていることを特徴とする半導体装置。3. The semiconductor device according to claim 1, wherein the plate-shaped members are stacked, and at least one set of the plate-shaped members is soldered to each other. Semiconductor device.
おいて、少なくとも一組のそれぞれの板状部材の平面寸
法が異なり、大きい平面を有する板状部材のはんだ接合
面の周囲に、接合時のはんだの流出を防止する表面処理
部を形成したことを特徴とする半導体装置。4. The semiconductor device according to claim 1, 2 or 3, wherein at least one pair of plate-shaped members have different plane dimensions, and the plate-shaped members having a large flat surface are soldered around the solder bonding surface. A semiconductor device having a surface treatment portion for preventing the solder from flowing out.
体装置において、表面処理部は、不動態皮膜を形成する
金属の膜で形成されていることを特徴とする半導体装
置。5. The semiconductor device according to claim 1, wherein the surface treatment section is formed of a metal film forming a passivation film.
体装置において、表面処理部は、耐熱性樹脂の膜で形成
されていることを特徴とする半導体装置。6. The semiconductor device according to claim 1, wherein the surface treatment section is formed of a heat resistant resin film.
て、それぞれの板状部材のはんだ接合面及び表面処理部
の下面の少なくともいずれか一方の面に、はんだの濡れ
性を向上する第２の表面処理部を形成したことを特徴と
する半導体装置。7. The semiconductor device according to claim 1, wherein at least one of the solder bonding surface of each plate-shaped member and the lower surface of the surface-treated portion has a second wettability improving property. A semiconductor device having a surface treatment portion.
れの半導体素子を搭載しかつはんだ接合する少なくとも
一つの板状部材と、それぞれの半導体素子をリードに接
続したのち封止する封止材とよりなる半導体装置におい
て、それぞれの板状部材のそれぞれの半導体素子とのは
んだ接合面と、該はんだ接合面の周囲以外の面とにはん
だの濡れ性を向上する第２の表面処理部を形成したこと
を特徴とする半導体装置。8. At least one semiconductor element, at least one plate-shaped member on which each semiconductor element is mounted and solder-bonded, and an encapsulant for connecting each semiconductor element to a lead and then sealing the leads. In the semiconductor device, the second surface treatment portion for improving the wettability of the solder is formed on the solder joint surface of each plate-shaped member with each semiconductor element and on the surface other than the periphery of the solder joint surface. Characteristic semiconductor device.
体装置を製造する半導体装置の製造方法において、いず
れか一方の板状部材のはんだ接合面にはんだを盛り上
げ、それぞれのはんだ接合面の周囲に表面処理を施し、
それぞれのはんだの上に他方の板状部材を搭載してはん
だ溶融温度に加熱し、冷却後のはんだ接合部を所定厚さ
に保持することを特徴とする半導体装置の製造方法。9. The method of manufacturing a semiconductor device according to claim 1, wherein the solder bonding surface of one of the plate-shaped members is filled with solder, and the solder bonding surface of each solder bonding surface is increased. Surface treatment is applied around the
A method for manufacturing a semiconductor device, comprising mounting the other plate-shaped member on each solder, heating the solder to a solder melting temperature, and maintaining the solder joint portion after cooling to a predetermined thickness.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6153487A JPH0823002A (en) | 1994-07-05 | 1994-07-05 | Semiconductor device and manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6153487A JPH0823002A (en) | 1994-07-05 | 1994-07-05 | Semiconductor device and manufacturing method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0823002A true JPH0823002A (en) | 1996-01-23 |
Family
ID=15563651
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6153487A Pending JPH0823002A (en) | 1994-07-05 | 1994-07-05 | Semiconductor device and manufacturing method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0823002A (en) |
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003264267A (en) * | 2002-03-08 | 2003-09-19 | Rohm Co Ltd | Semiconductor device using semiconductor chip |
| JP2004071899A (en) * | 2002-08-07 | 2004-03-04 | Sanyo Electric Co Ltd | Circuit device and its producing method |
| JP2011071297A (en) * | 2009-09-25 | 2011-04-07 | Denso Corp | Method of manufacturing semiconductor device |
| WO2011145176A1 (en) * | 2010-05-18 | 2011-11-24 | トヨタ自動車株式会社 | Semiconductor device and method for manufacturing the same |
| JP2012049575A (en) * | 2011-12-08 | 2012-03-08 | Fuji Electric Co Ltd | Semiconductor device |
| JP2014187180A (en) * | 2013-03-22 | 2014-10-02 | Mitsubishi Materials Corp | Assembly for semiconductor device, substrate for power module and power module |
| JP2015032765A (en) * | 2013-08-06 | 2015-02-16 | 三菱電機株式会社 | Semiconductor device |
| US9072206B2 (en) | 2009-03-12 | 2015-06-30 | Denso Corporation | Light source device |
| WO2016182425A1 (en) * | 2015-05-14 | 2016-11-17 | Chee Yang Ng | A lead frame for selective soldering |
| JP2016225552A (en) * | 2015-06-03 | 2016-12-28 | 国立大学法人茨城大学 | High heat-resistant solder bonded semiconductor device and manufacturing method thereof |
| WO2022059288A1 (en) * | 2020-09-18 | 2022-03-24 | 住友電気工業株式会社 | Semiconductor device |
| WO2022153780A1 (en) * | 2021-01-13 | 2022-07-21 | 三菱電機株式会社 | Semiconductor device, power conversion device, and manufacturing method for semiconductor device |
-
1994
- 1994-07-05 JP JP6153487A patent/JPH0823002A/en active Pending
Cited By (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003264267A (en) * | 2002-03-08 | 2003-09-19 | Rohm Co Ltd | Semiconductor device using semiconductor chip |
| JP2004071899A (en) * | 2002-08-07 | 2004-03-04 | Sanyo Electric Co Ltd | Circuit device and its producing method |
| US9072206B2 (en) | 2009-03-12 | 2015-06-30 | Denso Corporation | Light source device |
| JP2011071297A (en) * | 2009-09-25 | 2011-04-07 | Denso Corp | Method of manufacturing semiconductor device |
| WO2011145176A1 (en) * | 2010-05-18 | 2011-11-24 | トヨタ自動車株式会社 | Semiconductor device and method for manufacturing the same |
| JP5565315B2 (en) * | 2010-05-18 | 2014-08-06 | トヨタ自動車株式会社 | Manufacturing method of semiconductor device |
| US8865584B2 (en) | 2010-05-18 | 2014-10-21 | Toyota Jidosha Kabushiki Kaisha | Semiconductor device and manufacturing method thereof |
| EP2573809A4 (en) * | 2010-05-18 | 2017-05-24 | Toyota Jidosha Kabushiki Kaisha | Semiconductor device and method for manufacturing the same |
| JP2012049575A (en) * | 2011-12-08 | 2012-03-08 | Fuji Electric Co Ltd | Semiconductor device |
| JP2014187180A (en) * | 2013-03-22 | 2014-10-02 | Mitsubishi Materials Corp | Assembly for semiconductor device, substrate for power module and power module |
| JP2015032765A (en) * | 2013-08-06 | 2015-02-16 | 三菱電機株式会社 | Semiconductor device |
| WO2016182425A1 (en) * | 2015-05-14 | 2016-11-17 | Chee Yang Ng | A lead frame for selective soldering |
| JP2016225552A (en) * | 2015-06-03 | 2016-12-28 | 国立大学法人茨城大学 | High heat-resistant solder bonded semiconductor device and manufacturing method thereof |
| WO2022059288A1 (en) * | 2020-09-18 | 2022-03-24 | 住友電気工業株式会社 | Semiconductor device |
| WO2022153780A1 (en) * | 2021-01-13 | 2022-07-21 | 三菱電機株式会社 | Semiconductor device, power conversion device, and manufacturing method for semiconductor device |
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