JP5262408B2 - Positioning jig and method for manufacturing semiconductor device - Google Patents

Positioning jig and method for manufacturing semiconductor device Download PDF

Info

Publication number
JP5262408B2
JP5262408B2 JP2008203677A JP2008203677A JP5262408B2 JP 5262408 B2 JP5262408 B2 JP 5262408B2 JP 2008203677 A JP2008203677 A JP 2008203677A JP 2008203677 A JP2008203677 A JP 2008203677A JP 5262408 B2 JP5262408 B2 JP 5262408B2
Authority
JP
Japan
Prior art keywords
circuit board
semiconductor chip
metal
semiconductor device
insulating circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2008203677A
Other languages
Japanese (ja)
Other versions
JP2010040881A (en
Inventor
正樹 小野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd filed Critical Fuji Electric Co Ltd
Priority to JP2008203677A priority Critical patent/JP5262408B2/en
Publication of JP2010040881A publication Critical patent/JP2010040881A/en
Application granted granted Critical
Publication of JP5262408B2 publication Critical patent/JP5262408B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires

Description

本発明は、表裏面に金属回路と金属板がそれぞれ接合された絶縁回路基板の金属回路側に、半導体チップを半田付けによって実装するために使用する位置決め治具および半導体装置の製造方法に関し、とくに絶縁回路基板の表面形状の変形に対応可能な位置決め治具および半導体装置の製造方法に関する。   The present invention relates to a positioning jig used for mounting a semiconductor chip by soldering on a metal circuit side of an insulated circuit board in which a metal circuit and a metal plate are bonded to the front and back surfaces, and a method for manufacturing a semiconductor device, in particular. The present invention relates to a positioning jig that can cope with deformation of the surface shape of an insulated circuit board and a method for manufacturing a semiconductor device.

近年では、大電流・高電圧環境下でも動作可能なパワー半導体モジュールが様々な分野で用いられるようになっている。このようなパワーモジュールは、主に、絶縁ゲートバイポーラトランジスタ（Insulated Gate Bipolar Transistor：以下、ＩＧＢＴという。）やフリーホイーリングダイオード（Free Wheeling Diode：以下、ＦＷＤという。）等のパワー半導体を用いて構成される。   In recent years, power semiconductor modules that can operate even in a high-current / high-voltage environment have been used in various fields. Such a power module is mainly configured using a power semiconductor such as an insulated gate bipolar transistor (hereinafter referred to as IGBT) or a free wheeling diode (hereinafter referred to as FWD). Is done.

図８は、従来の半導体装置の製造方法に係る半田付け実装工程を示す図である。図において、絶縁回路基板１００は、主に絶縁性のセラミック基板と、セラミック基板の表裏面にそれぞれ金属回路、金属板（図示せず。）を接合して構成されている。この絶縁回路基板１００には、それと同形状のチップ位置決め用の治具（以下、位置決め治具という。）１０１を固定して、その表面金属回路側の所定位置にＩＧＢＴ、あるいはＦＷＤ等の半導体チップ１０２が実装される。なお、図８の平板形状の位置決め治具１０１には、ほぼ中央部に半導体チップ１０２を保持するための開口部１０１ａを１つだけ有しているが、複数の開口部を備えているものもある。   FIG. 8 is a diagram illustrating a solder mounting process according to a conventional method for manufacturing a semiconductor device. In the figure, an insulating circuit board 100 is mainly configured by bonding an insulating ceramic substrate and a metal circuit and a metal plate (not shown) to the front and back surfaces of the ceramic substrate. A chip positioning jig (hereinafter referred to as a positioning jig) 101 having the same shape is fixed to the insulated circuit board 100, and a semiconductor chip such as IGBT or FWD is placed at a predetermined position on the surface metal circuit side. 102 is implemented. Note that the flat plate-shaped positioning jig 101 in FIG. 8 has only one opening 101a for holding the semiconductor chip 102 in the substantially central portion, but some of them have a plurality of openings. is there.

こうしたチップ実装工程では、絶縁回路基板１００の表面に位置決め治具１０１を載せて、その開口部１０１ａ内に半導体チップ１０２を半田板１０３とともに落とし込んで、絶縁回路基板１００上で位置決めを行う。その後、全体を加熱炉に挿入して半田板１０３を溶融することによって、半田付けによるチップ実装が行われる。   In such a chip mounting process, the positioning jig 101 is placed on the surface of the insulated circuit board 100, and the semiconductor chip 102 is dropped into the opening 101a together with the solder plate 103 to perform positioning on the insulated circuit board 100. Thereafter, the whole is inserted into a heating furnace and the solder plate 103 is melted, whereby chip mounting by soldering is performed.

ところで、絶縁回路基板１００は、常温時にはほぼ平坦な平板形状であるが、その後、高温の加熱炉へ投入することによって、図８に示すように、その最下端から基板沿面までの高さ（ｈ）として測定されるような変形が一時的に生じる。すなわち、絶縁回路基板１００がその実装面の裏面側に凸形状に湾曲することによって、隙間（ｇ）が絶縁回路基板１００の表面金属回路側で位置決め治具１０１との間に生じる。   By the way, the insulated circuit board 100 has a substantially flat plate shape at room temperature. Thereafter, by inserting it into a high-temperature heating furnace, as shown in FIG. 8, the height (h ) Is temporarily generated as measured by. That is, the insulating circuit board 100 is curved in a convex shape on the back surface side of the mounting surface, whereby a gap (g) is generated between the surface metal circuit side of the insulating circuit board 100 and the positioning jig 101.

一般に、動作時に発熱するパワー半導体のような電子部品を搭載した絶縁回路基板１００では、放熱対策のために裏面の金属板に熱伝導率の高い大型の金属プレートが放熱板として貼り付けられて、発生した熱を拡散して放熱するようにしている。その際、絶縁回路基板１００がその実装面の裏面側に凸形状に湾曲していれば、放熱板との半田接合層に存在する気泡（ボイド）が自らの浮力によって凸状の曲面に沿って移動し、排出除去される。したがって、絶縁回路基板１００に生じる凸状の曲面は、両者の間の接合力を高めるうえで有効であり、接合面での熱伝導率が低下しないという効果があった（例えば、特許文献１参照。）。   In general, in the insulated circuit board 100 on which an electronic component such as a power semiconductor that generates heat during operation is mounted, a large metal plate having high thermal conductivity is attached to the metal plate on the back surface as a heat radiating plate for heat dissipation measures. The generated heat is diffused and released. At that time, if the insulated circuit board 100 is curved in a convex shape on the back surface side of the mounting surface, bubbles (voids) present in the solder joint layer with the heat radiating plate are formed along the convex curved surface by their buoyancy. Move and drain. Therefore, the convex curved surface generated in the insulating circuit board 100 is effective in increasing the bonding force between the two, and has the effect that the thermal conductivity at the bonding surface does not decrease (see, for example, Patent Document 1). .)

また、位置決め治具１０１の下面と絶縁回路基板１００との間に意図的に隙間を設けることによって、溶融した半田が毛管現象で周囲に浸透しないようにする技術も提案されている（例えば、特許文献２参照。）。
特開平１０−２７０６１２号公報（段落番号［００１９］〜［００２５］および図２） 特開平０６−２１１１０号公報（段落番号［０００７］〜［０００９］および図１〜図３） In addition, a technique for preventing molten solder from penetrating into the surroundings by capillary action by intentionally providing a gap between the lower surface of the positioning jig 101 and the insulated circuit board 100 has been proposed (for example, patents). Reference 2).
JP-A-10-270612 (paragraph numbers [0019] to [0025] and FIG. 2) Japanese Patent Laid-Open No. 06-21110 (paragraph numbers [0007] to [0009] and FIGS. 1 to 3)

ところで、こうした絶縁回路基板１００の変形量や変形形状等は、その寸法や材質、あるいは加熱温度等によっても異なるが、図８に示すように、その最下端から基板沿面までの高さ（ｈ）が数百μｍになる場合もある。すると、位置決め治具１０１との隙間（ｇ）も大きくなり、それが半導体チップ１０２および半田板１０３の厚みの合計より大きくなれば、半田板１０３が溶融したときに、絶縁回路基板１００の表面金属回路上で半田の流れ出しや半導体チップ１０２の位置ズレ等が生じるという問題があった。   By the way, although the deformation amount, deformation shape, and the like of the insulating circuit board 100 vary depending on the dimensions, material, heating temperature, and the like, as shown in FIG. May be several hundred μm. Then, the gap (g) with respect to the positioning jig 101 also increases, and if it becomes larger than the total thickness of the semiconductor chip 102 and the solder plate 103, the surface metal of the insulated circuit board 100 when the solder plate 103 is melted. There has been a problem that solder flows out on the circuit and the semiconductor chip 102 is displaced.

本発明はこのような点に鑑みてなされたものであり、絶縁回路基板の加熱による変形を考慮して、裏面形状が成形された位置決め治具を提供することを目的とする。
また、本発明の別の目的は、位置決め治具と絶縁回路基板との密着度を高めることで、製造歩留まりを向上させた半導体装置の製造方法を提供することである。 The present invention has been made in view of these points, and an object of the present invention is to provide a positioning jig having a back surface shape in consideration of deformation due to heating of an insulated circuit board.
Another object of the present invention is to provide a method for manufacturing a semiconductor device in which the manufacturing yield is improved by increasing the degree of adhesion between the positioning jig and the insulated circuit board.

本発明では、上記問題を解決するために、表面に金属回路が、裏面にはべた付けにて金属板がそれぞれ接合された絶縁回路基板の前記金属回路側に、半導体チップを半田付けによって実装するために使用する位置決め治具が提供される。この位置決め治具は、前記絶縁回路基板と接触する裏面形状が、前記半導体チップの半田付け時における前記絶縁回路基板の加熱によって変形する表面形状と対応する形状に加工された治具本体と、前記治具本体を貫通して形成され、前記半導体チップを落とし込んで前記金属回路上に位置決めをするための開口部と、から構成される。
In the present invention, in order to solve the above problems, the metal circuit on the surface, the back surface to the metal circuit side of the insulating circuit board in which the metal plate at solid with are bonded respectively, for mounting a semiconductor chip by soldering A positioning jig is provided for use. The positioning jig includes a jig body that has a back surface shape that comes into contact with the insulating circuit board and is processed into a shape corresponding to a surface shape that is deformed by heating of the insulating circuit board when the semiconductor chip is soldered, An opening is formed through the jig body and for positioning the semiconductor chip on the metal circuit by dropping the semiconductor chip.

この発明によれば、半導体チップが配置される絶縁回路基板との隙間を低減できる。
また、本発明の半導体装置の製造方法では、上述した位置決め治具を使用して、絶縁回路基板の金属回路側に半導体チップを半田付けによって実装する工程において、前記位置決め治具の開口部に半田板および半導体チップを配置し、前記絶縁回路基板とともに加熱して前記半田板を溶融して前記絶縁回路基板に前記半導体チップを実装することを特徴とする。 According to the present invention, it is possible to reduce the gap with the insulated circuit board on which the semiconductor chip is arranged.
Further, in the method of manufacturing a semiconductor device of the present invention, in the step of mounting the semiconductor chip on the metal circuit side of the insulating circuit board by using the positioning jig described above, soldering is performed on the opening of the positioning jig. A board and a semiconductor chip are arranged, heated together with the insulating circuit board to melt the solder plate, and the semiconductor chip is mounted on the insulating circuit board.

この発明の半導体装置の製造方法では、絶縁回路基板の金属回路側にＩＧＢＴチップ、ＦＷＤチップ等を半田付けによって実装する場合に、半田溶融から硬化に至る過程で位置決め治具と絶縁回路基板との密着度を高めることができる。   In the method of manufacturing a semiconductor device according to the present invention, when an IGBT chip, an FWD chip, or the like is mounted on the metal circuit side of the insulating circuit board by soldering, the positioning jig and the insulating circuit board are in the process from solder melting to curing. The degree of adhesion can be increased.

本発明の位置決め治具によれば、従来の絶縁回路基板上への半田のはみ出し、半導体チップ相互間での意図しない半田接合、および半導体チップの位置ずれを確実に防止することができる。   According to the positioning jig of the present invention, it is possible to reliably prevent solder from protruding onto a conventional insulated circuit board, unintentional solder bonding between semiconductor chips, and semiconductor chip position shift.

本発明の半導体装置の製造方法によれば、絶縁回路基板の金属回路側にＩＧＢＴチップ、ＦＷＤチップ等を半田付けによって実装する場合に、半田溶融から硬化に至る過程で位置決め治具と絶縁回路基板との密着度を高めることにより、両者間での隙間を最小に抑えて、製品不具合を低減できる。また、位置決め治具との間での干渉による半導体チップの損傷等が防止できる。   According to the method for manufacturing a semiconductor device of the present invention, when mounting an IGBT chip, an FWD chip or the like on the metal circuit side of the insulating circuit board by soldering, the positioning jig and the insulating circuit board in the process from solder melting to curing. By increasing the degree of close contact with each other, it is possible to minimize the gap between the two and reduce product defects. Further, damage to the semiconductor chip due to interference with the positioning jig can be prevented.

以下、この発明の実施の形態について、２つの位置決め治具、およびそれを用いた半導体装置の製造方法を、それぞれ図面を参照して説明する。
（実施の形態１）
図１は、実施の形態１に係る半導体装置の製造方法の一工程を示す側断面図である。 Hereinafter, two positioning jigs and a method for manufacturing a semiconductor device using the same will be described with reference to the drawings.
(Embodiment 1)
FIG. 1 is a side sectional view showing one step of the method of manufacturing a semiconductor device according to the first embodiment.

図において絶縁回路基板１の表面側には、位置決め用のカーボン治具２０と、その開口部２１に半田板３０および半導体チップ４０が配置され、その後、図示しない加熱炉に挿入される。加熱炉内では、全体が３００℃程度まで加熱され、半田板３０が溶融されることによって、絶縁回路基板１上へ半導体チップ４０が実装される。   In the drawing, a positioning carbon jig 20 and a solder plate 30 and a semiconductor chip 40 are disposed in the opening 21 on the surface side of the insulated circuit board 1, and then inserted into a heating furnace (not shown). In the heating furnace, the whole is heated to about 300 ° C., and the solder plate 30 is melted, whereby the semiconductor chip 40 is mounted on the insulating circuit board 1.

このとき、絶縁回路基板１が加熱されると、一時的に裏面側に凸形状となるように湾曲する「正反り」状態になる。そこで、実施の形態１では、カーボン治具２０の本体裏面形状として、その開口部２１から離れる方向で薄くなるように、段差部２２が形成されている。したがって、絶縁回路基板１とカーボン治具２０との隙間が低減され、溶融した半田が絶縁回路基板１上ではみ出したり、半導体チップ４０の実装位置がずれたりするおそれがなくなる。   At this time, when the insulating circuit board 1 is heated, it is in a “normal warpage” state in which the insulating circuit board 1 is curved so as to be temporarily convex on the back surface side. Therefore, in the first embodiment, the step portion 22 is formed as the main body back surface shape of the carbon jig 20 so as to be thin in the direction away from the opening 21. Therefore, the gap between the insulating circuit board 1 and the carbon jig 20 is reduced, and there is no possibility that the molten solder protrudes on the insulating circuit board 1 or the mounting position of the semiconductor chip 40 is shifted.

このように、高温時の絶縁回路基板１の湾曲形状に対応する形状で、カーボン治具２０の絶縁回路基板１との接触面に予め所定の大きさの段差を設けた構造とすることによって、絶縁回路基板１の半導体チップ４０を実装する表面との隙間を低減できる。なお、複数の開口部２１を有するカーボン治具２０では、絶縁回路基板１の湾曲の度合いが大きくなる周辺近傍に段差部２２を形成して、開口部２１から離れる方向で治具本体の厚みが薄くなるように構成することが好ましい。   In this way, by having a structure corresponding to the curved shape of the insulated circuit board 1 at a high temperature and having a step having a predetermined size on the contact surface of the carbon jig 20 with the insulated circuit board 1 in advance, It is possible to reduce a gap between the surface of the insulated circuit board 1 and the surface on which the semiconductor chip 40 is mounted. In the carbon jig 20 having a plurality of openings 21, the stepped portion 22 is formed in the vicinity of the periphery where the degree of curvature of the insulated circuit board 1 increases, and the thickness of the jig main body increases in the direction away from the openings 21. It is preferable to make it thin.

図２は、完成した半導体装置の断面構成の一例を示す図である。
絶縁回路基板１は、セラミック等からなる絶縁層１０の表面側に金属回路１１が形成され、その所定位置に半導体チップ４０が半田層４１によって実装される。絶縁層１０の裏面側には金属板１２が形成され、半田層４２によって放熱板となる金属ベース５０に固着されている。 FIG. 2 is a diagram illustrating an example of a cross-sectional configuration of a completed semiconductor device.
In the insulated circuit board 1, a metal circuit 11 is formed on the surface side of an insulating layer 10 made of ceramic or the like, and a semiconductor chip 40 is mounted by a solder layer 41 at a predetermined position. A metal plate 12 is formed on the back side of the insulating layer 10 and is fixed to a metal base 50 serving as a heat sink by a solder layer 42.

パワーモジュールを構成する半導体チップ４０は、アルミ等のボンディングワイヤ６０〜６２等によって金属回路１１の所定部分と接続され、さらに樹脂ケース７０から外部に引き出されているリード端子７１，７２と接続されている。また、樹脂ケース７０内部は、ボンディングワイヤ６０〜６２の腐食を防止するためにシリコーンゲル８０で埋められている。シリコーンゲル８０の代わりにエポキシ樹脂等の絶縁性樹脂を用いてもよいし、またシリコーンゲルと絶縁性樹脂を組み合せてもよい。なお、完成した半導体装置では、絶縁回路基板１は平坦な状態に復帰する。   The semiconductor chip 40 constituting the power module is connected to a predetermined portion of the metal circuit 11 by bonding wires 60 to 62 such as aluminum, and is further connected to lead terminals 71 and 72 drawn out from the resin case 70 to the outside. Yes. The resin case 70 is filled with silicone gel 80 to prevent the bonding wires 60 to 62 from corroding. Instead of the silicone gel 80, an insulating resin such as an epoxy resin may be used, or a silicone gel and an insulating resin may be combined. In the completed semiconductor device, the insulated circuit board 1 returns to a flat state.

こうした半導体装置の製造工程では、通常は絶縁回路基板１上に複数の半導体チップ４０を実装する際、同時に絶縁回路基板１の金属板１２側と金属ベース５０との半田付けが加熱炉によるリフロー半田付け方式によって実施される。そして、加熱炉内で高温となった絶縁回路基板１は、後に詳述する理由で大きく湾曲する。そのため、その後にワイヤボンディング工程が実行された時点では、従来は、絶縁回路基板１上での半導体チップ４０間での半田はみ出し、あるいは半導体チップ４０の位置ずれ、およびそれに伴う位置決め治具との干渉による傷等によって、１０〜１５％程度の製品不良率が発生していた。しかも、半田はみ出しや半導体チップ４０の位置ずれは、その大半が絶縁回路基板１の中央部で生じていた。   In the manufacturing process of such a semiconductor device, normally, when mounting a plurality of semiconductor chips 40 on the insulated circuit board 1, the soldering between the metal plate 12 side of the insulated circuit board 1 and the metal base 50 is performed by reflow soldering using a heating furnace. It is implemented by the attaching method. And the insulated circuit board 1 which became high temperature in a heating furnace curves greatly for the reason explained in full detail later. Therefore, when a wire bonding step is subsequently performed, conventionally, solder protrudes between the semiconductor chips 40 on the insulating circuit board 1 or the semiconductor chip 40 is displaced, and the interference with the positioning jig associated therewith. A product defect rate of about 10 to 15% occurred due to scratches or the like. In addition, most of the solder protrusion and the position shift of the semiconductor chip 40 occurred in the central portion of the insulating circuit board 1.

そこで、実施の形態１ではカーボン治具２０の裏面に段差部２２を設けて、カーボン治具２０が絶縁回路基板１の端部での最大の「正反り」部分で接触しないようにした。こうすれば、チップ実装時に加熱された絶縁回路基板１が大きく湾曲した場合でも、カーボン治具２０（図１）と絶縁回路基板１との隙間が大きくならない。したがって、絶縁回路基板１のチップ実装部の周辺でカーボン治具２０が密着して固定されるため、上述したような原因での半導体装置の製品不良率を低減することができる。   Therefore, in the first embodiment, the step portion 22 is provided on the back surface of the carbon jig 20 so that the carbon jig 20 does not come into contact with the maximum “positive warp” portion at the end of the insulated circuit board 1. By so doing, even when the insulated circuit board 1 heated during chip mounting is greatly curved, the gap between the carbon jig 20 (FIG. 1) and the insulated circuit board 1 does not become large. Therefore, since the carbon jig 20 is closely attached and fixed around the chip mounting portion of the insulating circuit board 1, the product defect rate of the semiconductor device due to the above-described causes can be reduced.

（実施の形態２）
図３は、実施の形態２に係る半導体装置の製造方法の一工程を示す側断面図である。
実施の形態２では、カーボン治具９０の裏面に、絶縁回路基板１の接触面に合致する曲面が加工されている。ここでは、高温時の絶縁回路基板１に生じる反り形状を予め測定しておき、それに合わせた曲率でカーボン治具９０の裏面を曲面とする加工を施すことができる。図３では、カーボン治具９０の開口部９１を１つだけ示しているが、複数の開口部９１を有している場合には、例えば予め絶縁回路基板１の反りの曲率が大きい開口部９１の近傍部分だけに曲面加工を施してもよい。 (Embodiment 2)
FIG. 3 is a sectional side view showing one step of the method of manufacturing the semiconductor device according to the second embodiment.
In the second embodiment, a curved surface that matches the contact surface of the insulated circuit board 1 is processed on the back surface of the carbon jig 90. Here, the warp shape generated in the insulated circuit board 1 at the time of high temperature is measured in advance, and the back surface of the carbon jig 90 can be processed to have a curved surface with a curvature corresponding thereto. In FIG. 3, only one opening 91 of the carbon jig 90 is shown. However, when the plurality of openings 91 are provided, for example, the opening 91 having a large curvature curvature of the insulating circuit board 1 in advance. The curved surface processing may be performed only on the vicinity of.

図４は、複数の開口部を有するカーボン治具を示す図であって、（Ａ）はその正面図、（Ｂ）はＢ−Ｂ線に沿う断面図である。
図では、８個の開口部９１が形成されたカーボン治具９０を示している。このカーボン治具９０は、例えば横方向Ｘが約４０ｍｍ、縦方向Ｙが約５０ｍｍ、最大の板厚Ｚが約３ｍｍに構成され、ほぼ同様の大きさの絶縁回路基板１上での半導体チップの位置決め治具として使用される。 4A and 4B are views showing a carbon jig having a plurality of openings, wherein FIG. 4A is a front view thereof, and FIG. 4B is a cross-sectional view taken along line BB.
In the figure, a carbon jig 90 in which eight openings 91 are formed is shown. For example, the carbon jig 90 is configured such that the horizontal direction X is about 40 mm, the vertical direction Y is about 50 mm, and the maximum plate thickness Z is about 3 mm, and the semiconductor chip on the insulating circuit substrate 1 having substantially the same size is formed. Used as a positioning jig.

つぎに、絶縁回路基板の一例として、セラミックの両面に金属材料を接合して構成されるＤＣＢ（direct copper bonding）基板について説明する。
図５は、半導体チップを実装するためのＤＣＢ基板の金属パターンを示す平面図、図６は、図５のＤＣＢ基板の断面構成を示す図である。 Next, as an example of the insulated circuit board, a DCB (direct copper bonding) board configured by bonding a metal material to both sides of a ceramic will be described.
FIG. 5 is a plan view showing a metal pattern of a DCB substrate for mounting a semiconductor chip, and FIG. 6 is a diagram showing a cross-sectional configuration of the DCB substrate of FIG.

３層構造の絶縁回路基板としては、セラミックの絶縁層１０に銅等の金属回路１１と、べた付けされた金属板１２が表裏面に設けられたＤＣＢ基板２が一般的である。ＤＣＢ基板２の表面の金属回路１１に、所定位置に半導体チップが実装される。また、裏面の金属板は半田付け接合によって、あるいはコンパウンドを塗布して放熱板に取り付けられる。   As an insulating circuit board having a three-layer structure, a DCB board 2 in which a metal circuit 11 such as copper and a solid metal plate 12 are provided on the front and back surfaces of a ceramic insulating layer 10 is generally used. A semiconductor chip is mounted at a predetermined position on the metal circuit 11 on the surface of the DCB substrate 2. Further, the metal plate on the back surface is attached to the heat radiating plate by soldering or by applying a compound.

ここで、金属回路１１や金属板１２を構成する銅、アルミの線膨張係数は、１７〜２３×１０-6（１／℃）であるのに対して、絶縁層１０を構成するセラミックのそれは３．０〜７．０×１０-6（１／℃）と小さい。こうした３層構造のＤＣＢ基板２を放熱板へ半田付けする際に鉛フリー半田を用いると、加熱温度が２５０℃以上に達するため、両者の線膨張係数の差から絶縁層１０の表裏面が引っ張られる。そこで、表裏面の接合金属量のバランスが取れていないと、ＤＣＢ基板２には反りが生じる。 Here, the linear expansion coefficient of copper and aluminum constituting the metal circuit 11 and the metal plate 12 is 17 to 23 × 10 −6 (1 / ° C.), whereas that of the ceramic constituting the insulating layer 10 is As small as 3.0 to 7.0 × 10 −6 (1 / ° C.). When lead-free solder is used when soldering the DCB substrate 2 having such a three-layer structure to the heat sink, the heating temperature reaches 250 ° C. or more, and therefore the front and back surfaces of the insulating layer 10 are pulled due to the difference in linear expansion coefficient between the two. It is done. Therefore, the DCB substrate 2 is warped if the amount of the joining metal on the front and back surfaces is not balanced.

ＤＣＢ基板２の表面に金属回路１１が形成されているため、裏面にべた付けされた金属板１２と比較して膨張が少ない。表裏面での膨張がこのように偏ることで、ＤＣＢ基板２は図６で破線によって示した「正反り」状態になる。   Since the metal circuit 11 is formed on the surface of the DCB substrate 2, the expansion is less than that of the metal plate 12 attached to the back surface. As the expansion on the front and back surfaces is biased in this way, the DCB substrate 2 enters the “normal warpage” state indicated by the broken line in FIG. 6.

一般的なＤＣＢ基板２は、金属回路１１と金属板１２とは同じ厚みに形成されるが、表裏面で厚みが異なる金属層を設けた絶縁回路基板もある。図６に示すように表面の金属回路１１の厚みｔ１を金属板１２の厚みｔ２より大きく形成する（ｔ１＞ｔ２）と、ＤＣＢ基板２の高温時には、より大きく下に凸方向に変形する「正反り」状態となって、放熱板との半田接合時の気泡（ボイド）抜けを促進することができる。   In the general DCB substrate 2, the metal circuit 11 and the metal plate 12 are formed to have the same thickness, but there is also an insulated circuit substrate provided with metal layers having different thicknesses on the front and back surfaces. As shown in FIG. 6, when the thickness t1 of the metal circuit 11 on the surface is larger than the thickness t2 of the metal plate 12 (t1> t2), when the DCB substrate 2 is at a high temperature, It becomes a “warp” state, and it is possible to promote the removal of air bubbles (voids) at the time of soldering with the heat sink.

とくに、ＤＣＢ基板２の端部では表裏面での金属ボリュームの差が大きくなって、高温時に中心付近より反りが大きくなる。また、表面に複雑な金属回路１１が形成されていると、金属ボリュームの差に応じて曲率の大きな変形が生じる。   In particular, at the end portion of the DCB substrate 2, the difference in metal volume between the front and back surfaces becomes large, and the warpage is greater than that near the center at high temperatures. In addition, when a complicated metal circuit 11 is formed on the surface, deformation with a large curvature occurs according to the difference in metal volume.

また、ＤＣＢ基板２にＩＧＢＴ等の半導体チップを半田付けによって実装する場合、表面の金属回路１１における絶縁距離を確保するために、その沿面距離ｄ１を裏面の金属板１２における沿面距離ｄ２よりも長くとっている。金属板１２の沿面距離を金属回路１１に合わせると、セラミックの絶縁層１０が突出することになって、放熱板との接合時にセラミックの絶縁層１０が割れやすくなるためである。   Further, when a semiconductor chip such as an IGBT is mounted on the DCB substrate 2 by soldering, the creepage distance d1 is longer than the creepage distance d2 on the back metal plate 12 in order to secure an insulation distance in the metal circuit 11 on the front surface. I'm taking it. This is because, when the creeping distance of the metal plate 12 is matched to the metal circuit 11, the ceramic insulating layer 10 protrudes, and the ceramic insulating layer 10 is easily broken when joined to the heat sink.

さらに、金属板１２は絶縁層１０の端部まで設けて、その沿面距離ｄ２を小さくしている。これによって、金属板１２が放熱板に接合された状態では、それらの隙間が半田フィレットによって埋められるから、シリコーンゲル８０（図２）を隙間無く充填することが可能になる。   Furthermore, the metal plate 12 is provided up to the end of the insulating layer 10 to reduce the creeping distance d2. Thereby, in a state where the metal plate 12 is bonded to the heat radiating plate, the gap is filled with the solder fillet, so that the silicone gel 80 (FIG. 2) can be filled without a gap.

図７は、ＤＣＢ基板の常温時および加熱時における反り量の測定結果を示す図である。
ここでは、図５に示すようなサイズのＤＣＢ基板を４枚用意し、それぞれ常温時およびＨ2一体炉による３００℃の加熱時に、Ｘ・Ｙの各方向と斜め方向（対角方向）での反り量を、レーザー三次元形状測定器によって測定した。加熱時の反り量の測定は、ＤＣＢ基板２の裏面において、その金属板１２の端部を測定位置とし、全体の温度が安定した状態で実施した。 FIG. 7 is a diagram showing measurement results of the warpage amount of the DCB substrate at normal temperature and during heating.
Here, four DCB substrates having a size as shown in FIG. 5 are prepared, and each of the X and Y directions and diagonal directions (diagonal directions) at room temperature and when heated at 300 ° C. in an H 2 integrated furnace, respectively. The amount of warpage was measured with a laser three-dimensional shape measuring instrument. The amount of warpage during heating was measured in a state where the end of the metal plate 12 was the measurement position on the back surface of the DCB substrate 2 and the overall temperature was stable.

ＤＣＢ基板２の大きさは、横方向Ｘが約４０ｍｍ、縦方向Ｙが約５０ｍｍであって、平均した反り量もそれぞれＸ方向で７１．３μｍ、Ｙ方向で１３６．８μｍとなる。また、対角方向ではさらに大きな反り量（２８７．５μｍ）となった。   The size of the DCB substrate 2 is about 40 mm in the horizontal direction X and about 50 mm in the vertical direction Y, and the average warpage amounts are 71.3 μm in the X direction and 136.8 μm in the Y direction, respectively. Further, the warpage amount (287.5 μm) was larger in the diagonal direction.

なお、計測データはＸ・Ｙ方向だけであって、対角方向の反り量は計測波形から算出された値である。また、ＤＣＢ基板２の中央部付近と比較して、縁辺部分になるほど反りが急激に大きくなっている。これは、金属回路１１のパターン形状にも関係するが、縁辺部分での表裏面間の金属ボリューム差が大きいためである。   The measurement data is only in the X and Y directions, and the amount of warpage in the diagonal direction is a value calculated from the measurement waveform. Further, as compared with the vicinity of the central portion of the DCB substrate 2, the warp increases rapidly as the edge portion is reached. This is related to the pattern shape of the metal circuit 11, but is because the metal volume difference between the front and back surfaces at the edge portion is large.

実施の形態１に係る半導体装置の製造方法の一工程を示す側断面図である。FIG. 6 is a side cross sectional view showing a step of the method of manufacturing a semiconductor device according to the first embodiment. 完成した半導体装置の断面構成の一例を示す図である。It is a figure which shows an example of the cross-sectional structure of the completed semiconductor device. 実施の形態２に係る半導体装置の製造方法の一工程を示す側断面図である。FIG. 10 is a side sectional view showing one step of a method for manufacturing a semiconductor device according to the second embodiment. 複数の開口部を有するカーボン治具を示す図であって、（Ａ）はその正面図、（Ｂ）はＢ−Ｂ線に沿う断面図である。It is a figure which shows the carbon jig | tool which has several opening part, Comprising: (A) is the front view, (B) is sectional drawing which follows the BB line. 半導体チップを実装するためのＤＣＢ基板の金属パターンを示す平面図である。It is a top view which shows the metal pattern of the DCB board | substrate for mounting a semiconductor chip. 図５のＤＣＢ基板の断面構成を示す図である。It is a figure which shows the cross-sectional structure of the DCB board | substrate of FIG. ＤＣＢ基板の常温時および加熱時における反り量の測定結果を示す図である。It is a figure which shows the measurement result of the curvature amount at the time of normal temperature and a heating of a DCB board | substrate. 従来の半導体装置の製造方法に係る半田付け実装工程を示す図である。It is a figure which shows the soldering mounting process which concerns on the manufacturing method of the conventional semiconductor device.

符号の説明Explanation of symbols

１ 絶縁回路基板
２ ＤＣＢ基板
１０ 絶縁層
１１ 金属回路
１２ 金属板
２０，９０ カーボン治具
２１，９１ 開口部
２２ 段差部
３０ 半田板
４０ 半導体チップ
４１，４２ 半田層
５０ 金属ベース
６０，６１，６２ ボンディングワイヤ
７０ 樹脂ケース
７１，７２ リード端子
８０ シリコーンゲル DESCRIPTION OF SYMBOLS 1 Insulation circuit board 2 DCB board 10 Insulation layer 11 Metal circuit 12 Metal plate 20, 90 Carbon jig 21, 91 Opening part 22 Step part 30 Solder plate 40 Semiconductor chip 41, 42 Solder layer 50 Metal base 60, 61, 62 Bonding Wire 70 Resin case 71, 72 Lead terminal 80 Silicone gel

Claims (12)

表面に金属回路が、裏面にはべた付けにて金属板がそれぞれ接合された絶縁回路基板の前記金属回路側に、半導体チップを半田付けによって実装するために使用する位置決め治具であって、
前記絶縁回路基板と接触する裏面形状が、前記半導体チップの半田付け時における前記絶縁回路基板の加熱によって変形する表面形状と対応する形状に加工された治具本体と、
前記治具本体を貫通して形成され、前記半導体チップを落とし込んで前記金属回路上に位置決めをするための開口部と、
を備えていることを特徴とする位置決め治具。 Metal circuit on the surface, the back surface to the metal circuit side of the insulating circuit board in which the metal plate at solid with are bonded respectively, a positioning jig to be used for mounting a semiconductor chip by soldering,
A jig body processed into a shape corresponding to a surface shape deformed by heating of the insulating circuit substrate when the back surface shape in contact with the insulating circuit substrate is soldered to the semiconductor chip;
An opening formed through the jig body, for positioning the semiconductor chip by dropping the semiconductor chip;
A positioning jig characterized by comprising: 前記絶縁回路基板が前記半導体チップの半田付け時における加熱によって裏面側に凸形状に変形する形状に対応して、
前記治具本体には、前記絶縁回路基板との接触面側に、前記開口部から離れる方向で薄くするような段差が形成されていることを特徴とする請求項１記載の位置決め治具。 Corresponding to the shape in which the insulating circuit board deforms into a convex shape on the back side by heating at the time of soldering the semiconductor chip,
The positioning jig according to claim 1, wherein a step is formed on the jig main body so as to be thinned in a direction away from the opening on the contact surface side with the insulated circuit board. 前記絶縁回路基板が前記半導体チップの半田付け時における加熱によって裏面側に凸の曲面形状に変形する反り形状に応じて、
前記治具本体には、変形した前記絶縁回路基板の接触面に合致する曲面が形成されていることを特徴とする請求項１記載の位置決め治具。 According to the warped shape in which the insulated circuit board is deformed into a curved shape convex on the back side by heating when soldering the semiconductor chip,
The positioning jig according to claim 1, wherein the jig body is formed with a curved surface that matches the deformed contact surface of the insulated circuit board. 前記治具本体には、前記開口部が複数形成されていることを特徴とする請求項１記載の位置決め治具。   The positioning jig according to claim 1, wherein a plurality of the openings are formed in the jig body. 前記治具本体は、耐熱性のカーボン材料によって構成されていることを特徴とする請求項１記載の位置決め治具。   The positioning jig according to claim 1, wherein the jig body is made of a heat-resistant carbon material. 請求項１から５のいずれか１項に記載の位置決め治具を使用して、絶縁回路基板の金属回路側に半導体チップを半田付けによって実装する工程において、
前記位置決め治具の開口部に半田板および半導体チップを配置し、前記絶縁回路基板とともに加熱して前記半田板を溶融して前記絶縁回路基板に前記半導体チップを実装することを特徴とする半導体装置の製造方法。 In the step of mounting the semiconductor chip by soldering on the metal circuit side of the insulating circuit board using the positioning jig according to any one of claims 1 to 5,
A semiconductor device comprising: a solder plate and a semiconductor chip disposed in an opening of the positioning jig; and heating with the insulating circuit substrate to melt the solder plate and mounting the semiconductor chip on the insulating circuit substrate. Manufacturing method. 前記絶縁回路基板への前記半導体チップの実装工程では、前記金属板側で放熱板が半田付けによって同時に固着するようにしたことを特徴とする請求項６記載の半導体装置の製造方法。   7. The method of manufacturing a semiconductor device according to claim 6, wherein in the step of mounting the semiconductor chip on the insulating circuit board, a heat radiating plate is simultaneously fixed by soldering on the metal plate side. 前記絶縁回路基板は、前記金属回路が前記金属板より厚く接合されていることを特徴とする請求項６記載の半導体装置の製造方法。   7. The method of manufacturing a semiconductor device according to claim 6, wherein the metal circuit is bonded to the insulating circuit board thicker than the metal plate. 前記絶縁回路基板は、前記金属回路および前記金属板が銅材あるいはアルミ材によって構成されていることを特徴とする請求項６記載の半導体装置の製造方法。   The method of manufacturing a semiconductor device according to claim 6, wherein the insulating circuit substrate includes the metal circuit and the metal plate made of a copper material or an aluminum material. 前記絶縁回路基板は、前記金属回路が前記金属板より沿面距離が長く形成されていることを特徴とする請求項６記載の半導体装置の製造方法。   The method of manufacturing a semiconductor device according to claim 6, wherein the insulating circuit board is formed such that the metal circuit has a creepage distance longer than that of the metal plate. 前記半導体チップは、ＩＧＢＴあるいはＦＷＤチップであることを特徴とする請求項６記載の半導体装置の製造方法。   The method of manufacturing a semiconductor device according to claim 6, wherein the semiconductor chip is an IGBT or an FWD chip. 前記絶縁回路基板を加熱炉に挿入して、前記半田板を溶融することを特徴とする請求項６記載の半導体装置の製造方法。   7. The method of manufacturing a semiconductor device according to claim 6, wherein the insulating circuit board is inserted into a heating furnace to melt the solder plate.
JP2008203677A 2008-08-07 2008-08-07 Positioning jig and method for manufacturing semiconductor device Active JP5262408B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2008203677A JP5262408B2 (en) 2008-08-07 2008-08-07 Positioning jig and method for manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2008203677A JP5262408B2 (en) 2008-08-07 2008-08-07 Positioning jig and method for manufacturing semiconductor device

Publications (2)

Publication Number Publication Date
JP2010040881A JP2010040881A (en) 2010-02-18
JP5262408B2 true JP5262408B2 (en) 2013-08-14

Family

ID=42013087

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2008203677A Active JP5262408B2 (en) 2008-08-07 2008-08-07 Positioning jig and method for manufacturing semiconductor device

Country Status (1)

Country Link
JP (1) JP5262408B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104332415A (en) * 2014-11-07 2015-02-04 无锡中微高科电子有限公司 Method for mounting and positioning semiconductor chip and positioning jig

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5838559B2 (en) 2011-02-08 2016-01-06 富士電機株式会社 Semiconductor device assembly jig and semiconductor device assembly method
JP5811648B2 (en) * 2011-07-12 2015-11-11 富士電機株式会社 Semiconductor device assembly jig and semiconductor device manufacturing method using the same
JP2013052361A (en) * 2011-09-05 2013-03-21 Fujifilm Corp Chemical bath deposition apparatus
JP5853525B2 (en) * 2011-09-16 2016-02-09 富士電機株式会社 Semiconductor chip positioning jig and semiconductor device manufacturing method
CN103240481B (en) * 2012-02-08 2016-07-06 西安永电电气有限责任公司 Welder's piece installing
JP7013717B2 (en) * 2017-08-17 2022-02-01 富士電機株式会社 Manufacturing method of semiconductor device and soldering auxiliary jig
CN109576676B (en) * 2018-12-25 2023-12-29 西安立芯光电科技有限公司 Clamp for coating side cavity surface of semiconductor laser

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5238885A (en) * 1975-09-22 1977-03-25 Nec Home Electronics Ltd Method for production of semiconductor device
JPH06232185A (en) * 1993-02-05 1994-08-19 Toshiba Corp Temporarily fixing method for semiconductor chip
JP3007086U (en) * 1994-06-30 1995-02-07 日本インター株式会社 Insulating substrate
JPH0832296A (en) * 1994-07-11 1996-02-02 Ibiden Co Ltd Positioning method for mounting electronic device
JP3333409B2 (en) * 1996-11-26 2002-10-15 株式会社日立製作所 Semiconductor module
JP3505950B2 (en) * 1997-03-21 2004-03-15 トヨタ自動車株式会社 Heat sink plate
JPH10308572A (en) * 1997-05-07 1998-11-17 Pfu Ltd Printed wiring board and mounting structure of surface mounting device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104332415A (en) * 2014-11-07 2015-02-04 无锡中微高科电子有限公司 Method for mounting and positioning semiconductor chip and positioning jig
CN104332415B (en) * 2014-11-07 2017-02-15 无锡中微高科电子有限公司 Method for mounting and positioning semiconductor chip and positioning jig

Also Published As

Publication number Publication date
JP2010040881A (en) 2010-02-18

Similar Documents

Publication Publication Date Title
JP5262408B2 (en) Positioning jig and method for manufacturing semiconductor device
JP4635564B2 (en) Semiconductor device
JP4438489B2 (en) Semiconductor device
JP5387685B2 (en) Manufacturing method of semiconductor device
JP5853525B2 (en) Semiconductor chip positioning jig and semiconductor device manufacturing method
JP6435945B2 (en) Power module board with heat sink
JP5214936B2 (en) Semiconductor device
JPH04137551A (en) Semiconductor device
JP2003273289A (en) Ceramic circuit board and power module
JP2014013908A (en) Molded semiconductor package with integrated through hole technology (tht) heat spreader pin and method of manufacturing the same
JP4385324B2 (en) Semiconductor module and manufacturing method thereof
JP6206494B2 (en) Semiconductor device
JP5151080B2 (en) Insulating substrate, method for manufacturing insulating substrate, power module substrate and power module
JP2958692B2 (en) Ball grid array semiconductor package member, method of manufacturing the same, and method of manufacturing ball grid array semiconductor package
JP6200759B2 (en) Semiconductor device and manufacturing method thereof
JP2010147053A (en) Semiconductor device
KR101994727B1 (en) Power module Package and Manufacturing Method for the same
JP2009147123A (en) Semiconductor device, and manufacturing method therefor
WO2019116910A1 (en) Semiconductor device and method for producing semiconductor device
JP2017212362A (en) Circuit board assembly, electronic device assembly, manufacturing method of circuit board assembly and manufacturing method of electronic device
JP7310161B2 (en) Semiconductor device and its manufacturing method
JP6011410B2 (en) Semiconductor device assembly, power module substrate and power module
KR102039791B1 (en) Mounting method of semiconductor chip and semiconductor chip package
JP2009224529A (en) Semiconductor device and its manufacturing method
JP7294068B2 (en) Terminal and manufacturing method thereof

Legal Events

Date Code Title Description
A711 Notification of change in applicant

Free format text: JAPANESE INTERMEDIATE CODE: A712

Effective date: 20091112

RD03 Notification of appointment of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7423

Effective date: 20091112

RD04 Notification of resignation of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7424

Effective date: 20091112

A711 Notification of change in applicant

Free format text: JAPANESE INTERMEDIATE CODE: A712

Effective date: 20110422

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20110614

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20120606

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20120710

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20120910

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20130402

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20130415

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

Ref document number: 5262408

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250