JP5853525B2 - Semiconductor chip positioning jig and semiconductor device manufacturing method - Google Patents

Semiconductor chip positioning jig and semiconductor device manufacturing method Download PDF

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JP5853525B2
JP5853525B2 JP2011202923A JP2011202923A JP5853525B2 JP 5853525 B2 JP5853525 B2 JP 5853525B2 JP 2011202923 A JP2011202923 A JP 2011202923A JP 2011202923 A JP2011202923 A JP 2011202923A JP 5853525 B2 JP5853525 B2 JP 5853525B2
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semiconductor chip
positioning jig
solder
circuit board
hole
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JP2013065662A (en
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健志 甲斐
健志 甲斐
孝敏 小林
孝敏 小林
小田　佳典
佳典 小田
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Fuji Electric Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/3201—Structure
    • H01L2224/32012—Structure relative to the bonding area, e.g. bond pad
    • H01L2224/32014—Structure relative to the bonding area, e.g. bond pad the layer connector being smaller than the bonding area, e.g. bond pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Die Bonding (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Description

本発明は、両面に金属薄板が接合されている絶縁回路基板の表面側の所定の位置に一以上の半導体チップを半田接合させて半導体モジュールとする半導体装置の製造方法および半導体チップを絶縁回路基板上の所定の位置にずれなく搭載し良好に半田接合させるために用いられる半導体チップの位置決め治具の改良に関する。   The present invention relates to a method of manufacturing a semiconductor device by soldering one or more semiconductor chips to a predetermined position on the surface side of an insulating circuit board having metal thin plates bonded to both sides to form a semiconductor module, and the semiconductor chip to an insulating circuit board The present invention relates to an improvement in a semiconductor chip positioning jig used for mounting in a predetermined position on the upper side without being displaced and for good solder bonding.

大電流・高電圧環境下でも動作可能なパワー半導体モジュールが様々な分野で用いられるようになっている。このようなパワー半導体モジュールの一例を図４の断面模式図に示す。図中の符号については、括弧内の符号を用いる。パワー半導体モジュール２００には、主に、絶縁ゲートバイポーラトランジスタ（Ｉｎｓｕｌａｔｅｄ Ｇａｔｅ Ｂｉｐｏｌａｒ Ｔｒａｎｓｉｓｔｏｒ：以下、ＩＧＢＴという。）やフリーホイーリングダイオード（Ｆｒｅｅ Ｗｈｅｅｌｉｎｇ Ｄｉｏｄｅ：以下、ＦＷＤという。）等の複数のパワー半導体チップ１０１が組み込まれる。これらの複数のパワー半導体チップ１０１は絶縁回路基板１００上の所定の位置に設けられる半田接合可能な金属薄板（図示せず）上に搭載され、絶縁回路基板１００はさらに金属放熱板１０６上に搭載され半田接合される。絶縁回路基板１００上に半田接合された半導体チップ１０１は、その表面の金属電極（図示せず）と外部端子１０８とを導電接続させるためにアルミワイヤ１０５などにより所要の配線接続処理が施され、半導体モジュール２００として組み立てられ、樹脂封止されて完成する。   Power semiconductor modules that can operate in a large current / high voltage environment are used in various fields. An example of such a power semiconductor module is shown in the schematic cross-sectional view of FIG. For the reference numerals in the figure, the reference numerals in parentheses are used. The power semiconductor module 200 mainly includes a plurality of power semiconductor chips 101 such as an insulated gate bipolar transistor (hereinafter referred to as IGBT) and a free wheeling diode (hereinafter referred to as FWD). Is incorporated. The plurality of power semiconductor chips 101 are mounted on a solderable metal thin plate (not shown) provided at a predetermined position on the insulating circuit board 100, and the insulating circuit board 100 is further mounted on a metal heat sink 106. And soldered. The semiconductor chip 101 soldered onto the insulating circuit board 100 is subjected to a required wiring connection process using an aluminum wire 105 or the like in order to conductively connect a metal electrode (not shown) on the surface and the external terminal 108, The semiconductor module 200 is assembled and resin-sealed to complete.

図５、図６に、そのような従来の半導体モジュールの製造方法に係る半田接合工程に用いられる半導体チップの位置決めに用いられるカーボン治具およびこのカーボン治具を用いて絶縁回路基板上に半田板と半導体チップをセットした半田接合組み立てセットを示す。詳細には図５（ａ）はカーボン治具１０３の平面図、同（ｂ）は同（ａ）のＡ−Ａ’線断面図である。図６は、絶縁回路基板１００上に、カーボン治具１０３を載せて固定し、このカーボン治具１０３の貫通孔１０２に半田板１０４と半導体チップ１０１を入れた半田接合組み立てセットの平面図（ａ）と、この図（ａ）のＢ−Ｂ’線断面図（ｂ）である。斜線ハッチングはカーボン治具１０３を示す。なお、前記図４では、搭載されている複数の半導体チップのうち、一個の半導体チップだけを示しているが、実際には図示しない複数の半導体チップが搭載されている。   FIG. 5 and FIG. 6 show a carbon jig used for positioning a semiconductor chip used in a solder bonding process according to such a conventional method for manufacturing a semiconductor module, and a solder plate on an insulating circuit board using the carbon jig. And a solder joint assembly set in which a semiconductor chip is set. Specifically, FIG. 5A is a plan view of the carbon jig 103, and FIG. 5B is a cross-sectional view taken along line A-A 'of FIG. FIG. 6 is a plan view of a solder joint assembly set in which a carbon jig 103 is placed and fixed on an insulating circuit board 100, and a solder plate 104 and a semiconductor chip 101 are placed in a through hole 102 of the carbon jig 103 (a). And BB ′ line cross-sectional view (b) of FIG. The hatched area indicates the carbon jig 103. FIG. 4 shows only one semiconductor chip among a plurality of mounted semiconductor chips, but a plurality of semiconductor chips (not shown) are actually mounted.

このような半導体モジュールを製造するための半導体チップの半田接合技術に関して、絶縁回路基板上に半導体チップのサイズに対応する貫通孔を有する位置決め用カーボン治具を載置して半導体チップの位置ズレを防止することが記載されている文献がある（特許文献１）。また、半田接合時にガスが発生し、ボイドができること、このガスの放散通路を確保してボイドの形成を抑制する方法などが知られている（特許文献２）。ダイボンディング時に溶剤の放散をよくするために、気泡の逃げ道を形成するとよいという公開文献がある（特許文献３）。ノンフラックス系ハンダ材を還元雰囲気中で使用するようにして、飛散するフラックスによる半導体素子の汚染を防止して歩留りの低下を防ぐ方法も公知になっている（特許文献４）。   Regarding semiconductor chip solder bonding technology for manufacturing such a semiconductor module, a positioning carbon jig having a through hole corresponding to the size of the semiconductor chip is placed on an insulating circuit board to shift the position of the semiconductor chip. There is a document describing prevention (Patent Document 1). Further, a method is known in which gas is generated during solder bonding and voids are formed, and a method for suppressing the formation of voids by securing a gas diffusion path (Patent Document 2). There is a published document in which a bubble escape path should be formed in order to improve solvent diffusion during die bonding (Patent Document 3). A method is also known in which a non-flux solder material is used in a reducing atmosphere to prevent contamination of a semiconductor element due to scattered flux and prevent a decrease in yield (Patent Document 4).

特開２０１０−４０８８１号公報（段落００１３）JP 2010-40881 A (paragraph 0013) 特開２００９−１６４２０３号公報（段落０００７）JP 2009-164203 A (paragraph 0007) 特開平０６−３１４７１８号公報（要約）JP 06-314718 A (summary) 特開平０５−２８３４５２号公報（要約）Japanese Patent Laid-Open No. 05-283452 (Summary)

しかしながら、前述のように、半導体モジュールの組み立てセットを半田板１０４の溶融温度以上に設定された減圧加熱炉に入れて半導体チップ１０１を絶縁回路基板１００上に半田接合させる際、図７に示すように溶融半田に巻き込まれた空気がボイド１０９となって混ざり、減圧とともにボイド１０９が溶融半田から飛び出し、その際に溶融した半田が半田飛沫１０７となって飛散することが問題となる。すなわち、このように半田板１０４に巻き込まれたボイド１０９とともに溶融半田から飛び出した半田飛沫１０７がカーボン治具１０３と半導体チップ１０１との間隙１１０から飛散すると、飛散した半田飛沫１０７が半導体チップ１０１の表面に落下し付着することがある。半導体チップ１０１上に落下付着した半田飛沫１０７に起因して半導体チップ１０１が特性不良となる場合があって問題となる。   However, as described above, when the assembly set of the semiconductor module is placed in a reduced pressure heating furnace set to a temperature equal to or higher than the melting temperature of the solder plate 104 and the semiconductor chip 101 is soldered onto the insulating circuit board 100, as shown in FIG. The air entrained in the molten solder becomes a void 109 and mixes. When the pressure is reduced, the void 109 jumps out of the molten solder, and the molten solder is scattered as solder droplets 107 at that time. That is, when the solder droplets 107 that have jumped out of the molten solder together with the voids 109 wound around the solder plate 104 scatter from the gap 110 between the carbon jig 103 and the semiconductor chip 101, the scattered solder droplets 107 form the semiconductor chip 101. May fall and adhere to the surface. The semiconductor chip 101 may have a characteristic defect due to the solder droplets 107 dropped and adhered onto the semiconductor chip 101, which is a problem.

本発明は、以上説明した課題を解消するためになされたものであり、本発明の目的は、減圧半田接合工程時に発生する溶融半田飛沫の飛散を防止し、半導体チップの汚染や不良発生を抑制することのできる半導体装置の製造方法および半導体チップの位置決め治具を提供することである。   The present invention has been made to solve the above-described problems, and an object of the present invention is to prevent molten solder droplets from being scattered during a reduced-pressure solder bonding process and to suppress the occurrence of contamination and defects of semiconductor chips. A semiconductor device manufacturing method and a semiconductor chip positioning jig that can be used.

本発明は、前記課題を解消して本発明の目的を達成するために、絶縁回路基板に設置された金属薄板上に半導体チップ半田付けする際に用いられる半導体チップの位置決め治具であって、前記位置決め治具は、前記半導体チップを嵌め合わせる貫通孔を有していて、前記貫通孔の下端部に前記半導体チップに面して切り込まれた空間である切込み部を有し、前記位置決め治具の下端面は前記絶縁回路基板の凹状の反りに合わせた曲面の加工が施された形状を有している半導体チップの位置決め治具とする。 The present invention is a semiconductor chip positioning jig used when soldering a semiconductor chip on a metal thin plate placed on an insulated circuit board in order to solve the above-mentioned problems and achieve the object of the present invention, the positioning jig, the fitting of the semiconductor chip have a through-hole has a notch portion is a space cut facing the semiconductor chip to the lower end of the through hole, the positioning jig The lower end surface of the tool is a semiconductor chip positioning jig having a shape in which a curved surface is processed in accordance with the concave warp of the insulated circuit board .

本発明においては、前記切り込み部が貫通孔の全周に設けられていることが好ましい。また、前記貫通孔の下端部に設けられる切り込み部の高さが、溶融半田の厚さ以上、半導体チップの上面以下であることも好ましい。前記位置決め治具の主面に沿った方向の前記切り込み部の距離が、前記切り込み部の高さと同程度であることもより好ましい。前記半導体チップの位置決め治具がカーボンを主材料としていることが好適である。前記半導体チップの位置決め治具の厚さが半田板と半導体チップの厚さの合計よりも厚いことがより望ましい。 In this invention, it is preferable that the said notch part is provided in the perimeter of a through-hole. Moreover, it is also preferable that the height of the notch provided in the lower end portion of the through hole is not less than the thickness of the molten solder and not more than the upper surface of the semiconductor chip. It is more preferable that the distance of the cut portion in the direction along the main surface of the positioning jig is substantially the same as the height of the cut portion. The semiconductor chip positioning jig is preferably made of carbon as a main material. More preferably, the thickness of the semiconductor chip positioning jig is larger than the total thickness of the solder plate and the semiconductor chip.

さらに、金属放熱板上に、その一方の面に半田板を挟んで絶縁回路基板を載せ、該絶縁回路基板のもう一方の面に、その下端面が前記絶縁回路基板の凹状の反りに合わせた曲面の加工が施された形状を有している半導体チップの位置決め治具を載置し固定し、前記位置決め治具の貫通孔であってその貫通孔の下端部に前記半導体チップに面して切り込まれた空間を有する貫通孔に半田板と半導体チップをセットし、減圧下で前記半田板の熔融温度以上に加熱して、前記金属放熱板、絶縁回路基板及び半導体チップとをそれぞれ半田接合する工程を有する半導体装置の製造方法とすることにより、前記発明の目的が達成される。前記半導体チップが絶縁ゲート型バイポーラトランジスタチップおよびダイオードチップとすることができる。
Furthermore, an insulating circuit board is placed on one surface of the metal heat sink with a solder plate interposed therebetween, and the lower end surface of the insulating circuit board is aligned with the concave warp of the insulating circuit board. A semiconductor chip positioning jig having a curved shape is placed and fixed, and the through hole of the positioning jig faces the semiconductor chip at the lower end of the through hole. A solder plate and a semiconductor chip are set in a through hole having a cut-in space, and heated to a temperature equal to or higher than the melting temperature of the solder plate under reduced pressure, and the metal heat dissipation plate, the insulating circuit board, and the semiconductor chip are soldered to each other. The object of the present invention is achieved by providing a method of manufacturing a semiconductor device having the steps of: The semiconductor chip may be an insulated gate bipolar transistor chip and a diode chip.

本発明によれば、減圧半田接合工程時に発生する溶融半田飛沫の飛散を防止し、半導体チップの汚染や不良発生を抑制することのできる半導体装置の製造方法および半導体チップの位置決め治具を提供することができる。   According to the present invention, there are provided a semiconductor device manufacturing method and a semiconductor chip positioning jig capable of preventing the molten solder droplets generated during the reduced-pressure solder bonding process from being scattered and suppressing the occurrence of contamination and defects of the semiconductor chip. be able to.

（ａ）は本発明のカーボン治具の平面図である。（ｂ）は（ａ）のＣ−Ｃ’線断面図である。（ｃ）は（ｂ）の破線○部の拡大断面図である。(A) is a top view of the carbon jig of the present invention. (B) is the sectional view on the C-C 'line of (a). (C) is an expanded sectional view of the broken-line (circle) part of (b). 本発明の半田接合工程を示す半田組み立てセットの要部断面図（その１）である。It is principal part sectional drawing (the 1) of the solder assembly set which shows the solder joining process of this invention. 本発明の半田接合工程を示す半田組み立てセットの要部断面図（その２）である。It is principal part sectional drawing (the 2) of the solder assembly set which shows the solder joining process of this invention. 一般的な半導体モジュールの断面模式図である。It is a cross-sectional schematic diagram of a general semiconductor module. （ａ）は従来のカーボン治具の平面図、（ｂ）は（ａ）のＡ−Ａ’線断面図である。(A) is a top view of the conventional carbon jig | tool, (b) is the sectional view on the A-A 'line of (a). （ａ）は従来の絶縁回路基板とカーボン治具と半田板と半導体チップの半田接合組み立てセットの平面図、（ｂ）は（ａ）のＢ−Ｂ’線断面図（ｂ）である。(A) is a plan view of a conventional soldered assembly set of an insulated circuit board, a carbon jig, a solder plate, and a semiconductor chip, and (b) is a cross-sectional view (b) taken along line B-B ′ of (a). 従来の半田接合工程を示す半田組み立てセットの要部断面図である。It is principal part sectional drawing of the solder assembly set which shows the conventional solder joining process.

本発明の半導体装置の製造方法および半導体チップの位置決め治具の実施例について、図面を参照して詳細に説明する。本発明はその要旨を超えない限り、以下説明する実施例のみに限定されるものではない。   Embodiments of a semiconductor device manufacturing method and a semiconductor chip positioning jig according to the present invention will be described in detail with reference to the drawings. The present invention is not limited to only the examples described below as long as the gist thereof is not exceeded.

図１は、本発明の実施例１に係る半導体チップの位置決め治具を示す平面図（ａ）とこの平面図（ａ）のＣ−Ｃ'線断面図（ｂ）と図（ｂ）の破線円の拡大断面図（ｃ）である。図２は、絶縁回路基板５上に、本発明の位置決め用のカーボン治具３、３ａ、３ｂをそれぞれ載せて固定し、これらのカーボン治具３、３ａ、３ｂの貫通孔２内に半田板４と半導体チップ１を落とし入れて減圧加熱炉（図示せず）で半田板４を溶融させるという本発明にかかる半田接合工程を説明するための半田組み立てセットの要部断面図である。図２の（ａ）、（ｂ）、（ｃ）はそれぞれ異なる形状の本発明の位置決め用カーボン治具を有することを示す半田組み立てセットの要部断面図である。   1A is a plan view showing a semiconductor chip positioning jig according to Embodiment 1 of the present invention, FIG. 1B is a cross-sectional view taken along the line CC ′ of FIG. It is an expanded sectional view (c) of a circle. FIG. 2 shows that the carbon jigs 3, 3 a, 3 b for positioning according to the present invention are respectively mounted and fixed on an insulating circuit board 5, and a solder plate is placed in the through holes 2 of these carbon jigs 3, 3 a, 3 b. 4 is a cross-sectional view of an essential part of a solder assembly set for explaining a solder joining process according to the present invention in which 4 and a semiconductor chip 1 are dropped and a solder plate 4 is melted in a reduced pressure heating furnace (not shown). FIGS. 2A, 2B, and 2C are cross-sectional views of main parts of a solder assembly set showing that the positioning carbon jigs of the present invention having different shapes are provided.

従来の半田接合では前記図７でも説明したように、絶縁回路基板１００とカーボン治具１０３と半田板１０４と半導体チップ１０１などからなる半田組み立てセットを半田板１０４の溶融温度以上、例えば３００℃程度の減圧加熱炉（図示せず）に入れて半導体チップ１０１を絶縁回路基板１００の所定の位置に半田接合させる。絶縁回路基板１００上の金属薄板（図示せず）と半導体チップ１０１との間に挟まれる半田板１０４が溶融する際に、巻き込まれた空気がボイド１０９となって溶融半田とともに半田飛沫１０７となって飛び出して飛散することがある。従来は、このような状態で溶融半田から飛散した半田飛沫１０７がカーボン治具１０３と半導体チップ１０１との間隙１１０から飛散し易く、飛散した半田飛沫１０７が半導体チップ１０１の表面に落下し付着して特性不良となることが問題であった。   In the conventional solder bonding, as described with reference to FIG. 7, a solder assembly set including the insulating circuit substrate 100, the carbon jig 103, the solder plate 104, the semiconductor chip 101, and the like is not less than the melting temperature of the solder plate 104, for example, about 300 ° C. The semiconductor chip 101 is soldered to a predetermined position of the insulating circuit board 100 in a reduced pressure heating furnace (not shown). When the solder plate 104 sandwiched between the thin metal plate (not shown) on the insulating circuit substrate 100 and the semiconductor chip 101 is melted, the entrained air becomes a void 109 and becomes a solder droplet 107 together with the molten solder. May fly out and scatter. Conventionally, the solder droplets 107 scattered from the molten solder in such a state are easily scattered from the gap 110 between the carbon jig 103 and the semiconductor chip 101, and the scattered solder droplets 107 fall and adhere to the surface of the semiconductor chip 101. The problem was that the characteristics were poor.

この問題は、間隙１１０を狭くすることでは解消されない。間隙１１０を狭くすると、半導体チップ１０１を貫通孔１０２へ落とし入れる作業性が悪くなるとともに、却って、間隙１１０から飛び出す圧力が高くなり、飛び出し距離が長くなる傾向があるからである。間隙を広くすれば、飛び出し距離は短くなるが、半導体チップ１０１の位置ズレが大きくなるので、採用することが困難である。   This problem cannot be solved by narrowing the gap 110. This is because if the gap 110 is narrowed, the workability of dropping the semiconductor chip 101 into the through-hole 102 is deteriorated, and on the contrary, the pressure popping out from the gap 110 tends to be high and the popping distance tends to be long. If the gap is widened, the jump-out distance is shortened, but the positional deviation of the semiconductor chip 101 is increased, which is difficult to adopt.

ここで、発明者らは、図２に示すように、本発明のカーボン治具３、３ａ、３ｂなどの実施例を用いて絶縁回路基板５上へ半導体チップ１を位置決めして半田接合すると、カーボン治具と半導体チップとの間隙を広くしなくても、前述のような半田飛沫の飛散を抑制することができることを見出した。その結果、半導体チップの位置ズレがなく、特性不良も抑制されるメリットが得られる。以下、その理由について説明する。   Here, as shown in FIG. 2, the inventors positioned the semiconductor chip 1 on the insulating circuit board 5 using the embodiment of the carbon jigs 3, 3a, 3b of the present invention and soldered them. It has been found that the above-described scattering of solder droplets can be suppressed without widening the gap between the carbon jig and the semiconductor chip. As a result, there is a merit that there is no misalignment of the semiconductor chip and characteristic defects are suppressed. The reason will be described below.

本発明にかかるカーボン治具３は、従来と同様に、半田接合材の溶融温度に対する充分な耐熱性を有し、溶融半田に濡れることのないグラファイトなどのカーボンの薄板を必要な形状に削りだして作成される。図１にそのようなカーボン治具３の一例を平面図、断面図で示す。従来のカーボン治具である図５に示すカーボン治具１０３との違いは、本発明のカーボン治具３には、例えば、図１（ｂ）およびその破線円の拡大断面図（ｃ）に示すように、貫通孔２の絶縁回路基板５に接触する側の下端部１０に面取りが施され、面取りで形成される切り込み面９による空間１３が設けられていることである。この貫通孔２は、従来と同様に絶縁回路基板５上の所定の位置に載置固定された後、半田板４と半導体チップ１が落とし入れられて、半導体チップ１を絶縁回路基板５上の決められた位置にズレなく半田接合させる機能を備えている。貫通孔２は半導体チップ１と相似形でやや大きい形状、例えば、貫通孔２に半導体チップ１を入れた時のカーボン治具３との間の一辺の間隙は０．３ｍｍ±０．１ｍｍ程度とすることが好ましい。これより間隙８が大きいと半田の溶融後に位置ズレがおき易くなるし、狭いと、半導体チップ１を入れる作業効率が悪くなるだけでなく、本発明にかかるカーボン治具３を用いても半田板４に巻き込まれた空気などのボイド６が突沸状に溶融半田から飛び出し、半田飛沫７となって飛散することがあるので、好ましくない。   The carbon jig 3 according to the present invention has a sufficient heat resistance with respect to the melting temperature of the solder bonding material as in the prior art, and cuts a carbon thin plate such as graphite that does not get wet with the molten solder into a required shape. Created. FIG. 1 shows an example of such a carbon jig 3 in a plan view and a cross-sectional view. The difference from the carbon jig 103 shown in FIG. 5 which is a conventional carbon jig is that the carbon jig 3 of the present invention is shown in, for example, FIG. Thus, the lower end portion 10 on the side of the through hole 2 that contacts the insulated circuit board 5 is chamfered, and the space 13 is formed by the cut surface 9 formed by chamfering. The through-hole 2 is placed and fixed at a predetermined position on the insulating circuit board 5 as in the prior art, and then the solder plate 4 and the semiconductor chip 1 are dropped, so that the semiconductor chip 1 is placed on the insulating circuit board 5. It is equipped with a function that allows solder joining to a predetermined position without deviation. The through hole 2 is similar in shape to the semiconductor chip 1 and slightly larger. For example, the gap between one side of the through hole 2 and the carbon jig 3 when the semiconductor chip 1 is inserted is about 0.3 mm ± 0.1 mm. It is preferable to do. If the gap 8 is larger than this, the positional deviation is likely to occur after melting of the solder, and if it is narrow, not only the work efficiency for inserting the semiconductor chip 1 is deteriorated, but also the solder plate is used even if the carbon jig 3 according to the present invention is used. Since voids 6 such as air entrained in 4 jump out of the molten solder in a bumpy manner and may be scattered as solder droplets 7, it is not preferable.

しかし、本発明のカーボン治具３では、図２に示すように貫通孔２の下端部１０の全周に前述のような前記半導体チップに面して切り込まれた空間となる切り込み部９、９ａ、９ｂが施されているので、溶融半田から飛び出してきた半田飛沫７があっても、多くは切り込み部９、９ａ、９ｂにより形成されたカーボン治具３の貫通孔２下端部の空間１３に留まり、半導体チップ１より外方に飛散することが抑制される。前記面取り部を含む切り取り部９、９ａ、９ｂの目的は貫通孔２の下端部１０に空間１３を形成することにある。従って、空間１３が形成されるならば、いわゆる面取りという方法だけでなく、例えば、図２（ｂ）に示すように、断面が円弧状の切り込み部９ａでもよいし、図２（ｃ）に示すように、断面矩形状の切り込み部９ｂでもよい。さらに、図２以外の切り込み部であってもよい。また、切り込み部９、９ａ、９ｂの目的は、前述のように、貫通孔２の下端部１０に空間１３を形成することにあるので、切り込み部９、９ａ、９ｂは必ずしも貫通孔２の下端部１０の全周に亘って完全に形成されていなくてもよい。一部、部分的に切り込み部が無い部分があっても構わない。   However, in the carbon jig 3 of the present invention, as shown in FIG. 2, a cut portion 9 that becomes a space cut into the entire periphery of the lower end portion 10 of the through hole 2 so as to face the semiconductor chip as described above, Since 9a and 9b are applied, even if there is a solder droplet 7 that has jumped out of the molten solder, most of the space 13 is located at the lower end of the through hole 2 of the carbon jig 3 formed by the notches 9, 9a, and 9b. It is restrained that the semiconductor chip 1 is scattered outside. The purpose of the cut-out portions 9, 9 a, 9 b including the chamfered portion is to form a space 13 in the lower end portion 10 of the through hole 2. Therefore, if the space 13 is formed, not only a so-called chamfering method, but also a cut portion 9a having a circular cross section as shown in FIG. 2B, for example, or shown in FIG. Thus, the cut portion 9b having a rectangular cross section may be used. Further, it may be a cut portion other than FIG. Moreover, since the purpose of the notches 9, 9a, 9b is to form the space 13 in the lower end 10 of the through hole 2 as described above, the notches 9, 9a, 9b are not necessarily the lower end of the through hole 2. It may not be completely formed over the entire circumference of the portion 10. There may be a part that does not have a cut part.

一方、切り込み部９、９ａ、９ｂのカーボン治具の下端部１０からの高さ１２は少なくとも、溶融半田の厚さ（または半導体チップの下面）よりは高く、半導体チップ１の上面よりは低くすることが望ましい。切り込み部９、９ａ、９ｂの高さ１２が溶融半田の厚さより低いと、溶融半田から飛散する半田飛沫７を切り込み部９、９ａ、９ｂの空間１３に留める機能が不充分になる惧れが生じる。また、切り込み部９、９ａ、９ｂの高さ１２が半導体チップ１の上面より高いと、一旦、切り込み部９、９ａ、９ｂの空間１３に取り込まれた半田飛沫７が半導体チップ１表面の方向に沿って飛散する惧れが大きくなるからである。また、カーボン治具３、３ａ、３ｂの上面は半田板４もしくは溶融半田と半導体チップ１の合計厚さより厚いことがカーボン治具３、３ａ、３ｂの強度の点からも望ましい。   On the other hand, the height 12 of the notches 9, 9a, 9b from the lower end 10 of the carbon jig is at least higher than the thickness of the molten solder (or the lower surface of the semiconductor chip) and lower than the upper surface of the semiconductor chip 1. It is desirable. If the heights 12 of the notches 9, 9a, 9b are lower than the thickness of the molten solder, the function of retaining the solder droplets 7 scattered from the molten solder in the space 13 of the notches 9, 9a, 9b may be insufficient. Arise. Further, when the height 12 of the notches 9, 9a, 9b is higher than the upper surface of the semiconductor chip 1, the solder droplets 7 once taken into the space 13 of the notches 9, 9a, 9b are directed in the direction of the surface of the semiconductor chip 1. This is because there is a greater risk of splashing along. It is also desirable from the viewpoint of the strength of the carbon jigs 3, 3 a, 3 b that the upper surfaces of the carbon jigs 3, 3 a, 3 b are thicker than the total thickness of the solder plate 4 or the molten solder and the semiconductor chip 1.

絶縁回路基板５の基板面に沿った方向の切り込み部９ａ、９ｂの距離１４を切り込み部の高さ１２に対して相対的に長くすると、カーボン治具３ａ、３ｂの下端面の、絶縁回路基板５との接触端部１１ａ、１１ｂは貫通孔２から外方に離れるので、切り込み部９ａ，９ｂによる空間１３は大きく形成されるので好ましいが、絶縁回路基板５と半導体チップ１との間の溶融半田の広がりが大きくなり過ぎる場合が生じる。溶融半田が広がりすぎると溶融半田の厚さが想定よりも薄くなり過ぎて、応力緩衝機能が弱くなり、接合強度の信頼性が低下する惧れが生じるので、好ましくない。従って、切り込み部９ａ、９ｂの高さ１２と同程度の水平方向の距離１４とすることが好ましい。いわゆる面取りは通常、高さと水平距離とが同程度に切り取られる切り込み部９となるので好ましい。しかし、この高さに対してこの水平距離が大きくてもこの発明の効果はある。   When the distance 14 between the cut portions 9a and 9b in the direction along the substrate surface of the insulated circuit board 5 is made relatively long with respect to the height 12 of the cut portions, the insulated circuit board on the lower end surfaces of the carbon jigs 3a and 3b. Since the contact end portions 11a and 11b with respect to 5 are separated from the through-hole 2 to the outside, the space 13 formed by the notches 9a and 9b is preferably formed large, but melting between the insulating circuit substrate 5 and the semiconductor chip 1 is preferable. In some cases, the solder spread becomes too large. If the molten solder spreads too much, the thickness of the molten solder becomes too thin as expected, the stress buffering function becomes weak, and the reliability of the bonding strength may be lowered. Therefore, it is preferable that the distance 14 in the horizontal direction is approximately the same as the height 12 of the notches 9a and 9b. So-called chamfering is usually preferable because the cut portion 9 is cut at the same height and horizontal distance. However, even if the horizontal distance is large with respect to the height, the effect of the present invention is obtained.

図３は、本発明の異なる半田接合工程を示す要部断面図であって、前記図２に示すカーボン治具３、３ａ、３ｂとは異なり、絶縁回路基板５が半導体チップの搭載側で凹状に沿っている場合に適したカーボン治具３ｃとした例である。すなわち、カーボン治具の下端面を絶縁回路基板５の凹状の反りに合わせた曲面の加工が施された形状を有している。この曲面加工により、絶縁回路基板５が沿っていてもカーボン治具３ｃが絶縁回路基板５から浮き上がることなく下端面を面で接触させることができるので、半導体チップ１を絶縁回路基板５上の所定の位置に精度よく、半田接合させることができる。   FIG. 3 is a cross-sectional view of the main part showing a different solder joining process of the present invention. Unlike the carbon jigs 3, 3a, 3b shown in FIG. 2, the insulated circuit board 5 has a concave shape on the semiconductor chip mounting side. This is an example in which the carbon jig 3c is suitable for the case along the line. In other words, the carbon jig has a shape in which the lower end surface of the carbon jig is curved to match the concave warpage of the insulated circuit board 5. By this curved surface processing, even if the insulated circuit board 5 is along, the carbon jig 3c can be brought into contact with the lower surface without being lifted from the insulated circuit board 5, so that the semiconductor chip 1 is placed on the insulated circuit board 5 in a predetermined manner. Can be soldered with high accuracy to the position.

絶縁回路基板５に前述のような反りがでる原因は、図４に示すように、絶縁回路基板５とその両面に接合される金属薄板（図示せず）と半田と絶縁回路基板５の下側に半田接合される厚い金属放熱板１５などとの間の線膨張係数の差である。金属の線膨張係数は１７〜２３×１０-6（１／℃）に対して絶縁回路基板５の主材料であるセラミックの線膨張係数は３．０〜７．０×１０-6（１／℃）のように、線膨張係数の差が大きいことが、絶縁回路基板５と金属放熱板を半田接合した際に、反りが生じる原因である（バイメタル効果）。本発明にかかる、図３に示すカーボン治具３ｃは、このような反りを含む構成の半導体モジュールの半田接合に適した構造である。 As shown in FIG. 4, the cause of the warping of the insulating circuit board 5 is as follows. This is a difference in linear expansion coefficient between the thick metal heatsink 15 and the like which are soldered to each other. The coefficient of linear expansion of the metal is 17 to 23 × 10 −6 (1 / ° C.), whereas the coefficient of linear expansion of the ceramic that is the main material of the insulating circuit board 5 is 3.0 to 7.0 × 10 −6 (1 / The difference in coefficient of linear expansion as in (° C.) is a cause of warping when the insulating circuit board 5 and the metal heat sink are soldered (bimetallic effect). The carbon jig 3c shown in FIG. 3 according to the present invention has a structure suitable for solder bonding of a semiconductor module having a configuration including such warpage.

次に、本発明の半導体装置の製造方法について説明する。以下の説明では、半導体装置として、半導体モジュールを採りあげて説明する。図４は、そのような本発明の半導体モジュールの製造方法を説明するために参照する一般的な半導体モジュールの断面模式図である。図中の符号は、上段の符号を用いて説明する、前記絶縁回路基板５は、窒化アルミニウムやアルミナなどの絶縁性のセラミック基板を主材料とし、両面には銅板などの半田接合の良好な金属薄板が接合されたものである。特に表面側の金属薄板は、複数の半導体チップ１がそれぞれ必要に応じて独立して半田接合可能なように、それぞれ所要の区画されたパターンで基板表面に接合形成されている。この絶縁回路基板５の裏面には、ほぼ全面に銅などの金属薄板が接合され、さらに半導体モジュール２００のパッケージのベース基板となり機械的強度およびヒートシンク機能も有する厚い金属放熱板１５が半田板４により接合固着される。この絶縁回路基板５の表面に前述の所要の区画パターンに加工され接合されている金属薄板上に、必要な半導体チップ１が半田板４により接合固着される。さらに半導体チップ１の表面上の半導体機能の外部取り出し用金属電極（コレクタ電極、エミッタ電極、ゲート電極など）と外部引き出し端子１８とは直接にまたは必要に応じて前記絶縁回路基板５内の中継位置を経てボンディング接続される。前記樹脂枠１７で囲まれたところへ保護用の樹脂を封入し、図示しない樹脂蓋を樹脂枠１７に接着させて半導体モジュール２００とする。   Next, a method for manufacturing a semiconductor device of the present invention will be described. In the following description, a semiconductor module will be described as a semiconductor device. FIG. 4 is a schematic cross-sectional view of a general semiconductor module referred to for describing such a method of manufacturing a semiconductor module of the present invention. The reference numerals in the figure are described using the upper reference numerals. The insulated circuit board 5 is mainly made of an insulating ceramic substrate such as aluminum nitride or alumina, and has a good solder joint such as a copper plate on both sides. Thin plates are joined. In particular, the metal thin plate on the front surface side is bonded and formed on the substrate surface in a predetermined divided pattern so that the plurality of semiconductor chips 1 can be soldered independently as needed. A thin metal plate made of copper or the like is bonded to almost the entire back surface of the insulating circuit board 5, and a thick metal heat radiating plate 15 serving as a base substrate of the package of the semiconductor module 200 and having mechanical strength and a heat sink function is formed by the solder plate 4. Bonded and fixed. A necessary semiconductor chip 1 is bonded and fixed to the surface of the insulating circuit board 5 by a solder plate 4 on a metal thin plate which is processed and bonded to the above-described required partition pattern. Further, a metal electrode (collector electrode, emitter electrode, gate electrode, etc.) for external extraction of the semiconductor function on the surface of the semiconductor chip 1 and the external lead terminal 18 are directly or as necessary relayed in the insulated circuit board 5. After that, the bonding connection is made. A protective resin is sealed in the area surrounded by the resin frame 17, and a resin lid (not shown) is adhered to the resin frame 17 to form the semiconductor module 200.

前述の半導体モジュール２００内の半導体チップ１の半田接合工程について、図４を参照して詳しく説明する。先ず、外周に外部端子１８が組み込まれた樹脂枠１７を固着させた厚い金属放熱板１５上に、半田板４を介して、前記絶縁回路基板５を図示しない基板用カーボン治具で位置決めして載せる。この絶縁回路基板５上に、前記図１に示す本発明にかかるカーボン治具３を用いて、ＩＧＢＴやＦＷＤなどの半導体チップ１を半田板４とともに所定の位置の貫通孔２にセットし位置決めして配置する。カーボン治具３には、半導体チップ１とほぼ同形状で少し大きい貫通孔２が形成されており、この貫通孔２に半田板４と半導体チップ１を落とし込むと、絶縁回路基板５上の所定の位置に半導体チップ１を位置ズレなく半田接合させることができるように構成されている。これらの金属放熱板１５、絶縁回路基板５、カーボン治具３、半田板４、半導体チップ１などの組み立てセットを半田板４の溶融温度以上、例えば、３００℃の減圧加熱炉（図示せず）に入れて半導体チップ１を絶縁回路基板５の所定の位置に半田接合させる。   The solder bonding process of the semiconductor chip 1 in the semiconductor module 200 will be described in detail with reference to FIG. First, the insulating circuit board 5 is positioned with a substrate carbon jig (not shown) through the solder plate 4 on the thick metal heat radiating plate 15 to which the resin frame 17 having the external terminals 18 incorporated on the outer periphery is fixed. Put it on. On the insulated circuit board 5, using the carbon jig 3 according to the present invention shown in FIG. 1, the semiconductor chip 1 such as IGBT or FWD is set and positioned in the through-hole 2 at a predetermined position together with the solder plate 4. Arrange. The carbon jig 3 is formed with a through hole 2 that is substantially the same shape as the semiconductor chip 1 and is slightly larger. When the solder plate 4 and the semiconductor chip 1 are dropped into the through hole 2, a predetermined on the insulating circuit board 5 is formed. The semiconductor chip 1 is configured to be solder-bonded at a position without any positional deviation. An assembly set of the metal heat sink 15, the insulating circuit board 5, the carbon jig 3, the solder plate 4, the semiconductor chip 1 and the like is a decompression heating furnace (not shown) at a temperature higher than the melting temperature of the solder plate 4, for example, 300 ° C. Then, the semiconductor chip 1 is soldered to a predetermined position of the insulated circuit board 5.

以上説明した実施例１に記載の半導体装置の製造方法および半導体チップの位置決め治具によれば、減圧半田接合工程時に発生する溶融半田飛沫の飛散を防止し、半導体チップの不良発生を抑制することができる。   According to the semiconductor device manufacturing method and the semiconductor chip positioning jig described in the first embodiment described above, it is possible to prevent the molten solder droplets from being scattered during the reduced-pressure solder bonding process and to suppress the occurrence of defects in the semiconductor chip. Can do.

１ 半導体チップ
２ 貫通孔
３、３ａ、３ｂ、３ｃ カーボン治具
４ 半田板
５ 絶縁回路基板
６ ボイド
７ 半田飛沫
８ 間隙
９、９ａ、９ｂ 切り込み部
１０ 下端部
１１ 接触端部
１２ 切り込み部の高さ
１３ 空間
１４ 距離
１５ 金属放熱板
１６ アルミワイヤ
１７ 樹脂枠
１８ 外部引き出し端子

DESCRIPTION OF SYMBOLS 1 Semiconductor chip 2 Through-hole 3, 3a, 3b, 3c Carbon jig 4 Solder plate 5 Insulated circuit board 6 Void 7 Solder splash 8 Gap 9, 9a, 9b Cut part 10 Lower end part 11 Contact end part 12 Cut part height 13 Space 14 Distance 15 Metal heat sink 16 Aluminum wire 17 Resin frame 18 External lead terminal

Claims (8)

絶縁回路基板に設置された金属薄板上に半導体チップ半田付けする際に用いられる半導体チップの位置決め治具であって、前記位置決め治具は、前記半導体チップを嵌め合わせる貫通孔を有していて、前記貫通孔の下端部に前記半導体チップに面して切り込まれた空間である切込み部を有し、前記位置決め治具の下端面は前記絶縁回路基板の凹状の反りに合わせた曲面の加工が施された形状を有していることを特徴とする半導体チップの位置決め治具。 A semiconductor chip positioning jig used when soldering a semiconductor chip on a thin metal plate installed on an insulating circuit board, the positioning jig having a through hole for fitting the semiconductor chip, The lower end portion of the through hole has a cut portion that is a space cut toward the semiconductor chip, and the lower end surface of the positioning jig is processed into a curved surface that matches the concave warp of the insulating circuit board. A semiconductor chip positioning jig characterized by having an applied shape. 前記貫通孔の下端部に設けられる切り込み部の高さが、溶融半田の厚さ以上、半導体チップの上面以下であることを特徴とする請求項１記載の半導体チップの位置決め治具。 The height of the cut portion provided at the lower end of the through hole, the molten solder or thickness, positioning jig according to claim 1 Symbol mounting semiconductor chips and equal to or less than the upper surface of the semiconductor chip. 前記位置決め治具の主面に沿った方向の前記切り込み部の距離が、前記切り込み部の高さと同程度であることを特徴とする請求項１または２記載の半導体チップの位置決め治具。 3. The semiconductor chip positioning jig according to claim 1, wherein a distance of the cut portion in a direction along a main surface of the positioning jig is substantially equal to a height of the cut portion. 前記切り込み部が貫通孔の全周に設けられていることを特徴とする請求項１乃至３のいずれか１項記載の半導体チップの位置決め治具。 Positioning jig of the semiconductor chip according to any one of claims 1 to 3, characterized in that the cut portion is provided on the entire circumference of the through hole. 前記半導体チップの位置決め治具の厚さが半田板と半導体チップの厚さの合計よりも厚いことを特徴とする請求項１乃至４のいずれか１項記載の半導体チップの位置決め治具。 The semiconductor chip positioning jig of the semiconductor chip according to any one of claims 1 to 4 the thickness of the positioning jig is characterized thicker than the total thickness of the solder plate and the semiconductor chip. 前記半導体チップの位置決め治具がカーボンを主材料としていることを特徴とする請求項１乃至５のいずれか１項記載の半導体チップの位置決め治具。 The semiconductor chip positioning jig of the semiconductor chip according to any one of claims 1 to 5 positioning jig is characterized in that as a main material of carbon. 金属放熱板上に、その一方の面に半田板を挟んで絶縁回路基板を載せ、該絶縁回路基板のもう一方の面に、その下端面が前記絶縁回路基板の凹状の反りに合わせた曲面の加工が施された形状を有している半導体チップの位置決め治具を載置し固定し、前記位置決め治具の貫通孔であってその貫通孔の下端部に前記半導体チップに面して切り込まれた空間を有する貫通孔に半田板と半導体チップをセットし、減圧下で前記半田板の熔融温度以上に加熱して、前記金属放熱板、絶縁回路基板及び半導体チップとをそれぞれ半田接合する工程を有することを特徴とする半導体装置の製造方法。 An insulating circuit board is placed on one surface of the metal heat sink with a solder plate interposed therebetween, and the lower surface of the insulating circuit board has a curved surface that matches the concave warpage of the insulating circuit board. A semiconductor chip positioning jig having a processed shape is placed and fixed, and the through hole of the positioning jig is cut into the lower end portion of the through hole so as to face the semiconductor chip. A step of setting a solder plate and a semiconductor chip in a through-hole having a space, and heating the metal heat dissipation plate, the insulating circuit board and the semiconductor chip to each other by heating to a temperature equal to or higher than the melting temperature of the solder plate under reduced pressure. A method for manufacturing a semiconductor device, comprising: 前記半導体チップが絶縁ゲート型バイポーラトランジスタチップおよびダイオードチップであることを特徴とする請求項７記載の半導体装置の製造方法。 8. The method of manufacturing a semiconductor device according to claim 7, wherein the semiconductor chip is an insulated gate bipolar transistor chip and a diode chip.
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