JP5077536B2 - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device Download PDF

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JP5077536B2
JP5077536B2 JP2007122998A JP2007122998A JP5077536B2 JP 5077536 B2 JP5077536 B2 JP 5077536B2 JP 2007122998 A JP2007122998 A JP 2007122998A JP 2007122998 A JP2007122998 A JP 2007122998A JP 5077536 B2 JP5077536 B2 JP 5077536B2
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copper foil
solder
insulating substrate
manufacturing
semiconductor device
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JP2008282834A (en
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パサン フェルナンド
豊重 坂口
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Fuji Electric Co Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83385Shape, e.g. interlocking features
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1305Bipolar Junction Transistor [BJT]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1305Bipolar Junction Transistor [BJT]
    • H01L2924/13055Insulated gate bipolar transistor [IGBT]

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Die Bonding (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Description

本発明は、パワー半導体モジュールを実施対象とした半導体装置の製造方法に関し、詳しくはモジュールを構成する部材相互間の半田接合方法に係わる   The present invention relates to a method of manufacturing a semiconductor device in which a power semiconductor module is an object of implementation, and more particularly to a method of solder bonding between members constituting the module.

まず、頭記のパワー半導体モジュールを例に従来における半導体装置の組立構造を図6,図7に示す。図6はプリント配線板などに適用する絶縁基板(銅張積層板)に半導体チップを半田マウントしたもので、1は例えばエポキシ樹脂にSiO2,Al2O3,AINなどの無機フィラーを添加した絶縁層1aを挟んでその表,裏両面に銅箔回路パターン1b,銅ベース1cを積層した絶縁基板、2は半導体チップ(例えば、IGBT(Insulated Gate Bipolar Transistor))、3は半田層である。一方、図7に示すモジュールは放
熱用金属ベース板4の上に絶縁基板5を重ねて半田接合し、この絶縁基板5に半導体チップ2を半田マウントしたもので、絶縁基板5は絶縁層(セラミック板)5aを挟んでその表,裏両面に銅箔回路パターン5a,裏面銅箔5cを積層した構造になる。
First, an assembly structure of a conventional semiconductor device is shown in FIGS. 6 and 7, taking the power semiconductor module described above as an example. FIG. 6 shows a semiconductor chip mounted on an insulating substrate (copper-clad laminate) applied to a printed wiring board or the like. Reference numeral 1 denotes an insulating layer 1a in which an inorganic filler such as SiO2, Al2O3 or AIN is added to an epoxy resin, for example. An insulating substrate having a copper foil circuit pattern 1b and a copper base 1c laminated on both the front and back sides of the substrate, 2 is a semiconductor chip (for example, IGBT (Insulated Gate Bipolar Transistor)), and 3 is a solder layer. On the other hand, the module shown in FIG. 7 is obtained by superposing an insulating substrate 5 on a heat radiating metal base plate 4 and soldering it, and mounting the semiconductor chip 2 on the insulating substrate 5 by soldering. Plate) 5a, and a copper foil circuit pattern 5a and a back copper foil 5c are laminated on both front and back surfaces.

なお、図示してないが、半導体チップの放熱性を高めるために、前記した絶縁基板1,5の銅箔回路パターンの上に銅材などで作られたヒートスプレッダを重ねて半田接合し、このヒートスプレッダの上に半導体チップ3を半田マウントした構造もある。
上記のモジュール組立構造で、絶縁基板1の銅箔回路パターン1b/半導体チップ2,銅ベース板4/絶縁基板5,絶縁基板5/半導体チップ2の間を半田接合するには、接合面域に塗布したクリーム半田、もしくは板半田を挟んで接合部材を上下に重ね合わせ、この状態で半田リフロー工程を経て各部材の相互間を半田接合する方法が一般的である。
Although not shown, in order to improve the heat dissipation of the semiconductor chip, a heat spreader made of a copper material or the like is stacked on the copper foil circuit pattern of the insulating substrates 1 and 5 and soldered, and this heat spreader is used. There is also a structure in which the semiconductor chip 3 is solder-mounted on top.
In the module assembly structure described above, in order to solder-bond the copper foil circuit pattern 1b / semiconductor chip 2, copper base plate 4 / insulating substrate 5, insulating substrate 5 / semiconductor chip 2 of the insulating substrate 1 to the bonding surface area. In general, the joining members are stacked one above the other with the applied cream solder or plate solder interposed therebetween, and in this state, the members are soldered together through a solder reflow process.

ところで、上記した半田接合方法では、半田リフロー工程の途上で半田が溶融した際に、半田塗布量,部材重量のアンバランスなどにより上側に重ねた部材が図示のように傾いたまま接合されることがある。このような半田接合の状態では半田層3の層厚が不均一となって部材間の伝熱性が不均一になるほか、半田のはみ出し,半田ボイドなどの接合不良が生じ易くなる。また、半導体チップ2の通電ON,OFFに伴う熱サイクルが繰り返し加わると、半田層3の薄い部分にクラックが発生,成長して放熱性,通電性が低下し、このために半導体素子の動作特性が低下する。   By the way, in the solder joining method described above, when the solder is melted in the course of the solder reflow process, the members stacked on the upper side are joined while being inclined as shown in the figure due to unbalance of the amount of solder applied and the weight of the member. There is. In such a solder joint state, the layer thickness of the solder layer 3 is non-uniform, the heat conductivity between the members becomes non-uniform, and joint defects such as solder protrusion and solder voids are likely to occur. Further, when a thermal cycle is repeatedly applied due to ON / OFF of the semiconductor chip 2, cracks are generated and grow in a thin portion of the solder layer 3, and heat dissipation and conductivity are deteriorated. Decreases.

一方、上記問題に対処して部材の相互間を接合する半田層の厚さを均一化するために、図7に示した金属ベース板4の上面,もしくは絶縁基板5の裏面銅箔5cの表面に、あらかじめ半田層3の適正厚さに対応する高さの突起をプレス加工,切削加工などの機械的加工法により分散形成しておき、この突起を部材間の間隔保持用サポートとして金属ベース板4と絶縁基板5との間に均一な厚さの半田層3を形成して部材の傾きなしにリフロー半田接合するようにした半導体装置の構成,およびその製造方法(突起の成形法)が知られている(例えば、特許文献1,特許文献2参照)。
特開平10−50928号公報 特開2000−277876号公報
On the other hand, in order to deal with the above problem and to make the thickness of the solder layer joining the members uniform, the upper surface of the metal base plate 4 shown in FIG. 7 or the surface of the back surface copper foil 5c of the insulating substrate 5 is used. In addition, protrusions having a height corresponding to the appropriate thickness of the solder layer 3 are previously distributed and formed by a mechanical processing method such as pressing or cutting, and the protrusions are used as a support for maintaining a gap between members. A structure of a semiconductor device in which a solder layer 3 having a uniform thickness is formed between 4 and an insulating substrate 5 and reflow soldering is performed without tilting the member, and a manufacturing method (projection forming method) is known. (For example, see Patent Document 1 and Patent Document 2).
Japanese Patent Laid-Open No. 10-50928 JP 2000-277876 A

前記のように上下に重ねて半田接合する部材のうち、一方の部材表面の複数箇所にあらかじめ同じ高さに揃えた突起を分散形成しておくことにより、金属ベース板/絶縁基板間を傾きなしに均一な層厚でリフロー半田接合することができる。
しかしながら、先記の特許文献1,特許文献2に開示されている従来の製造方法では、
プレス,切削などの機械的な加工法によりモジュールを構成する部材の表面に突起を刻設するようにしていることから、その突起の形成には専用の機械加工設備,プレス金型などを必要とするほか、加工の手間,時間もかかって製品がコスト高となる。
As described above, among the members to be soldered in the upper and lower layers, the metal base plate / insulating substrate is not tilted by forming protrusions aligned at the same height in advance at multiple locations on the surface of one member. Reflow soldering can be performed with a uniform layer thickness.
However, in the conventional manufacturing methods disclosed in Patent Document 1 and Patent Document 2 described above,
Since projections are engraved on the surface of the members that make up the module by mechanical processing methods such as pressing and cutting, special machining facilities and press dies are required to form the projections. In addition, it takes time and effort for processing, and the product becomes expensive.

本発明は上記の点に鑑みなされたものであり、従来の機械加工法に比べて簡単,かつ短時間で半田接合する部材の表面に間隔保持用の突起を精度よく形成し、部材相互間を均一な厚さでリフロー半田接合できるように工法を改良した半導体装置の製造方法を提供することを目的とする。   The present invention has been made in view of the above-mentioned points, and compared with the conventional machining method, the projection for holding the gap is formed on the surface of the member to be soldered easily and in a short time with high accuracy. It is an object of the present invention to provide a method for manufacturing a semiconductor device with an improved method so that reflow soldering can be performed with a uniform thickness.

上記目的を達成するために、本発明によれば、放熱用金属ベース板,絶縁基板,半導体チップ,ヒートスプレッダなどのモジュール構成部材を積み重ねてその部材相互間を半田接合した組立構造の半導体装置を対象に、
上下に重ね合わせて半田接合する第1の部材と第2の部材のいずれか一方の部材に対し、その接合面域内にレーザ光を照射して部材表面の複数箇所に半田接合層の層厚に対応する突起高さの凹凸状クレータを分散形成した上で、その接合面域にクリーム半田ないし板半田を挟んで第1,第2の部材を重ね合わせ、半田リフロー工程を経て各部材の相互間を接合するものとし、具体的には次記のような態様で部材表面にレーザ光を照射してクレータを形成する。
(1)絶縁層の表,裏両面に銅箔を積層した絶縁基板と該絶縁基板の銅箔に半導体チップを積み重ねてその部材相互間を半田接合した組立構造になる半導体装置の製造方法において、前記銅箔は、その厚さが0.5mm以上の厚銅箔とし、該厚銅箔を貫通しないようにレーザ光を照射して、その表面の複数箇所に半田接合層の層厚に対応する突起高さの凹凸状クレータを分散形成した上で、その接合面域にクリーム半田ないし板半田を挟み、前記半導体チップを前記厚銅箔に重ね合わせ、半田リフロー工程を経て相互間を接合する。
(2)絶縁層の表,裏両面に銅箔を積層した絶縁基板と放熱用金属ベース板を積み重ねてその部材相互間を半田接合した組立構造になる半導体装置の製造方法において、前記銅箔は、その厚さが0.5mm以上の厚銅箔とし、該厚銅箔を貫通しないようにレーザ光を照射して、その表面の複数箇所に半田接合層の層厚に対応する突起高さの凹凸状クレータを分散形成した上で、その接合面域にクリーム半田ないし板半田を挟み、前記放熱用金属ベース板を前記厚銅箔に重ね合わせ、半田リフロー工程を経て相互間を接合する。
(3)前項(1)または(2)において、前記レーザ光の出力,照射時間,照射角度を同一に設定して複数箇所にクレータを形成する。
(4)前項(1)または(2)において、前記半田接合する面域にクレータを少なくとも3箇所以上に分散して形成する。
In order to achieve the above object, according to the present invention, a semiconductor device having an assembly structure in which module components such as a metal base plate for heat dissipation, an insulating substrate, a semiconductor chip, and a heat spreader are stacked and soldered between the members is an object. In addition,
A laser beam is irradiated on the joining surface area of one of the first member and the second member that are superposed on each other and soldered together, and the thickness of the solder joint layer is increased at a plurality of locations on the surface of the member. After forming concavo-convex craters with corresponding projection heights in a dispersed manner, the first and second members are superposed on the joint surface area with cream solder or plate solder sandwiched between them, and each member is passed through a solder reflow process. It shall joining, in particular to form a crater by irradiating a laser beam on the surface of the member in a manner such as: Symbol.
(1) In a method for manufacturing a semiconductor device having an assembly structure in which a semiconductor chip is stacked on a copper foil of the insulating substrate and the copper foils of the insulating substrate are stacked on each side of the insulating layer, and the members are soldered together. The copper foil is a thick copper foil having a thickness of 0.5 mm or more, and is irradiated with laser light so as not to penetrate the thick copper foil, and corresponds to the layer thickness of the solder bonding layer at a plurality of locations on the surface. After forming uneven craters having protrusion heights, cream solder or plate solder is sandwiched between the joint surface areas, the semiconductor chip is overlaid on the thick copper foil, and they are joined to each other through a solder reflow process.
(2) In a method of manufacturing a semiconductor device having an assembly structure in which an insulating substrate in which copper foils are laminated on both front and back surfaces of an insulating layer and a metal base plate for heat dissipation are stacked and the members are soldered together, The thickness of the copper foil is 0.5 mm or more, and laser light is irradiated so as not to penetrate the thick copper foil, so that the protrusion height corresponding to the layer thickness of the solder bonding layer is applied to a plurality of locations on the surface. After forming uneven craters in a dispersed manner, cream solder or plate solder is sandwiched between the joining surface areas, the heat-dissipating metal base plate is overlaid on the thick copper foil, and they are joined together through a solder reflow process.
(3) In the preceding item (1) or (2), the laser light output, irradiation time, and irradiation angle are set to be the same, and craters are formed at a plurality of locations.
(4) In the preceding item (1) or (2), craters are dispersed and formed in at least three locations in the surface area to be soldered .

上記の製造方法によれば、専用の機械加工設備を用意することなく、上下に重ねて半田接合する部材に対し、一方部材の半田接合面域にレーザ光を極短時間照射してその表面にクレータを形成するだけで、部材の接合面に半田接合層の層厚に対応する所望高さの突起を簡単,かつ精度よく形成することができる。
すなわち、銅などの金属部材の表面にスポット状に集光したレーザ光を照射すると、照射を受けた部分の金属が溶融して溶け込み、その溶融金属(溶液)がレーザ照射点に生じ
たプラズマブルーム(金属蒸気)により周囲に押し退けられてレーザ照射点を中心に同心円状に突起が盛り上がった凹凸のクレータ(レーザ加工痕)を形成する。この場合に、クレータの周囲に形成される突起の高さはレーザ光の出力,照射時間,照射角度をパラメータに調整可能であり、このレーザ光の照射条件を適正な半田層の厚みに合わせて設定することで接合部材の表面複数箇所に同じ高さのクレータ突起を精度よく形成できる。
According to the above manufacturing method, without preparing a dedicated machining facility, the surface of the solder joint surface area of one member is irradiated with laser light for a very short time on a member to be soldered on top and bottom. By simply forming a crater, a projection having a desired height corresponding to the thickness of the solder joint layer can be easily and accurately formed on the joint surface of the member.
In other words, when the surface of a metal member such as copper is irradiated with a laser beam focused in a spot shape, the irradiated metal is melted and melted, and the molten metal (solution) is generated at the laser irradiation point. An uneven crater (laser machining trace) is formed which is pushed away by (metal vapor) and concentrically protrudes around the laser irradiation point. In this case, the height of the protrusions formed around the crater can be adjusted using the laser beam output, irradiation time, and irradiation angle as parameters, and the laser beam irradiation conditions can be adjusted to the appropriate solder layer thickness. By setting, crater protrusions of the same height can be formed with high accuracy at a plurality of locations on the surface of the joining member.

そして、この突起を部材間の間隔保持用サポートとして上下に重ねた接合部材の間をリフロー半田接合することにより、絶縁基板の銅箔と半導体チップとの間、絶縁基板と放熱用金属ベース板との間に均一な厚さの半田層を形成して高信頼性に半田接合することができる。 Then, by reflow soldering between the joining members that are vertically stacked as a support for holding the gap between the members, the insulating substrate and the heat dissipating metal base plate are provided between the copper foil of the insulating substrate and the semiconductor chip. A solder layer having a uniform thickness can be formed between them and soldered with high reliability.

以下、本発明の実施の形態を図1,2,4に示す実施例に基づいて説明する。なお、実施例の図中で図6,図7に対応する部材には同じ符号を付してその説明は省略する。   Hereinafter, embodiments of the present invention will be described based on the examples shown in FIGS. In the drawings of the embodiment, members corresponding to those in FIGS. 6 and 7 are denoted by the same reference numerals and description thereof is omitted.

<実施例1>
まず、図6の絶縁基板に適用して半導体チップを半田接合する本発明実施例の工法を図1(a)〜(d)により説明する。この実施例では半導体チップ2を半田マウントする絶縁基板1について、絶縁層1aの上面側に積層した銅箔回路パターン1bを、その厚さdが0.6mm(通常の絶縁基板に形成する銅箔回路パターンの厚さは200〜250μn程度)の厚銅箔とした上で、半導体チップ2を半田マウントする接合面域内に定めた複数箇所(図示例では銅箔回路パターンの四隅)にレーザ光を照射し(図1(a)参照)、銅箔回路パターン1bの表面に図1(b)で示すような凹凸状のクレータ1d(レーザ照射痕)を形成した。図2(a),(b)は前記クレータ1dの模式拡大図で、図示のように銅箔表面にはレーザ光の照射点を中心として、レーザ光のビーム径より一回り大きな直径の凹部1d−1,および該凹部1d−1の周縁に盛り上がったリング状突起1d−2が形成されている。
<Example 1>
First, the construction method of the embodiment of the present invention in which the semiconductor chip is soldered by applying to the insulating substrate of FIG. 6 will be described with reference to FIGS. In this embodiment, a copper foil circuit pattern 1b laminated on the upper surface side of an insulating layer 1a of an insulating substrate 1 on which a semiconductor chip 2 is solder mounted has a thickness d of 0.6 mm (a copper foil formed on a normal insulating substrate). The thickness of the circuit pattern is about 200 to 250 μn), and laser light is applied to a plurality of locations (four corners of the copper foil circuit pattern in the illustrated example) defined within the bonding surface area where the semiconductor chip 2 is solder mounted. Irradiation was performed (see FIG. 1A), and an uneven crater 1d (laser irradiation trace) as shown in FIG. 1B was formed on the surface of the copper foil circuit pattern 1b. 2 (a) and 2 (b) are schematic enlarged views of the crater 1d. As shown in the figure, the copper foil surface has a recess 1d having a diameter slightly larger than the beam diameter of the laser light, centered on the laser light irradiation point. -1 and a ring-shaped protrusion 1d-2 that is raised at the periphery of the recess 1d-1.

ここで、レーザ光の出力を500W,照射点に向けてレーザ光を導光する光ファイバーの径を0.6mm,照射時間を5msecとして、銅箔の表面に対し斜め方向(照射角度:60°)からスポット状にレーザ光を照射したところ、クレータ1dの周縁に盛り上がったリング状突起1d−2の高さhが約160μmであった。なお、図示の模式図ではクレータ1dの突起高さhを全周で同じ高さに描いているが、実際にはレーザ光を斜め方向から照射すると突起1d−2が多少片寄りして形成される。   Here, the output of the laser beam is 500 W, the diameter of the optical fiber that guides the laser beam toward the irradiation point is 0.6 mm, the irradiation time is 5 msec, and obliquely to the copper foil surface (irradiation angle: 60 °) When the laser beam was irradiated in a spot shape, the height h of the ring-shaped protrusion 1d-2 raised on the periphery of the crater 1d was about 160 μm. In the schematic diagram shown in the drawing, the height h of the crater 1d is drawn at the same height all around, but in reality, the projection 1d-2 is formed slightly offset when irradiated with laser light from an oblique direction. The

この場合に、クレータ1dの周縁に形成される突起1d−2の高さdは、レーザ光出力,照射角度,照射時間をパラメータに調整可能であり、とりわけレーザ光出力を変えることで効果的に高さを調整できる。なお、この実施例では絶縁基板1/半導体チップ2の間を接合する半田層3の適正な厚さに合わせてレーザ光の照射条件を前記のように設定し、同じ照射条件で図1(d)に示した銅箔回路パターン1bの表面四隅にクレータ1dを形成したところ、各クレータ1dは全て同じ高さ(h=160μm)に揃った突起1d−2が形成されることが確認されている。なお、銅箔面に対してレーザ光を垂直方向から照射すると、銅箔面で反射した反射光が光ファイバーに入光してレーザ装置の故障原因となるおそれがあるので、実施例では照射角度60°に設定して斜め方向からレーザ光を照射するようにした。   In this case, the height d of the protrusion 1d-2 formed on the periphery of the crater 1d can be adjusted by using the laser light output, the irradiation angle, and the irradiation time as parameters, and particularly effectively by changing the laser light output. The height can be adjusted. In this embodiment, the irradiation condition of the laser beam is set as described above according to the appropriate thickness of the solder layer 3 that joins between the insulating substrate 1 and the semiconductor chip 2, and the same irradiation condition as shown in FIG. When the craters 1d are formed at the four corners of the surface of the copper foil circuit pattern 1b shown in FIG. 2), it is confirmed that the protrusions 1d-2 are formed at the same height (h = 160 μm) in each crater 1d. . Note that, when laser light is irradiated on the copper foil surface from the vertical direction, the reflected light reflected by the copper foil surface may enter the optical fiber and cause a failure of the laser device. The laser beam was irradiated from an oblique direction by setting the angle to °.

そして、前記のように 銅箔回路パターン1bの半田接合面にレーザ光を照射して複数
のクレータ1dを分散形成した絶縁基板1に対して、その半田接合面域に適量のクリーム半田を塗布するか、または板半田を載せて上で絶縁基板1の上に半導体チップ2を重ね合わせ、半田リフロー工程を経て絶縁基板1/半導体チップ2の間を半田接合した。
図1(c)はリフロー半田接合した後の組立状態を表したものである。この図から判る
ように、絶縁基板2の銅箔回路パターン1bの表面四隅にあらかじめ分散形成しておいたクレータ1dの突起1d−2が半導体チップ2との間の間隔保持サポートとして機能し、半田リフロー工程中には絶縁基板1の上に載置した半導体チップ2を水平姿勢に保持する。これにより、図6で述べたように半導体チップ2の姿勢が傾くことなく、絶縁基板1/半導体チップ2の間の接合面域に均一な厚さの半田層3を形成して高信頼性に半田接合できる。
Then, as described above, an appropriate amount of cream solder is applied to the solder joint surface area of the insulating substrate 1 in which the solder joint surface of the copper foil circuit pattern 1b is irradiated with laser light and a plurality of craters 1d are dispersedly formed. Alternatively, the semiconductor chip 2 is overlaid on the insulating substrate 1 with the plate solder placed thereon, and the insulating substrate 1 / semiconductor chip 2 is soldered through a solder reflow process.
FIG. 1C shows the assembled state after reflow soldering. As can be seen from this figure, the protrusions 1d-2 of the crater 1d, which are distributed and formed in advance at the four corners of the surface of the copper foil circuit pattern 1b of the insulating substrate 2, function as a spacing support between the semiconductor chip 2 and solder. During the reflow process, the semiconductor chip 2 placed on the insulating substrate 1 is held in a horizontal posture. As a result, the solder layer 3 having a uniform thickness is formed in the bonding area between the insulating substrate 1 and the semiconductor chip 2 without tilting the posture of the semiconductor chip 2 as described in FIG. Can be soldered.

なお、前記のようにクレータ1dの突起1d−2を介して絶縁基板1の上に半導体チップ2を水平姿勢に保持するには、半田接合面域の少なくとも3箇所に凹凸状のクレータ1dを分散形成して3点支持すればよい。また、銅箔回路パターン1dの銅箔厚さが薄いと、レーザ光の照射によりクレータ1aが銅箔を貫通してセラミックの絶縁層1aに達するおそれがあるので、銅箔回路パターン1dの厚さは0.5mm以上とする。   In order to hold the semiconductor chip 2 in a horizontal position on the insulating substrate 1 via the protrusion 1d-2 of the crater 1d as described above, the uneven crater 1d is dispersed in at least three locations of the solder joint surface area. It may be formed and supported at three points. In addition, if the copper foil thickness of the copper foil circuit pattern 1d is thin, the crater 1a may penetrate the copper foil and reach the ceramic insulating layer 1a due to laser light irradiation. Is 0.5 mm or more.

<参考例>
次に、図7のモジュール構造における金属ベース板4と絶縁基板5との半田接合に適用した本発明の参考例を図(a)〜(c)に示す。この参考例では金属ベース板(銅板)4の上面に、先記実施例1と同様な手法で半田接合面域にレーザ光を照射し(図2(a)参照)、その表面の複数箇所(3箇所以上)に図2で述べた突起を同じ高さに揃えてクレータ4aを形成する(図2(b)参照)。
<Reference example>
Next, FIG. 3 (a) ~ (c) a reference example of the present invention applied to the solder bonding of the metal base plate 4 and the insulating substrate 5 in the module structure of Fig. In this reference example, the upper surface of the metal base plate (copper plate) 4 is irradiated with laser light on the solder joint surface area in the same manner as in the first embodiment (see FIG. 2A), and a plurality of locations ( The craters 4a are formed by aligning the protrusions described in FIG. 2 at the same height at three or more locations (see FIG. 2B).

その後、金属ベース板1の上面に適量のクリーム半田を塗布するか,または板半田を載せてその上に絶縁基板5を載置保持し、半田リフロー工程を経て金属ベース板4/絶縁基板5の間を接合する。これにより、図(c)で示すように金属ベース板4/絶縁基板5の間を均一な厚さの半田層3で半田接合することができる。 Thereafter, an appropriate amount of cream solder is applied to the upper surface of the metal base plate 1 or the plate solder is placed thereon, and the insulating substrate 5 is placed and held thereon. After the solder reflow process, the metal base plate 4 / insulating substrate 5 Join between. This makes it possible to solder bonding of a metal base plate 4 / insulating solder layer 3 between the uniform thickness of the substrate 5, as shown in FIG. 3 (c).

<実施例2>
次に、実施例2を図(a)〜(c)に示す。この実施例では、絶縁基板5に対して、その上面側の銅箔回路パターン5b,および裏面銅箔5cに先記実施例と同様な手法で半田接合面域にレーザ光を照射し(図4(a)参照)、銅箔回路パターン5b,裏面銅箔5cの表面複数箇所(3箇所以上)に突起高さを揃えてクレータ5dを形成する(図4(b)参照)。なお、絶縁基板5の銅箔回路パターン5bおよび裏面銅箔5cは、レーザ光の照射で形成するクレータ5dが銅箔を貫通しないようにするために、銅箔の厚さを0.5mm以上にしておく。
<Example 2>
Next, the second embodiment shown in FIG. 4 (a) ~ (c) . In this embodiment, the insulating substrate 5 is irradiated with laser light on the solder joint surface area on the upper surface side copper foil circuit pattern 5b and the back surface copper foil 5c in the same manner as in the previous embodiment (FIG. 4). (See (a)), the crater 5d is formed by aligning the protrusion height at a plurality of locations (three or more locations) on the front surface of the copper foil circuit pattern 5b and the back surface copper foil 5c (see FIG. 4B). The copper foil circuit pattern 5b and the back copper foil 5c of the insulating substrate 5 have a thickness of 0.5 mm or more so that the crater 5d formed by laser light irradiation does not penetrate the copper foil. Keep it.

そして、続く半田接合工程では絶縁基板5を搭載する金属ベース板3の上面,および半導体チップ2をマウントする絶縁基板5の銅箔回路パターン5bの半田接合面域に適量のクリーム半田を塗布するか板半田を載せた上で、金属ベース板4の上に絶縁基板5,および半導体チップ2を順に載置し、この状態で半田リフロー工程を経て金属ベース板4/絶縁基板5/半導体チップ2の相互間を半田接合する。   In the subsequent solder bonding step, is an appropriate amount of cream solder applied to the upper surface of the metal base plate 3 on which the insulating substrate 5 is mounted and the solder bonding surface area of the copper foil circuit pattern 5b of the insulating substrate 5 on which the semiconductor chip 2 is mounted? After the plate solder is placed, the insulating substrate 5 and the semiconductor chip 2 are sequentially placed on the metal base plate 4, and in this state, the metal base plate 4 / insulating substrate 5 / semiconductor chip 2 is subjected to a solder reflow process. Solder together.

図4(c)は半田接合後の状態を表しており、先記の各実施例で述べたと同様に、絶縁基板5の表,裏両両面の銅箔表面に形成したクレータ5dの突起(図2参照)を間隔保持用サポートとして、金属ベース板4/絶縁基板5/半導体チップ2の間を均一な厚さの半田層3で接合することができる。   FIG. 4C shows the state after the solder joint, and as described in the previous embodiments, the protrusions of the crater 5d formed on the copper foil surfaces on both the front and back surfaces of the insulating substrate 5 (see FIG. 4). 2) is used as a support for maintaining a distance, and the metal base plate 4 / insulating substrate 5 / semiconductor chip 2 can be joined with the solder layer 3 having a uniform thickness.

<参考例>
図5(a)〜(c)は、半導体チップの放熱性を高めるために、絶縁基板の上にヒートスプレッダを介して半導体チップを実装した参考例であり、図中で符号6が銅板で作られたヒートスプレッダである。
この参考例では、まずヒートスプレッダ6に対してその表,裏両面の半田接合面域に先
記の各実施例で述べたと同じ手法でレーザ光を照射し(図5(a)参照)、その表面の複数箇所(3箇所以上)に突起高さを揃えてクレータ6dを形成する(図5(b)参照)。
<Reference example>
FIGS. 5A to 5C are reference examples in which a semiconductor chip is mounted on an insulating substrate through a heat spreader in order to enhance the heat dissipation of the semiconductor chip. In the figure, reference numeral 6 is a copper plate. Heat spreader.
In this reference example, the heat spreader 6 is first irradiated with laser light in the same manner as described in the previous embodiments on the front and back solder joint areas (see FIG. 5 (a)), and the surface thereof. The crater 6d is formed by aligning the projection height at a plurality of locations (three or more locations) (see FIG. 5B).

次に、ヒートスプレッダ6を搭載する絶縁基板5の銅箔回路パターン5bの半田接合面域,および半導体チップ2をマウントするヒートスプレッダ5の上面に適量のクリーム半田を塗布するか板半田を載せた上で,絶縁基板5の銅箔回路パターン5bの上にヒートスプレッダ6,および半導体チップ2を順に載置し、この状態で半田リフロー工程を経て絶縁基板5/ヒートスプレッダ6/半導体チップ2の相互間を半田接合する。   Next, after applying an appropriate amount of cream solder or placing sheet solder on the solder joint surface area of the copper foil circuit pattern 5b of the insulating substrate 5 on which the heat spreader 6 is mounted and the upper surface of the heat spreader 5 on which the semiconductor chip 2 is mounted. The heat spreader 6 and the semiconductor chip 2 are placed in this order on the copper foil circuit pattern 5b of the insulating substrate 5, and in this state, the insulating substrate 5 / heat spreader 6 / semiconductor chip 2 are soldered together through a solder reflow process. To do.

図5(c)は半田接合後の状態を表しており、先記の各実施例で述べたと同様に、ヒートスプレッダ6の表,裏両面に形成したクレータ6dの突起(図2参照)を間隔保持用サポートとして、絶縁基板5/ヒートスプレッダ6/半導体チップ2の間を均一な厚さの半田層3で接合することができる。   FIG. 5 (c) shows the state after the solder joint, and the projections (see FIG. 2) of the crater 6d formed on the front and back surfaces of the heat spreader 6 are maintained at intervals as described in the previous embodiments. As a support, the insulating substrate 5 / heat spreader 6 / semiconductor chip 2 can be joined with the solder layer 3 having a uniform thickness.

本発明の実施例1に係わる半導体装置の製造工程説明図で、(a)は絶縁基板の銅箔回路パターンにレーザ光を照射する状態、(b)はレーザ照射により銅箔回路パターンに形成した凹凸状クレータ、(c)は絶縁基板の上に半導体チップをリフロー半田接合した状態を表す図、(d)は(c)における要部平面図BRIEF DESCRIPTION OF THE DRAWINGS It is manufacturing process explanatory drawing of the semiconductor device concerning Example 1 of this invention, (a) is the state which irradiates a laser beam to the copper foil circuit pattern of an insulated substrate, (b) was formed in the copper foil circuit pattern by laser irradiation. Concave and convex crater, (c) is a diagram showing a state where a semiconductor chip is reflow soldered on an insulating substrate, and (d) is a plan view of the main part in (c). 図1で銅箔回路パターンに形成したクレータの模式拡大図で、(a)は平面図、(b)は(a)の矢視A−A断面図It is a model enlarged view of the crater formed in the copper foil circuit pattern in FIG. 1, (a) is a plan view, (b) is an AA cross-sectional view of (a). 本発明の参考例に係わる製造工程の説明図で、(a)は金属ベース板の上面にレーザ光を照射する状態、(b)はレーザ照射により金属ベース板の表面に形成した凹凸状クレータ、(c)は金属ベース板の上に絶縁基板に半導体チップをリフロー半田接合した状態を表す図It is explanatory drawing of the manufacturing process concerning the reference example of this invention, (a) is the state which irradiates a laser beam to the upper surface of a metal base board, (b) is the uneven crater formed in the surface of the metal base board by laser irradiation, (C) is a figure showing the state which carried out the reflow soldering of the semiconductor chip to the insulating substrate on the metal base plate. 本発明の実施例に係わる製造工程の説明図で、(a)は絶縁基板の銅箔回路パターン,および裏面銅箔にレーザ光を照射する状態、(b)はレーザ照射により絶縁基板の表,裏両面の銅箔に形成した凹凸状クレータ、(c)は金属ベース板の上に絶縁基板,半導体チップを搭載してリフロー半田接合した状態を表す図It is explanatory drawing of the manufacturing process concerning Example 2 of this invention, (a) is the state which irradiates a laser beam to the copper foil circuit pattern and back surface copper foil of an insulated substrate, (b) is the surface of an insulated substrate by laser irradiation. , Uneven craters formed on copper foils on both sides, (c) is a diagram showing a state where an insulating substrate and a semiconductor chip are mounted on a metal base plate and reflow soldered 本発明の参考例に係わる製造工程の説明図で、(a)はヒートスプレッダの表,裏両面にレーザ光を照射する状態、(b)はレーザ照射によりヒートスプレッダの表,裏両面に形成した凹凸状クレータ、(c)は絶縁板の上にヒートスプレッダ,半導体チップを搭載してリフロー半田接合した状態を表す図BRIEF DESCRIPTION OF THE DRAWINGS It is explanatory drawing of the manufacturing process concerning the reference example of this invention, (a) is the state which irradiates a laser beam on the front and back both surfaces of a heat spreader, (b) is the uneven | corrugated shape formed in the front and back both surfaces of a heat spreader by laser irradiation. Crater, (c) is a diagram showing a state in which a heat spreader and a semiconductor chip are mounted on an insulating plate and reflow soldered. 絶縁基板の銅箔回路パターンに半導体チップを半田マウントしたモジュールの従来構造図Conventional structure of a module in which a semiconductor chip is solder-mounted on a copper foil circuit pattern on an insulating substrate 金属ベース板の上に絶縁基板,半導体チップを順に搭載して半田接合したモジュールの従来構造図Conventional structure of a module in which an insulating substrate and a semiconductor chip are mounted in order on a metal base plate and soldered

1 絶縁基板
1a 絶縁層
1b 銅箔回路パターン
1d クレータ
2 半導体チップ
3 半田層
4 金属ベース板
4a クレータ
5 絶縁基板
5a 絶縁層
5b 銅箔回路パターン
5c 裏面銅箔5d
5d クレータ
6 ヒートスプレッダ
6a クレータ
DESCRIPTION OF SYMBOLS 1 Insulating substrate 1a Insulating layer 1b Copper foil circuit pattern 1d Crater 2 Semiconductor chip 3 Solder layer 4 Metal base board 4a Crater 5 Insulating substrate 5a Insulating layer 5b Copper foil circuit pattern 5c Back surface copper foil 5d
5d crater 6 heat spreader 6a crater

Claims (4)

絶縁層の表,裏両面に銅箔を積層した絶縁基板と該絶縁基板の銅箔に半導体チップを積み重ねてその部材相互間を半田接合した組立構造になる半導体装置の製造方法において、
前記銅箔は、その厚さが0.5mm以上の厚銅箔とし、
該厚銅箔を貫通しないようにレーザ光を照射して、その表面の複数箇所に半田接合層の層厚に対応する突起高さの凹凸状クレータを分散形成した上で、その接合面域にクリーム半田ないし板半田を挟み、前記半導体チップを前記厚銅箔に重ね合わせ、半田リフロー工程を経て相互間を接合したことを特徴とする半導体装置の製造方法。
In a method of manufacturing a semiconductor device having an assembly structure in which a semiconductor chip is stacked on a copper foil of the insulating substrate and the copper foil of the insulating substrate is stacked on the front and back surfaces of the insulating layer and the members are soldered together.
The copper foil is a thick copper foil having a thickness of 0.5 mm or more,
Irradiate a laser beam so as not to penetrate the thick copper foil, and form a concavo-convex crater with projection heights corresponding to the layer thickness of the solder bonding layer at a plurality of locations on the surface, and then in the bonding surface area. look clamping solder cream solder or plate, wherein the semiconductor chip overlay the thick copper foil, a method of manufacturing a semiconductor device, characterized in that bonding the phase互間through a solder reflow process.
絶縁層の表,裏両面に銅箔を積層した絶縁基板と放熱用金属ベース板を積み重ねてその部材相互間を半田接合した組立構造になる半導体装置の製造方法において、
前記銅箔は、その厚さが0.5mm以上の厚銅箔とし、
該厚銅箔を貫通しないようにレーザ光を照射して、その表面の複数箇所に半田接合層の層厚に対応する突起高さの凹凸状クレータを分散形成した上で、その接合面域にクリーム半田ないし板半田を挟み、前記放熱用金属ベース板を前記厚銅箔に重ね合わせ、半田リフロー工程を経て相互間を接合したことを特徴とする半導体装置の製造方法。
In a manufacturing method of a semiconductor device having an assembly structure in which an insulating substrate in which copper foils are laminated on both front and back surfaces of an insulating layer and a metal base plate for heat radiation are stacked and soldered between the members.
The copper foil is a thick copper foil having a thickness of 0.5 mm or more,
Irradiate a laser beam so as not to penetrate the thick copper foil, and form a concavo-convex crater with projection heights corresponding to the layer thickness of the solder bonding layer at a plurality of locations on the surface, and then in the bonding surface area. A method of manufacturing a semiconductor device, characterized in that cream solder or plate solder is sandwiched, the heat dissipating metal base plate is superposed on the thick copper foil, and the two are joined together through a solder reflow process .
請求項1または2のいずれかに記載の製造方法において、前記レーザ光の出力,照射時間,照射角度を同一に設定して複数箇所にクレータを形成することを特徴とする半導体装置の製造方法。 3. The method of manufacturing a semiconductor device according to claim 1 , wherein the laser light output, irradiation time, and irradiation angle are set to be the same, and craters are formed at a plurality of locations . 請求項1または2のいずれかに記載の製造方法において、前記半田接合する面域にクレータを少なくとも3箇所以上に分散して形成することを特徴とする半導体装置の製造方法。
The method of manufacture according to claim 1 or 2, the method of manufacturing a semiconductor device, and forming dispersed craters on the surface area of the solder joint in at least three places.
JP2007122998A 2007-05-08 2007-05-08 Manufacturing method of semiconductor device Active JP5077536B2 (en)

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