JPH06152094A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH06152094A JPH06152094A JP4298390A JP29839092A JPH06152094A JP H06152094 A JPH06152094 A JP H06152094A JP 4298390 A JP4298390 A JP 4298390A JP 29839092 A JP29839092 A JP 29839092A JP H06152094 A JPH06152094 A JP H06152094A
- Authority
- JP
- Japan
- Prior art keywords
- metal base
- semiconductor device
- aln
- protrusion
- base
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/05—Insulated conductive substrates, e.g. insulated metal substrate
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
Landscapes
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Die Bonding (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は高信頼性を有する半導体
装置及びその製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a highly reliable semiconductor device and a method of manufacturing the same.
【０００２】[0002]
【従来の技術】パワーモジュールを例にとると、従来絶
縁板にはＡｌ2Ｏ3，ＢｅＯ等が、また最近ではＡｌＮ等
が採用され、ニッケルメッキを施したベースに半田にて
接続されている。しかし、モジュールが大容量の方向に
拡大しており、このため絶縁基板および金属ベースも大
形化し、臘材による均一な接続が臘材のかたより等が生
じることにより難しくなってきている。 2. Description of the Related Art Taking a power module as an example, a conventional insulating plate made of Al 2 O 3 , BeO or the like, and recently made of AlN or the like is connected to a nickel-plated base by soldering. . However, as the module is expanding in the direction of large capacity, the insulating substrate and the metal base are also becoming large in size, and it is becoming difficult to make a uniform connection by means of a bar member because of the bending of the bar member.
【０００３】また、より信頼性を要求される用途に採用
されつつあり、均一な臘材による接続技術が重要であ
る。Further, it is being adopted for applications requiring higher reliability, and a connection technique using a uniform bar is important.
【０００４】これに対し、図２に示すような所定臘付け
部の周囲に樹脂等による臘材の流れ止め６を設け、接続
部の臘材料を確保する構造、および図３に示すような絶
縁板４と金属ベース２の間に、凹凸を設けた薄い金属板
７を挿入し、臘材５ａ，５ｂ厚さの均一性を図った構造
が採用されている。On the other hand, as shown in FIG. 2, a structure for securing the flow material 6 for the connecting portion is provided around the predetermined attachment portion so that the flow material 6 for the connection material is secured, and the insulation as shown in FIG. A thin metal plate 7 having irregularities is inserted between the plate 4 and the metal base 2 so that the thickness of the bar members 5a and 5b is uniform.
【０００５】しかし、図２のような構造では、臘材面内
での傾きについてはコントロールできず、たとえば半導
体装置の動作，休止に伴う温度変化により熱膨張率の異
なる絶縁板４と金属ベース２の間の臘材５は疲労を受
け、臘材の薄い部分から亀裂を生じ極端な場合、剥離に
至る。臘材の厚さと亀裂発生までの温度変化のサイクル
数には、図４のような関係があり、臘材の均一性は信頼
性のばらつきを少なくする上で重要である。However, in the structure shown in FIG. 2, the inclination in the plane of the bar cannot be controlled, and for example, the insulating plate 4 and the metal base 2 having different thermal expansion coefficients due to the temperature change caused by the operation and rest of the semiconductor device. The bar 5 between them undergoes fatigue, causing cracking from the thin part of the bar and in extreme cases leading to peeling. There is a relationship as shown in FIG. 4 between the thickness of the bark and the number of cycles of temperature change until crack initiation, and the homogeneity of the bark is important in reducing the variation in reliability.
【０００６】また、図３のような構造では、半導体素子
が動作した時に発生する熱は、絶縁板４を通り金属ベー
ス２から放熱するが、その熱抵抗は部材が一層追加とな
ることにより増加し、素子に対する冷却性能が低下す
る。Further, in the structure as shown in FIG. 3, heat generated when the semiconductor element operates is radiated from the metal base 2 through the insulating plate 4, but its thermal resistance increases due to the additional member. However, the cooling performance for the element deteriorates.
【０００７】素子の動作時の発生熱密度は、素子の性能
改善と共に増加する傾向にあり、冷却性能の低下は、素
子の性能を引き出す上で弊害となる。The heat density generated during the operation of the device tends to increase as the performance of the device is improved, and the deterioration of the cooling performance is a detriment to the performance of the device.
【０００８】[0008]
【発明が解決しようとする課題】上記のように、装置の
大形化に対応した信頼性を確保する構造は、他の性能の
一部を犠牲にして達成されている。As described above, the structure for ensuring the reliability corresponding to the increase in the size of the device has been achieved at the expense of some of the other performances.
【０００９】本発明では、他の性能を犠牲にすることな
く、装置の大形化に対応した信頼性を確保する構造であ
る。The present invention has a structure that ensures reliability corresponding to an increase in size of the device without sacrificing other performances.
【００１０】[0010]
【課題を解決するための手段】図４の関係に着目し、臘
材厚さを均一にする構造とした。[Means for Solving the Problem] The structure shown in FIG.
【００１１】[0011]
【作用】臘材厚さを均一にすることにより、他の性能を
犠牲にすることなく信頼性のばらつきを低減でき、かつ
信頼性の高い半導体装置を提供できる。By making the thickness of the filler uniform, it is possible to reduce the variation in reliability without sacrificing other performances and to provide a highly reliable semiconductor device.
【００１２】[0012]
【実施例】図１に、本発明の一実施例を示す。FIG. 1 shows an embodiment of the present invention.
【００１３】絶縁基板４ｂは、熱伝導性の良好なＡｌＮ
を使用し、電極処理４ａ，４ｃはＣｕの薄板を臘材５に
より接続した構造を有す。The insulating substrate 4b is made of AlN having good thermal conductivity.
The electrode treatments 4a and 4c have a structure in which thin Cu plates are connected by a bar 5.
【００１４】半導体素子は、融点が３００℃程度のＰｂ
−Ｓｎ系半田を用いてＡｌＮのＣｕ電極上に半田付けさ
れる。半導体素子１の基体であるＳｉ及びＡｌＮの熱膨
張率は、それぞれ約３×１０-6／℃，４×１０-6／℃と
非常に近いため臘材の疲労は起こしにくい。The semiconductor element is made of Pb having a melting point of about 300.degree.
-Sn solder is used to solder on the Cu electrode of AlN. The thermal expansion coefficients of Si and AlN, which are the bases of the semiconductor element 1, are very close to about 3 × 10 −6 / ° C. and 4 × 10 −6 / ° C., respectively, so that fatigue of the barb is unlikely to occur.
【００１５】その後Ａｌワイヤ３により配線を施し、Ｃ
ｕベースに融点が１８０℃程度の半田で接着する。Ｃｕ
ベースの熱膨張率は、約１７×１０-ｖ6／℃とＳｉ及び
ＡｌＮに対し大きくこの部分の熱疲労耐量が半導体装置
の信頼性確保の上で重要である。After that, wiring is performed by the Al wire 3 and C
It is bonded to the u base with solder having a melting point of about 180 ° C. Cu
Thermal expansion coefficient of the base is about 17 × 10 - v increases to 6 / ° C. and Si and AlN thermal fatigue capability of this portion is important in ensuring the reliability of the semiconductor device.
【００１６】ここでは、ＣｕベースにＡｌＮ基板の座り
を考慮して突起２ａを適所に配置してある。Here, the projections 2a are arranged at appropriate positions on the Cu base in consideration of the sitting of the AlN substrate.
【００１７】突起の高さは、所定半田厚が１００μｍの
場合７０μｍ程度が適当である。It is appropriate that the height of the protrusion is about 70 μm when the predetermined solder thickness is 100 μm.
【００１８】高さが高すぎる場合は、突起２ａによりＡ
ｌＮ基板が持ち上げられボイドの原因となる。また、低
すぎる場合には、半田厚の均一性の確保が困難となる。If the height is too high, the protrusion 2a causes A
The 1N substrate is lifted and causes a void. On the other hand, if it is too low, it becomes difficult to secure the uniformity of the solder thickness.
【００１９】図５には、他の実施例を示す。本図は、そ
の製造方法の一例を示すものでＡｌＮ基板とＣｕベース
接続にシート状半田８を用いている。シート状半田８に
はＣｕベースの突起２ａ位置に対応した部分に、突起２
ａよりも一回り大きい穴が空いた形状をしており、半田
セット時に穴の部分を突起に会わせることにより位置決
めができ、治具等による位置決めの必要がない。また、
シート状半田の寸法がＡｌＮ基板より小さい場合、治具
方式では、半田の片寄りが起きるが、本構造ではそのよ
うな場合でも半田の位置を固定できる。図６には、他の
実施例としてフラックスと半田をペースト状に混ぜ合わ
せたクリーム半田９を使用した場合を示す。Ｃｕベース
には帯状に突起２ａを設けてある。クリーム半田９は、
印刷によりベース面２に塗布するが、帯の方向を印刷方
向とすることにより空間なく半田を塗布できる。FIG. 5 shows another embodiment. This drawing shows an example of the manufacturing method, and the sheet-like solder 8 is used for connecting the AlN substrate and the Cu base. In the sheet-shaped solder 8, the protrusion 2 is formed on the portion corresponding to the position of the Cu-based protrusion 2a.
The hole is slightly larger than a and has a hole shape. When the solder is set, positioning can be performed by bringing the hole portion into contact with the projection, and there is no need for positioning with a jig or the like. Also,
When the size of the sheet-shaped solder is smaller than that of the AlN substrate, the jig method causes deviation of the solder. However, in the present structure, the position of the solder can be fixed even in such a case. FIG. 6 shows a case where cream solder 9 in which flux and solder are mixed in a paste form is used as another embodiment. The Cu base is provided with strip-shaped projections 2a. Cream solder 9
Although it is applied to the base surface 2 by printing, solder can be applied without space by setting the direction of the band as the printing direction.
【００２０】以上、ＡｌＮ基板とＣｕベースの接続につ
いて述べたが、本材料に限定されるものではない。ま
た、臘材についても半田にて説明したが、本発明は半田
に限定されるものではない。The connection between the AlN substrate and the Cu base has been described above, but the material is not limited to this. Further, although the solder has been described as the solder, the present invention is not limited to the solder.
【００２１】[0021]
【発明の効果】大形の絶縁板を有する半導体装置の温度
変化に伴う熱疲労信頼性を向上できる構造の提供。また
作業性，組立精度の向上を図った製造方法の提供ができ
る。According to the present invention, there is provided a structure capable of improving the reliability of thermal fatigue of a semiconductor device having a large insulating plate due to temperature changes. It is also possible to provide a manufacturing method with improved workability and assembly accuracy.
【図１】本発明の一実施例の平面図および断面図であ
る。FIG. 1 is a plan view and a sectional view of an embodiment of the present invention.
【図２】従来例の平面図および断面図である。FIG. 2 is a plan view and a sectional view of a conventional example.
【図３】他の従来例の側面図である。FIG. 3 is a side view of another conventional example.
【図４】半田亀裂長さと温度変化サイクル数（対数表
示）の関係を示す図である。FIG. 4 is a diagram showing a relationship between a solder crack length and a temperature change cycle number (logarithmic display).
【図５】本発明の他の実施例の平面図および断面図であ
る。FIG. 5 is a plan view and a sectional view of another embodiment of the present invention.
【図６】本発明の他の実施例の平面図および断面図であ
る。FIG. 6 is a plan view and a sectional view of another embodiment of the present invention.
１…半導体素子、２ａ…金属ベース定起部、２ｂ…金属
ベース平面部、３…アルミワイヤ、４ａ…上側電極、４
ｂ…絶縁基板、４ｃ…下側電極、５…ろう材、６…流れ
止め樹脂。DESCRIPTION OF SYMBOLS 1 ... Semiconductor element, 2a ... Metal base fixed part, 2b ... Metal base plane part, 3 ... Aluminum wire, 4a ... Upper electrode, 4
b ... Insulating substrate, 4c ... Lower electrode, 5 ... Brazing material, 6 ... Flow stop resin.
───────────────────────────────────────────────────── フロントページの続き (72)発明者 八木原 俊樹 茨城県日立市弁天町三丁目10番２号 日立 原町電子工業株式会社内 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Toshiki Yagihara 3-10-2 Bentencho, Hitachi-shi, Ibaraki Hitachi Haramachi Electronics Co., Ltd.
Claims (10)
基板を配置し、その上に半導体素子が配置された半導体
装置において、金属ベースの絶縁基板側に突起が設けら
れていることを特徴とする半導体装置。1. In a semiconductor device in which an electrode-treated insulating substrate is arranged on a metal base, and a semiconductor element is arranged on the insulating substrate, a protrusion is provided on the insulating substrate side of the metal base. Characteristic semiconductor device.
が、円錐形であることを特徴とする半導体装置。2. The semiconductor device according to claim 1, wherein the projection of the metal base has a conical shape.
んだ周辺リング状の、平面部分より高い突起形状を具備
したことを特徴とする半導体装置。3. The semiconductor device according to claim 1, wherein the metal base has a shape of a protrusion having a shape of a peripheral ring whose center is recessed and which is higher than a flat portion.
が帯状であることを特徴とする半導体装置。4. The semiconductor device according to claim 1, wherein the metal base has a strip-shaped protruding portion.
ト状の凹凸を設けたことを特徴とする半導体装置。5. The semiconductor device according to claim 1, wherein the metal base is provided with knurled irregularities.
とを特徴とする半導体装置。6. The semiconductor device according to claim 1, wherein the metal material is copper.
ル被膜が施されていることを特徴とする半導体装置。7. The semiconductor device according to claim 1, wherein the metal base is provided with a nickel coating.
被膜はメッキにより形成されていることを特徴とする半
導体装置。8. The semiconductor device according to claim 7, wherein the nickel coating of metal base is formed by plating.
被膜は、突起形成後に施されることを特徴とする金属ベ
ースの製造方法。9. The method of manufacturing a metal base according to claim 7, wherein the nickel coating of the metal base is applied after the projection is formed.
板と金属ベースは臘材で接続され、臘材の形状はシート
状であり、金属ベースの突起に対応する位置に突起面よ
り多少大きい穴が設けられており、金属ベースの突起部
によりシート状臘材の位置を固定し、熱処理を加えるこ
とにより絶縁板と金属ベースを接着することを特徴とす
る半導体装置の製造方法。10. The electrode-treated insulating plate and the metal base are connected by a bar, and the bar is shaped like a sheet, which is slightly larger than the protruding surface at a position corresponding to the protrusion of the metal base. A method of manufacturing a semiconductor device, comprising a hole, wherein the projection of the metal base fixes the position of the sheet-shaped bar, and heat treatment is applied to bond the insulating plate and the metal base.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4298390A JPH06152094A (en) | 1992-11-09 | 1992-11-09 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4298390A JPH06152094A (en) | 1992-11-09 | 1992-11-09 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH06152094A true JPH06152094A (en) | 1994-05-31 |
Family
ID=17859087
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4298390A Pending JPH06152094A (en) | 1992-11-09 | 1992-11-09 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH06152094A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008282834A (en) * | 2007-05-08 | 2008-11-20 | Fuji Electric Device Technology Co Ltd | Manufacturing method of semiconductor device |
| JP2009054893A (en) * | 2007-08-28 | 2009-03-12 | Panasonic Electric Works Co Ltd | Light emitting device |
| JP5532147B1 (en) * | 2012-07-02 | 2014-06-25 | 三菱電機株式会社 | Semiconductor device and manufacturing method thereof |
-
1992
- 1992-11-09 JP JP4298390A patent/JPH06152094A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008282834A (en) * | 2007-05-08 | 2008-11-20 | Fuji Electric Device Technology Co Ltd | Manufacturing method of semiconductor device |
| JP2009054893A (en) * | 2007-08-28 | 2009-03-12 | Panasonic Electric Works Co Ltd | Light emitting device |
| JP5532147B1 (en) * | 2012-07-02 | 2014-06-25 | 三菱電機株式会社 | Semiconductor device and manufacturing method thereof |
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