TW460997B - Semiconductor device and method for manufacturing same - Google Patents

Semiconductor device and method for manufacturing same Download PDF

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Publication number
TW460997B
TW460997B TW089105871A TW89105871A TW460997B TW 460997 B TW460997 B TW 460997B TW 089105871 A TW089105871 A TW 089105871A TW 89105871 A TW89105871 A TW 89105871A TW 460997 B TW460997 B TW 460997B
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Taiwan
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electrode
raised
electrodes
pad
semiconductor
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TW089105871A
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Chinese (zh)
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Gorou Ikegami
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Nippon Electric Co
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    • HELECTRICITY
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    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
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    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
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    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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    • H01L2224/13138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
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Abstract

Parts of pad electrodes formed on an interconnection board so as to correspond to bump electrodes of a semiconductor pellet that neighbor parts superposed with the bump electrodes are caused to extend in substantially the same direction, and ultrasonic vibration is applies in this extension direction so as to make a connection between the pad electrodes and the bump electrodes.

Description

4 6 0 9 9 7 五、發明說明(1) 【發明背景】 【發明領域】 本發明係有 導體裝置中之一 起電極之半導體 之墊電極所形成 相互疊置、以及 【相關技藝之說 為了提高可 個人電腦、以及 更輕且更小。此 而集積度的電子 電子電路裳置可 兹將說明用 合方法如下: 關一種半導體裝置及其製造方法。 電連接係由下列方式所製成:使具有二隆 丸塊(pel let)與由形成於彈性絕緣基板上 接板位於相對位置、使該等電極 將超音波振動傳送至該等電極。 明】 攜性,期望能使供攝影機、筆記本尺、 類似者所使用之緻密型電子電路裝置變= 外株較:的電子元件或相同尺寸但採用: 凡件之達成,亦使得更緻密化且 以違成。 里化的 以製造依據本發明之半導體裝置的傳統接 # # &獻係有關一種超音波型接合裝置,用β # :裝於引線植上的半導體丸塊 用以使- 屬配線的引線框上。 电桠逼運接於具有細微金4 6 0 9 9 7 V. Description of the invention (1) [Background of the invention] [Field of the invention] The present invention is a semiconductor pad electrode with a single electrode in a conductor device stacked on top of each other, and the related art is to improve Available for personal computers as well as lighter and smaller. Therefore, the integration degree of the electronic circuit can be described as follows: A semiconductor device and a manufacturing method thereof. The electrical connection is made by placing the pellet with two bulges and the connector formed on the elastic insulating substrate at opposite positions so that the electrodes transmit ultrasonic vibrations to the electrodes. Ming] It is expected that the compact electronic circuit devices used by cameras, notebook rulers, and the like will be changed = external components: electronic components or the same size but using: The achievement of all parts will also make it more compact and To violate. The traditional connector for manufacturing semiconductor devices according to the present invention ## & is related to an ultrasonic-type bonding device using β #: a semiconductor pellet mounted on a lead plant to make a lead frame of wiring on. Electro-pneumatic forcing

禮&本參考文獻1係提供一接合裝置,用以藉由一缺汽A =超引線框輸料 、為唬琦以近乎45度角被配置在上述輸送路 460997 五、發明說明(2) 瓜上之引線框的送入方向。 當號筒以前述方式配置 約45度角而延伸,該引線自 框之縱方向。在此角度下, 至引線自由端,據此而輕易 一致化,藉此以解決習知的 時,號筒係與引線自由端形成 由端係平行排列且垂直於引線 超音波振動於打線接合時施加 使引線自由端之引線接合強度 問題。 利公開公報第Η3-4ϋ51 Μ.。 參考文獻2係有關接合的技術。在半導體裝置組件的 例子中’其中一種打線接合系統即為結合有超音波的「熱 超θ接合方法」。在引線框之内部引線位於四個方向之情 形下’位於超音波方向的内部引線之連接強度通常較大。 反之’與超音波方向形成直角的内部引線之接合強度則較 前者為弱。如上所述,所有内部引線的接合強度係不均勻 的’缺乏接合穩定度。 參考文獻2意圖藉由使所有内部引線部分及引線框的 晶粒焊墊部分位於引線框的對角線上,且以超音波執行打 線接合’而一致化接合強度並改善打線接合之良率。因 此’參考文獻2的構造如下: 引線框的每一個内部引線部分沿著一對角線X排列, 該對角線X係連接外框與内框之交又點。介於通過一標記 翼片懸吊引線的線Υ與對角線X間之夾角為45度。藉著經由 固定於一超音波傳送臂之頂端的接合工具而施加超音波, 以於連接配線送出時進行打線接合。同時,單向的超音波Li & This reference 1 provides a joint device for being placed on the above-mentioned conveying path at an angle of approximately 45 degrees for a bluffing A = super lead frame feeding. 460997 Description of the invention (2) Feeding direction of the lead frame on the melon. When the horn is arranged to extend at an angle of about 45 degrees in the foregoing manner, the lead is from the longitudinal direction of the frame. At this angle, to the free end of the lead, it is easy to unify it accordingly, in order to solve the conventional problem, the horn system and the free end of the lead are formed in parallel by the end system and perpendicular to the lead. Ultrasonic vibration is applied during wire bonding. Problems with wire bonding strength at the free end of the wire. Lee Publication Gazette Η3-4ϋ51 M. Reference 2 is a technique related to joining. In the example of a semiconductor device module, one of the wire bonding systems is a "thermal super-theta bonding method" in which ultrasonic waves are combined. In the case where the inner leads of the lead frame are located in four directions', the connection strength of the inner leads located in the ultrasonic direction is usually large. On the other hand, the bonding strength of the inner lead which forms a right angle with the ultrasonic direction is weaker than the former. As described above, the joint strength of all internal leads is uneven, and lacks joint stability. Reference 2 intends to uniformize the bonding strength and improve the yield of wire bonding by placing all the internal lead portions and the die pad portions of the lead frame on the diagonal of the lead frame, and performing wire bonding with ultrasonic waves. Therefore, the structure of 'Reference 2' is as follows: Each inner lead portion of the lead frame is arranged along a diagonal X, which connects the points where the outer frame intersects the inner frame. The angle between the line Υ and the diagonal line X through a marker suspending lead is 45 degrees. By applying an ultrasonic wave through a bonding tool fixed to the tip of an ultrasonic transmission arm, wire bonding is performed when the connection wiring is sent out. Meanwhile, one-way ultrasound

第5頁 460997 五、發明說明(3) ------ 以相同方向施加到所有内部引線部#’使得内部引線間接 合強度的不規則情況難以產生。 因此,可獲得介於晶片與每一個内部引線部分間之一 致且穩定的接合狀態。 1LJ的參專利公開公報第H4-335546號.〇 ^ 參考文獻3 係有關TAB(Table Automated Bonding,卷 帶自動接合)用之單點接合方法及設備。此方法意圖在引 線處獲得穩定而無不規則的接合強度,即使引線之寬度為 狹窄時亦然。因此,其構造如下: 提供一旋轉機構,用以相對地移動接合工具與引線其 中之一或一者,使工具藉由超音波之振動方向傾斜成與引 線之縱方向間形成-預定的角度。此工具係傾斜成與振動 方向間形成:預定的角度,以形成-裝置開口,並且配置 有引線的輸送帶係運送的。 利公開公報第扎7-169875 號。 、參考文獻4係有關球式接合方法。此方法意圖得到半 導體兀件f板2之高度可靠的連才妾,且該連接具有大的連 接強度、肉的=許電流值、以及低的連接電阻值。此方法 係藉由形成=半導體元件上之一隆起部與形成於板上之一 配線間所進行的固相擴散’而使該半導體元件連接於該板 上’此時係=短時間且高安裝密度之方式使該半導體元件 面朝下地安裝至該板上。 ___ ΊΙ 1 1 Ϊ ill 11 1 ill 1 iiiiPage 5 460997 V. Description of the invention (3) ------ It is applied to all internal lead portions # ′ in the same direction, making irregularities of the internal lead indirect strength difficult to occur. Therefore, it is possible to obtain a consistent and stable bonding state between the wafer and each of the internal lead portions. 1LJ Patent Publication No. H4-335546. 0 ^ Reference 3 is a single-point bonding method and equipment for TAB (Table Automated Bonding). This method is intended to obtain stable and irregular bond strength at the lead, even when the width of the lead is narrow. Therefore, the structure is as follows: A rotation mechanism is provided to relatively move one or one of the bonding tool and the lead wire, so that the tool is inclined by a vibration direction of the ultrasonic wave to form a predetermined angle with the longitudinal direction of the lead wire. This tool is inclined to form a predetermined angle with respect to the direction of vibration to form a device opening, and a conveyor belt equipped with a lead is transported. Li Gazette No. 7-169875. Reference 4 refers to the ball joint method. This method intends to obtain a highly reliable connection of the semiconductor element f-plate 2, and the connection has a large connection strength, a large current value, and a low connection resistance value. This method is to connect the semiconductor element to the board by forming a solid phase diffusion between a bump on the semiconductor element and a wiring formed on the board. 'At this time = short time and high mounting The density method enables the semiconductor element to be mounted face down on the board. ___ ΊΙ 1 1 Ϊ ill 11 1 ill 1 iiii

4 6 09 9 7 五、發明說明(4) 關於其結構方面,在—半 面朝下的安裝在構成一平面顯 ^中,半導體元件係 部之陶竟板上,該半導體件係茲玻璃板’或構成-熱頭 散,而接合至該板ί。、^ 之—配線間所進行的固相擴 圖1 〇係顯示可達成高密度 在圖示中,參考編號J代表—y Μ /置之例子。 示,多數的隆起電極3以矩形框且如圖π所 主要表面上,該半導艚3案形成於半導體基板2的 示)。 該丰導體基板2内有一半導體元件(未圖 用以形成隆起電極3之方法仫 用例如金之金屬的電鑛方法、炼m歹^中選出:使 法、以及使插入毛細管中之金屬化/金的晶粒之方 之方法,該金屬球係於超音波振動施成一金屬球 底部末端,然後拉出該金屬線振動施加時被壓在毛細管的 如圖1 2所示,參考編號4代表— 位於一絕緣基板5上的導電圖荦乂互連f板其1由 _ ^ P0 , , m _ N 〒电圃茶b所形成。此導電圖案Θ被 上,你兮道“不所覆蓋,且複數個窗孔形成於該光阻膜 置虛ΪΙΓί導電圖案_對應於半導體丸塊1之隆起電極3位 ^處之部分顯露出(圖式中之矩形窗孔),藉此而形成墊電 半導體丸塊1與交互連接板4係配置於彼此相對之位 置,使得隆起電3與墊電極7相疊置且電性連接。 為了減輕當半導體裝置8運作時所產生之熱造成應力4 6 09 9 7 V. Description of the invention (4) With regard to its structure, it is mounted on a half-face down on a ceramic display panel forming a planar display, the semiconductor element is a glass plate. 'Or constituted-thermal head scattered, and joined to the board. , ^-Solid phase expansion in the wiring room Figure 10 shows the high density can be achieved. In the figure, the reference number J represents -y Μ / placed example. It is shown that most of the raised electrodes 3 have a rectangular frame and are formed on the main surface as shown in FIG. Π, and the semiconductor electrodes 3 are formed on the semiconductor substrate 2). The semiconductor substrate 2 has a semiconductor element (not shown in the figure for forming the bump electrode 3), which is selected from a method such as a gold electrometallurgy method and metallurgy, and a method of metallization / insertion into a capillary tube. As for the method of gold grains, the metal ball is formed by the ultrasonic vibration to form the bottom end of a metal ball, and then the metal wire is pulled and pressed on the capillary when the vibration is applied, as shown in Fig. 12, and the reference number 4 represents- A conductive pattern 荦 乂 interconnected f-board 1 on an insulating substrate 5 is formed by _ ^ P0,, m _ N 〒 electric garden tea b. This conductive pattern Θ is on, and you say "not covered, and A plurality of window holes are formed in the photoresist film ΪΙΓί conductive pattern _ a portion corresponding to 3 places ^ of the raised electrode of the semiconductor pellet 1 is exposed (rectangular window holes in the figure), thereby forming an electrically conductive semiconductor The pill block 1 and the interactive connection plate 4 are arranged at positions opposite to each other, so that the bump 3 and the pad electrode 7 are stacked and electrically connected. In order to reduce the stress caused by the heat generated when the semiconductor device 8 operates

4 6 09 94 6 09 9

五、發明說明(5) 集中於電極連結部分’並為了改善抗潮渥性, 脂填滿半導體丸塊1與交互連接板4之間。 义要時以树 兹說明前述半導體裝置8之製造方法如下 置交互連接板4於加熱臺(夫^ ^ i先,放 上。 、堂C未圖不)上’其中墊電極7係面朝 作’使用-其底部末端設有 真空方式吸取半導體丸塊】,其中之整具,以 並且^多動該半導體丸塊1至交互連接板4的頂端 邊置隆起電極3於墊電極7上 茲 力至半導體丸塊!之受敎頂端表上面且二由工具施加壓 極7被擠壓在一起,藉: = 使传隆起電極3與塾電 形成-電性連接。 +導體丸塊1與交互連接板4間 中,ί ΐΪΐί文Ϊ4一日本專利公開公報第H7M 69875號 用於一半導體丸擒體裝置。丨中’球式接合法使 形成古八屆〃鬼及父互連接板上,該半導體丸塊上 成# Μ ί k起電極,且該交互連接板係由使鋁墊電極形 ΐί Π板上所製成。—支持臺支持被加熱至375。。之V. Description of the invention (5) Concentrating on the electrode connection portion 'and in order to improve the moisture resistance, the grease fills the space between the semiconductor pellet 1 and the interactive connection plate 4. When necessary, the manufacturing method of the aforementioned semiconductor device 8 will be described in the following manner. The interactive connection plate 4 is placed on a heating table (firstly, put it on.), Where the pad electrode 7 is facing. 'Use-the bottom end is provided with a vacuum method to suck semiconductor pellets], the whole of which is used to move the semiconductor pellets 1 to the top edge of the interactive connection plate 4 with a raised electrode 3 on the pad electrode 7 To the top of the wafer of the semiconductor pill! And the two pressure electrodes 7 are pressed together by the tool, by: = to make the conductive bump electrode 3 and -electrical connection-electrical connection. + Between the conductor pellet 1 and the interactive connection board 4, Japanese Patent Laid-Open Publication No. H7M 69875 is used for a semiconductor pellet capture device.丨 Chinese 'ball bonding method is used to form the ancient eighth ghost and father interconnection board. The semiconductor pellets are formed with electrodes, and the interactive connection board is formed by forming aluminum pad electrodes on the board. Made of. — The support desk support is heated to 375. . Of

之牟I <8#反,並且一真空吸頭以真空固持被加熱至300 °C g f Μ P ^丸塊。此等電極被疊置且被施加有每隆起部5 0 、=,持續0.15秒。藉此’在半導體丸塊與交互連接 切二ί ΐ 一良好的電性及機械性連接,其達到2. 7 kgf的 隻強度與33ιηΩ的平均電阻值。 平面則述揭露中提到:對於形成於每一個丸塊上之1 4 6個 尺寸為75 X 55/zm大小的隆起電極而言,當完成上述 4 6 0 9 9 7 若結合負 則半導體 技藝揭露 圖1 〇所示 示裝置之 或玻璃材 用到具有 裝置,儘 熱時間。 於如陶兗 百度°c的 變形。然 化,使得 環繞隆起 丸塊之負 觸表面, 極部分下 此趨近, 疊置電極 因,當使 空固持並 至隆起電 起時,隆 載為3 kg或4 kg且受熱溫度約為 丸塊與板之間可達成1.2至5.0 kgf 或玻璃 、、田 ώ: /皿度, 而,對 疊置電 電極的 載於凹 無法達 陷時, 倘若此 部分之 用樹脂 施壓半 極以及 起電極 五、發明說明(6) 的步驟時,倘 380 至460 〇C, 的切變強度。 上述先前 料,並且除了 至例如液晶顯 除了陶瓷 導體裝置可應 基板的半導體 加熱溫度與加 亦即,對 的,能容忍數 熱量所造成的 父互連接板軟 致墊電極流至 又方向施加至 外,亦增加接 當疊置電 互連接板會彼 更減弱施加至 基於此原 施加至用以真 音波振動施加 二者連結至一 以陶瓷與玻璃 的結構之外, 平面顯示器, 料之外,具有 例如玻螭纖維 管不可使用上 之堅硬 故可忽 於樹脂 極部分 末端邊 陷彎曲 到足夠 相對的 專相對 壓力。 交互連 導體丸 墊電極 以及墊 作為交互連接板之材 尚揭露可應用此技術 或者熱頭部上。 如圖1 0所示結構之半 J哀氧樹脂基板之樹脂 述習知技藝所揭露的 基板而言’其係耐熱 略疊置電極部分之因 基板而言,加熱導致 發生大量的下陷,導 緣’其除了使沿著交 表面間分散而變弱之 ,接合強度。 半導體丸塊表面與交 部分互相接觸時,則 接板時,超音波振動 塊之碩部,使得當超 之疊置部分上俾使此 電極之疊置部分受壓Zhimu I < 8 # is reversed, and a vacuum tip is heated to 300 ° C g f Μ P ^ pill block with vacuum holding. These electrodes are stacked and applied with 50 per ridge, = for 0.15 seconds. This ′ cuts and connects the semiconductor pellets with a double connection. A good electrical and mechanical connection, which has a strength of only 2.7 kgf and an average resistance value of 33 ιΩ. The disclosure of the planar description mentioned that for the 146 raised electrodes with a size of 75 X 55 / zm formed on each pellet, when the above 4 6 0 9 9 7 is completed if the negative is combined, the semiconductor technology The device shown in FIG. 10 or the glass material is used to have the device, and the warm-up time is disclosed. Deformation of Yu Rutao 兖 Baidu ° c. Naturally, the negative contact surface surrounding the bulge pellets approached, and the poles approached. When the electrodes were stacked and held in place, the bulge was 3 kg or 4 kg and the heating temperature was about 1.2 to 5.0 kgf or between glass and glass can be achieved between the block and the plate. However, if the recess of the stacked electric electrodes cannot be sunk, if this part of the electrode is pressed by the resin and the Electrode 5. In the step (6) of the invention, the shear strength is 380 to 460 ° C. In addition to the foregoing, and in addition to the liquid crystal display, for example, the ceramic conductor device can respond to the semiconductor heating temperature and addition of the substrate, that is, yes, it can tolerate the heat of the parent interconnect pad caused by several heat. In addition, it also increases the connection when the stacked electrical interconnection boards will be more weakened. Based on the original application, the two are connected to a ceramic and glass structure based on the original sound wave application. Flat displays, materials, For example, the glass fiber tube is hard to use, so the edge of the resin pole part can be bent to a sufficient relative specific pressure. Interactive connection Conductor pills, pad electrodes, and pads are used as the material of the connection board. It has been disclosed that this technology can be applied or heated on the head. As shown in Fig. 10, the structure of the substrate exposed by the resin technology of the semi-J-oxygen resin substrate is' the heat-resistant slightly overlapped electrode part. As a result of the substrate, a large amount of depression occurs due to heating, leading edges. 'In addition to dispersing and weakening along the intersecting surfaces, the joint strength is weakened. When the surface of the semiconductor pellet and the intersection part are in contact with each other, when the board is connected, the large part of the ultrasonic vibration block makes the superposed part of the electrode pressed when the superposed part is superposed.

460997460997

且受熱,而基板的溫度與先前 分的降低,藉此抑制基板之變形:1露的溫度相較下已充 藉由執行上述步驟,.對輪女、 置而言,有可能達到具有良好: 極的半導體裝 裝置。 變強度與電阻值之半導體 為了達成具有眾多電極 裝置,必須使半導體丸塊上 連接板上的導電圖案的空間 行於電極數量遠超過1〇個之 進行於電極數量少於1 〇個之 塾電極間之各電極切變強度 儘管在具有多數電極的半導 的電阻值變化仍大。 而同時保持外部尺寸之半導體 t隆起電極窄化,以及使交互 乍化。倘若整批超音波連接進 多重電極半導體丸塊上,以及 半導體丸塊上’則隆起電極與 似乎極度取決於電極之數量, 體裝置中隆起電極與墊電極間And it is heated, and the temperature of the substrate is reduced from the previous points, thereby suppressing the deformation of the substrate: 1 The temperature has been performed by performing the above steps compared to the temperature. For the wheel girl, it is possible to achieve a good: Semiconductor device. In order to achieve a large number of electrode devices, semiconductors with variable strength and resistance must make the space of the conductive pattern on the connection plate on the semiconductor pellets run over 10 electrodes, and 塾 electrodes with less than 10 electrodes. In spite of this, the shear strength of each electrode is large even in the resistance value of the semiconductor having most electrodes. At the same time, the semiconductor t-bump electrodes, while maintaining the external dimensions, are narrowed and the interaction is narrowed. If the whole batch of ultrasonic waves is connected to the multi-electrode semiconductor pellets, and the semiconductor pellets, then the raised electrode and the seemingly depend on the number of electrodes, between the raised electrode and the pad electrode in the body device

【發明概述】 據此本發明之一目的在於,藉由提供一種半導體 :以解決與,述先前技術有關的問題,其中利用超音波: ,形成於半導體丸塊上的隆起電極與形成於絕緣基板上 ”間形成電性連接"匕半導體裝置中之半導體丸塊 具有隆起電極,該隆起電極係排列於至少二條相互交叉 成直角的直線上。並且’形成於彈性交互連接板上的墊電 極之鄰近區域,其包括與隆起電極疊置之部分,係延伸於 與隆起電極之排列方向不同之方向。 本發明亦為一種半導體裝置之製造方法,該裝置具有[Summary of the Invention] Accordingly, an object of the present invention is to provide a semiconductor to solve the problems related to the prior art, in which ultrasonic waves are used: a raised electrode formed on a semiconductor pellet and an insulating substrate The semiconductor pellet in the semiconductor device has a raised electrode. The raised electrode is arranged on at least two straight lines crossing each other at right angles. And it is formed on the pad electrode of the elastic interactive connection board. The adjacent area, which includes a portion overlapping the raised electrodes, extends in a direction different from the direction in which the raised electrodes are arranged. The present invention is also a method for manufacturing a semiconductor device.

第10頁 460997 五、發明說明(8) 一半導體丸塊以及一彈性交互連接板,該半導體丸塊之主 要表面上具有複數個隆起電極,排列於至少二條相互蜜直 的直線上’並且該彈性交互連接板之對應於該複數個隆起 電極的位置處有複數個墊電極形成於一絕緣基板上。該複 數個隆起電極與該複數個墊電極被疊置,並且當壓力從半 導體丸塊的上方施加時,維持半導體丸塊與交互連接板間 之平行狀態,同時施加超音波振動。藉此在半導體丸塊及 隆起電極間形成一電連接。所用的交互連接板上具有鄰近 隆起電極的疊置部分的墊電極區域,該墊電極之延伸方向 不同於隆起電極之排列方向。經由半導體丸塊而施加至隆 起電極與墊電極之疊置部分的超音波振動之方向係設定成 依循墊電極之延伸方向。 在依據本發明之半導體裝置中,一半導體丸塊上的隆 起電極與一絕緣基板上的墊電極彼此疊置,並且超音波振 動施加於其上以形成一電連接。隆起電極係排列於眾多隆 起電極之至少兩條垂直交文吉& 肀土且父又直線上,並且一包括與隆起電 極且置之邛为的鄰近區域係延伸於與隆起電極排列方向不 同之方向。墊電極之刖述鄰近區域與隆起電極排列方向交 叉形成一位於30度至60度範圍内之角度。 在上述例子中,交互i車拔4c U β , 乂立連接板上之所有塾電極之排列方 向最好和包括與隆起電極疊詈 t I直之部分之鄰近區域的延伸方 向一致。Page 10 460997 V. Description of the invention (8) A semiconductor pellet and an elastic interactive connecting plate, the semiconductor pellet has a plurality of raised electrodes on a main surface thereof, which are arranged on at least two mutually straight straight lines, and the elasticity A plurality of pad electrodes are formed on an insulating substrate at positions of the interactive connection board corresponding to the plurality of raised electrodes. The plurality of raised electrodes and the plurality of pad electrodes are stacked, and when pressure is applied from above the semiconductor pellets, a parallel state between the semiconductor pellets and the interconnecting plate is maintained, and ultrasonic vibration is applied at the same time. Thereby, an electrical connection is formed between the semiconductor pellet and the bump electrode. The interactive connection board used has a pad electrode region adjacent to the overlapping portion of the raised electrode, and the pad electrode extends in a direction different from the direction in which the raised electrode is arranged. The direction of the ultrasonic vibration applied to the overlapped portion of the bump electrode and the pad electrode via the semiconductor pellet is set to follow the extending direction of the pad electrode. In the semiconductor device according to the present invention, a bump electrode on a semiconductor pellet and a pad electrode on an insulating substrate are superposed on each other, and an ultrasonic vibration is applied thereto to form an electrical connection. The raised electrode system is arranged on at least two vertically intersecting Wenji & soil and father lines of a plurality of raised electrodes, and an adjacent area including the raised electrode is disposed in a direction different from the direction in which the raised electrodes are arranged . The adjacent area of the pad electrode intersects with the alignment direction of the raised electrodes to form an angle in a range of 30 to 60 degrees. In the above example, it is preferable that the arrangement direction of all the 塾 electrodes on the stand-alone connection plate 4c U β is the same as the extension direction of the adjacent area including the portion straight with the raised electrode stack 詈 t I.

鄰近藝電極與隆起電極 設成較被疊置部分之長度長 之疊置部分的區域之長度,可The length of the area of the overlapping portion where the adjacent electrode and the raised electrode are longer than the length of the overlapping portion may be

4 6 099 7 五、發明說明 (9)4 6 099 7 V. Description of the invention (9)

墊電極與隆起電極之疊置區域的 中未因壓力之施加而變形之區 在上述例子中,鄰近 區域最好延伸至絕緣基板 域。 在依據本發明之半導體裝置之製造方法中,使用一交 ,其中一包括墊電極與隆起電極間疊置部份之鄰 近區域係延伸於與隆起電極之排列方向不同之方向。妳由 ::導體丸塊而施加至隆起電極與墊電極之疊置部分:超 曰波振動之方向係設定成沿著塾電極之延伸方向。並且, =音J之該振動方向可設定為一交又角度的一 :向’该交叉角度係由沿著至少二條彼此交叉的直線:該 隆起電極與該墊電極之排列方向所夾成。 【較佳實施例之詳細說明】 =參照”詳細說明本發明之實施例如下。 中,參考I Sc)矣貝施例將參考圖1而作說明。在此圖 Η的ίί'Ϊ 一半導體丸塊,其中之-半導體基板 u的主要表面上排列右容叙 係3.4 χ5 η =個隆起電極11,該半導體基板 一、 . )Χ〇·3(厚度)_且有半導體元件(夫圖 不)形成於其上。 ,干守瓶疋仟C未圖 如圖2所示 障膜(未in 1 μ >藉&由#在覆蓋著半導體基板10且電鍍於阻 之方法,或,由球式D、产不)之特定部分中形成窗孔 正方形或矩形半導體基^ ^式在 B、C、鱼]),呤芈抖认+丄 、w逭办珉馮電極群組Λ、 ,、千仃的電極配置群組Λ與C或者^與!)之延伸In the overlapped region of the pad electrode and the bump electrode, a region that is not deformed by the application of pressure. In the above example, the adjacent region preferably extends to the insulating substrate region. In the method for manufacturing a semiconductor device according to the present invention, an intersection is used. One of the adjacent areas including the overlapping portion between the pad electrode and the bump electrode extends in a direction different from the direction in which the bump electrodes are arranged. You apply the overlapped part of the bump electrode and the pad electrode from the :: conductor pellet: the direction of the super-wave vibration is set along the extension direction of the rubidium electrode. In addition, the vibration direction of the tone J can be set to be an intersection and an angle: the direction ′ The crossing angle is formed by at least two straight lines crossing each other: the alignment direction of the raised electrode and the pad electrode. [Detailed description of the preferred embodiment] = The detailed description of the embodiment of the present invention will be given with reference to the following. In the reference, I Sc) The example will be described with reference to FIG. Block, of which-the right side of the semiconductor substrate u is arranged on the main surface 3.4 x 5 η = raised electrodes 11, the semiconductor substrate I,.) Χ〇 · 3 (thickness) _ and there are semiconductor elements (Futu not) It is formed thereon, and the dry stopper bottle is not shown in FIG. 2 and the barrier film (not in 1 μ) is used to cover the semiconductor substrate 10 and is plated in a resistive method, or, by a ball A square or rectangular semiconductor substrate with a window hole is formed in a specific part of the formula (D). (Formulas are in B, C, and fish]), and the electrode group + ,, and 逭 are used to form the Feng electrode group Λ, ,, and 1000. Extension of 仃 's electrode configuration group Λ and C or ^ and!)

4 6 0 9 9 7 五、發明說明(10)4 6 0 9 9 7 V. Description of the invention (10)

邛刀係垂直父又於相鄰的電極配置群組 —雖然在圖示之例子+,電極配置群組A、B、C m隆起電極11係排列成單-環狀,以形成較多的電 極,但亦可排列於交錯形式之線上。 夕的電 圖幻號12表示一交互連接板’其係藉由形成一導電 化i稾嫩炉=性樹月旨基板13上所製成’例如由破璃纖維強 在導電圖成的彈性樹脂基板。並且,墊電極15形成 置上。案4上之對應於半導體丸塊9之隆起電極丨丨的位 粗、f ^供的此等墊電極1 5係適合隆起電極11之電極材 體丸娘Λ、以及尺寸。舉例而言,對於使用金電錄在半導 導=脂基?r,厚度12”的銅以 作為墊置上一 tif3到一的錄層形成於將 玉电b之位置上,此等位置被金覆蓋至厚度 ,以形成墊電極15於交互連接板12上。 由虛ί :3/斤不’當上述的步驟完成後,墊電極1 5係位於 7虛線所表示的半導體丸塊9的隆起電極i i之相對位置 近區電極11之部分(圖中之斜線區)的鄰 域::極配置群組A、B、c、及D之排列方向交叉成45 度角’並且延伸於單一且相同的方向上。 根據本發明之半導體裝置的製造方法如下。 上所示Λ一交互連接板]2被放置在如圖4戶斤*之一加熱臺 被疋位且加熱。為了達成隆起電極η與墊電極〗5間 第13頁 4 6 09 9 7 五、發明說明(11) 之良好的超音波連接,加熱此交互連接板1 2。在玻璃纖維 環氧樹脂板之例子中,加熱溫度係設定至8 0。(:。 繼而,如圖5所示之一真空固持頭1 7以真空方式吸取 半導體丸塊9 ’並放置在該交互連接板12上。該真空固持 頭17具有一位於平坦的下端表面I7a上的真空埠17b,且連 結於一施加超音波振動的號筒1 8,該號筒1 8係水平地上下 移動’以傳送超音波振動至交互連接板丨2上的半導體丸塊 連結於上述真空固持頭1 7的號筒1 8之配置如圖6所The scabbard is vertically arranged next to the adjacent electrode group-although in the example shown in the figure +, the electrode configuration group A, B, and C m. The raised electrodes 11 are arranged in a single-ring shape to form more electrodes. , But can also be arranged on a staggered line. The electric magic number 12 of the evening shows an interactive connection board 'made by forming a conductive substrate on the substrate 13', for example, an elastic resin made of broken glass fibers and strong on the conductive pattern. Substrate. Further, the pad electrode 15 is formed. The pad electrodes 15 corresponding to the bump electrodes of the semiconductor pellet 9 in the case 4 are thick, and the pad electrodes 15 provided for the bump electrodes 15 are suitable for the bump material 11 of the bump electrode 11 and the size. For example, for the use of gold recording on the semiconductor = lipid-based, r, 12 "thick copper as a pad on a tif3 to a recording layer is formed on the position of Yudian b, these positions are Gold is covered to a thickness to form a pad electrode 15 on the interactive connection plate 12. By the virtual: 3 / jinbu 'When the above steps are completed, the pad electrode 15 is located on the bump of the semiconductor pellet 9 indicated by the dashed line 7 The relative position of electrode ii is near the part of the electrode 11 (slashed area in the figure). Neighborhood: The arrangement directions of the pole arrangement groups A, B, c, and D intersect at a 45-degree angle 'and extend to a single and the same The method of manufacturing a semiconductor device according to the present invention is as follows. The above-mentioned Λ-interactive connection board] 2 is placed on a heating stage as shown in Fig. 4 and is heated and heated. In order to achieve the raised electrode η and Pad electrode [5] Page 13 4 6 09 9 7 V. Explanation of the invention (11) For good ultrasonic connection, heat this interactive connection board 12. In the example of glass fiber epoxy board, the heating temperature is set To 80. (:. Then, as shown in FIG. 5, one of the vacuum holding heads 17 is in a vacuum direction. The semiconductor pellet 9 'is sucked and placed on the interactive connection plate 12. The vacuum holding head 17 has a vacuum port 17b on a flat lower end surface I7a, and is connected to a horn 18 applying ultrasonic vibration. The horn 1 8 series moves horizontally up and down to transmit ultrasonic vibration to the interactive connection board 丨 2 The semiconductor pellets on the 2 are connected to the above-mentioned vacuum holding head 17 and the horn 18 is configured as shown in Figure 6

示’此係超音波振動方向’與墊電極1 5之延伸方向實質上 一致。 繼而,該真空固持頭1 7下降至交互連接板丨2的上方, 使隆起電極11與墊電極15疊置’且施加每隆起電極30 gf 之壓力至半導體丸塊9,持續〇. 3至3秒。因為交互連接板 1 2被加熱且軟化,所以墊電極丨5被局部擠壓且形成一凹步 彎曲。 y 當此事發生時,對應於所有隆起電極Π的墊電極丨5會 於相同方向上延伸,此方向係超音波振動之方向。It is shown that 'the ultrasonic vibration direction' is substantially the same as the extending direction of the pad electrode 15. Then, the vacuum holding head 17 is lowered to the top of the interactive connection plate 丨 2, so that the raised electrode 11 and the pad electrode 15 are stacked, and a pressure of 30 gf per raised electrode is applied to the semiconductor pellet 9 for 0.3 to 3 second. Because the interconnecting plate 12 is heated and softened, the pad electrode 5 is partially squeezed and formed into a concave bend. y When this happens, the pad electrodes 5 corresponding to all the raised electrodes Π will extend in the same direction, this direction is the direction of ultrasonic vibration.

亦即,由於施加在隆起電極丨丨的超音波振動係施加於 塾電極15的延伸方向上,在垂直於圖7之圖平面的方向上 所施加的超音波振動不會以寬度方向施加至墊電極1 5。 ^基於此原因’沒有引起墊電極1 5在寬度方向上扭曲變 形之外力’其中墊電極丨5之關於絕緣基板丨3的黏附長度是That is, since the ultrasonic vibration system applied to the raised electrode 丨 丨 is applied to the extension direction of the 塾 electrode 15, the ultrasonic vibration applied in the direction perpendicular to the plane of the drawing in FIG. 7 is not applied to the pad in the width direction. Electrode 1 5. ^ For this reason, 'the pad electrode 15 does not cause distortion in the width direction, and there is no external force.' Among them, the adhesion length of the pad electrode 5 to the insulating substrate 3 is

46〇99746〇997

如圖8所示,因為墊電極15之鄰近區域延伸至未因壓 施加至疊置部分而變形的區域,所以關於絕緣基板丨3之 ^附長度係足夠長,即使交互連接板丨2因加熱而軟化使得 極疊置部分下陷亦然。於平行於圖平面之方向上所施加 ^超音波振動係集中於電極疊置部分,而可達成一良好的 連結’其中该施加方向係墊電極1 5之延伸方向。 _因為依據本發明之半導體裝置之所有墊電極15均以相 同方向延伸,不僅可形成大的電極間接合強度與小的電阻 ’並且其變動亦可變小,使得即使沒有使用例如陶瓷基 板或玻璃基板之堅硬材料’仍可於隆起電極的數量遠超過 ^個時,例如在丨00個電極的半導體丸塊之例子中,達成 —個隆起電極為3〇gf或更大的切變強度,及約5〇 的低電阻值連接。 =當半導體丸塊9受切力而從交互連接板12分離且觀察 該疊置部分的連接情狀時,證實在所有墊電極丨5上皆殘留 有部分的隆起電極11 ’藉此表示出一強固且均勾的機械性 連接。 雖然在上述例子中’墊電極1 5係延伸於與電極配置群 纽A、B、C、及D之排列方向形成45度角之方向上,但只要 傾斜角度位於3 0度至6 0度的範圍内,如附圖9所示,則仍 可達成一良好的電性連接’其抑制切變強度之降低及電阻 值之增加。 在此例子中,超音波振動方向最好係傾斜方向之一中 間方向’舉例而言,倘若最大傾斜角度介於3〇度至6〇度之As shown in FIG. 8, since the adjacent area of the pad electrode 15 extends to an area that is not deformed by the pressure applied to the superimposed portion, the attached length of the insulating substrate 3 is long enough, even if the interactive connection plate 2 is heated due to heating. The softening caused the superposition of the poles to sink. The supersonic vibration system applied in a direction parallel to the plane of the drawing is concentrated on the electrode stacking portion, and a good connection can be achieved ', wherein the application direction is the extension direction of the pad electrode 15. _Because all the pad electrodes 15 of the semiconductor device according to the present invention extend in the same direction, not only a large inter-electrode bonding strength and a small resistance can be formed, but also its variation can be made small, so that even if no ceramic substrate or glass is used, for example, The hard material of the substrate can still be achieved when the number of bump electrodes is far more than ^, for example, in the case of a semiconductor pellet of 00 electrodes, a bump strength of 30 gf or more is achieved, and A low resistance value of about 50 is connected. = When the semiconductor pellet 9 is separated from the interactive connection plate 12 by the shear force and the connection condition of the overlapped portion is observed, it is confirmed that there are some raised electrodes 11 remaining on all the pad electrodes 5 ′, thereby showing a strong And even hook mechanical connection. Although in the above example, the "pad electrode 15" extends in a direction forming an angle of 45 degrees with the arrangement direction of the electrode arrangement groups A, B, C, and D, as long as the inclination angle is between 30 and 60 degrees Within the range, as shown in FIG. 9, a good electrical connection can still be achieved, which suppresses a decrease in shear strength and an increase in resistance value. In this example, the direction of the ultrasonic vibration is preferably the middle direction, which is one of the tilt directions. For example, if the maximum tilt angle is between 30 and 60 degrees,

460997 五、發明說明(13) 間,則超音波振動方向可以4 5度角對應於電極配置群組 A、B、C、及D。 雖然所有墊電極〗5之延伸方向最好一致,但對於那4匕 在丸塊角落的焊塾’在該處可於重疊部分中達成足夠的表 面面積,故可接受其延伸方向不同於其他隆起電極。 藉由使墊電極1 5與隆起電極11間之疊置部分之鄰近區 域的長度設定成較電極疊置部分長,可使得因施加於墊電 極1 5與絕緣基板1 3之壓力而造成的凹狀彎曲變長,且 使其延伸至未因魔力之施加而變形之區域。 應注意者為:本發明並未受前述實施 而言’除了正方形隆起電如外,也可採用長方例 形、或平打四邊形的隆起電極, 曼 度及延伸方向以適合傾斜角度。且更了改變塾電極15之寬 藉由採用前文詳述的構$ , 的樹脂交互連接板,本發明仍可,用在加熱時會軟化 導體丸塊形成一堅固的電性及機械;生2過1〇個電極之半 460997 圖式簡單說明 圖1係顯示依據本發明半導體裝置之剖面圖。 圖2係顯示圖1之半導體裝置所用的半導體丸塊之平面 圖。 圖3係顯示圖1之半導體裝置所用的交互連接版之局部 平面圖。 圖4係顯示製造圖1之半導體裝置的方法之剖面圖。 圖5係顯示在圖4之後的製程之剖面圖。 圖6係顯示在圖5製程中之交互連接板與超音波振動方 向之局部平面圖。 圖7係顯示施加於疊置電極部分之超音波振動條件之 局部剖面圖。 圖8係顯示施加於疊置電極部分之超音波振動條件之 局部剖面圖。 圖9係顯示電極配置群組及墊電極間所形成的角度之 局部平面圖。 圖1 0係顯示半導體裝置的例子之剖面圖。 圖11係顯示圖10之半導體裝置所用的半導體丸塊之平 面圖。 圖1 2係顯示圖1 0之半導體裝置所用的交互連接板之局 部平面圖。 〔標號說明〕 1〜半導體丸塊 2〜半導體基板460997 5. In the description of the invention (13), the ultrasonic vibration direction can correspond to the electrode arrangement groups A, B, C, and D at an angle of 45 degrees. Although the extension direction of all pad electrodes 5 is best consistent, the welding surface of the four daggers at the corner of the pellet can reach a sufficient surface area in the overlapping portion, so it can be accepted that its extension direction is different from other bulges. electrode. By setting the length of the adjacent area of the overlapping portion between the pad electrode 15 and the raised electrode 11 to be longer than the electrode overlapping portion, the depression caused by the pressure applied to the pad electrode 15 and the insulating substrate 13 can be made. The shape of the curve becomes longer, and it extends to the area that is not deformed by the application of magic force. It should be noted that the present invention is not affected by the foregoing implementation. In addition to square-shaped ridges, rectangular-shaped or flat-shaped ridged electrodes can also be used. Furthermore, the width of the rhenium electrode 15 is changed. By using the resin interactive connection plate of the structure described in detail above, the present invention is still applicable. It can soften the conductive pellets when heated to form a solid electrical and mechanical structure. Brief description of half of the 10 electrodes 460997. FIG. 1 is a cross-sectional view showing a semiconductor device according to the present invention. FIG. 2 is a plan view showing a semiconductor pellet used in the semiconductor device of FIG. 1. FIG. FIG. 3 is a partial plan view showing an interconnection board used in the semiconductor device of FIG. 1. FIG. FIG. 4 is a sectional view showing a method of manufacturing the semiconductor device of FIG. 1. FIG. FIG. 5 is a cross-sectional view showing a process subsequent to FIG. 4. Fig. 6 is a partial plan view showing the interactive connection plate and the direction of ultrasonic vibration in the process of Fig. 5; Fig. 7 is a partial cross-sectional view showing the ultrasonic vibration conditions applied to the stacked electrode portion. Fig. 8 is a partial cross-sectional view showing the ultrasonic vibration conditions applied to the stacked electrode portion. Fig. 9 is a partial plan view showing an angle formed between the electrode arrangement groups and the pad electrodes. FIG. 10 is a cross-sectional view showing an example of a semiconductor device. FIG. 11 is a plan view showing a semiconductor pellet used in the semiconductor device of FIG. 10. FIG. FIG. 12 is a partial plan view showing an interactive connection board used in the semiconductor device of FIG. 10. [Remarks] 1 ~ semiconductor pellet 2 ~ semiconductor substrate

460997 圖式簡單說明. 3〜隆起電極 4 ~ 交互連接板 5〜絕緣基板 6〜導電圖案 7 ~ 墊電極 8 ~半導體裝置 9〜半導體丸塊 10 ~ 半 導 體 基 板 11 ~ 隆 起 電 極 12〜 交 互 連 接 板 13 ~ 絕 緣 性 基 板 14 - 導 電 圖 案 15〜 塾 電 極 16 ~ 加 熱 臺 17〜 真 空 固 持 頭 17a ~ 下端表面 17b ~ 真空埠 1 8 ~號筒460997 Schematic illustration. 3 ~ Elevated electrode 4 ~ Interconnecting board 5 ~ Insulating substrate 6 ~ Conductive pattern 7 ~ Pad electrode 8 ~ Semiconductor device 9 ~ Semiconductor pellet 10 ~ Semiconductor substrate 11 ~ Elevated electrode 12 ~ Interconnecting board 13 ~ Insulating substrate 14-Conductive pattern 15 ~ Krypton electrode 16 ~ Heating stage 17 ~ Vacuum holding head 17a ~ Lower surface 17b ~ Vacuum port 1 8 ~ Horn

第18頁Page 18

Claims (1)

4 6 099 7 六、申請專利範圍 1. 一種半導體裝置,包含: 一半導體丸塊’其主要表面上形成複數個隆起電極; 一交互連接板,其由形成於一絕緣基板上之複數個墊 電極所形成,該複數個墊電極之位置係對應於該複數個隆 起電極之位置; 其中,使該半導體丸塊與交互連接板彼此相對,俾疊 置該複數個隆起電極與該複數個墊電極,且使其遭受壓力 及超音波振動,藉以電連接該半導體丸塊至該交互連接 板;以及 其中,在該半導體丸塊上之該隆起電極排列於至少二 條垂直交又的直線上,形成該交互連接板之該絕緣基板係 一具彈性之材料,並且包含該墊電極與該隆起電極間之一 Sί 一鄰近區域係延伸於與該隆起電極之排列方向 不同的方向上。 申請專利範圍第1項之半導體裝置,其中包含該墊電 亟/、Μ隆起電極間之疊置部分之該鄰近區 極之該排列方向形成—30度至6〇度的傾斜角。隆(電 3塾雷如極申二專:]範圍第2項之半導體裝置1中包含所有該 延伸方二單=疊置部分之該複數個鄰近區域的 干 且相冋的方向。 4·如申凊專利範圍第1項之半導體裝置,其中鄰近該墊電 4 6 〇99 7 六、申請專利範圍 極與該隆起電極間之該疊置部分之區域的長度較該疊置部 分的長度長。 5.如申請專利範圍第4項之半導體裝置,其中鄰近該墊電 極與該隆起電極間之疊置部分之該區域係延伸至超過該絕 緣基板中因施加壓力而變形的區域。 一種半導體裝置之製造方法,談半導體裝置具有一半 導體丸塊以及一彈性交互連接板,該半導體丸塊之主要表 面上具有複數個隆起電極’排列於至少二條相互垂直的直 線上,並且該彈性交互連接板之對應於該複數個隆起電極 的位置處有複數個墊電極形成於一絕緣基板上,藉以疊置 該複數個隆起電極與該複數個墊電極,並且當壓力從該半 導體丸塊的上方施加時,維持該半導體丸塊與該交互連接 板間之平行狀態,同時施加超音波振動,藉此在該半導體 丸塊及該隆起電極間形成一電連接’並且所用的交互連接 板上具有鄰近隆起電極的疊置部分的墊電極區域,該墊 極之延伸方向不同於該隆起電極之排列方向,經由該半 體丸塊施加至該隆起電極與該墊電極之該疊置部分之 波振動之方向係設定成依循該墊電極之延伸方向。 曰 7.如申請專利範圍第6項之半導 該超音波之該振動方向係設定為 方向,該交叉角度係由沿著至少 體裝置之製造方法,其 一交叉角度的一中間角 一條彼此交叉的直線之 中 度、 該4 6 099 7 VI. Scope of Patent Application 1. A semiconductor device comprising: a semiconductor pellet 'having a plurality of raised electrodes formed on a main surface thereof; an interactive connecting plate comprising a plurality of pad electrodes formed on an insulating substrate The position of the plurality of pad electrodes corresponds to the position of the plurality of raised electrodes; wherein the semiconductor pellet and the interactive connection plate are opposed to each other, and the plurality of raised electrodes and the plurality of pad electrodes are stacked, And subject it to pressure and ultrasonic vibration, thereby electrically connecting the semiconductor pellet to the interactive connection board; and wherein the raised electrodes on the semiconductor pellet are arranged on at least two perpendicularly crossing straight lines to form the interaction The insulating substrate of the connecting plate is a flexible material, and an adjacent area including one between the pad electrode and the raised electrode extends in a direction different from the direction in which the raised electrodes are arranged. The semiconductor device of the scope of application for patent No. 1 includes the pad / emergent electrode, the adjacent region of the overlapped portion of the M raised electrode, and the arrangement direction of the adjacent region electrode forms an inclination angle of -30 degrees to 60 degrees. Long (Electricity 3) The semiconductor device 1 of the second item in the range 2 includes all the extended squares = the overlapping and dry directions of the plurality of adjacent areas. 4 · 如The semiconductor device of claim 1 in the patent scope, wherein the pad is adjacent to the pad 4 6 099 7 6. The length of the area of the overlapped portion between the patented range electrode and the raised electrode is longer than the length of the overlapped portion. 5. The semiconductor device according to item 4 of the application, wherein the area adjacent to the overlapping portion between the pad electrode and the raised electrode extends beyond the area deformed by the applied pressure in the insulating substrate. The manufacturing method refers to a semiconductor device having a semiconductor pellet and an elastic interactive connection plate. The main surface of the semiconductor pellet has a plurality of raised electrodes' arranged on at least two mutually perpendicular straight lines, and the correspondence of the elastic interactive connection plate A plurality of pad electrodes are formed on an insulating substrate at the positions of the plurality of raised electrodes, thereby stacking the plurality of raised electrodes and the plurality of pads. And when pressure is applied from above the semiconductor pellet, maintaining a parallel state between the semiconductor pellet and the interactive connection plate, and simultaneously applying ultrasonic vibration, thereby forming a gap between the semiconductor pellet and the raised electrode The electrical connection is used, and the interactive connection board used has a pad electrode region adjacent to the overlapping portion of the raised electrode, and the extension direction of the pad electrode is different from that of the raised electrode, and is applied to the raised electrode and The direction of wave vibration of the superposed part of the pad electrode is set to follow the extension direction of the pad electrode. 7. If the direction of vibration of the superconducting ultrasonic wave of item 6 of the patent application range is set to the direction, the The crossing angle is determined by the method of manufacturing at least a body device, a middle angle of a crossing angle, a straight line crossing each other, 4 6 099 7 六、申請專利範圍 隆起電極與該墊電極之排列方向所夾成。4 6 099 7 6. Scope of patent application The raised electrode is sandwiched with the direction of arrangement of the pad electrode.
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Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002158258A (en) * 2000-11-17 2002-05-31 Sony Corp Semiconductor device, and its manufacturing method
JP4572465B2 (en) * 2000-12-15 2010-11-04 株式会社村田製作所 Manufacturing method of electronic component device
JP4341187B2 (en) * 2001-02-13 2009-10-07 日本電気株式会社 Semiconductor device
TW484172B (en) * 2001-02-15 2002-04-21 Au Optronics Corp Metal bump
JP3687610B2 (en) * 2002-01-18 2005-08-24 セイコーエプソン株式会社 Semiconductor device, circuit board, and electronic equipment
JP3603890B2 (en) * 2002-03-06 2004-12-22 セイコーエプソン株式会社 Electronic device, method of manufacturing the same, and electronic apparatus
JP3722137B2 (en) * 2002-08-21 2005-11-30 セイコーエプソン株式会社 Semiconductor device mounting method, semiconductor device mounting structure, electro-optical device, electro-optical device manufacturing method, and electronic apparatus
TWI225695B (en) * 2003-11-14 2004-12-21 Advanced Semiconductor Eng Structure of flip chip package and structure of chip
JP4905621B2 (en) * 2004-01-06 2012-03-28 セイコーエプソン株式会社 SEMICONDUCTOR DEVICE, ITS MANUFACTURING METHOD, AND ELECTRONIC DEVICE
US7255601B2 (en) * 2004-12-21 2007-08-14 Fci Americas Technology, Inc. Cap for an electrical connector
JP2006319211A (en) * 2005-05-13 2006-11-24 Sharp Corp Packaging structure of semiconductor chip
JP2008140891A (en) * 2006-11-30 2008-06-19 Nec Corp Element mounting structure and element mounting method
JP2007150370A (en) * 2007-03-15 2007-06-14 Seiko Epson Corp Semiconductor module, electronic device, electronic apparatus, and process for fabricating semiconductor module
CN104112684A (en) * 2014-07-03 2014-10-22 上海交通大学 Solid ultrasonic bonding method based on nickel micro cones
CN104112681A (en) * 2014-07-03 2014-10-22 上海交通大学 Solid-state ultrasonic bonding method based on copper microneedle cone
JP6451180B2 (en) * 2014-09-26 2019-01-16 富士電機株式会社 Semiconductor device manufacturing apparatus and semiconductor device
KR102481381B1 (en) * 2016-01-11 2022-12-27 삼성디스플레이 주식회사 Flexible display device

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0815167B2 (en) * 1986-03-26 1996-02-14 株式会社日立製作所 Semiconductor device
CA1340955C (en) 1988-02-24 2000-04-11 Michael Klaus Stilbene derivatives
JPH0344051A (en) 1989-07-12 1991-02-25 Hitachi Ltd Wire bonding method
JPH04335546A (en) 1991-05-10 1992-11-24 Toshiba Corp Method and apparatus for single point bonding
JP3506393B2 (en) 1993-03-11 2004-03-15 株式会社東芝 Liquid crystal display device and its manufacturing method, printer and its manufacturing method
US5394009A (en) * 1993-07-30 1995-02-28 Sun Microsystems, Inc. Tab semiconductor package with cushioned land grid array outer lead bumps
JP3383081B2 (en) * 1994-07-12 2003-03-04 三菱電機株式会社 Electronic component manufactured using anodic bonding and method of manufacturing electronic component
US5585667A (en) * 1994-12-23 1996-12-17 National Semiconductor Corporation Lead frame for handling crossing bonding wires
US5719440A (en) * 1995-12-19 1998-02-17 Micron Technology, Inc. Flip chip adaptor package for bare die
US5807767A (en) * 1996-01-02 1998-09-15 Micron Technology, Inc. Technique for attaching die to leads
JPH1174413A (en) * 1997-07-01 1999-03-16 Sony Corp Lead frame and its manufacture, semiconductor device and its assembling method, and electronic equipment
JPH1140702A (en) * 1997-07-23 1999-02-12 Nec Corp Substrate for mounting semiconductor element and manufacture of semiconductor device
JPH11297872A (en) * 1998-04-13 1999-10-29 Mitsubishi Electric Corp Semiconductor device
JP2000150701A (en) * 1998-11-05 2000-05-30 Shinko Electric Ind Co Ltd Semiconductor device, connection board used therefor, and manufacture thereof
US6313999B1 (en) * 1999-06-10 2001-11-06 Agere Systems Optoelectronics Guardian Corp. Self alignment device for ball grid array devices

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