JP2863426B2 - Semiconductor device mounting structure and mounting method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a mounting structure of a semiconductor device, and more particularly to a mounting structure of a semiconductor device in which a plurality of semiconductor chips are connected to a wiring board in a face-down manner and a mounting method thereof.

[0002]

2. Description of the Related Art As a method of mounting a semiconductor device in which a semiconductor chip is connected to a wiring board in a face-down manner, a method of connecting to a chip electrode of the semiconductor chip via a bump formed by plating, ball bonding, or the like, There are a method of pressing and connecting a semiconductor chip with an anisotropic conductive film interposed between wiring substrates, a method of arranging conductive particles on a chip electrode or a substrate electrode, and pressing and connecting a semiconductor chip. In any of these methods, a tool is applied from the back surface of the semiconductor chip when the semiconductor chip is temporarily fixed to the semiconductor substrate or when the semiconductor chip is connected to the wiring substrate.

When mounting a plurality of semiconductor chips,
In the conventional technologies, the thickness of the semiconductor substrate of the semiconductor chip, the connection structure for connecting the chip electrode of the semiconductor chip to the substrate electrode of the wiring substrate, and the wiring substrate for connecting the semiconductor chip are not changed. The height after connection from the reference surface to the back surface of the semiconductor chip was the same.

[0004]

In recent years, there has been an increasing demand for mounting a plurality of semiconductor chips at a high density and for reducing the distance between adjacent semiconductor chips in view of electrical characteristics.

However, when the height after connection from the reference surface of the wiring board to the back surface of the semiconductor chip is the same as before, the second semiconductor chip adjacent to the first temporarily connected or connected first semiconductor chip is used. When the semiconductor chip is temporarily fixed or connected, the following problem occurs.

As shown in FIG. 7A, the tool 4 is also in contact with the back surface 1r of the first semiconductor chip 1, and the first semiconductor chip 1 is displaced due to a slight blur or the like which normally occurs.

As shown in FIG. 7B, the tool 4 is also in contact with the back surface 1r of the first semiconductor chip 1, and the first semiconductor chip 1 is tilted due to a slight blur or the like that normally occurs.

As shown in FIG. 7C, the tool 4 is also in contact with the back surface 1r of the first semiconductor chip 1, and the first semiconductor chip 1 has cracks, chipping, etc. Damage occurs.

As shown in FIG. 7D, since the tool 4 is also in contact with the back surface 1r of the first semiconductor chip 1, heat, load, ultrasonic waves, and the like from the tool 4 are applied to the first semiconductor chip 1. Heat, load, ultrasonic waves, and the like are not sufficiently applied to the second semiconductor chip 2, and the connection of the second semiconductor chip 2 is insufficient.

As shown in FIG. 7 (e), since the tool 4 is also in contact with the back surface 1r of the first semiconductor chip 1, heat, load, ultrasonic waves, etc. from the tool 4 are applied to the first semiconductor chip 1. In the case of connection using, for example, Au and Sn, which also affects the semiconductor chip 1, metal diffusion excessively proceeds due to heat applied to the first semiconductor chip 1, and the connection of the first semiconductor chip 1 is deteriorated. .

As shown in FIG. 7F, since the tool 4 is also in contact with the back surface 1r of the first semiconductor chip 1, heat, load, ultrasonic waves, etc. from the tool 4 are transmitted to the first semiconductor chip 1. For example, an element 1x having a material configuration weak to heat is applied to the semiconductor chip 1.
And the like, which were not affected by the heat for connecting the first semiconductor chip 1, but were further affected by the heat for connecting the second semiconductor chip 2. 1x electrical characteristics deteriorate.

For this reason, some attempts have been made to make the pressing surface of the tool the same size as the semiconductor chip. However, it is necessary to manufacture the tool according to various sizes of the semiconductor chip, and the cost increases. In addition, since the tool must be replaced for each semiconductor chip, the number of work steps increases, leading to an increase in running cost. Also, if the size of the semiconductor chip is reduced to a certain extent or more, suction holes, heaters, load sensors, etc. cannot be provided on the tool,
Such a tool cannot be produced. In addition, when the pressing surface of the tool has the same size as the semiconductor chip, if the tool and the semiconductor chip are not sufficiently aligned, as shown in FIG. Damage such as cracking and chipping occurs.
The same applies to the case where the size of the pressing surface of the tool is smaller than that of the semiconductor chip. Thus, it has been difficult to meet the demand for reducing the distance between the semiconductor chip and the semiconductor chip.

[0013]

According to a first aspect of the present invention, there is provided a semiconductor device mounting structure in which a plurality of semiconductor chips are connected to a wiring board in a face-down manner. The height from the reference surface of the wiring board to the back surface of the second semiconductor chip is higher than the height to the back surface of the semiconductor chip, and the height from the reference surface of the wiring board to the main surface of the first semiconductor chip is higher than the height from the reference surface of the second semiconductor chip. Also, the height from the reference surface of the wiring board to the main surface of the second semiconductor chip is high, and the semiconductor chip is connected to the wiring board.

According to a second aspect of the present invention, there is provided a semiconductor device mounting structure in which a plurality of semiconductor chips are connected to a wiring board in a face-down manner, from a reference surface of the wiring board to a back surface of the first semiconductor chip. The height from the reference surface of the wiring substrate to the main surface of the second semiconductor chip is higher than the height, and the semiconductor device is connected to the wiring substrate.

According to a third aspect of the present invention, there is provided a semiconductor device mounting structure in which a plurality of semiconductor chips are connected to a wiring board in a face-down manner, from a reference surface of the wiring board to a back surface of the first semiconductor chip. The wiring board has a height from the reference surface of the wiring board to the main surface of the second semiconductor chip higher than the height, and the second semiconductor chip partially overlaps the first semiconductor chip. It is characterized by being connected above.

The present invention described in claim 4 is based on claim 1,
2. The method for mounting a semiconductor device according to item 2 or 3,
After the first semiconductor chip is connected to the wiring board, the second semiconductor chip is connected to the wiring board.

[0017]

According to the present invention, when an attempt is made to temporarily fix or connect a second semiconductor chip next to a first semiconductor chip that has already been temporarily fixed or connected, the first semiconductor chip is moved from the reference surface of the wiring board to the first semiconductor chip. Is lower than the height from the reference surface of the wiring substrate to the back surface of the second semiconductor chip, so that the tool for connecting the second semiconductor chip is connected to the back surface of the first semiconductor chip. Do not touch.

[0018]

Embodiments of the present invention will be described below with reference to the drawings.

First Embodiment FIGS. 1 (a) to 1 (e) are cross-sectional views showing main steps of a first embodiment of the present invention. Here, a case is shown in which a plurality of semiconductor chips having bumps formed on chip electrodes are mounted on a wiring board.

First, a wiring board 3 on which wirings 3w, electrodes 3e, etc. are formed is prepared (FIG. 1A). Here, the AIN substrate 3 on which the wiring 3w and the electrode 3e are formed is used.
Any of WB, glass substrate, and the like may be used.

Next, a first semiconductor chip 1 in which the thickness of the semiconductor substrate 1s is made smaller than the thickness of the semiconductor substrate 2s of the second semiconductor chip 2 described later is prepared, and the chip of the first semiconductor chip 1 is prepared. The electrode 1e and the corresponding substrate electrode 3e of the wiring board 3 are aligned (FIG. 1B). here,
Au is used for the chip electrode 1e using a GaAs semiconductor substrate 1s.
Although the semiconductor chip 1 on which the bumps 1a are formed is used, a semiconductor chip having solder bumps, Cu ball bumps, or the like formed on silicon or the like may be used.

Next, the first semiconductor chip 1 is connected to the wiring board 3
(FIG. 1 (c)). Here, the connection is performed by applying a load while heating using the tool 4, but an ultrasonic wave or the like may be further applied.

Next, a second semiconductor chip 2 is prepared in which the thickness of the semiconductor substrate 2s is larger than the thickness of the semiconductor substrate 1s of the first semiconductor chip 1, and the chip electrodes 2e of the second semiconductor chip 2 are prepared. And the corresponding substrate electrode 3e of the wiring substrate 3 are aligned (FIG. 1D).

Finally, the second semiconductor chip 2 is connected to the wiring board 3 (FIG. 1E). Here, the connection was made in the same manner as in FIG. At this time, the reference surface 3 of the wiring board 3
a to the back surface 2r of the second semiconductor chip ₂
Is the first semiconductor chip 1 from the reference surface 3a of the wiring board 3.
Is higher than the height H1 up to the back surface 1r of the _first semiconductor chip 2, even if the pressing surface of the tool 4 that presses the second semiconductor chip 2 protrudes from the second semiconductor chip 2, the tool 4 remains in the first position. Does not hit the semiconductor chip 1.

Second Embodiment FIGS. 2A to 2E are cross-sectional views showing main steps of a second embodiment of the present invention. Here, as a connection structure for connecting the chip electrode of the semiconductor chip and the substrate electrode of the wiring board,
A case is shown in which a semiconductor chip in which conductive particles are arranged on chip electrodes and a semiconductor chip connected to a wiring board via an anisotropic conductive film are mounted on a wiring board.

First, a wiring board 3 on which wirings 3w, electrodes 3e, etc. are formed is prepared (FIG. 2A). Here, the glass substrate 3 on which the wiring 3w and the electrode 3e are formed is used.
Any of WB, ceramic substrate, and the like may be used.

Next, a first semiconductor chip 1 in which small-diameter conductive particles 1a are arranged on the chip electrode 1e is prepared, and the chip electrode 1e of the first semiconductor chip 1 and the corresponding substrate electrode 3e of the wiring board 3 are connected. Are aligned (FIG. 2B). Here, a silicon semiconductor substrate 1s is used, and a chip electrode 1
e, a semiconductor chip 1 having conductive particles 1a obtained by coating a resin with Au was used. The method of arranging the conductive particles is to apply a photosensitive resin to the silicon wafer on which the electrodes are formed, to cure the resin other than the electrode portions by UV irradiation, to scatter the conductive particles, and to perform washing, etc. Since only the uncured electrode portion has tackiness, only the electrode portion has conductive particles attached thereto, and the other portions have no conductive particles attached thereto. Resin is also U
It is a method of curing by V irradiation.

Next, the first semiconductor chip 1 is connected to the wiring board 3
(FIG. 2 (c)). Here, the semiconductor chip 1
Alternatively, an appropriate amount of the photosensitive resin 1a 'is dropped on the wiring board 3, and the tool 4 is pressed while pressing the semiconductor chip 1 against the wiring board 3 with the tool 4.
V irradiation is performed. Here, the wiring substrate 3 used is one that transmits UV light.

Next, a second semiconductor chip 2 is prepared, and the chip electrodes 2e of the second semiconductor chip 2 are aligned with the corresponding substrate electrodes 3e of the wiring board 3 (FIG. 2).
(D)).

Finally, the second semiconductor chip 2 is connected to the wiring board 3 (FIG. 2E). Here, a load is applied by a tool 4 between the second semiconductor chip 2 and the wiring board 3 via an anisotropic conductive film 2a ″ composed of a connection structure 2a and a resin 2a ′. At this time, the first
Diameter d in the direction perpendicular to the horizontal plane of the substrate after connection of the conductive particles 1a used as the connection structure of the semiconductor chip 1 of FIG.
₁ is smaller than the thickness d _{2 of} the anisotropic conductive film 2a ″ used as the connection structure of the second semiconductor chip 2 after connection, and is smaller than the reference surface 3a of the wiring board 3 by the first semiconductor chip 1 distance h ₁ to the element surface 1f of smaller spacing h ₂ from the reference surface 3a of the wiring board 3 to the second element surface 2f of the semiconductor chip 2. That is, the second semiconductor from the reference surface 3a of the wiring board 3 The height H ₂ up to the back surface 2r of the chip 2 is
From the reference surface 3a of the wiring board 3 becomes higher than the height H ₁ to the first back 1r of the semiconductor chip 1, tool presses the second semiconductor chip 2 - pressing surface of the Le 4 a second semiconductor chip The tool 4 does not hit the first semiconductor chip 1 even if it extends beyond the second semiconductor chip 1.

In the above embodiment, different connection structures for connecting the chip electrodes of the semiconductor chip and the substrate electrodes of the wiring board are used for the first chip and the second chip. May be used to change the size, thickness, etc. of the connection structure, or use a connection structure of the same type and size, one of which is subjected to a high load or the like. It is also possible to use a method of changing connection conditions in which the connection condition is considerably crushed and the other is crushed weakly by a low load or the like.

Third Embodiment FIGS. 3 (a) to 3 (f) are cross-sectional views showing main steps of a third embodiment of the present invention. Here, a case is shown in which a plurality of semiconductor chips having bumps formed on chip electrodes are mounted on a wiring board.

First, the area 3h of the wiring board 3 to which the second semiconductor chip 2 is connected is made higher than the reference surface 3a of the wiring board 3, and the wiring board 3 on which the wiring 3w, the electrodes 3e and the like are formed.
Is prepared (FIG. 3A). Here, the insulating resin 3x is applied to the area 3h of the wiring board 3 to which the second semiconductor chip 2 is connected, cured, and made higher than the reference surface 3a of the wiring board 3 to form the wiring 3w and the electrode 3e. Although PWB3 was used, the area may be any of a ceramic substrate, a glass substrate, and the like, which are made by thickening the paste and co-firing.

Next, the first semiconductor chip 1 is prepared, and the chip electrodes 1e of the first semiconductor chip 1 are aligned with the substrate electrodes 3e corresponding to the wiring board 3 (FIG. 3B).
Here, a semiconductor chip 1 in which a solder bump 1a is formed on a chip electrode 1e using a silicon semiconductor substrate 1s is used.

Next, the first semiconductor chip 1 is connected to the wiring board 3
(FIG. 3 (c)). Here, the semiconductor chip 1 is lightly pressed against the wiring board 3 by the tool 4 and temporarily fixed.

Next, a second semiconductor chip 2 having substantially the same thickness as that of the first semiconductor chip is prepared.
Chip electrode 2e and corresponding substrate electrode 3e of wiring substrate 3
Are aligned (FIG. 3D).

Next, the second semiconductor chip 2 is connected to the wiring board 3
(FIG. 3 (e)). Here, temporary fixing was performed in the same manner as in FIG. At this time, the area 3h of the wiring board 3 to which the second semiconductor chip 2 is connected is higher than the reference surface 3a of the wiring board 3, and therefore, from the reference surface 3a of the wiring board 3 to the back surface 2r of the second semiconductor chip 2. Height H
₂ is higher than the height H ₁ from the reference surface 3a of the wiring board 3 to the first back 1r of the semiconductor chip 1, the pressing surface of the tool 4 that presses the second semiconductor chip 2 is the second semiconductor The tool 4 does not hit the first semiconductor chip 1 even if the tool 4 protrudes from the chip 2. Finally, the wiring board 3
Is reflowed to connect with the semiconductor chip (FIG. 3
(F)).

In the above-described embodiment, the wiring board in which the area of the wiring board for connecting the second semiconductor chip is higher than the reference plane of the wiring board is used. On the contrary, the connection of the first semiconductor chip is performed. A wiring board in which the area of the wiring board to be formed is lower than the reference plane of the wiring board may be used.

In the above embodiment, the solder bump is used as the connection structure.
The steps of temporarily fixing the semiconductor chip, temporarily fixing the second semiconductor chip, and collectively connecting the first and second semiconductor chips by reflow, in this order. The steps may be performed in the order of temporary fixing of the second semiconductor chip and connection by reflow.

Fourth Embodiment FIGS. 4A to 4C are cross-sectional views showing main steps of an embodiment of the present invention. In the above-described first to third embodiments, two semiconductor chips are described. However, here, a case is shown in which mounting is performed using more semiconductor chips. Further, the height of each of the semiconductor chips from the reference plane of the wiring board may be variously changed. The thicknesses D ₁ , D ₂ , and D ₃ of the semiconductor substrate have a relationship of D ₁ <D ₂ <D ₃ , and the connection structures have substantially the same size.

Firstly, the first thickness of the semiconductor substrate 1s is D ₁
4 is connected to the wiring board 3 (FIG. 4).
(A)).

Next, the second semiconductor substrate 2s having a thickness of D ₁
4 is connected to the wiring board 3 (see FIG. 4).
(B)).

At this time, since there is a relationship of D ₁ <D ₂ ,
The height from the reference surface 3a of the wiring board 3 to the back surfaces of the first and second semiconductor chips has a relationship of H ₁ <H ₂ , and the tool 4 that presses the second semiconductor chip 2 is a first semiconductor chip. There is no one.

The third of the thickness of the last semiconductor substrate 5s is D ₃
4 is connected to the wiring board 3 (FIG. 4).
(C)). At this time, since there is a relationship of D ₁ <D ₂ <D ₃ , the first, second and third positions are shifted from the reference surface 3 a of the wiring board 3.
The height of each of the semiconductor chips up to the back surface is H ₁ <
H ₂ <H ₃ , and the tool 4 pressing the third semiconductor chip 5 does not hit the first semiconductor chip 1 and the second semiconductor chip 2.

Fifth Embodiment FIG. 5 shows a sectional view of a semiconductor device according to a fifth embodiment of the present invention. Here, the first semiconductor chip 1 is mounted on a lower portion 3l in which the wiring board 3 is formed concavely from the reference surface 3a, and the back surface 1r is mounted on the second semiconductor chip 2 mounted on the wiring board 3. Element surface 2f. The mounting method at this time can be any of the methods described in the first to fourth embodiments. In this case, even if the connection structure 2a is crushed, the connection structure 2a is not directly short-circuited with the adjacent connection structure 1a, which is suitable for high-density mounting.

Sixth Embodiment FIG. 6 shows a sectional view and a plan view of a semiconductor device according to a sixth embodiment of the present invention. Here, the first semiconductor chip 1 is mounted on the reference surface 3a of the wiring substrate 3, and the second semiconductor chip 2 is mounted on a higher portion 3h where the wiring substrate 3 is formed more convexly than the reference surface 3a. Have been. The back surface 1r of the semiconductor chip 1 is mounted lower than the element surface 2f of the semiconductor chip 2 and, as is apparent from the drawing, mounted such that the semiconductor chips overlap each other when viewed from the plane. This case is particularly suitable for high-density mounting.

It should be noted that the present invention is not limited to the above embodiment, and various modifications can be made within the scope of the claims.

[0048]

As described above, according to the present invention, when the semiconductor chip is temporarily fixed or connected to the wiring board,
The height from the reference surface of the wiring substrate to the back surface of the semiconductor chip is different in the mounting structure of the adjacent semiconductor chip, and the second semiconductor chip is temporarily mounted next to the temporarily fixed or connected first semiconductor chip. When stopping or connecting, the height from the reference surface of the wiring board to the back surface of the first semiconductor chip is lower than the height from the reference surface of the wiring board to the back surface of the second semiconductor chip. , First
The tool for connecting the second semiconductor chip does not come into contact with the back surface of the semiconductor chip. For this reason, the space between adjacent semiconductor chips can be reduced without changing the tool, and as a result, the reliability, the mounting density, the electrical characteristics, and the like can be increased.

Further, when the height to the back surface of the first semiconductor chip is set lower than the height to the element surface of the second semiconductor chip, a better effect can be obtained.

[Brief description of the drawings]

FIG. 1 is a sectional view of a main process in a first embodiment.

FIG. 2 is a sectional view of a main process in a second embodiment.

FIG. 3 is a sectional view of a main process in a third embodiment.

FIG. 4 is a sectional view of a main process in a fourth embodiment.

FIG. 5 is a sectional view of a semiconductor device according to a fifth embodiment.

FIGS. 6A and 6B are a cross-sectional view and a plan view of a semiconductor device according to a sixth embodiment.

FIG. 7 is a diagram for explaining a problem of the related art.

FIG. 8 is a diagram for explaining a problem of another conventional technique.

[Explanation of symbols]

Reference Signs List 1 first semiconductor chip 1s semiconductor substrate of first semiconductor chip 1r back surface of first semiconductor chip 1f element surface of first semiconductor chip 1e chip electrode of first semiconductor chip 1a connection structure of first semiconductor chip Body 2 Second semiconductor chip 2s Semiconductor substrate of second semiconductor chip 2r Back surface of second semiconductor chip 2f Element surface of second semiconductor chip 2e Chip electrode of second semiconductor chip 2a Connection of second semiconductor chip Structure 3 Wiring board 3a Reference plane of wiring board 3h Part higher than reference plane of wiring board 3l Part lower than reference plane of wiring board 3w Wiring of wiring board 3e Board electrode of wiring board 4 Tool 5 Third semiconductor chip 5s Semiconductor substrate of third semiconductor chip 5r Back surface of third semiconductor chip H Height from reference surface of wiring substrate to back surface of semiconductor chip Thickness after connection of the connecting structure of thickness d semiconductor chip height D semiconductor chip of the semiconductor substrate from the reference plane of the h wiring substrate to the element surface of the semiconductor chip

Claims (4)

(57) [Claims] 1. A mounting structure of a semiconductor device in which a plurality of semiconductor chips are connected to a wiring board in a face-down manner, wherein a reference height of the wiring board is higher than a height from a reference surface of the wiring board to a back surface of the first semiconductor chip. The height from the surface to the back surface of the second semiconductor chip is higher, and the height of the second semiconductor chip from the reference surface of the wiring board is higher than the height from the reference surface of the wiring substrate to the main surface of the first semiconductor chip. A mounting structure of a semiconductor device, wherein a height to a main surface is high and connected to the wiring board. 2. A mounting structure of a semiconductor device in which a plurality of semiconductor chips are connected to a wiring board in a face-down manner, wherein the reference of the wiring board is higher than the height from the reference surface of the wiring board to the back surface of the first semiconductor chip. A mounting structure of a semiconductor device, wherein a height from a surface to a main surface of a second semiconductor chip is high, and the semiconductor device is connected to the wiring board. 3. A mounting structure of a semiconductor device in which a plurality of semiconductor chips are connected to a wiring board in a face-down manner, wherein the reference of the wiring board is higher than the height from the reference surface of the wiring board to the back surface of the first semiconductor chip. The height from the surface to the main surface of the second semiconductor chip is high, and the semiconductor chip is connected to the wiring board so that a part of the second semiconductor chip overlaps a part of the first semiconductor chip. Mounting structure of a semiconductor device. 4. The method for mounting a semiconductor device according to claim 1, wherein after connecting the first semiconductor chip to the wiring board, connecting the second semiconductor chip to the wiring board. A method for mounting a semiconductor device.